Semiconductor device

Abstract

Provided is a transistor that allows for a large flow of current. Provided is a transistor that allows for miniaturization. A semiconductor device according to the present invention includes a semiconductor layer, pairs of each of first and second buffer layers, pairs of each of first and second electroconductive layers, a third electroconductive layer, and a first insulation layer. The semiconductor layer is positioned on the first buffer layers. The second buffer layers are positioned on the semiconductor layer. The first electroconductive layers are positioned on the second buffer layers. The semiconductor layer has protruding parts that protrude further to the outside than the first buffer layers and the second buffer layers. The second electroconductive layers contact the first electroconductive layers, side surfaces of each of the first and second buffer layers, and the protruding parts. The first insulation layer contacts an upper surface and a lower surface of the semiconductor layer in a region that does not overlap the pair of first buffer layers. The third electroconductive layer is positioned above and below the semiconductor layer with the first insulation layer therebetween.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor that combines miniaturization with high reliability. Another object is to provide a semiconductor device in which transistors can be arranged at high density.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including first and second semiconductor layers, pairs of first to third buffer layers, pairs of first and second conductive layers, a third conductive layer, and a first insulating layer. The first semiconductor layer is located above the pair of first buffer layers. The pair of second buffer layers is located above the first semiconductor layer. The second semiconductor layer is located above the pair of second buffer layers. The pair of third buffer layers is located above the second semiconductor layer. The pair of first conductive layers is located above the third buffer layer. The side surfaces of the first semiconductor layer and the second semiconductor layer each have protruding portions that protrude outward beyond the side surfaces of the first buffer layer, the second buffer layer, and the third buffer layer. The pair of second conductive layers are in contact with the side surfaces of the first conductive layer, the side surfaces of the first to third buffer layers, and the protruding portions of the first and second semiconductor layers, respectively. The first insulating layer contacts the upper and lower surfaces of the first semiconductor layer in regions that do not overlap with the pair of first buffer layers, and contacts the upper and lower surfaces of the second semiconductor layer in regions that do not overlap with the second buffer layer. The third conductive layer has a portion located below the first semiconductor layer with the first insulating layer interposed therebetween, a portion located between the first semiconductor layer and the second semiconductor layer with the first insulating layer interposed therebetween, and a portion located above the second semiconductor layer with the first insulating layer interposed therebetween.

[0013] In the above, the first buffer layer preferably has a first crystalline region in which a first crystal orientation is oriented substantially perpendicular to the surface of the first buffer layer, and the first semiconductor layer preferably has a second crystalline region in which a second crystal orientation is oriented substantially perpendicular to the surface of the first buffer layer.

[0014] Another embodiment of the present invention is a semiconductor device including first to n-th semiconductor layers (n is an integer of 2 or more), pairs of first to n+1th buffer layers, pairs of first and second conductive layers, a third conductive layer, and a first insulating layer. The k-th semiconductor layer (k is an integer of 1 to n-1) is located above the pair of k-th buffer layers. The pair of k+1th buffer layers is located above the k-th semiconductor layer. The pair of first conductive layers is located above the n+1th buffer layer. The side surfaces of the first to n-th semiconductor layers each have protruding portions that protrude outward beyond the side surfaces of the first to n+1th buffer layers. The pair of second conductive layers are in contact with the side surfaces of the first conductive layer, the side surfaces of the first to n+1th buffer layers, and the protruding portions of the first to n-th semiconductor layers, respectively. The first insulating layer is in contact with the top surface and the bottom surface of the k-th semiconductor layer in a region that does not overlap with the pair of k-th buffer layers. The third conductive layer has a portion located below the first semiconductor layer via the first insulating layer, a portion located between the kth semiconductor layer and the k+1th semiconductor layer via the first insulating layer, and a portion located above the nth semiconductor layer via the first insulating layer.

[0015] In the above, the kth buffer layer preferably has a first crystalline region in which a first crystalline orientation is oriented substantially perpendicular to the surface thereof, and the kth semiconductor layer preferably has a second crystalline region in which a second crystalline orientation is oriented substantially perpendicular to the surface thereof.

[0016] Another embodiment of the present invention is a semiconductor device including a semiconductor layer, pairs of first and second buffer layers, pairs of first and second conductive layers, a third conductive layer, and a first insulating layer. The semiconductor layer is located above the pair of first buffer layers. The pair of second buffer layers is located above the semiconductor layer. The pair of first conductive layers is located above the second buffer layer. The semiconductor layer has a side surface that protrudes outward beyond the side surface of the first buffer layer and the side surface of the second buffer layer. The pair of second conductive layers are in contact with the side surface of the first conductive layer, the side surfaces of the first and second buffer layers, and the protruding portion of the semiconductor layer, respectively. The first insulating layer is in contact with the top surface and the bottom surface of the semiconductor layer in a region that does not overlap with the pair of first buffer layers. The third conductive layer has a portion located below the semiconductor layer with the first insulating layer interposed therebetween and a portion located above the semiconductor layer with the first insulating layer interposed therebetween.

[0017] In the above, the first buffer layer preferably has a first crystalline region in which a first crystal orientation is oriented substantially perpendicular to the surface of the first buffer layer, and the semiconductor layer preferably has a second crystalline region in which a second crystal orientation is oriented substantially perpendicular to the surface of the semiconductor layer.

[0018] In the above, the first crystalline region preferably has a hexagonal crystal structure, the second crystalline region preferably has a cubic crystal structure, and the first crystalline orientation is preferably the

[001] orientation and the second crystalline orientation is preferably the

[111] orientation.

[0019] Alternatively, in the above, the first crystalline region and the second crystalline region each preferably have a cubic crystal structure, and the first crystalline orientation and the second crystalline orientation are preferably the

[111] orientation, the

[100] orientation, or the

[110] orientation, respectively.

[0020] Furthermore, in the above, it is preferable that the first insulating layer has a portion located between the third conductive layer and the first buffer layer, a portion located between the third conductive layer and the second buffer layer, and a portion located between the third conductive layer and the first conductive layer.

[0021] In the above, it is preferable that the first and second semiconductor layers each contain a first metal oxide, the first to third buffer layers each contain a second metal oxide, and the pair of second conductive layers each contain a third metal oxide. Furthermore, it is preferable that the first to third metal oxides each contain indium. In this case, it is preferable that the second metal oxide contains gallium and the third metal oxide contains tin.

[0022] In the above, it is preferable that the semiconductor device further includes fourth and fifth conductive layers, second and third insulating layers, and a connection electrode. The second insulating layer is preferably located above the pair of first and third conductive layers. The fourth conductive layer is preferably located above the second insulating layer. It is preferable that the third insulating layer covers the fourth conductive layer, and the fifth conductive layer covers the fourth conductive layer via the third insulating layer. It is preferable that the connection electrode penetrates the second insulating layer and connects one of the pair of first conductive layers to the fourth conductive layer.

[0023] In the above, the fourth conductive layer preferably has a columnar shape. In the above, the third insulating layer preferably contains an insulator exhibiting ferroelectricity. In the above, the third insulating layer preferably contains one or both of hafnium and zirconium.

[0024] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor that can be miniaturized and has high reliability can be provided. Alternatively, a semiconductor device in which transistors can be arranged at high density can be provided.

[0025] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0027] FIGS. 1A to 1C are structural examples of a semiconductor device. FIGS. 2A to 2C are structural examples of a semiconductor device. FIGS. 3A to 3C are structural examples of a semiconductor device. FIGS. 4A to 4C are structural examples of a semiconductor device. FIGS. 5A to 5C are structural examples of a semiconductor device. FIGS. 6A to 6C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 7A to 7C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 8A to 8C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 9A to 9C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 11A to 11C are structural examples of a memory device. FIGS. 12A to 12C are structural examples of a memory device. FIGS. 13A and 13B are diagrams illustrating carrier concentration dependence of hole mobility. FIG. 13C is a cross-sectional view illustrating an indium oxide film. FIG. 14 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 15A to 15H are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 16A and 16B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 17 is a block diagram illustrating a CPU. FIGS. 18A and 18B are perspective views of a semiconductor device. FIGS. 19A and 19B are perspective views of a semiconductor device. FIG. 20A is an example of a configuration of a memory device. FIG. 20B is an example of a hysteresis characteristic. FIG. 20C is a diagram illustrating a method of driving a memory device. FIGS. 21A and 21B are example configurations of electronic components. FIGS. 22A to 22C are example configurations of a mainframe computer. FIG. 23A is an example configuration of space equipment. FIG. 23B is an example configuration of a storage system.

[0028] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0030] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0031] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0034] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0035] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0036] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0037] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0038] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0039] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0040] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0041] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0042] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0043] In this specification, "two lines parallel" refers to a state in which the two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. "Two lines approximately parallel" refers to a state in which the two lines are arranged at an angle of -30 degrees or more and 30 degrees or less (including parallel). "Two lines perpendicular" refers to a state in which the two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. "Two lines approximately perpendicular" refers to a state in which the two lines are arranged at an angle of 60 degrees or more and 120 degrees or less (including perpendicular).

[0044] In this specification, "two surfaces are parallel" refers to a state in which their interior angle is between -10 degrees and 10 degrees. "Two surfaces are approximately parallel" refers to a state in which their interior angle is between -30 degrees and 30 degrees (including parallel). "Two surfaces are perpendicular" refers to a state in which their interior angle is between 80 degrees and 100 degrees (including perpendicular). "Two surfaces are approximately perpendicular" refers to a state in which their interior angle is between 60 degrees and 120 degrees (including perpendicular).

[0045] Embodiment 1 In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. As a specific example of a semiconductor device, a transistor will be described below.

[0046] One embodiment of the present invention is a transistor including a sheet-shaped semiconductor layer. The transistor includes gate insulating layers covering upper and lower surfaces of the sheet-shaped semiconductor layer and gate electrodes sandwiching the semiconductor layer from above and below with the gate insulating layers interposed therebetween. A region of the semiconductor layer covered by the gate insulating layers functions as a channel formation region. With this structure, a gate electric field is applied to the semiconductor layer from above and below, and thus a source-drain current (also referred to as on-current) can be increased when the transistor is turned on.

[0047] The sheet-like semiconductor layer is preferably not one layer but two or more layers. When multiple semiconductor layers are used, the semiconductor layers are preferably stacked vertically with a gap therebetween. In this case, the gate insulating layer is provided to cover the channel formation regions of all the semiconductor layers. The gate electrode has portions located below the lowest semiconductor layer, above the highest semiconductor layer, and between the two semiconductor layers. With this configuration, a gate electric field can be applied to all the semiconductor layers from above and below, thereby obtaining a larger on-current than simply stacking semiconductor layers and increasing the effective channel width.

[0048] A pair of buffer layers is provided above and below the semiconductor layer so as to sandwich a channel formation region therebetween. The buffer layers function as spacers for securing a space for providing a gate insulating layer and a gate electrode above and below the channel formation region of the semiconductor layer. When semiconductor layers are stacked, a pair of buffer layers is provided between two adjacent semiconductor layers, and the buffer layers can secure the space between the channel formation regions of the two semiconductor layers.

[0049] Furthermore, a pair of first electrodes is preferably provided on the pair of uppermost buffer layers. Furthermore, a pair of second electrodes is preferably further provided. The pair of second electrodes is provided in contact with the side surface of the semiconductor layer, the outer side surface of the buffer layer (opposite the gate electrode), and the outer side surface of the first electrode, respectively. The second electrodes can connect the semiconductor layer and the first electrode. That is, there is a pair of connected first and second electrodes, one of which functions as a source electrode and the other as a drain electrode. When multiple semiconductor layers are provided, the second electrodes connect the side surfaces of all the semiconductor layers to the first electrode.

[0050] Here, the semiconductor layer preferably has a protruding portion whose side surface protrudes beyond the outer side surface of the buffer layer (the side opposite the gate electrode). Furthermore, the second electrode preferably contacts not only the side surface of the protruding portion of the semiconductor layer but also the top and bottom surfaces. This increases the contact area between the second electrode and the semiconductor layer, thereby reducing the contact resistance between the second electrode and the semiconductor layer.

[0051] In addition, it is preferable to use a conductor or a semiconductor for the buffer layer. When the buffer layer is conductive, the semiconductor layer and the first conductive layer can be connected not only by the second electrode but also by the buffer layer, thereby reducing the electrical resistance between the semiconductor layer and the first electrode. Furthermore, when a plurality of semiconductor layers are provided, the semiconductor layers can be connected to each other by the buffer layer. When the buffer layer is a semiconductor, a channel is formed in the buffer layer itself when subjected to a gate electric field, so that the resistance can be low when the transistor is in an on state and high when it is in an off state. In other words, it is possible to increase the on-current when the transistor is in an on state and reduce the leakage current when the transistor is in an off state.

[0052] As the semiconductor material used for the semiconductor layer, it is preferable to use a metal oxide (oxide semiconductor) that exhibits semiconductor properties. In this case, it is also preferable to use a metal oxide for the buffer layer and the second electrode. This is preferable because it can reduce the contact resistance between the semiconductor layer, the buffer layer, and the second electrode. Furthermore, by using a metal oxide for the semiconductor layer, the buffer layer, and the second electrode, it becomes easy to process two or three of them in the same process, which makes it easier to simplify the manufacturing process and improves productivity and yield.

[0053] Here, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer. In particular, a metal oxide having a single crystal structure or a polycrystalline structure is preferable. In this case, the crystal structure of the semiconductor layer may be affected by the crystal structure of the buffer layer in contact with the underside of the semiconductor layer. More specifically, the crystal structure of the semiconductor layer may be a structure in which the crystal orientation of the crystalline regions of the buffer layer is aligned in a specific direction depending on the crystal orientation of the crystalline regions of the buffer layer. For example, when a metal oxide having a hexagonal crystal structure such as In—Ga—Zn oxide is used for the buffer layer and a metal oxide having a cubic crystal structure such as indium oxide is used for the semiconductor layer, if the

[001] orientation of the crystalline regions of the buffer layer is oriented perpendicular to the surface on which the semiconductor layer is formed, the semiconductor layer may have a single crystal structure or a polycrystalline structure in which the

[111] orientation of the crystalline regions is oriented perpendicular to the surface on which the semiconductor layer is formed. In this way, by using a metal oxide having a uniaxially oriented crystal region for the buffer layer, a semiconductor layer with high crystallinity can be obtained. This allows for the realization of a transistor with high on-state current and high reliability.

[0054] A more specific example will be described below with reference to the drawings.

[0055] [Configuration Example] Fig. 1A shows a schematic top view of a transistor 10. Figs. 1B and 1C show schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in Fig. 1A, respectively. Fig. 2A shows a schematic perspective view of the transistor 10. Figs. 2B and 2C show schematic perspective views taken along the cutting lines A1-A2 and B1-B2, respectively. Figs. 1B and 2B correspond to cross sections in the channel length direction, and Figs. 1C and 2C correspond to cross sections in the channel width direction. Note that some components (such as an insulating layer 31) are omitted in Fig. 1A.

[0056] The transistor 10 includes a plurality of semiconductor layers (semiconductor layers 21_1 to 21_3), an insulating layer 22, a conductive layer 23, a pair of conductive layers 24 (conductive layer 24a and conductive layer 24b), a pair of conductive layers 25 (conductive layer 25a and conductive layer 25b), and a plurality of pairs of buffer layers 12 (buffer layers 12_1 to 12_4). Here, a transistor including three semiconductor layers will be described. A part of the insulating layer 22 functions as a gate insulating layer, and a part of the conductive layer 23 functions as a gate electrode. The conductive layer 24a and the conductive layer 24b function as a source electrode and a drain electrode, respectively. The conductive layer 25a and the conductive layer 25b also function as a source electrode and a drain electrode, respectively.

[0057] In this embodiment, when describing matters common to components distinguished by alphabets attached to symbols (conductive layer 24a, conductive layer 24b, etc.) and components distinguished by numbers attached to symbols (semiconductor layer 21_1, semiconductor layer 21_2, etc.), the description may be made using symbols (conductive layer 24, semiconductor layer 21, etc.) with the alphabets or numbers omitted.

[0058] The transistor 10 is provided over an insulating layer 11 that is provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0059] A pair of buffer layers 12_1 is provided on the insulating layer 11, and a semiconductor layer 21_1 is provided on the buffer layer 12_1. The pair of buffer layers 12_1 are provided spaced apart from each other, and the semiconductor layer 21_1 has a region between a portion located on one buffer layer 12_1 and a portion located on the other buffer layer 12_1 that does not overlap with either buffer layer 12_1.

[0060] The pair of buffer layers 12_2 are provided on the semiconductor layer 21_1. Each of the pair of buffer layers 12_2 is provided at a position overlapping with the buffer layer 12_1. The semiconductor layer 21_1 has a region between the pair of buffer layers 12_2 that does not overlap with either of the buffer layers 12_2.

[0061] Similarly to the above, a semiconductor layer 21_2, a buffer layer 12_3, a semiconductor layer 21_3, and a buffer layer 12_4 are stacked in this order on the buffer layer 12_2. Furthermore, a conductive layer 25a and a conductive layer 25b are provided on the buffer layer 12_4.

[0062] The regions of the semiconductor layer 21 that are located between a pair of buffer layers 12 located below the semiconductor layer 21 and between a pair of buffer layers 12 located above the semiconductor layer 21 and that do not overlap with any of the buffer layers 12 function as channel formation regions.

[0063] The conductive layers 24a and 24b are provided in contact with the side surfaces of the semiconductor layers 21, the outer side surfaces (opposite the conductive layer 23) of the buffer layers 12, and the outer side surfaces of the conductive layers 25a and 25b, respectively. The conductive layers 24 can connect the semiconductor layers 21 and the conductive layers 25.

[0064] 1B and other figures, each semiconductor layer 21 preferably has a protruding portion 21t that protrudes outward beyond the respective side surfaces of the buffer layer 12 that it contacts. Furthermore, the conductive layer 24 is preferably provided in contact with not only the side surfaces of the protruding portion 21t of each semiconductor layer 21, but also the upper and lower surfaces of the protruding portion 21t. This increases the contact area between the conductive layer 24 and the semiconductor layer 21, thereby reducing the contact resistance therebetween.

[0065] The insulating layer 22 is provided so as to surround the region of the semiconductor layer 21 that does not overlap with the buffer layer 12. The insulating layer 22 is provided in contact with the upper and lower surfaces of each semiconductor layer 21 in the region that does not overlap with each pair of buffer layers 12. As shown in FIG. 1C , the insulating layer 22 is also provided so as to surround the upper surface, lower surface, and both side surfaces of the semiconductor layer 21 in the channel width direction.

[0066] The conductive layer 23 is provided so as to surround the top, side, and bottom surfaces of each semiconductor layer 21 via the insulating layer 22. This allows an electric field from the conductive layer 23 to be applied to the channel formation region of the semiconductor layer 21 from above and below, thereby increasing the on-current per semiconductor layer 21. Furthermore, by providing a plurality of semiconductor layers 21, the on-current of the transistor 10 can be made extremely high.

[0067] Furthermore, the insulating layer 22 is provided between each buffer layer 12 and the conductive layer 23, and between each conductive layer 25 and the conductive layer 23, to insulate them from each other. This makes it possible to prevent electrical short circuits between the buffer layer 12 and the conductive layer 23, and between the conductive layer 25 and the conductive layer 23.

[0068] 1B , when a distance L1 between a pair of opposing side surfaces of the conductive layer 25a and the conductive layer 25b is compared with a distance L2 between a pair of opposing side surfaces of the pair of buffer layers 12, it is preferable that L2 is larger than L1. This reduces the distance between the channel formation region of the semiconductor layer 21 and the conductive layer 24a or 24b, thereby reducing the electrical resistance therebetween and further increasing the on-current of the transistor 10.

[0069] An insulating layer 31 is provided covering the conductive layers 24 and 25. A slit is provided in the insulating layer 31, and an insulating layer 22 and a conductive layer 23 are formed inside the slit. The insulating layer 22 is provided along the side surface of the slit in the insulating layer 31, and the conductive layer 23 is provided so as to fill the slit in the insulating layer 31. A portion of the conductive layer 23 functions as wiring that follows the shape of the slit.

[0070] Here, a metal oxide (oxide semiconductor) exhibiting semiconductor properties is preferably used for the semiconductor layer 21. In this case, a conductive metal oxide (oxide conductor) is preferably used for the conductive layer 24 in contact with the semiconductor layer 21. By using a metal oxide for the conductive film in contact with the metal oxide-containing semiconductor layer 21, the contact resistance therebetween can be reduced, the load on the wiring can be reduced, and the on-current of the transistor 10 can be increased.

[0071] The conductive layer 24 preferably contains a metal oxide containing the same metal element as the semiconductor layer 21. In particular, it is preferable that both the conductive layer 24 and the semiconductor layer 21 contain a metal oxide containing indium. This reduces the contact resistance between the semiconductor layer 21 and the conductive layer 24. Furthermore, when processing the conductive layer 24 and the semiconductor layer 21, etching can be performed under the same conditions, which simplifies the manufacturing process and improves yield and productivity. It is preferable to use a metal oxide containing indium and tin for the conductive layer 24, as this can increase conductivity.

[0072] Furthermore, it is preferable to use a metal oxide for the buffer layer 12. By using a metal oxide for the buffer layer 12, the buffer layer 12 itself can function as a source electrode or a drain electrode. Furthermore, by using a metal oxide for both the buffer layer 12 and the conductive layer 24, not only can the contact resistance between them be reduced, but also the current path between the semiconductor layer 21 and the conductive layer 25 can be expanded, thereby further reducing the load on the wiring.

[0073] The semiconductor layer 21, the buffer layer 12, and the conductive layer 24 preferably have a metal oxide containing the same metal element. More specifically, the semiconductor layer 21, the buffer layer 12, and the conductive layer 24 each preferably contain one or more of In, Sn, and Zn. In particular, it is preferable that they contain In. When the semiconductor layer 21, the buffer layer 12, and the conductive layer 24 contain the same metal element, contact resistance can be reduced in any combination of these. Furthermore, this makes it easy to process (etch) two or more of these in the same process, which is preferable because it simplifies the manufacturing process of the transistor 10 and improves productivity and yield.

[0074] Furthermore, it is preferable that the semiconductor layer 21 and the buffer layer 12 have a large etching rate selectivity in wet etching. Therefore, it is preferable that the semiconductor layer 21 and the buffer layer 12 are made of metal oxides that differ in at least one of constituent elements, composition, or crystallinity, rather than using films formed under the same conditions. As an example, indium oxide can be used for the semiconductor layer 21, and indium-gallium-zinc oxide (also referred to as IGZO) can be used for the buffer layer 12. In this case, indium oxide has the property of being more easily crystallized than IGZO, so it is easy to make the constituent elements and composition as well as the crystallinity different.

[0075] Alternatively, the buffer layer 12 may have a stacked structure, and one or more of the stacked films may be made of a material that can achieve a high etching rate selectivity with respect to the semiconductor layer 21. For example, when an oxide film containing indium is used for the semiconductor layer 21, the buffer layer 12 preferably has a stacked structure of an oxide film containing indium (e.g., IGZO) and a gallium oxide film. In this case, it is more preferable for the buffer layer 12 to have a stacked structure in which an oxide film containing indium is stacked on a gallium oxide film. Furthermore, the lowest buffer layer 12_1 of the buffer layers 12 may be more susceptible to etching than the buffer layers 12 located above it. In this case, it is preferable for only the lowest buffer layer 12_1 to have the above-described stacked structure. In this case, the gallium content of the film used for the buffer layer 12_1 may be higher than that of the other buffer layers 12, so that the etching rate of the lowest buffer layer 12_1 is slower.

[0076] Here, the crystal structures of the semiconductor layer 21 and the buffer layer 12 will be described.

[0077] Fig. 3A is a schematic cross-sectional view of a portion of Fig. 1B. Fig. 3B is a schematic perspective view of a region P including the semiconductor layer 21 (semiconductor layer 21_2), the buffer layer 12 (buffer layer 12_2), and the insulating layer 22 shown in Fig. 3A.

[0078] Here, an example is shown in which the buffer layer 12 has multiple crystalline regions 12C. The right side of FIG. 3B schematically shows a unit cell of a crystal contained in the crystalline region 12C. The crystalline region 12C has a hexagonal crystal structure, and the c-axis (

[001] orientation) is oriented approximately perpendicular to the surface on which the buffer layer 12 is formed or to the surface of the buffer layer 12. The buffer layer 12 can be made of a metal oxide that easily forms a layered crystal structure, such as In—Ga—Zn oxide, In—Ga oxide, In—Zn oxide, or zinc oxide. The buffer layer 12 preferably has a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, or a microcrystalline structure.

[0079] FIG. 3B illustrates an example in which the semiconductor layer 21 has a single crystal structure. The semiconductor layer 21 has a crystalline region 21C in which the crystal orientation is aligned throughout the layer. The upper right corner of FIG. 3B schematically illustrates a unit lattice of a crystal contained in the crystalline region 21C. The crystalline region 21C has a cubic crystal structure, and the

[111] orientation is oriented approximately perpendicular to the surface on which the semiconductor layer 21 is formed or the surface of the semiconductor layer 21. It can also be said that the

[111] orientation of the crystalline region 21C is oriented approximately parallel to the c-axis (

[001] orientation) of the crystalline region 12C of the buffer layer 12. For the semiconductor layer 21, it is preferable to use a metal oxide, such as indium oxide, that easily forms a cubic crystal structure, and indium oxide is particularly preferable.

[0080] For example, InGaZnO ３ In the crystal structure of In, the distance between metal atoms on the c-plane ((001) plane) is approximately 0.330 nm. ２ O ３ In the crystal structure of indium oxide, the In-In distances on the (111) plane are 0.334 nm and 0.385 nm. That is, since the arrangement of metal atoms is similar between the c-plane of the CAAC structure and the (111) plane of indium oxide, it is presumed that an indium oxide film is likely to grow heteroepitaxially on a film having a CAAC structure.

[0081] Furthermore, the semiconductor layer 21 has a single-crystal crystalline structure not only above the buffer layer 12 but also above the insulating layer 22. That is, the portion of the semiconductor layer 21 that functions as a channel formation region has a single-crystal structure, thereby realizing a transistor that has both a high on-state current and high reliability.

[0082] In this way, the crystal orientation of the crystalline region of the semiconductor layer 21 is affected by the crystal orientation of the crystalline region of the buffer layer 12 that is in contact with the lower surface of the semiconductor layer 21. In other words, the crystal structure of the semiconductor layer 21 can be controlled by controlling the crystallinity, crystal structure, etc. of the buffer layer 12.

[0083] FIG. 3C illustrates an example in which the semiconductor layer 21 has a polycrystalline crystal structure. The semiconductor layer 21 has multiple crystal grains (also referred to as grains) and crystal grain boundaries (also referred to as grain boundaries) between them. One crystal grain can be considered as one single-crystal region. FIG. 3C also illustrates the crystal lattices of crystal regions 21C1 and 21C2, which belong to different crystal grains. The

[111] direction of both crystal regions 21C1 and 21C2 is oriented approximately perpendicular to the surface on which they are formed. Thus, even when the semiconductor layer 21 has a polycrystalline crystal structure, it is preferable that each crystal grain has uniaxial orientation (including orientation in a specific direction other than the crystal axis). This allows for the realization of a transistor with superior electrical characteristics and reliability compared to polycrystalline structures with disordered crystal orientations.

[0084] The semiconductor layer 21 can be formed into a single crystal structure as shown in FIG. 3B or a polycrystalline structure as shown in FIG. 3C by crystal growth using the buffer layer 12 or a part thereof as a seed crystal by heat treatment during or after film formation.

[0085] A polycrystalline film is composed of two or more crystal grains, whereas a single-crystal film can be considered to be composed of a single crystal grain. Grain boundaries are observed in polycrystalline films, whereas they are not observed in single-crystal films. Impurities (typically, insulating impurities, insulating oxides, etc.) that impede carrier flow are likely to segregate at grain boundaries. Therefore, if grain boundaries are present in the channel formation region, there is a risk of significant variations in transistor characteristics. Therefore, if grain boundaries are not observed in the channel formation region, there is an excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0086] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation (including a specific orientation other than the crystal axis) faces in one direction in the channel formation region can be called a single crystal film.

[0087] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer and is located between a region in contact with the source electrode and a region in contact with the drain electrode.

[0088] A semiconductor layer in which no crystal grain boundary is observed in the region between the region in contact with the source electrode and the region in contact with the drain electrode, a semiconductor layer in which the region between the region in contact with the source electrode and the region in contact with the drain electrode is included in a single crystal grain, a semiconductor layer in which the crystal axis direction is the same in at least two regions located between the region in contact with the source electrode and the region in contact with the drain electrode, or a semiconductor layer in which at least one crystal orientation is oriented in one direction in the region between the region in contact with the source electrode and the region in contact with the drain electrode can be called a single crystal film.

[0089] In the channel formation region, the current path is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region or in the region between the region in contact with the source electrode and the region in contact with the drain electrode can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0090] When there are multiple buffer layers 12 and multiple semiconductor layers 21, the crystallinity of one semiconductor layer 21 is affected by the crystal structure of the buffer layer in contact with its lower surface. Therefore, in order to align the crystal structures of the multiple semiconductor layers 21, it is preferable to align the crystallinity of each buffer layer 12. On the other hand, by making the crystallinity of the multiple buffer layers 12 different, it is also possible to make the crystal structures of the multiple semiconductor layers 21 different. For example, one or more of the multiple semiconductor layers 21 may have a single crystal structure, and the other one or more may have a polycrystalline structure.

[0091] Although an example has been shown in which the buffer layer 12 and the semiconductor layer 21 have crystal structures with different crystal systems, metal oxides with the same crystal system may also be used for the buffer layer 12 and the semiconductor layer 21. For example, when indium oxide is used for both the buffer layer 12 and the semiconductor layer 21, the crystal orientation of the crystalline region of the buffer layer 12 may coincide with that of the crystalline region of the semiconductor layer 21 located thereover. For example, when the crystalline region of the buffer layer 12 is oriented in the

[111] ,

[100] , or

[110] direction, which is approximately perpendicular to the surface on which it is formed, the crystalline region of the semiconductor layer 21 also has the same orientation as the buffer layer 12, among the

[111] ,

[100] , and

[110] directions, which is approximately perpendicular to the surface on which it is formed. In this case, if the buffer layer 12 can be considered single crystalline, the semiconductor layer 21 can also be single crystalline.

[0092] Although the above description has been given of a structure in which three semiconductor layers 21 are stacked, the number of semiconductor layers 21 included in the transistor 10 is not limited to this. A larger number of semiconductor layers 21 is preferable because it can increase the on-state current of the transistor 10. On the other hand, a smaller number of semiconductor layers 21 can simplify the manufacturing process of the transistor 10 and improve yield.

[0093] 4A shows an example in which the semiconductor layer 21 is one layer. Similar to FIG. 2B , FIG. 4A is a perspective view including a cross section of the transistor in the channel length direction. A pair of buffer layers 12_1 is provided below the semiconductor layer 21, a pair of buffer layers 12_2 is provided above the semiconductor layer 21, and conductive layers 25 a and 25 b are provided in contact with the top surfaces of the buffer layers 12_2. Thus, even if the semiconductor layer 21 is a single layer, the conductive layer 23 is provided to surround the channel formation region of the semiconductor layer 21, thereby realizing a transistor 10 with a large on-state current.

[0094] 4B shows an example in which two semiconductor layers 21 are included. The structure shown in FIG. 4B includes two semiconductor layers 21 (semiconductor layer 21_1 and semiconductor layer 21_2) and three buffer layers 12 (buffer layers 12_1 to 12_3). The conductive layer 25a and the conductive layer 25b are provided in contact with the top surface of the buffer layer 12_3.

[0095] 4C shows an example in which five semiconductor layers 21 are included. The structure shown in FIG. 4C shows an example in which five semiconductor layers 21 (semiconductor layers 21_1 to 21_5) and six buffer layers 12 (buffer layers 12_1 to 12_6) are included. The conductive layer 25a and the conductive layer 25b are provided in contact with the top surface of the buffer layer 12_6.

[0096] For example, in a structure having n semiconductor layers 21 (n is an integer of 2 or more), n+1 pairs of buffer layers 12 are provided. In this case, the kth (k is an integer of 1 to n-1) semiconductor layer among the n semiconductor layers 21 is provided between the pair of kth buffer layers 12 and the pair of k+1th buffer layers 12. The conductive layers 25a and 25b are provided in contact with the upper surface of the uppermost (n+1th) buffer layer. The conductive layers 24a and 24b are provided in contact with the protruding portions of the 1st to nth semiconductor layers 21, the side surfaces of the 1st to n+1th buffer layers 12, and the side surface of the conductive layer 24a or 24b, respectively. The insulating layer 22 is provided in contact with the upper surface, lower surface, and side surfaces of the kth semiconductor layer 21 so as to surround them. The conductive layer 23 has, via the insulating layer 22, a portion located below the first semiconductor layer 21 which is the lowest, a portion located between the kth semiconductor layer 21 and the (k+1)th semiconductor layer 21, and a portion located above the nth semiconductor layer 21 which is the highest.

[0097] Here, when an oxide conductor is used for the buffer layer 12, the conductive layer 24 a and the conductive layer 24 b may not be provided. In this case, two adjacent semiconductor layers 21 and the uppermost semiconductor layer 21 and the conductive layer 25 are connected by the buffer layer 12 therebetween.

[0098] Fig. 5A shows an example in which the conductive layer 24a and the conductive layer 24b are omitted from the structure having three semiconductor layers 21 shown in Fig. 2B etc. Fig. 5B shows an example in which the conductive layer 24a and the conductive layer 24b are omitted from the structure having one semiconductor layer 21 shown in Fig. 4A.

[0099] 5C , a configuration may be adopted in which the buffer layer 12 is not provided and parts of the conductive layer 24 a and the conductive layer 24 b are located between two adjacent semiconductor layers 21. With such a configuration, the distance between the conductive layer 24 and the channel formation region of the semiconductor layer 21 can be shortened. Furthermore, since the conductive layer 25 contacts the upper surface of the conductive layer 24, the contact area between the conductive layer 25 and the conductive layer 24 can be increased. As a result, a transistor with a larger on-state current can be obtained.

[0100] The above is a description of an example of the configuration of the semiconductor device.

[0101] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0102] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0103] The semiconductor layer 21 is preferably made of indium oxide.

[0104] Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0105] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0106] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0107] The semiconductor layer 21 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, or In—Ga—Al—Zn oxide. Ga—Zn oxide may also be used. On the other hand, a material containing Zn is preferred because it is easy to increase crystallinity.

[0108] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0109] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0110] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0111] In this specification, the content of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0112] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0113] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0114] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0115] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0116] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0117] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0118] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0119] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:3:2, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0120] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a single crystal structure, a CAAC structure, a polycrystalline structure, a nano-crystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the density of defect states in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0121] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0122] In particular, it is preferable to use indium oxide for the semiconductor layer 21. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 21, and it is particularly preferable to use indium oxide with a single-crystal structure. However, indium oxide with a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide with a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 23). As a result, even indium oxide with a polycrystalline structure can achieve the same effects as indium oxide with a single-crystal structure.

[0123] The thickness of the semiconductor layer 21 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 21 within the above range, the crystallinity of the semiconductor layer 21 can be improved.

[0124] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide is a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 21, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0125] The semiconductor layer 21 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0126] Furthermore, when indium oxide is used for the semiconductor layer 21, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may result in a large amount of fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the semiconductor layer 21, the gallium concentration in the semiconductor layer 21 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0127] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0128] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0129] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0130] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0131] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0132] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0133] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0134] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0135] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0136] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0137] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0138] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials, and preferably by using a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown can be suppressed.

[0139] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0140] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0141] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0142] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0143] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film that releases oxygen when heated as a film in contact with the semiconductor layer 21, an insulating film that has barrier properties against hydrogen and oxygen as a film located on the conductive layer 23 side, and an insulating film that has the function of capturing or fixing hydrogen as a film located between them. Silicon oxide or silicon oxynitride can be used as the film that releases oxygen when heated. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0144] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0145] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film that releases oxygen when heated, an insulating film that has the function of capturing or fixing hydrogen, and an insulating film that has a barrier property against hydrogen and oxygen, in order from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being released from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0146] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0147] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0148] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0149] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride can be used.

[0150] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0151] <Conductive Layer> The conductive layer 24 is in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 and the semiconductor layer 21, hindering electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 in contact with the semiconductor layer 21.

[0152] The conductive layer 24 in contact with the semiconductor layer 21 is preferably made of, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0153] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0154] For example, the conductive layer 24 can be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0155] The conductive layers 23 and 25 are preferably made of a low-resistance conductive material. For the conductive layers 23 and 25, it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0156] The conductive layers 23 and 25 may be made of the same nitrides and oxides as those used for the conductive layer 24 .

[0157] <Insulating Layer> The insulating layer 31 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0158] The insulating layer 31 preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0159] Since the insulating layer 31 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 31 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0160] The insulating layer 11, which functions as a base insulating layer, also functions as an interlayer insulating layer. The insulating layer 11 can be made of the same insulating material as can be used for the insulating layer 31.

[0161] <Buffer Layer> The buffer layer 12 can be made of an insulating material, a semiconductor material, or a conductive material. The buffer layer 12 can be made of a material that has an etching rate selectivity at least similar to that of the semiconductor layer 21. The buffer layer 12 can be made of a material that differs from the semiconductor layer 21 in at least one of the constituent elements, composition, crystallinity, and density.

[0162] It is particularly preferable to use, as the buffer layer 12, a material that can be used for the semiconductor layer 21 or a material that can be used for the conductive layer 24. Note that, as the buffer layer 12, a material that can be used for the conductive layer 23 and the conductive layer 25, a material that can be used for the insulating layer 22, or a material that can be used for the insulating layer 31 can also be applied.

[0163] This concludes the description of the components.

[0164] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking the transistor 10 exemplified in the above structure example as an example.

[0165] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0166] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0167] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0168] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0169] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0170] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0171] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0172] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0173] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0174] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0175] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0176] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0177] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0178] 6A to 9C are schematic perspective views corresponding to the steps in the example of the fabrication method described below. Fig. 9B is a perspective view including a cross section corresponding to Fig. 2B, and the other figures are perspective views corresponding to Fig. 2A.

[0179] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0180] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0181] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0182] Next, a film to be the buffer layer 12_1 is formed on the insulating layer 11. The film can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. For example, when indium-gallium-zinc oxide is used for the buffer layer 12_1, the film can be formed by a sputtering method or an ALD method. When a metal oxide film is used for the buffer layer 12_1, the description of a method for forming a semiconductor film to be the semiconductor layer 21_1 described below can be referred to.

[0183] The thickness of the buffer layer 12_1 is determined by the thicknesses of the insulating layer 22 and the conductive layer 23 (thicknesses in the regions overlapping with the semiconductor layer 21) to be formed later. The thickness of the film that will become the buffer layer 12_1 is set to at least twice the thickness of the insulating layer 22. For example, the thickness of the film is set to more than twice but not more than 10 times the thickness of the insulating layer 22, preferably 2.5 times or more but not more than 10 times, and more preferably 3 times or more but not more than 10 times.

[0184] Here, the film to be the buffer layer 12_1 is preferably a film having crystallinity. When an indium-gallium-zinc oxide film is formed by sputtering as the film to be the buffer layer 12_1, a film with higher crystallinity can be formed by increasing the proportion of oxygen gas in the film formation gas and by increasing the substrate temperature during film formation. The film to be the buffer layer 12_1 is preferably formed to have a CAAC structure, a polycrystalline structure, a single-crystalline structure, or a microcrystalline structure, and particularly preferably has a CAAC structure.

[0185] Subsequently, a semiconductor film that will become the semiconductor layer 21_1 is formed on the above film.

[0186] The semiconductor film may be a metal oxide (oxide semiconductor) film having semiconductor properties, which may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0187] The metal oxide film preferably has crystallinity. In particular, the metal oxide film according to one embodiment of the present invention preferably has a metal oxide having a single crystal structure, a polycrystalline structure, or a CAAC structure.

[0188] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0189] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0190] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering may be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0191] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0192] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0193] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0194] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0195] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0196] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0197] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0198] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0199] The deposition conditions for the metal oxide film are such that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0200] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0201] For example, when a metal oxide is used for the semiconductor film, the film can be formed by an ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0202] For example, when forming an indium oxide film, a precursor containing indium can be used.

[0203] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0204] Examples of precursors that can be used that contain indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0205] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0206] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0207] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), nitrogen dioxide (NO ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used, and two or more of these may be used.

[0208] In order to reduce the hydrogen and nitrogen concentrations in the film, O is used as an oxidizing agent. ２ or O ３ It is preferable to use O ３ On the other hand, when forming a single crystal or a polycrystal with a large grain size, it is preferable to use an oxidizing agent containing hydrogen in order to suppress the generation of crystal nuclei in the initial stage of film formation. For example, H ２ O or H ２ O ２ After forming a film with few crystal nuclei, crystal growth can be caused by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size.

[0209] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0210] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0211] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0212] In the following drawings, the semiconductor layer is shown as a single layer, but it may also have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it is also possible to form the first layer by the sputtering method and the second layer by the ALD method. The semiconductor layer may also have a laminated structure of four or more layers.

[0213] When forming the semiconductor film, a film having a single crystal or polycrystalline crystal structure can be formed using the crystals of the buffer layer 12_1 as seed crystals. When the buffer layer 12_1 has uniaxial orientation, such as a CAAC structure, a semiconductor film having a crystal structure with a specific orientation can be formed, reflecting the crystal structure. In particular, the ALD method is preferable because it makes it easy to form a semiconductor film with high crystallinity that reflects the crystal structure of the buffer layer 12_1.

[0214] Alternatively, a heat treatment may be performed after the semiconductor film is formed to induce crystal growth and form a film having a single-crystal or polycrystalline crystal structure. The heat treatment may be performed, for example, at a temperature of 120°C to 300°C, preferably 120°C to 250°C, and more preferably 120°C to 200°C. Note that the heat treatment may also be performed at a temperature exceeding 300°C (e.g., higher than 300°C to 600°C). The heat treatment may be performed each time a semiconductor film is formed, or after all the semiconductor films of the semiconductor layer 21 are formed, or after that. Furthermore, another process involving substrate heating (such as a film formation process) may also serve as the heat treatment.

[0215] This makes it possible to form a semiconductor layer 21 having a single-crystal crystal structure as illustrated in FIG. 3B, or a semiconductor layer 21 having a polycrystalline crystal structure with uniaxial orientation as illustrated in FIG. 3C.

[0216] Subsequently, a film to be the buffer layer 12_2, a semiconductor film to be the semiconductor layer 21_2, a film to be the buffer layer 12_3, a semiconductor film to be the semiconductor layer 21_3, and a film to be the buffer layer 12_4 are formed in this order on the semiconductor film. These films and semiconductor films can be formed in the same manner as described above.

[0217] Here, we will explain the case where there are three semiconductor layers 21, but if there are n semiconductor layers 21, it is sufficient to alternately stack films that will become the buffer layer 12 (n+1 layers) and semiconductor films that will become the semiconductor layer 21 (n layers).

[0218] Subsequently, a conductive film that will become the conductive layer 25 is formed on the film that will become the buffer layer 12_4. The conductive film can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0219] Next, a resist mask is formed over the conductive film, and portions of each film located above the insulating layer 11 that are not covered by the resist mask are etched to form buffer layers 12_1 to 12_4, semiconductor layers 21_1 to 21_3, and a conductive layer 25 (FIG. 6A).

[0220] It is preferable to use anisotropic dry etching for the etching. While Fig. 6A shows an example in which the side surfaces of each layer are perpendicular to the upper surface of the insulating layer 11, the side surfaces of each layer may have a tapered shape depending on the etching conditions. In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed.

[0221] Next, the buffer layers 12_1 to 12_4 are each etched by isotropic etching to recess the side surfaces. This allows the protrusions 21t to be formed in each semiconductor layer 21 ( FIG. 6B ). Isotropic dry etching or wet etching can be used for the etching. Alternatively, atomic layer etching can be used. In particular, wet etching is preferable because it is easier to perform isotropic etching than dry etching and also makes it easier to increase the etching rate selectivity between the buffer layer 12 and the semiconductor layer 21.

[0222] For example, when metal oxide films containing indium are used for the semiconductor layer 21 and the buffer layer 12, and the semiconductor layer 21 is a film having higher crystallinity than the buffer layer 12, wet etching is preferably used to achieve a large etching rate selectivity. For wet etching, for example, phosphoric acid, oxalic acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, or an aqueous solution of tetramethylammonium hydroxide (TMAH), or a mixed solution or mixed aqueous solution containing two or more of these, can be used. The chemical solution used for wet etching may be alkaline or acidic.

[0223] Subsequently, a conductive film 24f is formed to cover the conductive layer 25, the semiconductor layers 21, and the buffer layers 12 (FIG. 6C). The conductive film 24f can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0224] At this time, it is preferable that the conductive film 24f is also formed on the top and bottom surfaces of the protruding portions 21t of each semiconductor layer 21. Therefore, it is particularly preferable that the conductive film 24f be formed using the ALD method or the CVD method (particularly the thermal CVD method) which has high coverage.

[0225] 7A , a resist mask 15 is formed to cover a portion of the conductive film 24f. When the stacked body including the conductive layer 25, the semiconductor layers 21, and the buffer layers 12 has two pairs of opposing side surfaces, the resist mask 15 can be provided so as to overlap one of the pair of side surfaces but not the other.

[0226] Next, the conductive film 24f, the conductive layer 25, the semiconductor layers 21, and the buffer layers 12 are etched in the portions not covered by the resist mask 15, and then the resist mask 15 is removed (FIG. 7B). Anisotropic dry etching is preferably used for the etching. As a result, a pair of side surfaces of the conductive layer 25, the semiconductor layers 21, and the buffer layers 12 are exposed.

[0227] Next, the conductive film 24f is anisotropically etched to remove the portion of the conductive film 24f that contacts the upper surface of the conductive layer 25 and the portion that contacts the upper surface of the insulating layer 11 (FIG. 7C). As a result, the conductive film 24f is divided into two, forming the conductive layer 24a and the conductive layer 24b. Anisotropic dry etching is preferably used for the etching.

[0228] Next, a sacrificial layer 16 is formed to cover the conductive layer 25, the semiconductor layers 21, and a portion of the buffer layers 12 ( FIG. 8A ). The sacrificial layer 16 is provided in the region between the conductive layer 24 a and the conductive layer 24 b. The sacrificial layer 16 is also provided across the stack of the conductive layer 25, the semiconductor layers 21, and the buffer layers 12.

[0229] The sacrificial layer 16 can be made of a material having a high etching rate selectivity with respect to the semiconductor layer 21, the conductive layer 25, the insulating layer 11, and the insulating layer 31 to be formed later. For example, the sacrificial layer 16 can be made of an organic or inorganic material formed by a coating method. More specifically, a coating-type insulating film such as an SOC (spin on carbon) film or an SOG (spin on glass) film can be used. Alternatively, the sacrificial layer 16 can be formed by a film formation method such as a sputtering method or a CVD method. The material used for the sacrificial layer 16 preferably satisfies conditions such as being able to be formed thick, being able to be formed or processed vertically, and being easy to remove (leaving no residue and causing little damage to the surface on which it is formed).

[0230] Subsequently, an insulating layer 31 is formed, and then a planarization process is performed until the sacrificial layer 16 is exposed (FIG. 8B).

[0231] The insulating layer 31 can be formed by a film formation method such as sputtering, ALD, CVD, etc. The planarization process can be performed by, for example, CMP (Chemical Mechanical Polishing), dry etching, etc.

[0232] Next, the sacrificial layer 16 is removed, thereby forming grooves in the insulating layer 31 that reach the conductive layer 25 and the insulating layer 11. After that, the conductive layer 25 and the regions of each buffer layer 12 that are not covered by the insulating layer 31 (i.e., that are located inside the grooves) are removed by etching. As a result, the conductive layer 25 is divided into two at the groove, forming conductive layers 25a and 25b. Each buffer layer 12 is also divided into two, forming a pair of buffer layers 12 ( FIG. 8C ).

[0233] At this time, it is preferable to etch the sacrificial layer 16, the conductive layer 25, and the buffer layer 12 under conditions that minimize etching of the semiconductor layer 21. By etching a portion of the buffer layer 12, spaces are formed between the semiconductor layer 21_1 and the insulating layer 11, and between two adjacent semiconductor layers 21, as shown in FIG. 8C . Furthermore, each semiconductor layer 21 is configured to be supported by the buffer layer 12 located below it. Furthermore, the height of the spaces is approximately equal to the thickness of the buffer layer 12.

[0234] When etching the buffer layer 12, isotropic etching can be used to etch the region located between two adjacent semiconductor layers 21. Similarly, the region of the buffer layer 12_1 between the semiconductor layer 21_1 and the insulating layer 11 can also be etched. For the etching method of the buffer layer 12, the description of the formation of the protrusion 21t of the semiconductor layer 21 can be referred to.

[0235] It is also preferable to etch a part of the region overlapping with the conductive layer 25a and the conductive layer 25b when etching the buffer layer 12. This makes it possible to reduce the width of the buffer layer 12 in the channel length direction.

[0236] Next, the insulating layer 22 is formed by a film forming method with high step coverage (FIG. 9A). The insulating layer 22 can be formed typically by ALD.

[0237] 9B shows a perspective view including a cross section in the channel length direction obtained by cutting a portion of FIG. 9A. As shown in FIGS. 9A and 9B, the insulating layer 22 is formed in contact with all exposed surfaces. Inside the groove of the insulating layer 31, the insulating layer 22 is formed in contact with the side and bottom surfaces of the conductive layers 25a and 25b, the top, side, and bottom surfaces of each semiconductor layer 21, the side surfaces of each buffer layer 12, and the top surface of the insulating layer 11. In practice, the insulating layer 22 may also be formed on the top surface of the insulating layer 31, but this is not shown here for ease of viewing.

[0238] Next, a conductive film that will become conductive layer 23 is formed so as to fill the grooves in insulating layer 31, and then planarization is performed until the top surface of insulating layer 31 (or the top surface (not shown) of insulating layer 22 on insulating layer 31) is exposed ( FIG. 9C ). This allows conductive layer 23 to be formed so as to be buried in the grooves in insulating layer 31.

[0239] The conductive film that becomes the conductive layer 23 can be formed by ALD or CVD, with thermal CVD being particularly preferred.

[0240] Through the above steps, the transistor 10 can be manufactured.

[0241] The above is a description of an example of the manufacturing method.

[0242] [Modification] Hereinafter, a manufacturing method example of a semiconductor device that is partially different from the above-described manufacturing method example will be described. Here, a manufacturing method of the structure illustrated in Fig. 5C will be described. Note that a description of parts that overlap with the above-described manufacturing method example will be omitted.

[0243] First, in the same manner as described above, a stacked body is formed in which the buffer layers 12, the semiconductor layers 21, and the conductive layer 25 are stacked (see FIG. 6A).

[0244] Subsequently, when isotropic etching is performed to recess the side surfaces of the buffer layer 12, the etching is performed to a deeper position than the above. More specifically, the side surfaces of the buffer layer 12 are recessed by etching until the width of the buffer layer 12 roughly matches the channel length of the transistor 10.

[0245] Subsequently, a conductive film 24f is formed in the same manner as above, covering the stacked body including each buffer layer 12, each semiconductor layer 21, and the conductive layer 25. At this time, the conductive film 24f is formed so as to fill in the gap between two adjacent semiconductor layers 21 and the gap between the semiconductor layer 21_1 and the insulating layer 11.

[0246] Next, in the same manner as above, a resist mask 15 is formed, and a portion of the stack including the conductive film 24f, the buffer layers 12, the semiconductor layers 21, and the conductive layer 25 is etched. Thereafter, the portion of the conductive film 24f in contact with the upper surface of the conductive layer 25 and the portion in contact with the upper surface of the insulating layer 11 are removed. A perspective schematic view at this stage corresponds to FIG. 10A .

[0247] Next, a sacrificial layer 16 and an insulating layer 31 are formed, and the sacrificial layer 16 is removed. After that, the portion of the conductive layer 25 that does not overlap with the insulating layer 31 is etched to form conductive layers 25a and 25b. Next, each buffer layer 12 is completely removed by etching. A perspective schematic diagram including a cross section in the channel length direction at this stage corresponds to FIG. 10B. Inside the groove of the insulating layer 31, the side surfaces of the conductive layers 24a and 24b are exposed. Furthermore, each semiconductor layer 21 is supported with one end sandwiched between the conductive layer 24a and the other end sandwiched between the conductive layer 24b.

[0248] Thereafter, the insulating layer 22 and the conductive layer 23 are formed in the same manner as in the above-described manufacturing method (FIG. 10C). At this time, the insulating layer 22 is provided in contact with the inner side surfaces (on the conductive layer 23 side) of the conductive layers 24a and 24b.

[0249] Through the above steps, a transistor can be manufactured.

[0250] The above is a description of the modified example.

[0251] [Application Example] The transistor according to one embodiment of the present invention described in the above structure example can be applied to, for example, a switch of a memory device. An example of application of the transistor to a memory device will be described below.

[0252] 11A shows a circuit diagram of a memory cell 30. The memory cell 30 includes one transistor Tr and one capacitor C, and can also be expressed as 1Tr1C. The transistor Tr has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to a wiring PL.

[0253] The memory cell 30 can store data by holding, in the capacitor C, a data potential input from the wiring BL via the transistor Tr. The data can be held by turning the transistor Tr off. By turning the transistor Tr on, a potential corresponding to the held data is output to the wiring BL, allowing the data to be read. A signal that controls the conduction and non-conduction of the transistor Tr is applied to the wiring WL. A predetermined potential (e.g., a fixed potential) is applied to the wiring PL.

[0254] 11B shows a schematic cross-sectional view of the memory cell 30. The memory cell 30 shown in Fig. 11B includes a transistor 10 and a capacitance element 50 stacked on the transistor 10. The transistor 10 corresponds to the transistor Tr, and the capacitance element 50 corresponds to the capacitance element C.

[0255] The structure of the transistor 10 can be explained by referring to the description of the above-mentioned structure example, and therefore the explanation thereof will be omitted. Note that although an example in which the semiconductor layer 21 has three layers is shown here, the present invention is not limited to this, and the transistor 10 can be replaced with any of the various transistors exemplified in the above-mentioned structure example and modification example. Here, the conductive layer 23 of the transistor 10 corresponds to the wiring WL.

[0256] An insulating layer 32 is provided over the insulating layer 31, and a conductive layer 45 is provided over the insulating layer 32. An insulating layer 33 is provided to cover the insulating layer 32 and the conductive layer 45, and a capacitor 50 is provided over the insulating layer 33.

[0257] The capacitor 50 includes a conductive layer 51, an insulating layer 52, and a conductive layer 53. The conductive layer 51 has a columnar (also referred to as a needle or pillar) shape. The insulating layer 52 is provided to cover the conductive layer 51 and the insulating layer 53. The conductive layer 53 is provided to cover the conductive layer 51 with the insulating layer 52 interposed therebetween. The capacitor 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0258] The higher the height of the conductive layer 51, the larger the capacitance of the capacitive element 50 can be. On the other hand, the smaller the diameter of the conductive layer 51, the higher the integration density of the memory cell 30 can be. The conductive layer 51 can be appropriately set according to the capacitance required depending on the circuit driving method. The height of the conductive layer 51 is preferably, for example, 100 nm to 10 μm, preferably 200 nm to 8 μm, and more preferably 500 nm to 5 μm.

[0259] A low-resistance conductive material is preferably used for the conductive layers 51 and 53. For example, the materials that can be used for the conductive layer 23 or the conductive layer 25 can be used.

[0260] The insulating layer 52 functions as a dielectric for the capacitance element 50. The insulating layer 52 can be made of the same insulating material as the insulating layer 22. In particular, it is preferable to use the high-k material. Furthermore, by using the ferroelectric material for the insulating layer 52, the capacitance element 50 can be made into a ferroelectric capacitor, thereby realizing a nonvolatile memory device. Note that a resistance change type memory element utilizing the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect can also be used as the capacitance element 50.

[0261] Furthermore, an insulating layer 34 is provided so as to fill the conductive layer 53, and a conductive layer 46 is provided on the insulating layer 34. The conductive layer 46 corresponds to the wiring PL. Note that the conductive layer 53 may be used as the wiring PL without providing the insulating layer 34 and the conductive layer 46. In this case, it is preferable that the upper surface of the region of the conductive layer 53 that does not overlap with the conductive layer 51 is higher than the highest portion of the insulating layer 52, and that the upper surface of the conductive layer 53 is flattened.

[0262] The conductive layer 45 and the conductive layer 25a are connected via a connection electrode 41 that is embedded in the insulating layer 32 and the insulating layer 31 and penetrates the insulating layer 32 and the insulating layer 31. The conductive layer 45 corresponds to the wiring BL. The conductive layer 51 and the conductive layer 25b are connected via a connection electrode 42 that is embedded in the insulating layer 33, the insulating layer 32, and the insulating layer 31 and penetrates the insulating layer 33, the insulating layer 32, and the insulating layer 31. Here, an example is shown in which the connection electrode 42 is formed by the dual damascene method and the width of the upper part is made wider than the lower part to increase the contact area between the connection electrode 42 and the conductive layer 51, but this is not limited to this. The connection electrode 42 may also be formed by the single damascene method, or another conductive layer may be provided between the connection electrode 42 and the conductive layer 51.

[0263] 11C shows an example of a capacitor element 50a having a conductive layer 51 with a different shape than that shown in FIG. 11B. The conductive layer 51 has a flat portion in contact with the connection electrode 42 and a ring-shaped portion above the flat portion. The conductive layer 51 can also be said to have a tall, cup-like shape. This configuration increases the area over which the conductive layer 51 and the conductive layer 53 face each other via the insulating layer 52, thereby increasing the capacitance. Furthermore, the increased contact area between the conductive layer 51 and the connection electrode 42 also reduces the electrical resistance between them.

[0264] Next, an example of the configuration of a memory device that uses the memory cells 30 and is suitable for high integration will be described.

[0265] 12A shows a circuit diagram having two memory cells (memory cell 30a and memory cell 30b). Each of the memory cells 30a and 30b has a transistor Tr and a capacitor C. A wiring BL and a wiring PL are provided in common between the two memory cells. A wiring WL1 is connected to the gate of the transistor Tr of the memory cell 30a, and a wiring WL2 is connected to the gate of the transistor Tr of the memory cell 30b. For example, when writing or reading data to or from the memory cell 30a, a potential that turns on the transistor Tr is applied to the wiring WL1, and a potential that turns off the transistor Tr is applied to the wiring WL2.

[0266] FIG. 12B shows an example of a schematic top view of a plurality of memory cells 30a and 30b arranged. The plurality of wirings WL and the plurality of wirings BL are arranged in a direction perpendicular to each other. The memory cells 30a and 30b are arranged so as to be inclined with respect to the wirings WL and BL, respectively. The memory cells 30a and 30b each have a capacitance element 50. The memory cells 30a and 30b also share one connection electrode 41. The connection electrode 41 is arranged in a position overlapping the wiring BL. The capacitance element 50 is arranged in a region surrounded by a pair of wirings WL and a pair of wirings BL. By using this arrangement method, the area occupied by one memory cell can be reduced to 6F. ２ (F is the minimum processing dimension).

[0267] FIG. 12C corresponds to the cutting line C1-C2 in FIG. 12B and is a schematic cross-sectional view of the memory cells 30a and 30b in the L-length direction.

[0268] The two transistors 10 are provided symmetrically with respect to the connection electrode 41. The semiconductor layers 21 (semiconductor layers 21_1 to 21_3) and the conductive layer 25a are provided in common between the two transistors 10. The buffer layers 12 (buffer layers 12_1 to 12_4) connected to the conductive layer 25a are also provided in common between the two transistors 10. The two transistors 10 are provided with conductive layers 24b in contact with the side surfaces of the semiconductor layers 21, but are not provided with conductive layers 24a. The conductive layers 25a are connected to the semiconductor layers 21 via the buffer layers 12, not via the conductive layers 24a. By sharing some components between the two transistors 10 in this way, the occupied area can be reduced compared to when these components are provided separately.

[0269] The above is a description of the application example.

[0270] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0271] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0272] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0273] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0274] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 13A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ) and FIG. 13B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0275] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 13B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 13A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 13A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 13A.

[0276] 13A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0277] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0278] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0279] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of the element include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0280] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 13A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0281] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0282] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0283] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0284] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0285] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0286] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0287] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0288] The indium oxide film in the channel formation region may contain elements that can maintain a low carrier concentration, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such elements include gallium, aluminum, scandium, yttrium, and lanthanides (lanthanum, neodymium, samarium, erbium, ytterbium, etc.). These elements exist primarily as trivalent cations in oxides, and therefore can maintain a low carrier concentration in indium oxide.

[0289] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0290] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 13C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0291] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0292] Furthermore, as shown in FIG. 13C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0293] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0294] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0295]

[0296] A layer (hereinafter referred to as a seed layer) in contact with at least a portion of the crystalline indium oxide film is preferably made of a material containing crystals with a small difference in lattice constant (also referred to as lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0297] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0298] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0299] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0300] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0301] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0302] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0303] Fig. 14 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 14 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 14 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0304] The memory cell 30 exemplified in the above embodiment can be applied to the memory cell 950 .

[0305] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0306] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0307] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0308] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0309] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0310] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0311] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0312] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0313] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 14, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0314] 15A to 15H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0315] In the following, when two components are described as being connected, this includes being electrically connected via a circuit element (such as a transistor, a switch, a diode, or a resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or a transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0316] 15A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0317] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0318] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0319] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0320] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0321] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 may have the configuration of a memory cell 952 as shown in FIG. 15B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0322] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0323] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0324] 15C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a Nonvolatile Oxide Semiconductor RAM (NOSRAM) (registered trademark).

[0325] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0326] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0327] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0328] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0329] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 15D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0330] 15E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, a memory cell 956 in Fig. 15F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the degree of integration of the memory cells can be increased.

[0331] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0332] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0333] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0334] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0335] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0336] 15G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0337] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0338] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0339] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0340] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0341] Note that at least the transistor M4 is preferably an OS transistor.

[0342] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0343] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0344] 15H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 15H is a memory cell of an SRAM capable of backing up data.

[0345] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0346] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0347] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0348] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0349] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0350] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0351] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0352] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0353] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0354] The following describes how data is read. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. Since the potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0355] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0356] Note that Si transistors may be used as the transistors MS1 to MS4.

[0357] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 16A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 16B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0358] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0359] 17 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 17 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0360] The arithmetic device 960 shown in FIG. 17 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0361] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0362] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0363] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0364] The arithmetic device 960 shown in FIG. 17 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 17 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0365] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0366] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0367] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0368] 17, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0369] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 18A and 18B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in FIG. 18B.

[0370] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0371] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0372] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0373] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0374] 18B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0375] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0376] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0377] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0378] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0379] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 19A shows a perspective view of a semiconductor device 970B.

[0380] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 19A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0381] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0382] Also, multiple memory arrays may be stacked. Figure 19B shows a perspective view of a semiconductor device 970C.

[0383] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0384] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0385] Fourth Embodiment In this embodiment, a memory device including a ferroelectric capacitor and a method for driving the memory device will be described.

[0386] 20A shows an example of a circuit configuration of a memory cell using a ferroelectric capacitor. The memory cell 1480 includes a transistor Tr1 and a capacitance element Cfe. The memory cell 30 exemplified in the second embodiment can be used as the memory cell 1480.

[0387] The OS transistor described in the above embodiment is preferably used as the transistor Tr1. An OS transistor has a characteristic of high withstand voltage between the source and drain. That is, an OS transistor can be called a micro-high-voltage device. Therefore, by using an OS transistor as the transistor Tr1, a high voltage can be applied to the transistor Tr1 even when the transistor Tr1 is miniaturized. Miniaturizing the transistor Tr1 reduces the area occupied by the semiconductor device. Therefore, semiconductor devices can be arranged at high density. This allows a memory device with a large storage capacity to be realized.

[0388] One of the source and drain of the transistor Tr1 is electrically connected to the wiring BL. The other of the source and drain of the transistor Tr1 is electrically connected to one electrode of the capacitor Cfe. The gate of the transistor Tr1 is electrically connected to the wiring WL. The other electrode of the capacitor Cfe is electrically connected to the wiring PL.

[0389] The wiring WL functions as a word line, and the on / off state of the transistor Tr1 can be controlled by controlling the potential of the wiring WL. For example, the transistor Tr1 can be turned on by setting the potential of the wiring WL to a high potential (H), and the transistor Tr1 can be turned off by setting the potential of the wiring WL to a low potential (L). The wiring WL is electrically connected to a word line driver circuit, and the potential of the wiring WL can be controlled by the word line driver circuit.

[0390] The wiring BL functions as a bit line, and when the transistor Tr1 is on, a potential corresponding to the potential of the wiring BL is supplied to one electrode of the capacitor Cfe. The wiring BL is electrically connected to a bit line driver circuit. The bit line driver circuit has a function of generating data to be written to the memory cell 1480. The bit line driver circuit also has a function of reading data output from the memory cell 1480. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell 1480 can be read using the sense amplifier.

[0391] The wiring PL functions as a plate line. A potential is supplied to the other electrode of the capacitor Cfe through the wiring PL.

[0392] The capacitance element Cfe has a ferroelectric insulator (also called a ferroelectric layer) between two electrodes as a dielectric layer. For example, hafnium oxide, zirconium oxide, or HfZrO Ｘ (X is a real number greater than 0) is preferably used.

[0393] The ferroelectric layer of the capacitance element Cfe has a hysteresis characteristic. Fig. 20B is a graph showing an example of the hysteresis characteristic. In Fig. 20B, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe.

[0394] 20B, the vertical axis represents the polarization of the ferroelectric layer, and a positive value indicates that positive charges are biased toward one electrode of the capacitance element Cfe and negative charges are biased toward the other electrode of the capacitance element Cfe. On the other hand, a negative value indicates that positive charges are biased toward the other electrode of the capacitance element Cfe and negative charges are biased toward one electrode of the capacitance element Cfe.

[0395] 20B, the hysteresis characteristic of the ferroelectric layer can be expressed by a curve 61 and a curve 62. The voltages at the intersections of the curve 61 and the curve 62 are defined as VSP and −VSP. It can be said that VSP and −VSP have opposite polarities.

[0396] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 61. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can each be referred to as a saturation polarization voltage. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Also, while FIG. 20B shows a case where the absolute values ​​of the first and second saturation polarization voltages are equal, the absolute values ​​of the two may be different.

[0397] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 61 and the polarization of the ferroelectric layer is 0. Furthermore, −Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 62 and the polarization of the ferroelectric layer is 0. Vc and Vc can be referred to as coercive voltages, respectively. The values ​​of Vc and Vc can be referred to as values ​​between −VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and −Vc may be referred to as the second coercive voltage. Furthermore, although FIG. 20B shows that the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, the absolute values ​​of the two may be different.

[0398] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "remanent polarization Pr" and the minimum value is called "remanent polarization -Pr". Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "remanent polarization 2Pr".

[0399] The other electrode of the capacitance element Cfe is electrically connected to the wiring PL, so that the voltage applied to the ferroelectric layer of the capacitance element Cfe can be controlled by controlling the potential of the wiring PL.

[0400] An example of a method for driving the memory cell 1480 shown in Fig. 20A will be described below. In the following description, the transistor Tr1 is an n-channel transistor.

[0401] 20C is a timing chart showing an example of a method for driving the memory cell 1480. FIG. 20C shows an example of writing and reading binary digital data to the memory cell 1480. Specifically, FIG. 20C shows an example in which data “1” is written to the memory cell 1480 from time T01 to time T02, read and rewrite are performed from time T03 to time T05, read and write data “0” to the memory cell 1480 from time T11 to time T13, read and rewrite are performed from time T14 to time T16, and read and write data “1” to the memory cell 1480 from time T17 to time T19.

[0402] A reference potential Vref is supplied to the sense amplifier electrically connected to the wiring BL. In the read operation shown in FIG. 20C etc., when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0403] From time T01 to time T02, the potential of the wiring WL is set to a high potential. This turns on the transistor Tr1. The potential of the wiring BL is set to Vw. Since the transistor Tr1 is on, the potential of one electrode of the capacitor Cfe becomes Vw. Furthermore, the potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe becomes "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T01 to time T02 can be considered a period during which a write operation is performed.

[0404] Here, Vw is preferably equal to or greater than VSP, for example, equal to VSP. Although GND is a ground potential in this specification and the like, it is not necessarily required to be a ground potential as long as the memory cell 1480 can be driven to satisfy the spirit of one embodiment of the present invention. For example, if the absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage are different and the absolute values ​​of the first coercive voltage and the second coercive voltage are different, GND can be a potential other than ground.

[0405] From time T02 to time T03, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. From time T01 to time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be set to VSP or higher, so from time T02 to time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 62 shown in FIG. 20B. As a result, from time T02 to time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

[0406] After the potentials of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor Tr1. This completes the write operation, and data "1" is stored in the memory cell 1480. Note that the potentials of the wiring BL and the wiring PL can be set to any potential as long as polarization inversion does not occur in the ferroelectric layer of the capacitance element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or higher than the second coercive voltage -Vc.

[0407] From time T03 to time T04, the potential of the wiring WL is set to a high potential. This turns on the transistor Tr1. The potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" from time T01 to time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in the memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may be higher than Vw, for example.

[0408] Since the above read is destructive read, the data "1" stored in the memory cell 1480 is lost. Therefore, from time T04 to time T05, the potential of the wiring BL is set to Vw, and the potential of the wiring PL is set to GND. As a result, the data "1" is rewritten to the memory cell 1480. Therefore, the period from time T04 to time T05 can be considered as a period in which a rewrite operation is performed.

[0409] From time T05 to time T11, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the rewriting operation is completed, and data "1" is held in the memory cell 1480.

[0410] From time T11 to time T12, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since data "1" is stored in the memory cell 1480, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the memory cell 1480 is read. Therefore, the period from time T11 to time T12 can be considered a period in which a read operation is performed.

[0411] From time T12 to time T13, the potential of the wiring BL is set to GND. Because the transistor Tr1 is on, the potential of one electrode of the capacitor Cfe is set to GND. The potential of the wiring PL is set to Vw. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe is "GND-Vw." This allows data "0" to be written to the memory cell 1480. Therefore, the period from time T12 to time T13 can be considered a period during which a write operation is performed.

[0412] From time T13 to time T14, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to the curve 61 shown in FIG. 20B from time T13 to time T14. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.

[0413] After the potentials of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor Tr1. This completes the write operation, and data "0" is stored in the memory cell 1480. Note that the potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0414] From time T14 to time T15, the potential of the wiring WL is set to a high potential. This turns on the transistor Tr1. The potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" from time T12 to time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Specifically, the potential of the wiring BL becomes Vref or lower. Therefore, the bit line driver circuit can read the data "0" stored in the memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0415] From time T15 to time T16, the potential of the wiring BL is set to GND, and the potential of the wiring PL is set to Vw, thereby rewriting data "0" to the memory cell 1480. Therefore, the period from time T15 to time T16 can be considered a period in which a rewriting operation is performed.

[0416] From time T16 to time T17, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the rewriting operation is completed, and data "0" is held in the memory cell 1480.

[0417] From time T17 to time T18, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since data "0" is stored in the memory cell 1480, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the memory cell 1480 is read. Therefore, the period from time T17 to time T18 can be considered a period in which a read operation is performed.

[0418] From time T18 to time T19, the potential of the wiring BL is set to Vw. Because the transistor Tr1 is on, the potential of one electrode of the capacitor Cfe is set to Vw. The potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe is "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T18 to time T19 can be considered a period during which a write operation is performed.

[0419] After time T19, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the write operation is completed, and data "1" is held in the memory cell 1480.

[0420] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0421] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, so power consumption can be reduced.

[0422] The ferroelectric memory (also referred to as FE memory) exemplified in this embodiment has a capacitance of 1×10 １０ or more, preferably 1×10 １２ or more, more preferably 1×10 １５ The FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0423] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more in a temperature environment of 150°C or 200°C.

[0424] The FE memory can also be applied to cache memories and registers of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc. By combining the FE memory with the cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0425] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0426] Embodiment 5 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0427] [Electronic Component] FIG. 21A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 21A has semiconductor device 710 inside mold 711. FIG. 21A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0428] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0429] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0430] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0431] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0432] 21B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0433] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0434] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0435] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0436] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0437] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0438] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0439] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0440] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 21B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0441] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0442] 22A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0443] 22B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0444] Fig. 22C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 22C illustrates components other than electronic components 5626, 5627, and 5628.

[0445] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0446] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0447] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0448] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0449] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0450] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0451] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0452] Fig. 23A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 23A shows a planet 6804 in space as an example.

[0453] 23A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0454] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0455] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0456] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0457] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0458] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0459] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0460] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0461] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0462] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0463] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0464] Fig. 23B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 23B has multiple servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has multiple storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0465] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0466] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0467] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0468] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0469] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0470] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0471] 10: transistor, 11: insulating layer, 12: buffer layer, 12_1: buffer layer, 12_2: buffer layer, 12_3: buffer layer, 12_4: buffer layer, 12_6: buffer layer, 15: resist mask, 16: sacrificial layer, 21: semiconductor layer, 21_1: semiconductor layer, 21_2: semiconductor layer, 21_3: semiconductor layer, 21_5: semiconductor layer, 21t: protrusion, 22: insulating layer, 23: conductive layer, 24: conductive layer, 24a: conductive layer, 24b: conductive layer, 24f: conductive film, 25: conductive layer, 25a: conductive layer, 25b: conductive layer, 30: memory cell, 30a: memory cell, 30b: memory Recell, 31: insulating layer, 32: insulating layer, 33: insulating layer, 34: insulating layer, 41: connecting electrode, 42: connecting electrode, 45: conductive layer, 46: conductive layer, 50: capacitive element, 50a: capacitive element, 51: conductive layer, 52: insulating layer, 53: conductive layer, 61: curve, 62: curve, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor Semiconductor device, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 58: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 1480: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card,5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6000: storage system, 6001: host, 6001sb: server, 6002: storage control circuit, 6003: storage, 6003md: storage device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

a first semiconductor layer and a second semiconductor layer, a pair of first to third buffer layers, a pair of first and second conductive layers, a third conductive layer, and a first insulating layer; the first semiconductor layer is located above the pair of first buffer layers; the pair of second buffer layers are located above the first semiconductor layer; the second semiconductor layer is located above the pair of second buffer layers; the pair of third buffer layers are located above the second semiconductor layer; the pair of first conductive layers are respectively located above the third buffer layer; the first semiconductor layer and the second semiconductor layer each have a side surface that protrudes outward beyond a side surface of the first buffer layer, a side surface of the second buffer layer, and a side surface of the third buffer layer; the pair of second conductive layers are in contact with a side surface of the first conductive layer, side surfaces of the first to third buffer layers, and the protruding portions of the first and second semiconductor layers, respectively; the first insulating layer contacts an upper surface and a lower surface of the first semiconductor layer in a region not overlapping with the pair of first buffer layers, and contacts an upper surface and a lower surface of the second semiconductor layer in a region not overlapping with the pair of second buffer layers; the third conductive layer has a portion located below the first semiconductor layer with the first insulating layer interposed therebetween, a portion located between the first semiconductor layer and the second semiconductor layer with the first insulating layer interposed therebetween, and a portion located above the second semiconductor layer with the first insulating layer interposed therebetween. Semiconductor device. 　 a first to n-th semiconductor layer (n is an integer of 2 or more), a pair of first to n+1-th buffer layers, a pair of first and second conductive layers, a third conductive layer, and a first insulating layer; the kth semiconductor layer (k is an integer of 1 or more and n-1 or less) is located above the pair of kth buffer layers, the pair of (k+1)th buffer layers is located above the kth semiconductor layer, the pair of first conductive layers are respectively located above the (n+1)th buffer layer; the first to n-th semiconductor layers each have a protruding portion whose side surface protrudes outward beyond the side surfaces of the first to n+1-th buffer layers, the pair of second conductive layers are in contact with side surfaces of the first conductive layer, side surfaces of the first to (n+1)th buffer layers, and the protruding portions of the first to nth semiconductor layers, respectively; the first insulating layer is in contact with an upper surface and a lower surface of the kth semiconductor layer in a region that does not overlap with the pair of kth buffer layers; the third conductive layer has a portion located below the first semiconductor layer with the first insulating layer interposed therebetween, a portion located between the kth semiconductor layer and the (k+1)th semiconductor layer with the first insulating layer interposed therebetween, and a portion located above the nth semiconductor layer with the first insulating layer interposed therebetween. Semiconductor device. 　 a semiconductor layer, a pair of first and second buffer layers, a pair of first and second conductive layers, a third conductive layer, and a first insulating layer; the semiconductor layer is located above the pair of first buffer layers; the pair of second buffer layers are located above the semiconductor layer; the pair of first conductive layers are respectively located above the second buffer layer; the semiconductor layer has a side surface having a protruding portion that protrudes outward beyond a side surface of the first buffer layer and a side surface of the second buffer layer; the pair of second conductive layers are in contact with a side surface of the first conductive layer, side surfaces of the first and second buffer layers, and the protruding portion of the semiconductor layer, respectively; the first insulating layer contacts the upper and lower surfaces of the semiconductor layer in regions that do not overlap with the pair of first buffer layers; the third conductive layer has a portion located below the semiconductor layer with the first insulating layer interposed therebetween, and a portion located above the semiconductor layer with the first insulating layer interposed therebetween. Semiconductor device. 　 In claim 1, the first buffer layer has a first crystalline region in which a first crystal orientation is oriented substantially perpendicular to a surface of the first buffer layer; the first semiconductor layer has a second crystalline region in which a second crystal orientation is oriented approximately perpendicular to a surface of the first semiconductor layer; Semiconductor device. 　 In claim 2, the kth buffer layer has a first crystalline region in which a first crystal orientation is oriented substantially perpendicular to a surface of the kth buffer layer; the kth semiconductor layer has a second crystalline region in which a second crystal orientation is oriented approximately perpendicular to a surface of the kth semiconductor layer; Semiconductor device. 　 In claim 3, the first buffer layer has a first crystalline region in which a first crystal orientation is oriented substantially perpendicular to a surface of the first buffer layer; the semiconductor layer has a second crystalline region in which a second crystal orientation is oriented approximately perpendicular to a surface of the semiconductor layer; Semiconductor device. 　 In any one of claims 4 to 6, the first crystalline region has a hexagonal crystal structure, The second crystalline region has a cubic crystal structure. Semiconductor device. 　 In claim 7, the first crystal orientation is the [001] orientation; The second crystal orientation is the [111] orientation. Semiconductor device. 　 In any one of claims 4 to 6, the first crystalline region and the second crystalline region each have a cubic crystal structure; Semiconductor device. 　 In claim 9, The first crystal orientation and the second crystal orientation are a [111] orientation, a [100] orientation, or a [110] orientation, respectively. Semiconductor device. 　 In claim 1, the first insulating layer has a portion located between the third conductive layer and the first buffer layer, a portion located between the third conductive layer and the second buffer layer, and a portion located between the third conductive layer and the first conductive layer. Semiconductor device. 　 In claim 1, the first and second semiconductor layers each include a first metal oxide; the first to third buffer layers each contain a second metal oxide; the pair of second conductive layers each contain a third metal oxide; each of the first to third metal oxides contains indium; Semiconductor device. 　 In claim 12, the second metal oxide comprises gallium; the third metal oxide comprises tin; Semiconductor device.

2. The method according to claim 1, further comprising: forming a first insulating layer on the first insulating layer; forming a second insulating layer on the second insulating layer; the second insulating layer is located above the pair of first conductive layers and the third conductive layer; the fourth conductive layer is located above the second insulating layer; the third insulating layer covers the fourth conductive layer; the fifth conductive layer covers the fourth conductive layer via the third insulating layer; the connection electrode penetrates the second insulating layer and connects one of the pair of first conductive layers to the fourth conductive layer; Semiconductor device. 　 In claim 14, the fourth conductive layer has a columnar shape. Semiconductor device. 　 In claim 14, the third insulating layer includes an insulator exhibiting ferroelectricity; Semiconductor device. 　 In claim 14, the third insulating layer contains one or both of hafnium and zirconium; Semiconductor device.

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