Semiconductor device, pressure sensor device, fuel cell system, and method for manufacturing semiconductor device

Abstract

A semiconductor device (1) comprises: a semiconductor substrate (6); an integrated circuit (11) having a semiconductor element (7) formed on the semiconductor substrate (6), one or a plurality of interlayer insulation layers (8) laminated on the semiconductor element (7), and a metal wiring layer (9); a protective layer (12) provided to the integrated circuit (11); a first silicon compound layer (13) provided to the protective layer (12); a second silicon compound layer (14) provided to the first silicon compound layer (13); a second silicon compound layer (14) provided to the first silicon compound layer (13); and a third silicon compound layer (15) provided to the second silicon compound layer (14). A section of the metal wiring layer (9) is exposed through an electrode opening (5) that penetrates the protective layer (12), the first silicon compound layer (13), the second silicon compound layer (14), and the third silicon compound layer (15). A section of the protective layer (12) and the first silicon compound layer (13) on the electrode opening side thereof is covered by the second silicon compound layer (14).

Description

Semiconductor device, pressure sensor device, fuel cell system, and method for manufacturing semiconductor device

[0001] The present disclosure relates to a semiconductor device, a pressure sensor device, a fuel cell system, and a method for manufacturing a semiconductor device.

[0002] In semiconductor devices such as integrated circuits (ICs) that use semiconductor materials as substrates, silicon compound layers, for example, stacked structures of silicon oxide and silicon nitride films, are generally used as surface protective films. Silicon oxide and silicon nitride films as protective films play a role in protecting ICs from the external environment. Silicon nitride films fabricated by plasma-enhanced chemical vapor deposition (CVD) are particularly dense. Therefore, silicon nitride films are expected to have high environmental resistance, such as preventing moisture from penetrating into ICs from the outside and protecting ICs from metal contamination.

[0003] However, ICs protected by surface passivation films have many issues that need to be addressed. Among surface passivation films, silicon nitride films are expected to have high environmental resistance, but it is difficult for them to provide a complete barrier against gases such as water vapor. For example, it is known that nano- and micro-level defects and pinholes present in silicon nitride films reduce the barrier properties of silicon nitride films. These defects can allow moisture and other substances to penetrate into the IC. Moisture penetration from the outside into the IC can cause problems such as corrosion of the metal wiring layers inside the IC and moisture absorption by hygroscopic materials underneath the silicon nitride film.

[0004] Silicon oxide films are primarily used as interlayer insulating films in semiconductor devices to protect semiconductor elements and metal wiring layers. From the viewpoint of the heat resistance of metal materials used for wiring, tetraethyl orthosilicate (TEOS: Tetra Eth Oxy Silane) oxide films, which are produced by plasma CVD and have excellent insulating properties, are commonly used as insulating films that can be formed at low temperatures. Furthermore, TEOS oxide films, which have excellent step coverage, are sometimes used as surface protection films.

[0005] On the other hand, silicon oxide films used as interlayer insulating films or surface protective films are hygroscopic. It is known that moisture absorption, especially in TEOS oxide films, can cause expansion, compressive film stress, reduced hardness, or film cracking. If the barrier properties of the silicon nitride film provided on the top layer are insufficient, moisture penetration from the outside can cause the underlying silicon oxide film to absorb moisture. Moisture absorption by the silicon oxide film can cause compressive film stress or film cracking in the silicon oxide film, which can affect nearby semiconductor elements and metal wiring layers. In semiconductor devices used in environments containing water or water vapor, aging due to the influence of moisture can cause abnormalities in the characteristics of devices using the semiconductor device. In the worst case, this can cause failures such as wiring breakage, leading to serious device malfunctions.

[0006] By mounting a highly moisture-resistant semiconductor device on a device (e.g., a sensor device), the device can be used in harsh environments such as high humidity. The improved environmental resistance of a device leads to a wider range of uses for the device, and has the advantage of allowing the device to be mounted in flexible locations. A typical example of a sensor device that is mounted in a high-humidity environment and requires high accuracy is a pressure sensor device used in fuel cell systems such as those installed in fuel cell vehicles. To efficiently generate power in a fuel cell system, it is necessary to measure the amount of gas supplied to the fuel cell stack with high accuracy and control it so that it is neither too much nor too little before supplying the gas to the fuel cell stack. A pressure sensor device is used to control the gas, and high accuracy and high reliability are required of the pressure sensor device.

[0007] As efforts toward a decarbonized society progress, the market for fuel cell systems is expected to expand. With the future widespread use of fuel cell systems in mind, systems with high power generation efficiency are being developed. As one technology for improving power generation efficiency, a fuel return structure has attracted attention. This structure recirculates a portion of the gas not used in power generation (hereinafter referred to as fuel off-gas) back into the fuel cell for reuse in power generation. Recycling the fuel exhaust gas generated by fuel cell power generation increases the fuel utilization rate and improves power generation efficiency. However, fuel off-gas contains a relatively high moisture content because it passes through the fuel cell, which generates water. However, sensor devices incorporating conventional semiconductor devices are not intended for use in fuel cell systems, and therefore, sufficient measures have not been taken to address the environmental resistance issues of semiconductor devices.

[0008] When a pressure sensor device incorporating a conventional semiconductor device is used to measure the pressure of gas in the above-mentioned fuel cell system, the gas being measured contains moisture, and moisture absorption inside the semiconductor device affects the semiconductor elements and metal wiring layers, causing fluctuations in the electrical characteristics of the semiconductor device. As a result, the sensor device cannot maintain high accuracy. Because the accuracy of the sensor device is directly linked to the power generation efficiency of the fuel cell system, even slight fluctuations in characteristics due to the influence of moisture cannot be tolerated. Therefore, it is difficult for a sensor device incorporating a conventional semiconductor device to measure the pressure of a gas containing moisture with high accuracy.

[0009] A configuration has been disclosed in which moisture infiltrating from the outside is absorbed in a semiconductor device protected by a surface protection film, preventing it from reaching the inside of the IC (see, for example, Patent Document 1). The semiconductor device disclosed in Patent Document 1 has a three-layer structure in which a first silicon compound layer, an SOG (Spin On Glass)-SiO2 layer, and a second silicon compound layer are sequentially stacked. The water-absorbent SOG-SiO2 layer absorbs moisture that infiltrates from the outside, preventing the moisture from reaching the underlying first silicon compound layer and metal wiring layer.

[0010] Japanese Patent Application Publication No. 5-234991

[0011] As described above, preventing moisture absorption by the metal wiring layer and the hygroscopic interlayer insulating film and surface protective film of a semiconductor device is an important issue in improving the reliability of the semiconductor device. In the structure of the semiconductor device disclosed in Patent Document 1, the presence of a water-absorbent SOG-SiO2 layer below the second silicon compound layer can prevent a certain amount of moisture from penetrating into the lower layers.

[0012] Furthermore, with the recent trend toward smaller electronic devices and lower power consumption, it is becoming increasingly important to increase the precision of semiconductor devices such as ICs. Therefore, even a slight fluctuation in the electrical characteristics of an IC, even if it does not lead to a breakdown, can have a significant impact on device characteristics, making the effects of moisture and other factors an even greater problem.

[0013] In semiconductor devices whose surfaces are protected by moisture-resistant protective films, such as the disclosed semiconductor device, the surface protective film and interlayer insulating film are exposed to the outside on the side surfaces of the semiconductor device. Multiple semiconductor devices are manufactured on a wafer, which is a substrate of semiconductor material, and the semiconductor devices are separated into individual pieces by a dicing process. In the manufacture of semiconductor devices using semiconductor processes, the exposure of the surface protective film and interlayer insulating film to the outside is unavoidable. Furthermore, semiconductor devices have electrode openings that expose portions of metal wiring layers for electrical connection to the outside. When the surface protective film has a stacked structure, portions of all layers, including the underlying protective film, are exposed to the outside through the electrode openings. If the exposed layer is hygroscopic or moisture-permeable, moisture will penetrate into the semiconductor device through the exposed portions. Compared to the side surfaces of the dicing line regions where integrated circuits are not formed, the exposed portions of the electrode openings in the semiconductor chip regions where integrated circuits are formed are particularly susceptible to moisture penetration. Therefore, moisture penetration through the electrode openings to the inside of the semiconductor device fluctuates the electrical characteristics of the semiconductor device, impairing the accuracy and reliability of the device. Furthermore, when used in harsh environments and where high precision must be maintained, the impact of moisture infiltration through the exposed side surfaces of the surface protection film may become significant.

[0014] Semiconductor devices whose surfaces are protected by moisture-resistant protective films, such as the disclosed semiconductor device, aim to prevent device failure for a certain period of time in high-humidity environments, but do not provide measures to maintain high accuracy when electrode openings are formed. In electrode openings necessary for electrical connection to the outside through metal wiring layers, portions of all layers of the single-layer or multilayer protective film are exposed to the outside on the electrode opening side. When a silicon oxide film, such as a TEOS oxide film, is used as a protective film, which exhibits significant stress fluctuation due to moisture absorption, moisture absorption by the silicon oxide film through the exposed portions can cause fluctuations in the electrical characteristics of the semiconductor device, making it impossible to maintain high accuracy. Sensor devices and other devices incorporating semiconductor devices that cannot maintain high accuracy will experience reduced measurement reliability.

[0015] Therefore, an object of the present disclosure is to obtain a semiconductor device that has stable electrical characteristics, high accuracy, and high reliability even when used continuously in a high humidity environment.

[0016] The semiconductor device of the present disclosure includes a semiconductor substrate, a semiconductor element portion formed on a main surface, which is one surface of the semiconductor substrate, one or more interlayer insulating layers made of a silicon oxide film and stacked on the side of the semiconductor element portion opposite to the semiconductor substrate side, an integrated circuit portion connected to the semiconductor element portion and having metal wiring layers provided on the other side of the interlayer insulating layer, which is the side of the semiconductor element portion, and one side of the interlayer insulating layer opposite to the semiconductor element portion side, a protective layer made of a silicon oxide film and provided on the side of the integrated circuit portion opposite to the semiconductor substrate side, and a first silicon oxide film provided on the side of the protective layer opposite to the integrated circuit portion side. a compound layer, a second silicon compound layer provided on the side of the first silicon compound layer opposite to the protective layer side, and a third silicon compound layer provided on the side of the second silicon compound layer opposite to the first silicon compound layer side, wherein a portion of the metal wiring layer on one side of the interlayer insulating layer and adjacent to the protective layer is exposed through an electrode opening that penetrates the protective layer, the first silicon compound layer, the second silicon compound layer, and the third silicon compound layer, and portions of the protective layer and the first silicon compound layer on the side of the electrode opening are covered by the second silicon compound layer.

[0017] According to the semiconductor device of the present disclosure, there is provided a semiconductor substrate, an integrated circuit portion having a semiconductor element portion formed on a main surface of the semiconductor substrate, one or more interlayer insulating layers made of a silicon oxide film stacked on the semiconductor element portion, and a metal wiring layer connected to the semiconductor element portion, a protective layer made of a silicon oxide film and provided on the integrated circuit portion, a first silicon compound layer provided on the protective layer, a second silicon compound layer provided on the first silicon compound layer, and a third silicon compound layer provided on the second silicon compound layer, wherein a portion of the metal wiring layer on one side of the interlayer insulating layer and adjacent to the protective layer is exposed through an electrode opening that penetrates the protective layer, the first silicon compound layer, the second silicon compound layer, and the third silicon compound layer, and portions of the protective layer and the first silicon compound layer on the electrode opening side are covered by the second silicon compound layer, and therefore the hygroscopic protective layer is not exposed to the outside, and therefore it is possible to suppress moisture penetration into the semiconductor device. Since the penetration of moisture into the interior of the semiconductor device is suppressed, even if the semiconductor device is continuously used in a high humidity environment, the electrical characteristics are stabilized, and a semiconductor device with high precision and high reliability can be obtained.

[0018] FIG. 2 is a plan view schematically showing a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view showing an outline of the semiconductor device cut at the A-A cross section position of FIG. 1. FIG. 4 is a cross-sectional view showing an outline of the semiconductor device cut at the B-B cross section position of FIG. 1. FIG. 5 is a cross-sectional view showing an outline of another semiconductor device cut at the A-A cross section position of FIG. 1. FIG. 6 is a diagram showing a configuration of a pressure sensor device according to a first embodiment. FIG. 7 is a diagram showing a configuration of a fuel cell system according to a first embodiment. FIG. 8 is a diagram showing output fluctuations of a semiconductor device according to a first embodiment and a comparative example. FIG. 9 is a cross-sectional view showing an outline of a semiconductor device of a comparative example. FIG. 10 is a cross-sectional view showing an outline of a semiconductor device of a comparative example. FIG. 11 is a diagram showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 12 is a cross-sectional view showing an outline of a main part of a semiconductor device according to a second embodiment. FIG. 13 is a cross-sectional view showing an outline of a main part of a semiconductor device according to a third embodiment.

[0019] Hereinafter, a semiconductor device, a pressure sensor device, a fuel cell system, and a method for manufacturing a semiconductor device according to embodiments of the present disclosure will be described with reference to the drawings. Note that the same or equivalent members and parts in each drawing will be denoted by the same reference numerals.

[0020]

[0023] Fig. 1 is a plan view schematically showing a semiconductor device 1 according to a first embodiment, Fig. 2 is a cross-sectional view showing an outline of the semiconductor device 1 taken along the A-A cross section of Fig. 1, showing an electrode opening 5, Fig. 3 is a cross-sectional view showing an outline of the semiconductor device 1 taken along the B-B cross section of Fig. 1, showing a dicing line region 3 and a prevention wall formation region 4, Fig. 4 is a cross-sectional view showing an outline of another semiconductor device 1 taken along the A-A cross section of Fig. 1, showing an electrode opening 5, Fig. 5 is a diagram showing the configuration of a pressure sensor device 100 according to the first embodiment, Fig. 6 is a diagram showing the configuration of a fuel cell system 200 according to the first embodiment, Fig. 7 is a diagram showing the output fluctuations of the semiconductor device 1 according to the first embodiment and a comparative example, showing an example of the effect of the present disclosure, Fig. 8 is a cross-sectional view showing an outline of a semiconductor device 1a according to a comparative example, taken along the same position as Fig. 2, Fig. 9 is a cross-sectional view showing an outline of a semiconductor device 1b according to a comparative example, taken along the same position as Fig. 2, and Fig. 10 is a diagram showing a manufacturing process of the semiconductor device 1 according to the first embodiment. 3 also shows the area to be removed by dicing. The semiconductor device 1 of the present embodiment is an IC that is manufactured by a semiconductor process and can amplify, compensate, calibrate, and the like the sensor signal when used in combination with a sensor, for example.

[0021] <Structure of Semiconductor Device 1> The structure of the semiconductor device 1 will be described. The semiconductor device 1 includes, for example, an integrated circuit such as an operational amplifier that amplifies signals, and a non-volatile memory element such as an EEPROM (Electrically Erasable Programmable Read-Only Memory). When combined with a sensor, the semiconductor device 1 can process the sensor output. As shown in FIG. 1 , when viewed perpendicularly to a main surface 6a (not shown in FIG. 1 ) of a semiconductor substrate 6, the semiconductor substrate 6 includes a semiconductor chip region 2 in which an integrated circuit portion 11 (not shown in FIG. 1 ) is formed, a dicing line region 3 surrounding the semiconductor chip region 2, and a prevention wall formation region 4 provided in all or part of the space between the dicing line region 3 and the semiconductor chip region 2. In this embodiment, the prevention wall formation region 4 is provided in the entire space between the dicing line region 3 and the semiconductor chip region 2, but this is not limiting. The prevention wall forming region 4 may be provided partially between the dicing line region 3 and the semiconductor chip region 2 .

[0022] The semiconductor chip region 2 is a region where an integrated circuit portion 11 constituting a circuit used for each application of the semiconductor device 1 is formed. Multiple semiconductor chip regions 2 are formed on the wafer. The dicing line region 3 is located between the semiconductor chip region 2 and the semiconductor chip regions 2 of multiple adjacent semiconductor devices 1 in the wafer state. The semiconductor device 1 is a die chip having the semiconductor chip region 2, a prevention wall formation region 4, and a dicing line region 3. The semiconductor device 1 has multiple electrode openings 5 ​​in the semiconductor chip region 2, exposing portions of the metal wiring layer 9 (not shown in FIG. 1 ) for electrical connection to the outside. The number and positions of the electrode openings 5 ​​shown in FIG. 1 are merely examples and are not limited thereto. The number of electrodes required for external connection varies depending on the arrangement of electrodes for prior confirmation of the electrical characteristics of the semiconductor device 1, etc. The number and positions of the electrode openings 5 ​​may be freely determined depending on the design of the optimal electrode position taking into account simplification of manufacturing processes such as wire bonding.

[0023] 2, the semiconductor device includes a semiconductor substrate 6, a semiconductor element portion 7 formed on a main surface 6a of the semiconductor substrate 6, one or more interlayer insulating layers 8 made of silicon oxide films stacked on the side of the semiconductor element portion 7 opposite the semiconductor substrate 6, an integrated circuit portion 11 connected to the semiconductor element portion 7 and having metal wiring layers 9 provided on a portion of each interlayer insulating layer 8 on the other side facing the semiconductor element portion 7 and on one side facing the semiconductor element portion 7, a protective layer 12 made of silicon oxide film and provided on the side of the integrated circuit portion 11 opposite the semiconductor substrate 6, a first silicon compound layer 13 provided on the side of the protective layer 12 opposite the integrated circuit portion 11, a second silicon compound layer 14 provided on the side of the first silicon compound layer 13 opposite the protective layer 12, and a third silicon compound layer 15 provided on the side of the second silicon compound layer 14 opposite the first silicon compound layer 13. The semiconductor substrate 6 is, for example, a single-crystal silicon substrate. In this embodiment, a protective layer 12, a first silicon compound layer 13, a second silicon compound layer 14, and a third silicon compound layer 15 are provided in the semiconductor device 1 as surface protective films covering the integrated circuit portion 11. The semiconductor element portion 7 has a semiconductor element, an insulating layer, and a contact layer. The semiconductor element (not shown) and the metal wiring layer 9 are connected by a contact layer (not shown). Adjacent metal wiring layers 9 are connected by a contact layer 10. Although two interlayer insulating layers 8 are provided in FIG. 2, the number of interlayer insulating layers 8 is not limited to this.

[0024] Comparative Example 1 Prior to describing the surface protective film of the present disclosure, Comparative Example 1 will be described with reference to Fig. 8. The semiconductor device 1a shown in Fig. 8 has, as surface protective films, a silicon oxide film which is a protective layer 12 and a silicon nitride film which is a first silicon compound layer 13. The configuration of the integrated circuit unit 11 of the semiconductor device 1a is similar to the configuration of the integrated circuit unit 11 of the semiconductor device 1 shown in Fig. 2. A silicon oxide film and a silicon nitride film are stacked on the integrated circuit unit 11, and the integrated circuit unit 11 is protected by two layers of surface protective films.

[0025] However, it is difficult to avoid the formation of nano- and micro-level defects and pinholes in inorganic films such as silicon nitride films. Therefore, gases such as water vapor penetrate into the interior of the semiconductor device 1a through these defects. When moisture penetrates, the silicon oxide film, interlayer insulating layer 8, and insulating layer 16 (not shown), which are formed below the silicon nitride film, absorb moisture. Moisture absorption by the silicon oxide film causes the silicon oxide film to expand, generate compressive film stress, and crack, affecting the adjacent semiconductor element portion 7 and metal wiring layer 9. Moisture penetration into the interior of the semiconductor device 1a can prevent the semiconductor device 1a from maintaining high precision and may ultimately lead to failure. Therefore, in environments such as high humidity, the two-layer surface protection film structure shown in Comparative Example 1 is insufficient to protect the interior of the semiconductor device 1a from the external environment.

[0026] <Surface Protective Film of Semiconductor Device 1> The surface protective film of semiconductor device 1 will now be described. In this embodiment, as shown in FIG. 2 , four layers, namely, a protective layer 12, a first silicon compound layer 13, a second silicon compound layer 14, and a third silicon compound layer 15, are provided on semiconductor device 1 as a surface protective film covering integrated circuit portion 11. By providing second silicon compound layer 14 in addition to the two layers, protective layer 12 and first silicon compound layer 13, shown in Comparative Example 1, defects such as pinholes formed in the underlying first silicon compound layer 13 can be sealed. By sealing the defects, a path for gases such as water vapor to pass through is eliminated, thereby improving the environmental resistance of semiconductor device 1. Furthermore, by forming third silicon compound layer 15 on second silicon compound layer 14, semiconductor device 1 with excellent performance in terms of barrier properties against the external environment can be obtained.

[0027] The first silicon compound layer 13, the second silicon compound layer 14, and the third silicon compound layer 15 can be easily and accurately formed in a film formation step of a semiconductor process. The film types of these silicon compound layers include SiN, SiON, SiO, SiOC, etc. The film type combination and the stacking order can be designed arbitrarily.

[0028] In this embodiment, the first silicon compound layer 13 and the third silicon compound layer 15 are silicon nitride films. Because the third silicon compound layer 15, formed on the outermost surface, is likely to be exposed to the external environment, the third silicon compound layer 15 is made of a silicon nitride film, which has the highest moisture resistance compared to other materials, thereby achieving a semiconductor device 1 with excellent moisture resistance and environmental resistance. Furthermore, the protective layer 12, which is made of a silicon oxide film and has moisture absorption properties, is provided below the first silicon compound layer 13. If the protective layer 12 absorbs moisture, problems may occur in the integrated circuit portion 11. By using a silicon nitride film, which has the highest moisture resistance compared to other materials, for the first silicon compound layer 13 covering the protective layer 12, moisture absorption by the protective layer 12 can be suppressed. Since moisture absorption by the protective layer 12 is suppressed, problems in the integrated circuit portion 11 are suppressed, resulting in stable electrical characteristics and a semiconductor device 1 with high precision and reliability.

[0029] In this embodiment, the second silicon compound layer 14 is a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbide film. It is desirable to select a film type different from that of the first silicon compound layer 13 for the second silicon compound layer 14 covering the first silicon compound layer 13. By using different film types for the upper and lower layers, even if defects are formed in the upper and lower layers, the defects can be separated (i.e., continuous defect growth can be suppressed). Since the defects are separated, a distance is created between the defects in the lower layer and the defects in the upper layer, thereby improving the moisture resistance of the semiconductor device 1. Furthermore, as will be described later, a portion of the second silicon compound layer 14 is exposed to the outside on the side of the electrode opening 5. Therefore, it is preferable to use a non-hygroscopic silicon oxynitride film or a silicon oxycarbide film for the second silicon compound layer 14. Silicon oxynitride films and silicon oxycarbide films are known to have high moisture resistance, similar to silicon nitride films.

[0030] Comparative Example 2 Prior to describing the electrode opening 5, which is a key feature of the present disclosure, Comparative Example 2 will be described with reference to FIG. 9 . The configuration of the integrated circuit unit 11 of Comparative Example 2 is similar to that of the integrated circuit unit 11 of the semiconductor device 1 shown in FIG. 2 . Comparative Example 2 differs from the configuration of the semiconductor device 1 shown in FIG. 2 in the configuration of the electrode opening 5. The semiconductor device 1 and the semiconductor device 1b each have an electrode opening 5 that exposes a portion of the metal wiring layer 9, for example, to connect an external sensor device to the integrated circuit unit 11 and to extract electrical signals output from the semiconductor device 1 and the semiconductor device 1b to the outside. The metal wiring layer 9 is configured as a multilayer wiring, and a portion of the uppermost metal wiring layer 9 of the multilayer wiring is exposed in the electrode opening 5. The electrode opening 5 can generally be easily and accurately formed by removing the surface protection film covering the metal wiring layer 9 through an etching process in a semiconductor process after the formation of the top surface protection film.

[0031] The electrode opening 5 shown in FIG. 9 has a structure formed by applying a typical etching process in semiconductor manufacturing. The electrode opening 5 is formed by etching the third silicon compound layer 15, which is the outermost surface protective film, until a portion of the metal wiring layer 9 is exposed. Because the surface protective film has a stacked structure, the portion of the protective layer 12, which is made of the second silicon compound layer 14, the first silicon compound layer 13, and a silicon oxide film formed below the third silicon compound layer 15, on the side of the electrode opening 5 is exposed to the outside. Because many electrode openings 5 ​​are formed in the semiconductor chip region 2, the exposed portions of the surface protective film in the electrode opening 5 have a significant impact. The exposed portions of the surface protective film in the electrode opening 5 serve as paths for moisture and other elements to penetrate into the semiconductor device 1b, causing moisture absorption in the protective layer 12, the interlayer insulating layer 8, and the insulating layer 16. Moisture absorption by a hygroscopic film can, for example, change film stress, resulting in a piezoelectric effect, which affects the semiconductor element region 7 and the metal wiring layer 9, thereby fluctuating the electrical characteristics of the semiconductor device 1b. If the electrical characteristics of the semiconductor device 1b fluctuate, the semiconductor device 1b will no longer be able to maintain high precision, and the reliability of a device incorporating the semiconductor device 1b will decrease.

[0032] <Structure of Electrode Opening 5> The structure of the electrode opening 5, which is a key feature of the present disclosure, will be described with reference to FIG. 2 . A portion of the metal wiring layer 9 adjacent to the protective layer 12 on one side of the interlayer insulating layer 8 is exposed through the electrode opening 5 penetrating the protective layer 12, the first silicon compound layer 13, the second silicon compound layer 14, and the third silicon compound layer 15. The portions of the protective layer 12 and the first silicon compound layer 13 on the electrode opening 5 side are covered by the second silicon compound layer 14. This configuration prevents the hygroscopic protective layer 12 from being exposed to the outside, thereby preventing moisture from penetrating into the semiconductor device 1. The moisture resistance of the semiconductor device 1 having multiple electrode openings 5 ​​is improved, resulting in stable electrical characteristics and a highly accurate and reliable semiconductor device 1, even when the semiconductor device 1 is continuously used in a high-humidity environment. As will be described later, the electrode opening 5 shown in FIG. 2 can be easily formed by combining the film formation and etching steps of the semiconductor process without significantly modifying the configuration shown in FIG. 8 , eliminating the need for complex processing or advanced technology. Therefore, a highly reliable semiconductor device 1 can be easily obtained without deteriorating production efficiency or significantly increasing material and manufacturing costs.

[0033] <Structure of Prevention-Wall Formation Region 4> The structure of the prevention-wall formation region 4 of the present disclosure will be described with reference to FIG. 3 . When the semiconductor device 1 is separated into individual pieces in the dicing process, the protective layer 12, the interlayer insulating layer 8, the insulating layer 16, and the like are exposed to the outside on the side surfaces of the semiconductor device 1. The exposed portions of the side surfaces of the semiconductor device 1 are formed in the dicing line region 3, which is a certain distance from the semiconductor element portion 7 and the metal wiring layer 9. Therefore, even if moisture penetrates into the semiconductor device 1 through the exposed portions of the side surfaces, it is expected that the impact on the electrical characteristics of the semiconductor device 1 will be relatively small. However, when the semiconductor device 1 is required to maintain high precision for a long period of time when used in a harsh environment, the impact of the exposed portions of the side surfaces may become significant.

[0034] In this embodiment, the prevention-wall-forming region 4 is provided with an insulating layer 16 formed on the main surface 6a and one or more interlayer insulating layers 8 stacked on the side of the insulating layer 16 opposite the semiconductor substrate 6 side. An exposure prevention wall 4a for protecting the semiconductor chip region 2 from the surroundings is formed on the insulating layer 16 and the one or more interlayer insulating layers 8 in the prevention-wall-forming region 4. The side of the exposure prevention wall 4a opposite the semiconductor substrate 6 side is covered with a protective layer 12, a first silicon compound layer 13, a second silicon compound layer 14, and a third silicon compound layer 15 in this order in the direction away from the semiconductor substrate 6. The portions of the protective layer 12 and the first silicon compound layer 13 closer to the dicing line region 3 than the exposure prevention wall 4a are covered with the second silicon compound layer 14. Although two interlayer insulating layers 8 are provided in FIG. 3 , the number of interlayer insulating layers 8 is not limited thereto.

[0035] With this configuration, the hygroscopic protective layer 12 is not exposed to the outside on the side of the dicing line region 3, thereby suppressing moisture penetration into the interior of the semiconductor device 1. Since moisture penetration into the interior of the semiconductor device 1 is suppressed, the moisture resistance of the semiconductor device 1 having the dicing line region 3 is improved, and therefore, even when the semiconductor device 1 is continuously used in a high humidity environment, the electrical characteristics are stabilized, and a semiconductor device with high precision and high reliability can be obtained.

[0036] The structure of the exposure prevention wall 4a will be described. In this embodiment, in the prevention-wall-forming region 4, peripheral metal wiring layers 9a, 9b, and 9c are provided in a portion of each interlayer insulating layer 8 on the other side thereof, which is on the insulating layer 16 side, and on one side thereof opposite to the insulating layer 16 side, and extend in the direction in which the prevention-wall-forming region 4 extends, first contact layers 10a and 10b penetrating the interlayer insulating layer 8 to connect adjacent peripheral metal wiring layers 9a, 9b, and 9c, and a second contact layer 10c penetrating the insulating layer 16 to connect the main surface 6a of the semiconductor substrate 6 and the peripheral metal wiring layer 9c, thereby forming the exposure prevention wall 4a. In the configuration shown in Figure 3, two interlayer insulating layers 8 are provided and outer peripheral metal wiring layers 9a, 9b, and 9c are formed, so that as first contact layers, a first contact layer 10a connecting the outer peripheral metal wiring layer 9a and the outer peripheral metal wiring layer 9b, and a first contact layer 10b connecting the outer peripheral metal wiring layer 9b and the outer peripheral metal wiring layer 9c are provided.

[0037] In this manner, the exposure prevention wall 4a is formed by sequentially forming first contact layers 10a, 10b, a second contact layer 10c, and peripheral metal wiring layers 9a, 9b, and 9c on the semiconductor substrate 6. Ideally, the number of peripheral metal wiring layers of the exposure prevention wall 4a should match the number of layers of the metal wiring layer 9 formed in multiple layers in the semiconductor chip region 2. The multiple peripheral metal wiring layers 9a, 9b, and 9c are connected to each other by the first contact layers 10a, 10b, forming a continuous wall perpendicular to the main surface 6a. By configuring the exposure prevention wall 4a in this manner, moisture penetration into the semiconductor chip region 2 from the exposed side surfaces of the semiconductor device 1 can be suppressed. Since moisture penetration into the semiconductor chip region 2 is suppressed, the moisture resistance of the semiconductor device 1 with its side surfaces exposed to the outside can be improved. The improved moisture resistance of the semiconductor device 1 allows for the production of a semiconductor device 1 that maintains high precision. Furthermore, since the exposure prevention wall 4a is formed by the first contact layers 10a, 10b, the second contact layer 10c, and the outer metal wiring layers 9a, 9b, 9c, there is no need to increase the number of materials or manufacturing steps, so a semiconductor device 1 can be obtained that is inexpensive and maintains high reliability.

[0038] The greater the number of first contact layers 10a, 10b connecting the peripheral metal wiring layers 9a, 9b, 9c and the greater the number of second contact layers 10c connecting the peripheral metal wiring layers 9c and the semiconductor substrate 6, the greater the effectiveness in preventing moisture penetration into the semiconductor chip region 2. On the other hand, increasing the number of these contact layers increases the width of the peripheral metal wiring layers 9a, 9b, 9c, thereby necessitating an increase in the size of the semiconductor device 1. Therefore, it is preferable to arrange multiple first contact layers and second contact layers within a range that does not require a change in the size of the semiconductor device 1. Furthermore, these contact layers may be formed at the same position perpendicular to the main surface 6a. However, if the peripheral metal wiring layer connected to the contact layer has a stepped shape, the contact layer may be formed on the flat portion of the peripheral metal wiring layer, offset from the stepped portion, taking into account the stepped shape of the peripheral metal wiring layer on the contact layer. Furthermore, to maximize the moisture resistance effect, it is preferable to form the exposure prevention wall 4a continuously around the periphery of the semiconductor chip region 2.

[0039] <Pressure Sensor Device 100> A representative example of a sensor device incorporating the semiconductor device 1 is a pressure sensor device 100 used in a fuel cell system of a type mounted on a fuel cell vehicle or the like. The pressure sensor device 100 will be described with reference to FIG. 5 . The pressure sensor device 100 includes the semiconductor device 1 configured as described above and a semiconductor pressure sensor 50 connected to the semiconductor device 1. The semiconductor pressure sensor 50 is, for example, a piezo-resistive semiconductor pressure sensor, but is not limited to the piezo-resistive type and may be of another type. The semiconductor pressure sensor 50 of this embodiment is a pressure sensor that utilizes the piezo-resistive effect of piezo-resistance formed on a silicon diaphragm (pressure-receiving portion). Piezo-resistive semiconductor pressure sensors are characterized by their small size, high sensitivity, and high accuracy. A Wheatstone bridge 51 is formed by the piezo-resistance, and a sensor signal (output potential difference) proportional to pressure can be obtained from the Wheatstone bridge 51.

[0040] The pressure of gases such as air (oxygen) or hydrogen can be accurately measured by amplifying, compensating, and calibrating the sensor signal output from the semiconductor pressure sensor 50 using the semiconductor device 1. By using the semiconductor device 1 having improved moisture resistance as described above as the semiconductor device to which the semiconductor pressure sensor 50 is connected, the electrical characteristics can be stabilized even when the pressure sensor device 100 is continuously used in a high humidity environment, resulting in a pressure sensor device 100 with high accuracy and reliability.

[0041] <Fuel Cell System 200> The fuel cell system 200 will be described with reference to FIG. 6 . The fuel cell system 200 includes the pressure sensor device 100 configured as described above and a fuel cell 150 connected to the pressure sensor device 100 and controlling power generation based on the fuel gas supply pressure detected by the pressure sensor device 100. One example of the fuel cell system 200 is a fuel recirculation structure designed to improve power generation efficiency. By recirculating a portion of the fuel off-gas into the fuel cell 150 and reusing the fuel off-gas for power generation, the fuel utilization rate is increased, thereby improving the power generation efficiency of the fuel cell system 200. However, since the fuel off-gas passes through the fuel cell 150, which generates water, it contains a relatively large amount of moisture. For efficient power generation by the fuel cell system 200, it is important to accurately measure the pressure of the gas, including the fuel off-gas. This requires a pressure sensor device 100 that can maintain high accuracy even in a high-humidity environment.

[0042] By using the pressure sensor device 100 equipped with the semiconductor device 1 having the above-described configuration and high moisture resistance in the fuel cell system 200, it becomes possible to measure the pressure of gas including fuel off-gas with high accuracy, thereby achieving an improvement in the power generation efficiency of the fuel cell system 200.

[0043] <Moisture Resistance of Semiconductor Device 1> The moisture resistance of the semiconductor device 1 will be described with reference to FIG. 7 . To evaluate moisture resistance in environmental reliability tests for electronic devices, a PCT (Pressure Cooker Test) under saturated conditions is used. The PCT is a testing method that can evaluate the impact of moisture penetration into a test sample by significantly increasing the water vapor pressure in a test chamber relative to the water vapor partial pressure inside the test sample. To demonstrate an example of the effect of the semiconductor device 1 according to the first embodiment of the present disclosure, the output fluctuation amount of the semiconductor device 1 due to the PCT was evaluated. The semiconductor device 1 according to the first embodiment of the present disclosure and a semiconductor device 1a shown as Comparative Example 1 were placed in the PCT test chamber. As described above, the semiconductor device 1a shown in FIG. 8 , which is a test sample, has a two-layer surface protective film including a silicon oxide film and a silicon nitride film stacked thereon.

[0044] The PCT test conditions were a temperature of 121°C, humidity of 100%, and pressure of 202.6 kPa. Each test sample was removed from the PCT test chamber after 300, 500, 750, 1000, and 1500 hours of PCT testing, and their electrical characteristics were evaluated. The electrical characteristics of the semiconductor devices 1 and 1a were measured while electrically connected to the semiconductor pressure sensor 50. The output voltage of the pressure sensor device 100 equipped with the semiconductor device 1 and 1a obtained before the start of the PCT was defined as the initial value, and the difference between the output voltage of the pressure sensor device 100 equipped with the semiconductor device 1 and 1a after each PCT test time and the initial value was defined as the output fluctuation due to the PCT.

[0045] FIG. 7 shows the PCT results for semiconductor device 1 according to the first embodiment of the present disclosure and semiconductor device 1a according to Comparative Example 1. Approximately 20 samples were tested for each test, and the maximum output fluctuations due to PCT are shown in FIG. 7 . The allowable range of output fluctuations due to PCT is indicated by the dashed line in the electrical characteristics shown in FIG. 7 . For semiconductor device 1a with a two-layer surface protective film, the output fluctuations due to PCT exceeded the allowable range after 300 hours of PCT testing. As can be seen from FIG. 7 , the output fluctuations due to PCT increased with increasing test time. Experiments have confirmed that the output fluctuations due to PCT for semiconductor device 1a are very small even after high-temperature testing (at 140°C), suggesting that the influence of moisture intrusion is likely the primary cause of the output fluctuations due to PCT. On the other hand, for semiconductor device 1 according to the first embodiment of the present disclosure, the output fluctuations due to PCT were very small even after 1500 hours of PCT testing, demonstrating high accuracy. The pressure sensor device 100 equipped with the semiconductor device 1 according to embodiment 1 of the present disclosure does not have an output that fluctuates due to PCT, and therefore the pressure sensor device 100 can maintain high-precision measurements even when used in a high-humidity environment such as a fuel cell system 200.

[0046] <Method for Manufacturing Semiconductor Device 1> A method for manufacturing the semiconductor device 1 will be described with reference to Fig. 10. A plurality of semiconductor devices 1 are simultaneously manufactured using a semiconductor process on a wafer, which is a semiconductor substrate such as a single crystal silicon substrate. The method for manufacturing the semiconductor device 1 shown in the first embodiment includes a member preparation step (S11), a semiconductor element portion formation step (S12), a multilayer metal wiring formation step (S13), a first protective film formation step (S14), a first electrode opening formation step (S15), a second protective film formation step (S16), a second electrode opening formation step (S17), and a dicing step (S18).

[0047] First, an overview of each step will be described. The member preparation step is a step of preparing a semiconductor substrate 6. The semiconductor element portion formation step is a step of forming a plurality of semiconductor element portions 7 on a main surface 6a, which is one surface of the semiconductor substrate 6. The multilayer metal wiring formation step is a step of forming one or more interlayer insulating layers 8 made of silicon oxide film on the side of the semiconductor element portion 7 opposite the semiconductor substrate 6 side, and a metal wiring layer 9 connected to the semiconductor element portion 7, on the other side of the interlayer insulating layer 8 that is the semiconductor element portion 7 side and on one side opposite the semiconductor element portion 7 side. The first protective film formation step is a step of forming a protective layer 12 made of silicon oxide film on the side of the integrated circuit portion 11 formed from the semiconductor element portion 7, the interlayer insulating layer 8, and the metal wiring layer 9 opposite the semiconductor substrate 6 side, and further forming a first silicon compound layer 13 on the protective layer 12 opposite the integrated circuit portion 11 side.

[0048] The first electrode opening forming step is a step of penetrating the protective layer 12 and the first silicon compound layer 13 to expose a portion of the metal wiring layer 9 adjacent to the protective layer 12, thereby forming the electrode opening 5. The second protective film forming step is a step of forming a second silicon compound layer 14 on the portion of the first silicon compound layer 13 opposite to the protective layer 12 side, the portion of the first silicon compound layer 13 exposed on the electrode opening 5 side, the portion of the protective layer 12 exposed on the electrode opening 5 side, and the metal wiring layer 9 exposed in the electrode opening 5, and further forming a third silicon compound layer 15 on the side of the second silicon compound layer 14 opposite to the semiconductor substrate 6 side.

[0049] The second electrode opening formation step is a step of penetrating the second silicon compound layer 14 and the third silicon compound layer 15 to expose a portion of the metal wiring layer 9 exposed in the first electrode opening formation step, thereby forming an electrode opening 5. The dicing step is a step of cutting the dicing line regions 3 surrounding each of the semiconductor chip regions 2 in which the integrated circuit portions 11 are formed, to separate the semiconductor chip regions 2 into individual semiconductor chip regions 2. Through these steps, the semiconductor device 1 is manufactured, and the portions of the protective layer 12 and the first silicon compound layer 13 on the side of the electrode opening 5 are covered with the second silicon compound layer 14.

[0050] 2 in this manner, the semiconductor device 1 in which the hygroscopic protective layer 12 is not exposed to the outside can be easily manufactured without using complex processing or advanced technology, and without deteriorating production efficiency. Furthermore, the semiconductor device 1 can be easily manufactured with high precision and high reliability without significantly increasing material and manufacturing costs.

[0051] Next, each step will be described in detail. In the semiconductor element portion formation step, semiconductor elements such as transistors are formed on the main surface 6a of the semiconductor substrate 6 by repeating semiconductor processes such as thermal oxidation, film formation, lithography using photoresist, etching, and ion implantation. A technique such as the local oxidation of silicon (LOCOS) method is used for element isolation. An insulating layer made of a silicon oxide film is formed on the semiconductor elements. The insulating layer is planarized by reflowing it at high temperature. To achieve even higher flatness, chemical mechanical polishing (CMP) may be used in combination. To raise the electrodes of the semiconductor elements above the insulating layer, contact holes are opened in the insulating layer, and a contact layer is formed by filling the contact holes with tungsten or the like. The semiconductor element portion 7 is formed from the semiconductor elements, the insulating layer, and the contact layer.

[0052] In the multilayer metal wiring formation process, metal wiring layers 9 and interlayer insulating layers 8 are formed in multiple layers, and as shown in FIG. 2 , upper and lower metal wiring layers 9 are connected to each other by contact layers 10. The contact layers 10 are electrodes connecting the upper and lower metal wiring layers 9. The contact layers 10 are formed by contact holes formed in the interlayer insulating layers 8 between the metal wiring layers 9 and by metals such as tungsten embedded in the contact holes. As an example of multilayer metal wiring, the semiconductor device 1 according to the first embodiment of the present disclosure has three metal wiring layers 9. The metal wiring layers 9 made of Al, Cu, AlCu, AlSiCu, or the like for connection to the semiconductor element portion 7 are formed on the contact layers of the semiconductor element portion 7 and on the insulating layer 16.

[0053] Metal films made of Ta, Ti, TaN, TiN, or the like may be formed as barrier metals on the upper and lower layers of the metal wiring layer 9. After patterning the metal wiring layer 9 by lithography and etching, an interlayer insulating layer 8 is formed on the metal wiring layer 9. For the interlayer insulating layer 8, a TEOS oxide film or the like fabricated by plasma CVD is used as an insulating film that can be formed at low temperatures, taking into account the heat resistance of the metal material used for the wiring. While the TEOS oxide film has excellent insulating properties, moisture absorption can cause expansion, compressive film stress, and film cracking. After forming the interlayer insulating layer 8, CMP may be used for planarization. Contact holes are formed in the interlayer insulating layer 8 by lithography and etching, and a metal such as tungsten is filled into the contact holes to form the contact layer 10. Furthermore, a metal wiring layer 9 is formed on the contact layer 10 and the interlayer insulating layer 8. By repeating the above-described process, a multilayer metal wiring is formed.

[0054] The exposure prevention wall 4a is formed by a multilayer metal wiring formation process in a prevention wall formation region 4 provided in all or part of the area between the dicing line region 3 and the semiconductor chip region 2. The exposure prevention wall 4a is a dummy wiring pattern that is not used in the circuit in the integrated circuit portion 11. The exposure prevention wall 4a is a wall that is separated from the circuit provided in the semiconductor device 1 and serves to prevent the intrusion of moisture and the like from the outside.

[0055] In the first protective film forming process, the first electrode opening forming process, the second protective film forming process, and the second electrode opening forming process, a surface protective film is formed to protect the surface of the integrated circuit portion 11, and an electrode opening 5 is formed to expose a portion of the metal wiring layer 9 in order to connect to the pressure sensor device 100 and to extract the electrical signal output from the semiconductor device 1 to the outside.

[0056] The semiconductor device 1a shown in FIG. 8 as Comparative Example 1 includes a protective layer 12 made of a silicon oxide film and a first silicon compound layer 13 as surface protective films. The protective layer 12 is made of a TEOS oxide film or the like fabricated by plasma CVD, and the first silicon compound layer 13 is made of a silicon nitride film or the like fabricated by plasma CVD, which has high environmental resistance. The electrode opening 5 is formed by lithography and etching, exposing a portion of the uppermost metal wiring layer 9 of the multilayer wiring. At the same time, a portion of the protective layer 12 is exposed on the side of the electrode opening 5. Simultaneously with the formation of the electrode opening 5, portions of the first silicon compound layer 13 and the protective layer 12 around the dicing line region 3 may be removed.

[0057] 7, the evaluation results of the output fluctuation amount by PCT for the semiconductor device 1a of Comparative Example 1 reveal that in a configuration with a two-layer surface protective film, the characteristics of the semiconductor device 1a fluctuate due to the influence of moisture penetrating into the semiconductor device 1a. Possible routes of penetration of external moisture are defects formed in the first silicon compound layer 13 and exposed portions of the protective layer 12 at the electrode openings 5. When the surface protective film on the protective layer 12 is a single-layer first silicon compound layer 13, nano- and micro-level defects and pinholes present in inorganic films such as silicon nitride films can reduce moisture-proofing performance.

[0058] Furthermore, the two-layer surface protective film structure is affected by the shape of the recesses and protrusions in the lower layer. The lower layer of the surface protective film is formed by a metal wiring layer 9 and an interlayer insulating layer 8, forming steps. Multiple corners of the steps are formed, and a protective layer 12 is formed on the corners of the steps. When a surface protective film is formed by plasma CVD, the surface protective film inherits the step shape of the lower layer, resulting in the formation of recesses and protrusions in the surface protective film. The corners of the steps are prone to poor film adhesion during film formation by plasma CVD, and voids may form in the early stages of film formation. If gaps form continuously starting from the initially formed voids, they become through-holes that penetrate to the outermost surface of the surface protective film. Even if through-holes are not formed, the surface protective film at the corners of the steps may become sparse, potentially reducing its moisture-proofing performance. Moisture penetrates from the outside through the through holes in the surface protection film formed at the corners of such steps and through the portions where the film is thin, causing the insulating layer 16 inside the semiconductor device 1a to absorb moisture.

[0059] When the protective film and insulating film inside the semiconductor device 1a absorb moisture, expansion, compressive film stress, film cracking, etc. occur in the protective film and insulating film. As an example of the effects of moisture absorption, the stress change due to PCT of a single-layer silicon oxide film and a single-layer silicon nitride film was evaluated. A test sample in which a TEOS oxide film (0.5 μm thick) was formed on a single-crystal silicon substrate by plasma CVD, and a test sample in which a silicon nitride film (0.5 μm thick) was formed on a single-crystal silicon substrate by plasma CVD, were each placed in a PCT test chamber for a test time of 300 hours. As a result, the stress change of the silicon nitride film test sample was −4.5 MPa. On the other hand, it was experimentally confirmed that the stress change of the TEOS oxide film test sample was −164.0 MPa, which is two orders of magnitude lower than that of the silicon nitride film. The stress change evaluation results indicate that film stress changes due to moisture absorption in the protective film and insulating film of the semiconductor device 1a. For example, a change in film stress causes a piezoelectric effect, which affects the semiconductor element portion 7 and the metal wiring layer 9, causing the electrical characteristics of the semiconductor device 1a to fluctuate.

[0060] In this embodiment, a second silicon compound layer 14 is formed on the first silicon compound layer 13, and a third silicon compound layer 15 is further formed on the second silicon compound layer 14. By stacking the surface protective films, the moisture-proof performance of the semiconductor device 1 can be improved.

[0061] The second silicon compound layer 14 may be formed by spin coating using an SOG-SiO2 film mainly composed of silicon and oxygen, or an SOG-SiOC film mainly composed of silicon, oxygen, and carbon. Alternatively, the second silicon compound layer 14 may be formed by plasma CVD using an SiN film, SiON film, SiOC film, or SiO2 film. The third silicon compound layer 15 may be formed by plasma CVD using an SiN film, SiON film, SiOC film, or SiO2 film. Because the third silicon compound layer 15 is likely to be exposed to the external environment, it is preferable to use an SiN film or SiON film formed by plasma CVD, which has high environmental resistance.

[0062] In this embodiment, the second silicon compound layer 14 is an SOG film, and is formed by spin coating in the second protective film formation step. FIG. 2 shows a structure in which the second silicon compound layer 14 is formed by spin coating. In the semiconductor device 1 shown in FIG. 2 , a protective layer 12 and a first silicon compound layer 13 are formed as surface protective films, and then an electrode opening 5 is formed by lithography and etching in the first electrode opening formation step. As shown in FIG. 3 , simultaneously with the formation of the electrode opening 5, the protective layer 12 and the first silicon compound layer 13 are removed from the periphery of the dicing line region 3 and the region outside the exposure prevention wall 4 a. Then, a second silicon compound layer 14 (SOG film) is formed on the first silicon compound layer 13 by spin coating, and a third silicon compound layer 15 is formed on the second silicon compound layer 14. Before forming the third silicon compound layer 15, a heat treatment may be performed to remove adsorbed components, such as moisture, from the atmospheric environment of the second silicon compound layer 14.

[0063] By using an SOG film for the second silicon compound layer 14, even if defects or pinholes are formed in the first silicon compound layer 13, the defects or pinholes can be filled with the SOG film because the material of the SOG film formed by spin coating is liquid. Since the defects or pinholes in the first silicon compound layer 13 are filled with the SOG film, the infiltration path of moisture and the like can be blocked, thereby improving the moisture resistance of the semiconductor device 1. Furthermore, the second silicon compound layer 14 formed by spin coating reduces (flattens) the shape of the corners of steps, which are a weak point in film formation by plasma CVD, and the third silicon compound layer 15 formed by plasma CVD becomes dense, thereby maximizing the moisture-proof performance of the semiconductor device 1.

[0064] The optimal thickness of the second silicon compound layer 14 formed by spin coating varies depending on the height of the step on the outermost surface of the semiconductor device 1 before the second silicon compound layer 14 is formed. The second silicon compound layer 14 is preferably formed to a thickness ranging from approximately 0.1 μm to the height of the step on the outermost surface. The thickness of the film formed by spin coating is controlled by the rotation speed (unit: rpm) of the coater. For example, the rotation speed conditions for forming a 0.1 μm thick film on a single crystal silicon substrate are confirmed. When these conditions are applied to the semiconductor device 1, a film with a thickness of 0.1 μm or more is formed in the recessed portions of the step on the outermost surface of the semiconductor device 1, and a film with a thickness of 0.1 μm or less is formed in the protruding portions. Even under conditions for forming a 0.1 μm thick film, the corners of the step are formed with a relatively thick film, thereby fully achieving the effect of reducing the shape of the step.

[0065] After the third silicon compound layer 15 is formed, the electrode opening 5 is formed by lithography and etching in a second electrode opening formation step. The opening size of the electrode opening 5 is smaller than the opening size of the electrode opening 5 formed in the first electrode opening formation step after the formation of the protective layer 12 and the first silicon compound layer 13, and the electrode opening 5 is formed in a region inside the electrode opening 5 formed in the first electrode opening formation step. The electrode opening 5 sides of the protective layer 12 and the first silicon compound layer 13 are covered with the second silicon compound layer 14. Since the protective layer 12 is not exposed, it is possible to prevent moisture and the like from penetrating into the interior of the semiconductor device 1 from the outside.

[0066] Simultaneously with the formation of the electrode opening 5 in the second electrode opening formation step, the third silicon compound layer 15 and the second silicon compound layer 14 are removed from the dicing line region 3 and from the region outside the region where the protective layer 12 and the first silicon compound layer 13 have been removed. Even in the region around the dicing line region 3, the protective layer 12 and the first silicon compound layer 13 are covered with the second silicon compound layer 14, as shown in Fig. 3. Since the protective layer 12 is not exposed, it is possible to prevent moisture and the like from penetrating into the semiconductor device 1 from the outside.

[0067] The second silicon compound layer 14, which is an SOG film, will now be described in more detail. An SOG film is a film primarily composed of silicon and oxygen. Alternatively, an SOG film is a film primarily composed of silicon, oxygen, and carbon. Examples of SOG film types include an SOG-SiO2 film primarily composed of silicon and oxygen, or an SOG-SiOC film primarily composed of silicon, oxygen, and carbon. When an SOG-SiO2 film is used as the second silicon compound layer 14, the SOG-SiO2 film has water absorption properties, which can effectively address the problem of moisture penetration into the underlying layers due to moisture absorption by the SOG-SiO2 film, thereby improving the moisture resistance of the semiconductor device 1. Since the moisture resistance of the semiconductor device 1 is improved, fluctuations in the electrical characteristics of the semiconductor device 1 can be suppressed to a level that allows the target to be achieved. Furthermore, by forming an SOG film primarily composed of silicon and oxygen using a spin coating method, a semiconductor device 1 with improved moisture resistance can be easily manufactured.

[0068] To further improve moisture resistance, it is preferable to use an SOG-SiOC film for the second silicon compound layer 14. The reason for this is explained below. As mentioned above, an SOG-SiO2 film is a film that absorbs moisture like a TEOS oxide film. A test sample in which an SOG-SiO2 film is formed on a single crystal silicon substrate was placed in a PCT test chamber for a test time of 300 hours, and the amount of stress change was -146.5 MPa, which shows that the stress change is at a level equivalent to the amount of stress change in a TEOS oxide film due to moisture absorption.

[0069] Because a portion of the second silicon compound layer 14 is exposed to the outside in the electrode opening 5, the exposed portion of the SOG-SiO2 film may absorb moisture. Because the second silicon compound layer 14 is a surface protective film and is located farther from the semiconductor element portion 7 and the metal wiring layer 9 than the insulating layer 16 and the interlayer insulating layer 8, it is expected that even if the SOG-SiO2 film absorbs moisture, its effect on the electrical characteristics of the semiconductor device 1 will be relatively small. However, if the SOG-SiO2 film changes due to moisture absorption, film cracking, film lifting, or film peeling may occur, potentially causing it to lose its function as a surface protective film. If film lifting or film peeling occurs, the amount of moisture penetrating from the lifted or peeled portion will be greater than the amount of moisture penetrating from the outside through the top silicon compound layer, affecting the semiconductor element portion 7 and the metal wiring layer 9 inside the semiconductor device 1.

[0070] On the other hand, SOG-SiOC films, which are primarily composed of silicon, oxygen, and carbon, are known to be non-hygroscopic. Furthermore, when a test sample with an SOG-SiOC film formed on a single-crystal silicon substrate was placed in a PCT test chamber for 300 hours, the stress change was 13.9 MPa, indicating a very small stress change. By using an SOG-SiOC film for the second silicon compound layer 14, the effects of external moisture and the like can be minimized even in the exposed portions of the second silicon compound layer 14 in the electrode openings 5, resulting in stable electrical characteristics and a semiconductor device 1 with high precision and reliability. Furthermore, by forming an SOG film primarily composed of silicon, oxygen, and carbon using a spin coating method, a semiconductor device 1 with improved moisture resistance can be easily manufactured.

[0071] The above describes an example in which the second silicon compound layer 14 is an SOG film, and in the second protective film formation step, the second silicon compound layer 14 is formed by a spin coating method. Another example of the configuration of a semiconductor device 1 will be described with reference to FIG. 4 . The second silicon compound layer 14 shown in FIG. 4 is a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbide film, and in the second protective film formation step, the second silicon compound layer is formed by a plasma CVD method. In the semiconductor device 1 shown in FIG. 4 , after the protective layer 12 and the first silicon compound layer 13 are formed as surface protective films, the electrode opening 5 is formed by lithography and etching in the first electrode opening formation step. Thereafter, the second silicon compound layer 14 is formed on the first silicon compound layer 13 by a plasma CVD method, and the third silicon compound layer 15 is formed on the second silicon compound layer 14.

[0072] If the surface of the semiconductor device 1 on which the surface protection film is formed has recesses and protrusions due to the influence of the metal wiring layer 9 or the like, forming a silicon compound layer by plasma CVD will result in recesses and protrusions in the surface protection film that inherit the shapes of the recesses and protrusions in the underlying layer. If defects such as pinholes are formed in the first silicon compound layer 13, the second silicon compound layer 14 formed by plasma CVD can seal the defects in the first silicon compound layer 13. By sealing the defects, a path for gases such as water vapor to pass through is eliminated, thereby improving the environmental resistance of the semiconductor device 1. Furthermore, by forming a third silicon compound layer 15 on the second silicon compound layer 14, a semiconductor device 1 with excellent performance in terms of barrier properties against the external environment can be obtained.

[0073] The thicker the silicon compound layer formed by plasma CVD or the like, the greater the moisture-proofing effect. However, if the film thickness is too thick, the internal stress of the film increases, which may cause film lifting and peeling, resulting in a loss of function as a surface protective film. Considering the need to maintain a certain level of moisture-proofing performance while preventing problems such as film peeling, it is preferable to design the film thickness of each layer within a range of approximately 0.1 to 2.0 μm. On the other hand, it is possible to improve moisture resistance even with a film thickness of less than 0.1 μm. Furthermore, even if the film thickness exceeds 2.0 μm, it is possible to suppress the occurrence of problems by forming the film under film formation conditions that reduce the internal stress of the film. It is advisable to optimally design the film thickness of the silicon compound layer depending on the balance between the target level of moisture resistance and film stress.

[0074] When the second silicon compound layer 14 and the third silicon compound layer 15 are formed of the same type of film, for example, SiN films, these films are deposited successively in a vacuum. If defects such as pinholes are formed in the first SiN film during deposition of the first SiN film, the defects in the first SiN film may continue to grow in the second SiN film during deposition of the second SiN film. When depositing the same type of film in succession, to suppress the continuous growth of defects, it is preferable to open the first layer to the atmosphere upon completion of deposition of the first layer before starting deposition of the second layer. By breaking the continuity by opening to the atmosphere, the layer formed initially in the second layer is deposited without inheriting the defects of the first layer, suppressing the continuous growth of defects and enabling the defects in the first layer to be sealed by the second layer. Furthermore, to enhance the effect of suppressing the continuous growth of defects, it is preferable to select different types of films for the second silicon compound layer 14 and the third silicon compound layer 15.

[0075] When the second silicon compound layer 14 is formed by plasma CVD, examples of the film type of the second silicon compound layer 14 include a SiN film, a SiON film, a SiOC film, and a SiO2 film. When the protective layer 12 is a SiO2 film and the first silicon compound layer 13 is a SiN film, as in the configuration of the semiconductor device 1a shown in Comparative Example 1, it is preferable to select a SiON film, a SiOC film, or a SiO2 film, which is a film type different from that of the underlying SiN film, for the second silicon compound layer 14. This is to suppress the continuous growth of defects.

[0076] The performance of a SiOC film may change depending on the type and ratio of gases used during film formation by plasma CVD. The SiOC film is formed using a mixed gas of a carbon-containing gas and an oxygen gas. When a SiOC film is formed with a high ratio of oxygen gas, the SiOC film may have properties similar to those of a SiO2 film. Because a SiO2 film is hygroscopic, it is desirable to form the SiOC film with a high ratio of a carbon-containing gas compared to oxygen gas.

[0077] By selecting a SiN film with the highest moisture resistance for the third silicon compound layer 15, which is different from the film type of the second silicon compound layer 14 below, it is possible to obtain a semiconductor device 1 with extremely high moisture resistance.

[0078] In the dicing process, the semiconductor device 1 is divided into individual pieces. The dicing process can obtain the semiconductor device 1 shown in FIG. 1. Since multiple semiconductor devices 1 are manufactured on a wafer, the semiconductor device 1 is divided into individual pieces as die chips by dicing. As shown in FIG. 3, an exposure prevention wall 4a is formed in a prevention wall formation region 4 that is inside the dicing line region 3 and outside the semiconductor chip region 2. A portion of the dicing line region 3 is removed by dicing. In FIG. 3, the region removed by dicing is shown to the right of the dashed line in the figure (the portion indicated by the arrow). Even when the side surface of the semiconductor device 1 is exposed by dicing, the exposure prevention wall 4a can prevent moisture and the like from penetrating into the interior of the semiconductor device 1 from the outside.

[0079] As described above, the semiconductor device 1 according to the first embodiment includes the semiconductor substrate 6, the semiconductor element portion 7 formed on the main surface 6 a of the semiconductor substrate 6, the integrated circuit portion 11 made of a silicon oxide film and having one or more interlayer insulating layers 8 stacked on the semiconductor element portion 7 and the metal wiring layer 9 connected to the semiconductor element portion 7, the protective layer 12 made of a silicon oxide film and provided on the integrated circuit portion 11, the first silicon compound layer 13 provided on the protective layer 12, the second silicon compound layer 14 provided on the first silicon compound layer 13, and the third silicon compound layer 15 provided on the second silicon compound layer 14. and a silicon compound layer 15, wherein a portion of the metal wiring layer 9 on one side of the interlayer insulating layer 8 and adjacent to the protective layer 12 is exposed through an electrode opening 5 that penetrates the protective layer 12, the first silicon compound layer 13, the second silicon compound layer 14, and the third silicon compound layer 15, and the portions of the protective layer 12 and the first silicon compound layer 13 on the side of the electrode opening 5 are covered with the second silicon compound layer 14, so that the hygroscopic protective layer 12 is not exposed to the outside, thereby suppressing the penetration of moisture into the semiconductor device 1. Since the penetration of moisture into the semiconductor device 1 is suppressed, the electrical characteristics are stabilized, and a semiconductor device 1 with high precision and high reliability can be obtained even when the semiconductor device 1 is continuously used in a high-humidity environment.

[0080] The prevention-wall formation region 4 is provided with an insulating layer 16 formed on the main surface 6 a, and one or more interlayer insulating layers 8 stacked on the side of the insulating layer 16 opposite the semiconductor substrate 6 side. An exposure prevention wall 4 a for protecting the semiconductor chip region 2 from the surroundings is formed on the insulating layer 16 and the one or more interlayer insulating layers 8 in the prevention-wall formation region 4. The side of the exposure prevention wall 4 a opposite the semiconductor substrate 6 side is covered with a protective layer 12, a first silicon compound layer 13, a second silicon compound layer 14, and a third silicon compound layer 15 in that order in the direction away from the semiconductor substrate 6. When the portions of the protective layer 12 and the first silicon compound layer 13 on the dicing line region 3 side of the exposure prevention wall 4 a are covered with the second silicon compound layer 14, the hygroscopic protective layer 12 is not exposed to the outside on the dicing line region 3 side, thereby suppressing moisture from penetrating into the interior of the semiconductor device 1. Since the penetration of moisture into the interior of the semiconductor device 1 is suppressed, even if the semiconductor device 1 is continuously used in a high humidity environment, the electrical characteristics are stabilized, and a semiconductor device 1 with high precision and high reliability can be obtained.

[0081] In the prevention wall formation region 4, peripheral metal wiring layers 9a, 9b, 9c are provided in the other side portion of each interlayer insulating layer 8, which is on the insulating layer 16 side, and in one side portion opposite the insulating layer 16 side, and extend in the direction of extension of the prevention wall formation region 4, first contact layers 10a, 10b which penetrate the interlayer insulating layer 8 to connect adjacent peripheral metal wiring layers 9a, 9b, 9c, and second contact layers 10c which penetrate the insulating layer 16 to connect the main surface 6a of the semiconductor substrate 6 and the peripheral metal wiring layer 9c are provided, and when the exposure prevention wall 4a is formed, the multiple peripheral metal wiring layers 9a, 9b, 9c are each connected by the first contact layers 10a, 10b, and a continuous wall is formed in a direction perpendicular to the main surface 6a, so that it is possible to suppress moisture from penetrating into the semiconductor chip region 2 from the exposed portion of the side of the semiconductor device 1. Since the intrusion of moisture into the semiconductor chip region 2 is suppressed, it is possible to improve the moisture resistance of the semiconductor device 1 whose side surfaces are exposed to the outside. Since the moisture resistance of the semiconductor device 1 is improved, it is possible to obtain the semiconductor device 1 that maintains high precision.

[0082] When the first silicon compound layer 13 and the third silicon compound layer 15 are silicon nitride films, the third silicon compound layer 15, which is likely to be exposed to the external environment, can be made of a silicon nitride film, which has the highest moisture resistance compared to other materials, thereby obtaining a semiconductor device 1 with excellent moisture resistance and environmental resistance. Furthermore, since the hygroscopic protective layer 12 made of a silicon oxide film is provided below the first silicon compound layer 13, the first silicon compound layer 13 covering the protective layer 12 can be made of a silicon nitride film, which has the highest moisture resistance compared to other materials, thereby suppressing moisture absorption by the protective layer 12. Since moisture absorption by the protective layer 12 is suppressed, defects in the integrated circuit portion 11 are suppressed, resulting in stable electrical characteristics and a semiconductor device 1 with high precision and reliability.

[0083] When the second silicon compound layer 14 is a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbide film, by selecting a film type for the second silicon compound layer 14 covering the first silicon compound layer 13 that is different from that of the first silicon compound layer 13, it is possible to separate the defects (suppress continuous growth of the defects) even when defects are formed in the upper and lower layers. Since the defects are separated, a distance is generated between the defects in the lower layer and the defects in the upper layer, and therefore the moisture resistance of the semiconductor device 1 can be improved.

[0084] When the second silicon compound layer 14 is an SOG film, the material of the SOG film formed by spin coating is liquid, and therefore, even if defects or pinholes are formed in the first silicon compound layer 13, the defects or pinholes can be filled with the SOG film. Since the defects or pinholes in the first silicon compound layer 13 are filled with the SOG film, a path for penetration of moisture or the like can be blocked, and the moisture resistance of the semiconductor device 1 can be improved.

[0085] When the SOG film is a film containing silicon and oxygen as its main components (for example, an SOG-SiO2 film), the SOG-SiO2 film has water absorption properties, and therefore has a certain effect on the problem of moisture penetration into the lower layers due to the SOG-SiO2 film absorbing moisture, thereby improving the moisture resistance of the semiconductor device 1. Since the moisture resistance of the semiconductor device 1 is improved, fluctuations in the electrical characteristics of the semiconductor device 1 can be suppressed to a level at which the target can be achieved.

[0086] When the SOG film is a film containing silicon, oxygen, and carbon as its main components (for example, an SOG-SiOC film), an SOG-SiOC film containing silicon, oxygen, and carbon as its main components is not hygroscopic and has a very small amount of stress change. Therefore, it is possible to minimize the influence of external moisture, etc., even on the exposed portion of the second silicon compound layer 14 on the side of the electrode opening 5, and therefore it is possible to obtain a semiconductor device 1 with stable electrical characteristics and high precision and high reliability.

[0087] When the pressure sensor device 100 according to embodiment 1 comprises a semiconductor device 1 having the above-described configuration and a semiconductor pressure sensor 50 connected to the semiconductor device 1, the electrical characteristics are stabilized even when the pressure sensor device 100 is continuously used in a high humidity environment, and a pressure sensor device 100 with high accuracy and high reliability can be obtained.

[0088] When the fuel cell system 200 according to embodiment 1 comprises a pressure sensor device 100 having the above-described configuration and a fuel cell 150 connected to the pressure sensor device 100 and controlling power generation based on the supply pressure of fuel gas detected by the pressure sensor device 100, by using the pressure sensor device 100 equipped with a semiconductor device 1 having high moisture resistance in the fuel cell system 200, it becomes possible to measure the pressure of gas including fuel off-gas with high accuracy, thereby achieving an improvement in the power generation efficiency of the fuel cell system 200.

[0089] The method for manufacturing the semiconductor device 1 according to the first embodiment includes a member preparation step, a semiconductor element portion formation step, a multilayer metal wiring formation step, a first protective film formation step, a first electrode opening formation step, a second protective film formation step, a second electrode opening formation step, and a dicing step, and the semiconductor device 1 is manufactured by these steps, and the protective layer 12 and the portion of the first silicon compound layer 13 on the side of the electrode opening 5 are covered with the second silicon compound layer 14. Therefore, the semiconductor device 1 in which the hygroscopic protective layer 12 is not exposed to the outside can be easily manufactured without using complex processing or advanced technology and without deteriorating production efficiency. Furthermore, the semiconductor device 1 can be easily manufactured with high precision and high reliability without significantly increasing material and manufacturing costs.

[0090] When the second silicon compound layer 14 is a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbide film and is formed by plasma CVD in the second protective film formation step, even if defects such as pinholes are formed in the first silicon compound layer 13, the defects in the first silicon compound layer 13 can be sealed by the second silicon compound layer 14 formed by plasma CVD. By sealing the defects, a path for gases such as water vapor to pass through is eliminated, thereby improving the environmental resistance of the semiconductor device 1.

[0091] When the second silicon compound layer 14 is an SOG film and is formed by spin coating in the second protective film formation step, the SOG film material formed by spin coating is liquid, so even if defects or pinholes are formed in the first silicon compound layer 13, the defects or pinholes can be filled with the SOG film. Filling the defects or pinholes in the first silicon compound layer 13 with the SOG film blocks the path of moisture penetration, thereby improving the moisture resistance of the semiconductor device 1. Furthermore, the second silicon compound layer 14 formed by spin coating reduces (flattens) the shape of the corners of steps, which are a weakness of film formation by plasma CVD. This allows the third silicon compound layer 15 formed by plasma CVD to be dense, thereby maximizing the moisture-proof performance of the semiconductor device 1.

[0092] When the SOG film formed by spin coating is a film primarily composed of silicon and oxygen (e.g., an SOG-SiO2 film), the SOG-SiO2 film has water absorption properties, which has a certain effect on the problem of moisture penetration into the underlying layers due to moisture absorption by the SOG-SiO2 film, thereby improving the moisture resistance of the semiconductor device 1. Since the moisture resistance of the semiconductor device 1 is improved, fluctuations in the electrical characteristics of the semiconductor device 1 can be suppressed to a level that allows targets to be achieved. By forming an SOG film primarily composed of silicon and oxygen by spin coating, a semiconductor device 1 with improved moisture resistance can be easily manufactured.

[0093] When the SOG film formed by spin coating is a film containing silicon, oxygen, and carbon as its main components (for example, an SOG-SiOC film), the SOG-SiOC film containing silicon, oxygen, and carbon as its main components is not hygroscopic and has a very small amount of stress change, so that it is possible to minimize the influence of external moisture, etc., even in the exposed portion of the second silicon compound layer 14 on the side of the electrode opening 5, thereby stabilizing the electrical characteristics and obtaining a semiconductor device 1 with high precision and high reliability. By forming an SOG film containing silicon, oxygen, and carbon as its main components by spin coating, a semiconductor device 1 with improved moisture resistance can be easily manufactured.

[0094] Second Embodiment A semiconductor device 1 according to a second embodiment will now be described. Fig. 11 is a cross-sectional view showing an outline of a main part of the semiconductor device 1 according to the second embodiment, taken at a position equivalent to that of Fig. 2, and Fig. 12 is a cross-sectional view showing an outline of a main part of the semiconductor device 1 according to the second embodiment, taken at a position equivalent to that of Fig. 3. The semiconductor device 1 according to the second embodiment differs from that according to the first embodiment in the configuration of the second silicon compound layer 14. The configuration shown in Fig. 11 is a modified example of the configuration shown in Fig. 4 of the first embodiment.

[0095] 4 of the first embodiment, the second silicon compound layer 14 and the third silicon compound layer 15 have shapes that inherit the shapes of the recesses and protrusions of the underlying layers. In this embodiment, as shown in FIG. 11 , the second silicon compound layer 14 is flattened on the side opposite to the first silicon compound layer 13. Since the second silicon compound layer 14 is flattened on the side facing the third silicon compound layer 15, the surface of the third silicon compound layer 15 facing the second silicon compound layer 14 and the surface of the third silicon compound layer 15 opposite to the second silicon compound layer 14 are also flat.

[0096] By planarizing the second silicon compound layer 14 in this manner, the third silicon compound layer 15 can be formed on the flat second silicon compound layer 14 without any step corners, and the third silicon compound layer 15 becomes a dense film with excellent film quality, thereby maximizing the environmental resistance effect of the semiconductor device 1. Because a film with extremely high environmental resistance can be formed on the outermost surface, the semiconductor device 1 can maintain high precision even when the semiconductor device 1 is continuously used in a high humidity environment.

[0097] A method for manufacturing a semiconductor device 1 according to a second embodiment of the present disclosure will be described. Similar to the first embodiment, the method for manufacturing the semiconductor device 1 includes a member preparation step, a semiconductor element portion formation step, a multilayer metal wiring formation step, a first protective film formation step, a first electrode opening portion formation step, a second protective film formation step, a second electrode opening portion formation step, and a dicing step, as shown in Fig. 10. Except for the second protective film formation step, the member preparation step, the semiconductor element portion formation step, the multilayer metal wiring formation step, the first protective film formation step, the first electrode opening portion formation step, the second electrode opening portion formation step, and the dicing step are the same as those in the manufacturing method of the first embodiment, and therefore will not be described again.

[0098] In the manufacturing method of the semiconductor device 1 of this embodiment, in the second protective film formation step, the second silicon compound layer 14 covering the first silicon compound layer 13 is formed by a plasma CVD method. The second silicon compound layer 14 immediately after being formed by the plasma CVD method has a shape with recesses and protrusions inheriting the stepped shape of the underlying layer, as shown in FIG. 4 . Furthermore, in the manufacturing method of the semiconductor device 1 of this embodiment, in the second protective film formation step, the second silicon compound layer 14 is planarized by CMP before the third silicon compound layer 15 is formed. The third silicon compound layer 15 is formed on the second silicon compound layer 14 with a flat surface by a plasma CVD method, as shown in FIG. 11 . By planarizing the surface of the underlying second silicon compound layer 14 by CMP, the third silicon compound layer 15 in a dense film state can be easily and uniformly formed on the second silicon compound layer 14. Since the third silicon compound layer 15 in a dense film state can be easily and uniformly formed, the environmental resistance of the semiconductor device 1 can be further easily improved.

[0099] When the second silicon compound layer 14 is planarized by CMP, the film thickness of the second silicon compound layer 14 is preferably designed to be equal to or greater than the height of the steps of the recesses and protrusions in the underlying layer. By making the film thickness greater than the height of the steps, the corners of the steps on the surface of the second silicon compound layer 14 can be removed by using CMP, and a flat surface can be obtained.

[0100] Next, the configuration of the exposure prevention wall 4a in this embodiment will be described. In this embodiment, as in the first embodiment, the exposure prevention wall 4a is formed in the prevention-wall formation region 4, as shown in Fig. 12. This embodiment differs from the first embodiment in that a portion of the protection layer 12 and the first silicon compound layer 13 on the outer periphery metal wiring layer 9a formed on the uppermost layer of the exposure prevention wall 4a is removed.

[0101] The portion of the exposure prevention wall 4a opposite the semiconductor substrate 6 is covered with the following layers in the direction away from the semiconductor substrate 6: a protective layer 12, a first silicon compound layer 13, a second silicon compound layer 14, and a third silicon compound layer 15, in that order. The portions of the protective layer 12 and the first silicon compound layer 13 covering the portion of the exposure prevention wall 4a on the dicing line region 3 side, and at least a portion of the exposure prevention wall 4a on the dicing line region 3 side, are covered with the second silicon compound layer 14.

[0102] With this configuration, even if the side surface of the semiconductor device 1 is exposed to the outside due to dicing, the semiconductor chip region 2 is completely covered by the moisture-proof exposure prevention wall 4a and the second silicon compound layer 14, thereby preventing moisture and the like from penetrating from the outside into the semiconductor chip region 2. Furthermore, if a crack is formed in the insulating layer 16 or the like on the side surface of the semiconductor device 1 due to dicing, this also has the effect of preventing the crack from progressing into the inside of the semiconductor chip region 2.

[0103] A method for manufacturing the semiconductor device 1 shown in Figure 12 will now be described. After the formation of the first silicon compound layer 13, when forming the electrode opening 5 in the first electrode opening formation step, portions of the first silicon compound layer 13 and the protective layer 12 on the exposure prevention wall 4a are removed. When forming the electrode opening 5 in the second electrode opening formation step, the second silicon compound layer 14 and the third silicon compound layer 15 are removed in a region closer to the dicing line region 3 than the region where the protective layer 12 on the exposure prevention wall 4a and portions of the first silicon compound layer 13 have been removed. The outer peripheral metal wiring layer 9a, the protective layer 12, and the first silicon compound layer 13 are covered with the second silicon compound layer 14. In Figure 12, the region removed by dicing is also shown to the right of the dashed line (the portion indicated by the arrow).

[0104] As described above, in the semiconductor device 1 according to the second embodiment, the portion of the exposure prevention wall 4 a opposite to the semiconductor substrate 6 side is covered with the protective layer 12, the first silicon compound layer 13, the second silicon compound layer 14, and the third silicon compound layer 15 in that order in the direction away from the semiconductor substrate 6, and the portions of the protective layer 12 and the first silicon compound layer 13 covering the portion of the exposure prevention wall 4 a on the dicing line region 3 side, and at least a part of the exposure prevention wall 4 a on the dicing line region 3 side are covered with the second silicon compound layer 14. Therefore, even if the side portions of the semiconductor device 1 are exposed to the outside by dicing, the semiconductor chip region 2 is completely covered by the exposure prevention wall 4 a and the second silicon compound layer 14, which have moisture-proof properties, and therefore it is possible to prevent moisture and the like from penetrating into the semiconductor chip region 2 from the outside.

[0105] Because the side of the second silicon compound layer 14 opposite to the first silicon compound layer 13 is flattened, the third silicon compound layer 15 can be formed on the flat second silicon compound layer 14 without any step corners, and the third silicon compound layer 15 becomes a dense film with excellent film quality, maximizing the environmental resistance effect of the semiconductor device 1. Because a film with extremely high environmental resistance can be formed on the outermost surface, the semiconductor device 1 can maintain high precision even when it is continuously used in a high-humidity environment.

[0106] In the manufacturing method of the semiconductor device 1 according to the second embodiment, in the second protective film formation step, the second silicon compound layer 14 is planarized by CMP before the third silicon compound layer 15 is formed, and therefore, by planarizing the surface of the underlying second silicon compound layer 14 by CMP, the third silicon compound layer 15 in a dense film state can be easily and uniformly formed on the second silicon compound layer 14. Since the third silicon compound layer 15 in a dense film state can be easily and uniformly formed, the environmental resistance of the semiconductor device 1 can be further easily improved.

[0107] Third Embodiment A semiconductor device 1 according to a third embodiment will now be described. Fig. 13 is a cross-sectional view showing an outline of a main part of the semiconductor device 1 according to the third embodiment, taken at the same position as in Fig. 2. The semiconductor device 1 according to the third embodiment differs from that of the first embodiment in the configuration of the second silicon compound layer 14. The configuration shown in Fig. 13 is a modified example of the configuration shown in Fig. 2 of the first embodiment.

[0108] In the semiconductor device 1 shown in FIG. 2 of the first embodiment, the second silicon compound layer 14 is formed to have a thin film thickness in protruding portions overlapping the metal wiring layer 9 and a thick film thickness in recessed portions not overlapping the metal wiring layer 9. The second silicon compound layer 14 is also formed continuously in the horizontal direction (the lateral direction in the figure). In this embodiment, as shown in FIG. 13 , the second silicon compound layer 14 provided on the side of the first silicon compound layer 13 opposite the protective layer 12 is provided in a recessed portion 17, which is a portion of the first silicon compound layer 13 opposite the protective layer 12 and does not overlap the metal wiring layer 9. The third silicon compound layer 15 is provided on a portion of the first silicon compound layer 13 opposite the protective layer 12, where the second silicon compound layer 14 is not provided, and on a portion of the second silicon compound layer 14 opposite the first silicon compound layer 13.

[0109] With this configuration, the portion of the first silicon compound layer 13 opposite the protective layer 12 and the portion of the second silicon compound layer 14 opposite the first silicon compound layer 13, where the third silicon compound layer 15 is provided, are planarized. Therefore, the third silicon compound layer 15 becomes a dense film of excellent film quality, thereby maximizing the environmental resistance effect of the semiconductor device 1. Furthermore, because a film with extremely high environmental resistance is formed on the outermost surface, the semiconductor device 1 can maintain high precision even when continuously used in a high-humidity environment. Furthermore, because the second silicon compound layer 14 is partially formed, even if the second silicon compound layer 14 absorbs moisture and changes, the occurrence of defects in the second silicon compound layer 14, such as film peeling, can be suppressed. Since defects in the second silicon compound layer 14 are suppressed, the reliability of the semiconductor device 1 can be further improved.

[0110] A manufacturing method of semiconductor device 1 according to embodiment 3 of the present disclosure will be described. Similar to embodiment 1, the manufacturing method of semiconductor device 1 includes a member preparation step, a semiconductor element portion formation step, a multilayer metal wiring formation step, a first protective film formation step, a first electrode opening portion formation step, a second protective film formation step, a second electrode opening portion formation step, and a dicing step, as shown in Figure 10. Except for the second protective film formation step, the member preparation step, the semiconductor element portion formation step, the multilayer metal wiring formation step, the first protective film formation step, the first electrode opening portion formation step, the second electrode opening portion formation step, and the dicing step are the same as those in the manufacturing method of embodiment 1, and therefore description thereof will be omitted.

[0111] In the manufacturing method of the semiconductor device 1 according to the present embodiment, in the second protective film formation step, the second silicon compound layer 14 covering the first silicon compound layer 13 is formed by spin coating. If the layer below the second silicon compound layer 14 has stepped portions, such as recesses and protrusions, forming the second silicon compound layer 14 by spin coating results in the second silicon compound layer 14 being thinner at the protrusions, such as on the metal wiring layer 9, and thicker at the recesses. Although the thickness is not uniform, the second silicon compound layer 14 is formed in a horizontally continuous state. By designing the second silicon compound layer 14 to be thin using spin coating, the thickness of the film formed on the protrusions can be minimized, but it is difficult to completely break the horizontal film continuity by controlling the film thickness alone.

[0112] An SOG-SiO2 film, an SOG-SiOC film, or the like is selected as the film type for the second silicon compound layer 14. For example, if an SOG-SiO2 film is selected as the second silicon compound layer 14, the SOG-SiO2 film will change due to moisture absorption. Therefore, if the second silicon compound layer 14 is in a state where it is continuously connected in the horizontal direction as a film, it is expected that film cracks or film lifting that occur in part of the film will be the starting point and cause the film to completely peel off.

[0113] In the manufacturing method of the semiconductor device 1 of this embodiment, in the second protective film formation step, the second silicon compound layer 14 is formed by spin coating on the portion of the first silicon compound layer 13 opposite to the protective layer 12 side, the portion of the first silicon compound layer 13 exposed on the electrode opening 5 side, the portion of the protective layer 12 exposed on the electrode opening 5 side, and the metal wiring layer 9 exposed at the electrode opening 5. Then, the second silicon compound layer 14 on the portion of the first silicon compound layer 13 opposite to the protective layer 12 side is formed by etch-back in the recess 17, which is a portion of the first silicon compound layer 13 opposite to the protective layer 12 side and does not overlap with the metal wiring layer 9. Thereafter, the third silicon compound layer 15 is formed on the portion of the first silicon compound layer 13 opposite to the protective layer 12 side and on the portion of the second silicon compound layer 14 opposite to the first silicon compound layer 13 side, where the second silicon compound layer 14 is not provided.

[0114] The second protective film formation process will be described in detail. After the second silicon compound layer 14 is formed, only the portion of the second silicon compound layer 14 formed in the protruding portion region below the second silicon compound layer 14 is removed by an etch-back method. In the etch-back method, for example, a photoresist is formed on the second silicon compound layer 14 by a spin coating method. The recesses and protruding portions on the surface of the second silicon compound layer 14 are filled with the photoresist, so that the surface of the second silicon compound layer 14 is planarized by the photoresist. After the photoresist is formed, the photoresist and a portion of the second silicon compound layer 14 are removed by etching. The etching is terminated when the second silicon compound layer 14 formed in the protruding portion region is removed from above the first silicon compound layer 13.

[0115] A flat surface can be formed by etching under conditions that make the etching rates of the photoresist and the second silicon compound layer 14 the same. The photoresist that remains partially formed after the etch-back is completely removed by ashing or the like. Thereafter, the third silicon compound layer 15 is formed on the first silicon compound layer 13 and the second silicon compound layer 14 by plasma CVD. Before forming the third silicon compound layer 15, a heat treatment may be performed to remove components adsorbed on the second silicon compound layer 14, such as moisture in the atmospheric environment.

[0116] By forming the second silicon compound layer 14 by the spin coating method, even if defects such as pinholes are formed in the first silicon compound layer 13, the defects can be filled, thereby blocking the path of penetration of moisture and the like into the semiconductor device 1. Furthermore, in addition to the planarizing effect of the SOG film, the planarizing effect of the etch-back method can be obtained, thereby further improving the flatness of the surface on which the third silicon compound layer 15 is formed. Therefore, the third silicon compound layer 15 is formed as a film with excellent film quality, thereby maximizing the environmental resistance effect of the semiconductor device 1. Furthermore, since the planarization is performed by the etch-back method in the second protective film formation step, the third silicon compound layer 15 can be easily and uniformly formed in a dense film state on the first silicon compound layer 13 and the second silicon compound layer 14. Since the third silicon compound layer 15 in a dense film state can be easily and uniformly formed, the environmental resistance of the semiconductor device 1 can be further easily improved.

[0117] In this embodiment, either the configuration shown in Fig. 3 of Embodiment 1 or the configuration shown in Fig. 12 of Embodiment 2 may be selected as the structure of the prevention-wall-forming region 4. The combination of the structures of the prevention-wall-forming region 4 may be freely selected depending on the desired performance.

[0118] As described above, in the semiconductor device 1 according to the third embodiment, the second silicon compound layer 14 provided on the side of the first silicon compound layer 13 opposite the protective layer 12 side is provided in the recess 17, which is a portion of the first silicon compound layer 13 opposite the protective layer 12 side and does not overlap with the metal wiring layer 9. The third silicon compound layer 15 is provided on a portion of the first silicon compound layer 13 opposite the protective layer 12 side, where the second silicon compound layer 14 is not provided, and on a portion of the second silicon compound layer 14 opposite the first silicon compound layer 13 side. Therefore, the portion of the first silicon compound layer 13 opposite the protective layer 12 side and the portion of the second silicon compound layer 14 opposite the first silicon compound layer 13 side, where the third silicon compound layer 15 is provided, are planarized, and the third silicon compound layer 15 becomes a dense film with excellent film quality, thereby maximizing the environmental resistance effect of the semiconductor device 1. Furthermore, since a film with extremely high environmental resistance is formed on the outermost surface, the semiconductor device 1 can maintain high precision even if it is continuously used in a high humidity environment.

[0119] In the method for manufacturing the semiconductor device 1 according to the third embodiment, after forming the second silicon compound layer 14 by spin coating, the second silicon compound layer 14 is formed by etching back in the recess 17, which is a portion of the first silicon compound layer 13 opposite the protective layer 12 and does not overlap with the metal wiring layer 9, and the third silicon compound layer 15 is formed in the portion of the first silicon compound layer 13 opposite the protective layer 12 and in the portion of the second silicon compound layer 14 opposite the first silicon compound layer 13, where the second silicon compound layer 14 is not provided. Therefore, the third silicon compound layer 15 can be easily and uniformly formed on the first silicon compound layer 13 and the second silicon compound layer 14. Since the third silicon compound layer 15 is easily and uniformly formed, the environmental resistance of the semiconductor device 1 can be further easily improved.

[0120] Furthermore, although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0121] REFERENCE SIGNS LIST 1, 1a, 1b semiconductor device, 2 semiconductor chip region, 3 dicing line region, 4 prevention wall formation region, 4a exposure prevention wall, 5 electrode opening, 6 semiconductor substrate, 6a main surface, 7 semiconductor element portion, 8 interlayer insulating layer, 9 metal wiring layer, 9a, 9b, 9c outer peripheral metal wiring layer, 10 contact layer, 10a, 10b first contact layer, 10c second contact layer, 11 integrated circuit portion, 12 protective layer, 13 first silicon compound layer, 14 second silicon compound layer, 15 third silicon compound layer, 16 insulating layer, 17 recess, 50 semiconductor pressure sensor, 51 Wheatstone bridge, 100 pressure sensor device, 150 fuel cell, 200 fuel cell system

Claims

1. A semiconductor substrate, a semiconductor element portion formed on a main surface that is one surface of the semiconductor substrate, one or more interlayer insulating layers made of silicon oxide film laminated on the side of the semiconductor element portion opposite the semiconductor substrate side, and an integrated circuit portion connected to the semiconductor element portion and having metal wiring layers provided on the other side of the interlayer insulating layer that is on the semiconductor element portion side and on one side opposite the semiconductor element portion side, a protective layer made of silicon oxide film and provided on the side of the integrated circuit portion opposite the semiconductor substrate side, a first silicon compound layer provided on the protective layer opposite the integrated circuit portion side, a second silicon compound layer provided on the first silicon compound layer opposite the protective layer side, and a third silicon compound layer provided on the second silicon compound layer opposite the first silicon compound layer side, A semiconductor device in which a portion of the metal wiring layer on one side of the interlayer insulating layer and adjacent to the protective layer is exposed through an electrode opening that penetrates the protective layer, the first silicon compound layer, the second silicon compound layer, and the third silicon compound layer, and portions of the protective layer and the first silicon compound layer on the side of the electrode opening are covered by the second silicon compound layer.

2. The semiconductor device according to claim 1, wherein, when viewed perpendicularly to the main surface of the semiconductor substrate, the semiconductor substrate comprises: a semiconductor chip region in which the integrated circuit portion is formed; a dicing line region surrounding the semiconductor chip region; and a prevention wall formation region provided in all or part of the space between the dicing line region and the semiconductor chip region, wherein the prevention wall formation region is provided with an insulating layer formed on the main surface and one or more interlayer insulating layers stacked on the insulating layer opposite the semiconductor substrate side, an exposure prevention wall for protecting the semiconductor chip region from the surroundings is formed on the insulating layer and the one or more interlayer insulating layers in the prevention wall formation region, the side of the exposure prevention wall opposite the semiconductor substrate side is covered with the protective layer, the first silicon compound layer, the second silicon compound layer, and the third silicon compound layer in that order in a direction away from the semiconductor substrate, and portions of the protective layer and the first silicon compound layer on the dicing line region side of the exposure prevention wall are covered with the second silicon compound layer.

3. When viewed perpendicularly to the main surface of the semiconductor substrate, the semiconductor substrate comprises: a semiconductor chip region in which the integrated circuit portion is formed; a dicing line region surrounding the semiconductor chip region; and a prevention wall formation region provided in all or part of the area between the dicing line region and the semiconductor chip region, wherein the prevention wall formation region is provided with an insulating layer formed on the main surface and one or more interlayer insulating layers stacked on the insulating layer opposite to the semiconductor substrate side, an exposure prevention wall for protecting the semiconductor chip region from the surroundings is formed on the insulating layer and the one or more interlayer insulating layers in the prevention wall formation region, and a portion of the exposure prevention wall opposite to the semiconductor substrate side is covered with the protective layer, the first silicon compound layer, the second silicon compound layer, and the third silicon compound layer in that order in a direction away from the semiconductor substrate, 2. The semiconductor device according to claim 1, wherein the protective layer covering the portion of the exposure prevention wall and the portion of the first silicon compound layer on the side of the dicing line region, and at least a portion of the exposure prevention wall on the side of the dicing line region, are covered with the second silicon compound layer.

4. A semiconductor device as described in claim 2 or 3, wherein in the prevention wall formation region, an outer periphery metal wiring layer is provided in the other side portion of each interlayer insulating layer that is on the insulating layer side and one side portion that is opposite the insulating layer side, extending in the direction in which the prevention wall formation region extends, a first contact layer that penetrates the interlayer insulating layer to connect adjacent outer periphery metal wiring layers, and a second contact layer that penetrates the insulating layer to connect the main surface of the semiconductor substrate and the outer periphery metal wiring layer, thereby forming the exposure prevention wall.

5. A semiconductor device according to any one of claims 1 to 4, wherein the second silicon compound layer provided on the side opposite the protective layer of the first silicon compound layer is provided in a recess that is a portion of the first silicon compound layer opposite the protective layer and that does not overlap with the metal wiring layer, and a third silicon compound layer is provided on a portion of the first silicon compound layer opposite the protective layer and on a portion of the second silicon compound layer opposite the first silicon compound layer, where the second silicon compound layer is not provided.

6. The semiconductor device according to any one of claims 1 to 4, wherein the first silicon compound layer and the third silicon compound layer are silicon nitride films.

7. The semiconductor device according to any one of claims 1 to 4, wherein the second silicon compound layer is a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbide film.

8. The semiconductor device according to any one of claims 1 to 5, wherein the second silicon compound layer is an SOG film.

9. The semiconductor device according to claim 8, wherein said SOG film is a film containing silicon and oxygen as its main components.

10. The semiconductor device according to claim 8, wherein said SOG film is a film containing silicon, oxygen and carbon as its main components.

11. The semiconductor device according to claim 7, wherein the second silicon compound layer has a surface opposite to the first silicon compound layer side that is planarized.

12. A pressure sensor device comprising the semiconductor device according to any one of claims 1 to 11 and a semiconductor pressure sensor connected to said semiconductor device.

13. A fuel cell system comprising the pressure sensor device according to claim 12 and a fuel cell connected to said pressure sensor device and controlling power generation based on the fuel gas supply pressure detected by said pressure sensor device.

14. A member preparation step of preparing a semiconductor substrate; a semiconductor element portion formation step of forming a plurality of semiconductor element portions on one of the principal surfaces of the semiconductor substrate; a multilayer metal wiring formation step of forming one or more interlayer insulating layers made of silicon oxide film on the side of the semiconductor element portion opposite the semiconductor substrate, and a metal wiring layer connected to the semiconductor element portion and on the other side of the interlayer insulating layer that is on the semiconductor element portion side and on one side opposite the semiconductor element portion side; a first protective film formation step of forming a protective layer made of silicon oxide film on the side of an integrated circuit portion formed from the semiconductor element portion, the interlayer insulating layer, and the metal wiring layer opposite the semiconductor substrate, and further forming a first silicon compound layer on the protective layer opposite the integrated circuit portion side; a first electrode opening formation step of penetrating the protective layer and the first silicon compound layer to expose a portion of the metal wiring layer adjacent to the protective layer and form an electrode opening. a second protective film forming step of forming a second silicon compound layer on a portion of the first silicon compound layer opposite to the protective layer side, a portion of the first silicon compound layer exposed on the electrode opening side, a portion of the protective layer exposed on the electrode opening side, and the metal wiring layer exposed in the electrode opening, and further forming a third silicon compound layer on the second silicon compound layer opposite to the semiconductor substrate side; a second electrode opening forming step of penetrating the second silicon compound layer and the third silicon compound layer to expose a portion of the metal wiring layer exposed in the first electrode opening forming step, and forming an electrode opening; and a dicing step of cutting dicing line regions surrounding each of the semiconductor chip regions in which the integrated circuit portion is formed, to separate the semiconductor chip regions into individual pieces, wherein the protective layer and the portion of the first silicon compound layer on the electrode opening side are covered with the second silicon compound layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the second silicon compound layer is a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbide film, and in the second protective film formation process, the second silicon compound layer is formed by a plasma CVD method.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the second silicon compound layer is an SOG film, and in the second protective film forming step, the second silicon compound layer is formed by a spin coating method.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the SOG film is a film containing silicon and oxygen as its main components.

18. The method for manufacturing a semiconductor device according to claim 16, wherein the SOG film is a film containing silicon, oxygen, and carbon as its main components.

19. The method for manufacturing a semiconductor device according to claim 14, wherein in the second protective film forming step, a second silicon compound layer is formed by spin coating on a portion of the first silicon compound layer opposite to the protective layer side, a portion of the first silicon compound layer exposed on the electrode opening side, a portion of the protective layer exposed on the electrode opening side, and the metal wiring layer exposed in the electrode opening; then, the second silicon compound layer on the portion of the first silicon compound layer opposite to the protective layer side is formed by etch-back in a recess that is a portion of the first silicon compound layer opposite to the protective layer side and that does not overlap with the metal wiring layer; and a third silicon compound layer is formed on a portion of the first silicon compound layer opposite to the protective layer side and a portion of the second silicon compound layer opposite to the first silicon compound layer side, where the second silicon compound layer is not provided.

20. The method for manufacturing a semiconductor device according to claim 15, wherein in the second protective film forming step, the second silicon compound layer is planarized by CMP before the third silicon compound layer is formed.

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