Pixel circuit, driving method therefor, display substrate and display apparatus

Abstract

A pixel circuit (DR), comprising: a driving unit (110) comprising a first end, a second end and a third end, the second end of the driving unit (110) being connected to a first electrode of a light-emitting device (OLED); a first light-emitting control unit (120) connected between a first power line (ELVDD) and the first end and configured to control the connection and disconnection of the first power line (ELVDD) and the first end; a second light-emitting control unit (130) connected between the second end and the first electrode of the light-emitting device (OLED) and configured to control the connection and disconnection of the second end and the first electrode of the light-emitting device (OLED); a threshold compensation unit (140) connected between the first end and the first electrode of the light-emitting device (OLED) and configured to control the connection and disconnection of the first end and the first electrode of the light-emitting device (OLED); a first storage unit (150) and second storage unit (160) connected in series between the third end and the first electrode of the light-emitting device (OLED), the first storage unit (C1) and the second storage unit (C2) being connected to a first node (N1); and a gating unit (170) connected between a first reference signal line (Vini1) and the first node (N1) and configured to control the connection and disconnection of the first reference signal line (Vini1) and the first node (N1).

Description

Pixel circuits and their driving methods, display substrates and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a pixel circuit and its driving method, a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix light-emitting devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. Currently, driving current is supplied to the light-emitting device through pixel circuits. However, the driving current in the pixel circuits is easily interfered with by the external DC power supply, which leads to a reduction in display quality.

[0003] Summary of the Invention

[0004] This disclosure provides a pixel circuit, comprising: a driving unit including a first terminal, a second terminal, and a third terminal, the second terminal of the driving unit being connected to a first electrode of a light-emitting device, the driving unit being configured to: provide a driving current to the light-emitting device during a light-emitting phase; a first light-emitting control unit connected between a first power line and the first terminal of the driving unit, the first light-emitting control unit being configured to: control the on / off state of the first power line and the first terminal of the driving unit; and a second light-emitting control unit connected between the second terminal of the driving unit and the first electrode of the light-emitting device, the second light-emitting control unit being configured to: control the second terminal of the driving unit... The driving unit is configured to control the connection and disconnection between the first terminal of the driving unit and the first electrode of the light-emitting device; a threshold compensation unit is connected between the first terminal of the driving unit and the first electrode of the light-emitting device, and the threshold compensation unit is configured to control the connection and disconnection between the first terminal of the driving unit and the first electrode of the light-emitting device; a first storage unit and a second storage unit are connected in series between the third terminal of the driving unit and the first electrode of the light-emitting device, and the first storage unit and the second storage unit are connected to a first node; a gating unit is connected between a first reference signal line and the first node, and the gating unit is configured to control the connection and disconnection between the first reference signal line and the first node.

[0005] According to some exemplary embodiments, the pixel circuit further includes a first reset unit connected between the gating unit and the first reference signal line, and the second ends of the first reset unit, the gating unit, and the driving unit are connected to a second node; the first reset unit is configured to control the connection and disconnection between the first reference signal line and the second node.

[0006] According to some exemplary embodiments, the first reset unit includes: a first reset transistor, a first terminal of the first reset transistor being connected to the first reference signal line, a second terminal of the first reset transistor being connected to the second node, and a gate of the first reset transistor being connected to a first reset control line; wherein, the first reference signal line is configured to provide a second reference signal during the reset phase and a first reference signal during the threshold compensation phase and the data writing phase.

[0007] According to some exemplary embodiments, the first reset unit is also connected to a second reference signal line, and the first reset unit is further configured to control the connection and disconnection between the second reference signal line and the second node.

[0008] According to some exemplary embodiments, the first reset unit includes: a first reset transistor, the first terminal of the first reset transistor being connected to the first reference signal line, the second terminal of the first reset transistor being connected to the second node, and the gate of the first reset transistor being connected to the first reset control line; and a second reset transistor, the first terminal of the second reset transistor being connected to the second reference signal line, the second terminal of the second reset transistor being connected to the second node, and the gate of the second reset transistor being connected to the second reset control line.

[0009] According to some exemplary embodiments, the gating unit includes a gating transistor, the first terminal of the gating transistor is connected to the second node, the second terminal of the gating transistor is connected to the first node, and the gate of the gating transistor is connected to a gating control line; wherein the gating control line and the first reset control line are configured in one of the following ways: the gating control line and the first reset control line are formed into an integral structure; the gating control line and the first reset control line are insulated from each other.

[0010] According to some exemplary embodiments, the pixel circuit further includes an input unit connected between a data line and a third terminal of the driving unit, the input unit being configured to control the connection and disconnection between the data line and the third terminal of the driving unit; the input unit is also connected between a reset signal line and the third terminal of the driving unit, the input unit being further configured to control the connection and disconnection between the reset signal line and the third terminal of the driving unit.

[0011] According to some exemplary embodiments, the input unit includes: an input transistor, the first terminal of which is connected to the third terminal of the driving unit, the second terminal of which is connected to the data line, and the gate of which is connected to the input control line; and a third reset transistor, the first terminal of which is connected to the third terminal of the driving unit, the second terminal of which is connected to the reset signal line, and the gate of which is connected to the third reset control line.

[0012] According to some exemplary embodiments, the threshold compensation unit includes: a threshold compensation transistor, the first terminal of the threshold compensation transistor being connected to the first terminal of the light-emitting device, the second terminal of the threshold compensation transistor being connected to the first terminal of the driving unit, and the gate of the threshold compensation transistor being connected to a threshold compensation control line; the third reset control line and the threshold compensation control line are configured in one of the following ways: the third reset control line and the threshold compensation control line are formed into an integral structure; the third reset control line and the threshold compensation control line are insulated from each other.

[0013] According to some exemplary embodiments, the input unit includes:

[0014] An input transistor is provided, wherein the first terminal of the input transistor is connected to the third terminal of the driving unit, the second terminal of the input transistor is connected to the reset signal line and the data line, and the gate of the input transistor is connected to the input control line.

[0015] According to some exemplary embodiments, the first light-emitting control unit includes: a first light-emitting control transistor, the first electrode of the first light-emitting control transistor being connected to the first power line, the second electrode of the first light-emitting control transistor being connected to the first end of the driving unit, and the gate of the first light-emitting control transistor being connected to the first light-emitting control line; the second light-emitting control unit includes: a second light-emitting control transistor, the first electrode of the second light-emitting control transistor being connected to the second end of the driving unit, the second electrode of the second light-emitting control transistor being connected to the first electrode of the light-emitting device, and the gate of the second light-emitting control transistor being connected to the second light-emitting control line.

[0016] According to some exemplary embodiments, the first storage unit includes: a first capacitor, the first plate of the first capacitor being connected to the third terminal of the driving unit, and the second plate of the first capacitor being connected to the first node; the second storage unit includes: a second capacitor, the first plate of the second capacitor being connected to the first node, and the second plate of the first capacitor, the second light-emitting control unit, the threshold compensation unit, and the first electrode of the light-emitting device being connected to the third node.

[0017] According to some exemplary embodiments, the pixel circuit further includes: a third light-emitting control unit connected between the third node and the first electrode of the light-emitting device, the third light-emitting control unit being configured to control the on / off state between the third node and the first electrode of the light-emitting device.

[0018] According to some exemplary embodiments, the third light-emitting control unit includes: a third light-emitting control transistor, the first electrode of the third light-emitting control transistor being connected to the third node, the second electrode of the third light-emitting control transistor being connected to the first electrode of the light-emitting device, and the gate of the third light-emitting control transistor being connected to the third light-emitting control line.

[0019] According to some exemplary embodiments, the driving unit includes: a driving transistor, the driving transistor including an oxide thin film transistor; a first electrode of the driving transistor is formed as a first terminal of the driving unit, a second electrode of the driving transistor is formed as a second terminal of the driving unit, and a gate of the driving transistor is formed as a third terminal of the driving unit.

[0020] According to some exemplary embodiments, the pixel circuit further includes a first substrate, the driving unit includes a driving transistor, the first light-emitting unit includes a first light-emitting control transistor, the second light-emitting control unit includes a second light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the gating unit includes a gating transistor, and the first storage unit includes a first capacitor; the orthographic projections of the first light-emitting control transistor on the first substrate and the orthographic projections of the threshold compensation transistor on the first substrate are arranged along a first direction, and the orthographic projections of the driving transistor, the first capacitor, the second light-emitting control transistor, and the gating transistor on the first substrate are located between the orthographic projections of the first light-emitting control transistor on the first substrate and the orthographic projections of the threshold compensation transistor on the first substrate.

[0021] According to some exemplary embodiments, the second electrode of the first light-emitting control transistor and the second electrode of the threshold compensation transistor are connected through a first connection portion, and the orthographic projections of the first light-emitting control transistor, the driving transistor, the first capacitor, the second light-emitting control transistor, the gating transistor, and the threshold compensation transistor on the first substrate are located on the same side of the orthographic projection of the first connection portion on the first substrate.

[0022] According to some exemplary embodiments, the orthographic projection of the driving transistor on the first substrate overlaps with the orthographic projection of the first capacitor on the first substrate.

[0023] According to some exemplary embodiments, the second storage cell includes a second capacitor, the orthographic projections of the first capacitor on the first substrate and the orthographic projections of the second capacitor on the first substrate are arranged along the first direction, and the orthographic projections of the second light-emitting control transistor and the gating transistor on the first substrate are located between the orthographic projections of the first capacitor on the first substrate and the orthographic projections of the second capacitor on the first substrate.

[0024] According to some exemplary embodiments, the orthographic projection of the threshold compensation transistor on the first substrate overlaps with the orthographic projection of the second capacitor on the first substrate.

[0025] According to some exemplary embodiments, the orthographic projection of the gating transistor on the first substrate is located between the orthographic projection of the second light-emitting control transistor on the first substrate and the orthographic projection of the driving transistor on the first substrate; the second terminal of the driving transistor, the first terminal of the second light-emitting control transistor, and the second terminal of the driving transistor are connected by a second connection portion; the orthographic projection of the gating transistor on the first substrate is located between the orthographic projection of the second connection portion on the first substrate and the orthographic projection of the first connection portion on the first substrate; and the first terminal of the gating transistor is connected to the second connection portion by a third connection portion.

[0026] According to some exemplary embodiments, the pixel circuit further includes an input unit, the input unit further includes an input transistor, the orthographic projection of the input transistor on the first substrate is located on the side where the orthographic projection of the first capacitor on the first substrate is opposite to the orthographic projection of the first light-emitting control transistor on the first substrate, and the orthographic projection of the gating transistor on the first substrate is located between the orthographic projection of the input transistor on the first substrate and the orthographic projection of the first connection portion on the first substrate.

[0027] According to some exemplary embodiments, the input unit further includes a third reset transistor, the orthographic projection of the third reset transistor on the first substrate being located on the side of the orthographic projection of the first capacitor on the first substrate close to the orthographic projection of the first light-emitting control transistor on the first substrate, and the orthographic projection of the first light-emitting control transistor on the first substrate being located between the orthographic projection of the third reset transistor on the first substrate and the orthographic projection of the first connection portion on the first substrate.

[0028] According to some exemplary embodiments, the second capacitor includes a first electrode plate and a second electrode plate. The second electrode plate is located on the side of the first electrode plate close to the first substrate. A first opening is provided on the first electrode plate of the second capacitor, exposing the second electrode plate of the second capacitor. The orthographic projection of the first opening on the first substrate and the orthographic projection of the threshold compensation transistor on the first substrate are aligned along a second direction, which intersects the first direction. After the first electrode of the threshold compensation transistor is connected to the second electrode of the second light-emitting control transistor, it is connected to a fourth connection portion. The second connection portion is located on the side of the first electrode plate of the second capacitor away from the first substrate. A portion of the fourth connection portion passes through the first opening and connects to the second electrode plate of the second capacitor.

[0029] According to some exemplary embodiments, the pixel circuit further includes a first reset unit, the first reset unit further includes a first reset transistor, the orthographic projection of the first reset transistor on the first substrate is located on the side of the orthographic projection of the second capacitor on the first substrate close to the orthographic projection of the first light-emitting control transistor on the first substrate, and the orthographic projection of the first reset transistor on the first substrate and the orthographic projection of the first opening on the first substrate are aligned along the first direction.

[0030] On the other hand, a display substrate is provided, wherein the pixel circuit described above is included.

[0031] In another aspect, a display device is provided, comprising a display substrate as described above.

[0032] In another aspect, a driving method for a pixel circuit is provided, wherein the method is applied to the pixel circuit described above, the driving method comprising:

[0033] During the threshold compensation phase, an invalid signal is provided to the first light-emitting control unit to cause the first light-emitting control unit to disconnect the first power line from the first end of the driving unit; an invalid signal is provided to the second light-emitting control unit to cause the second light-emitting control unit to disconnect the second end of the driving unit from the first electrode of the light-emitting device; an valid signal is provided to the threshold compensation unit to cause the threshold compensation unit to connect the first end of the driving unit to the first electrode of the light-emitting device; and an valid signal is provided to the gating unit to cause the gating unit to connect the first reference signal line to the first node.

[0034] During the data writing phase, an invalid signal is provided to the threshold compensation unit so that the threshold compensation unit disconnects the first end of the driving unit from the first electrode of the light-emitting device.

[0035] During the light-emitting phase, a valid signal is provided to the first light-emitting control unit so that the first light-emitting control unit connects the first power line to the first end of the driving unit, and a valid signal is provided to the second light-emitting control unit so that the second light-emitting control unit connects the second end of the driving unit to the first electrode of the light-emitting device. An invalid signal is provided to the gating unit so that the gating unit disconnects the first reference signal line from the first node. Attached Figure Description

[0036] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0037] Figure 1 schematically illustrates a pair of pixel circuits in a proportional configuration;

[0038] Figure 2 schematically illustrates a pixel circuit in another pair of proportions;

[0039] Figure 3 schematically shows a plan view of the display substrate in an embodiment of the present disclosure;

[0040] Figure 4 schematically illustrates a pixel circuit in an embodiment of this disclosure;

[0041] Figure 5 schematically illustrates one of the driving timing diagrams of an embodiment of this disclosure;

[0042] Figure 6 schematically illustrates a pixel circuit in some exemplary embodiments of the present disclosure;

[0043] Figures 7 to 14 schematically illustrate the planar structure of a pixel circuit according to an embodiment of the present disclosure, wherein Figures 7 to 14 schematically illustrate different film layers or combinations of different film layers in the planar structure of the pixel circuit.

[0044] Figure 15 schematically illustrates a pixel circuit in some exemplary embodiments of the present disclosure;

[0045] Figure 16 is the driving timing diagram corresponding to Figure 15;

[0046] Figure 17 schematically illustrates a pixel circuit in some exemplary embodiments of the present disclosure;

[0047] Figure 18 schematically illustrates a pixel circuit in some exemplary embodiments of the present disclosure;

[0048] Figure 19 schematically illustrates a pixel circuit in some exemplary embodiments of this disclosure; and

[0049] Figure 20 is the timing diagram corresponding to Figure 19. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0051] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0052] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0053] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0054] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0055] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0056] It should be noted that in this article, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern the film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. Multiple elements, components, structures, and / or parts that are "same layer and same material" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or parts that are "same layer and same material" have approximately the same thickness.

[0057] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of the individual film layers disposed perpendicular to the display panel, i.e., the dimensions along the light-emitting direction of the display panel, or the dimensions along the normal direction of the display device.

[0058] Figure 1 schematically shows a pair of pixel circuits in a proportional configuration.

[0059] Referring to Figure 1, in this comparative example, the pixel circuit includes a first transistor Tdata, a second transistor Tgate, a third transistor Tem1, a fourth transistor Tem2, a fifth transistor Tini, a sixth transistor Tar, a driving transistor Tdrive, and a first capacitor Cst.

[0060] The first transistor Tdata has its first terminal connected to the data line Vdata, and its second terminal connected to the gate G of the driving transistor Tdrive, the second terminal of the second transistor Tgate, and the first plate of the first capacitor Cst. Its gate is connected to the first scan line SCAN1. The second transistor Tgate has its first terminal connected to the reset signal line Vref, and its gate is connected to the second scan line SCAN2. The third transistor Tem1 has its first terminal connected to the first power line VDDEL, its second terminal connected to the first terminal D of the driving transistor Tdrive, and its gate connected to the first light-emitting control line EM1. The fourth transistor Tem2 has its first terminal connected to the second plate of the first capacitor Cst, the second terminal S of the driving transistor Tdrive, and the second terminal of the fifth transistor Tini. Its second terminal is connected to the first terminal of the light-emitting device 26 and the second terminal of the sixth transistor Tar. Its gate is connected to the second light-emitting control line EM2. The fifth transistor Tini has its first terminal connected to the first reference signal line Vini, and its gate is connected to the third scan line SCAN3. The sixth transistor Tar has its first terminal connected to the second reference signal Var, and its gate is connected to the third scan line SCAN3. The second electrode of the light-emitting device 26 is connected to the second power line VSSEL, and the light-emitting device 26 is also connected in parallel with a light-emitting capacitor Coled.

[0061] In the circuit described above, during the light-emitting stage, the driving transistor Tdrive can provide a corresponding driving current to the light-emitting device 26 based on its gate voltage. However, when outputting the driving current, the driving current is proportional to [Coled′ / (Cst′+Coled′)]. If the light-emitting capacitor Coled is smaller than the first capacitor Cst, the driving current will decrease. Here, Coled′ represents the capacitance of the light-emitting capacitor Coled, and Cst′ represents the capacitance of the first capacitor Cst.

[0062] Figure 2 schematically illustrates a pixel circuit in another pair of proportions.

[0063] Referring to Figure 2, in this comparative example, a second capacitor Cboost is added. The first plate of the second capacitor Cboost is connected to the second terminal S of the driving transistor Tdrive, the second plate of the first capacitor Cst, the second terminal of the fifth transistor Tini, and the first terminal of the fourth transistor Tem2. The second terminal of the second capacitor Cboost is connected to the DC power supply Vdc. Therefore, the driving current can be proportional to [(Coled′+Cboost′) / (Cst′+Coled′+Cboost′)]. By appropriately adjusting the size of the second capacitor Cboost, the attenuation of the driving current can be improved; therefore, the second capacitor Cboost is sometimes called a current boost capacitor. Here, Coled′ represents the capacitance of the light-emitting capacitor Coled, Cst′ represents the capacitance of the first capacitor Cst, and Cboost′ represents the capacitance of the second capacitor Cboost.

[0064] However, since the second capacitor Cboost is always connected to the DC power supply Vdc, fluctuations in the DC power supply Vdc during the light-emitting stage can cause instability in the gate voltage of the driving transistor Tdrive, thereby affecting the driving current.

[0065] In view of this, embodiments of the present disclosure provide a pixel circuit, which includes: a driving unit, a first light-emitting control unit, a second light-emitting control unit, a threshold compensation unit, a first storage unit, a second storage unit, and a gating unit.

[0066] The driving unit includes a first terminal, a second terminal, and a third terminal. The second terminal of the driving unit is connected to the first electrode of the light-emitting device. The driving unit is configured to provide driving current to the light-emitting device during the light-emitting phase. A first light-emitting control unit is connected between a first power line and the first terminal of the driving unit. The first light-emitting control unit is configured to control the on / off state of the connection between the first power line and the first terminal of the driving unit. A second light-emitting control unit is connected between the second terminal of the driving unit and the first electrode of the light-emitting device. The second light-emitting control unit is configured to control the on / off state of the connection between the second terminal of the driving unit and the first electrode of the light-emitting device. A threshold compensation unit is connected between the first terminal of the driving unit and the first electrode of the light-emitting device. The threshold compensation unit is configured to control the on / off state of the connection between the first terminal of the driving unit and the first electrode of the light-emitting device. A first storage unit and a second storage unit are connected in series between the third terminal of the driving unit and the first electrode of the light-emitting device. The first storage unit and the second storage unit are connected to a first node. A gating unit is connected between a first reference signal line and the first node. The gating unit is configured to control the on / off state of the connection between the first reference signal line and the first node.

[0067] Compared to the pixel circuit in the comparative example, the pixel circuit of this embodiment can also achieve threshold compensation and reduce the attenuation of the drive current. Furthermore, in the pixel circuit of this embodiment, either the first storage unit or the second storage unit is no longer constantly connected to an external DC power supply. This avoids interference from the external DC power supply to the gate (i.e., the second node) of the drive transistor during the light-emitting phase, thereby improving the stability of the drive current.

[0068] The pixel circuits in the embodiments of this disclosure will be described in detail below with reference to Figures 3 to 20.

[0069] Exemplarily, the pixel circuitry in this disclosure embodiment can be applied to a display substrate, which may be an OLED display substrate. FIG3 schematically shows a plan view of the display substrate in an embodiment of this disclosure. Referring to FIG3, the display substrate may include: a display area AA and a peripheral area NA located on at least one side of the display area AA. The display area AA may have various shapes. For example, the display area AA may be configured in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle, an ellipse, etc., including curved edges, and a semicircle, a semi-ellipse, etc., including straight edges and curved edges. In the embodiments of this disclosure, the display area AA is configured as a region having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0070] The display substrate may further include a substrate 310 and a plurality of pixel units P disposed on the substrate 310 and located in the display area AA. The plurality of pixel units P may be arranged in an array along a third direction Z1 and a fourth direction Z2. The third direction Z1 and the fourth direction Z2 intersect. For example, the third direction Z1 may include the vertical direction in FIG3, and the fourth direction Z2 may include the horizontal direction in FIG3. That is, the third direction Z1 and the fourth direction Z2 are perpendicular to each other.

[0071] Each pixel unit P may include multiple sub-pixels PX. For example, pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. For instance, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0072] Multiple sub-pixels PX can be arranged in an array along the third direction Z1 and the fourth direction Z2; however, the embodiments of this disclosure are not limited thereto. For ease of description, the embodiments of this disclosure refer to multiple sub-pixels PX arranged along the third direction Z1 as a column of sub-pixels PX, and multiple sub-pixels PX arranged along the fourth direction Z2 as a row of sub-pixels PX.

[0073] The display substrate also includes a plurality of first control lines G1 and a plurality of data lines Vdata disposed on the substrate 310 and at least located in the display area AA. The plurality of data lines Vdata extend along a third direction Z1, and the plurality of first control lines G1 extend along a fourth direction Z2. A sub-pixel PX is connected to one data line Vdata and one first control line G1. For example, sub-pixels PX in the same row are connected to the same first control line G1, sub-pixels PX in different rows are connected to different first control lines G1, sub-pixels PX in the same column are connected to the same data line Vdata, and sub-pixels PX in different columns are connected to different data lines Vdata.

[0074] The peripheral area NA can be disposed on at least one side of the display area AA. For example, the peripheral area NA can surround the display area AA. In embodiments of this disclosure, the peripheral area NA may include a vertical portion extending in a third direction Z1 and a horizontal portion extending in a fourth direction Z2.

[0075] The display substrate may further include a gate driving circuit 320 and a display bonding terminal 330 disposed on the substrate 310 and located in the peripheral region NA. For example, the gate driving circuit 320 may be located on at least one side of the display region AA. In the embodiment shown in FIG3, the gate driving circuit 320 is located on the left and right sides of the display region AA, respectively. It should be noted that the left and right sides may refer to "the left and right sides of the display substrate (screen) as viewed by the human eye during display". For example, the display bonding terminal 330 may be located on at least one side of the display region AA. In the embodiment shown in FIG3, the display bonding terminal 330 is located on the lower side of the display region AA. It should be noted that the lower side may refer to "the lower side of the display substrate (screen) as viewed by the human eye during display". The display bonding terminal 330 is used to bond with a display driving component. Exemplarily, the display driving component may include devices such as flexible circuit boards and display driving chips. The display bonding terminal 330 can be connected to devices such as printed circuit boards located on the back side of the display substrate through the display driving component. The display bonding terminal 330 is also connected to the signal line (such as the data line Vdata mentioned above) in the display area AA. Thus, the electrical signals on the printed circuit board can be transmitted through the display bonding terminal 330 to the corresponding signal line in the display area AA, and then to the corresponding sub-pixel PX to realize the display function.

[0076] It should be noted that although Figure 3 shows the gate driving circuit 320 located on the left and right sides of the display area AA and the display bonding terminal 330 located on the lower side of the display area AA, the embodiments of this disclosure are not limited to this, and the gate driving circuit 320 and the display bonding terminal 330 can be located at any suitable position in the peripheral area NA.

[0077] In embodiments of this disclosure, the gate driving circuit 320 can employ GOA (Gate Driver on Array) technology. In GOA technology, the gate driving circuit 320 is directly disposed on the array substrate, replacing an external chip. Each GOA unit serves as a first-stage shift register, and each shift register is connected to a first control line G1. The scanning signals are output sequentially from each shift register to achieve line-by-line scanning of the sub-pixel PX. In some embodiments, each shift register can also be connected to multiple first control lines G1. This adapts to the trend of high resolution and narrow bezels in display substrates.

[0078] For example, a sub-pixel PX includes an OLED and a pixel circuit DR. The pixel circuit DR is used to provide a corresponding driving current to the OLED based on the data voltage signal on the data line Vdata in one frame cycle, so that the OLED emits light and displays the corresponding image.

[0079] Figure 4 schematically illustrates a pixel circuit DR in an embodiment of the present disclosure. Referring to Figure 4, the pixel circuit DR in an embodiment of the present disclosure includes: a driving unit 110, a first light-emitting control unit 120, a second light-emitting control unit 130, a threshold compensation unit 140, a first storage unit 150, a second storage unit 160, and a gating unit 170.

[0080] The driving unit 110 includes a first terminal, a second terminal, and a third terminal. The second terminal of the driving unit 110 is electrically connected to the first electrode of the OLED light-emitting device. The driving unit 110 is configured to provide driving current to the OLED during the light-emitting phase. A first light-emitting control unit 120 is connected between the first power line ELVDD and the first terminal of the driving unit 110. The first light-emitting control unit 120 is configured to control the on / off state of the connection between the first power line ELVDD and the first terminal of the driving unit 110. A second light-emitting control unit 130 is connected between the second terminal of the driving unit 110 and the first electrode of the OLED. The second light-emitting control unit 130 is configured to control the on / off state of the connection between the second terminal of the driving unit 110 and the first electrode of the OLED. A threshold compensation unit 140 is connected between the first terminal of the driving unit 110 and the first electrode of the OLED. The threshold compensation unit 140 is configured to control the on / off state of the connection between the first terminal of the driving unit 110 and the first electrode of the OLED. The first storage unit 150 and the second storage unit 160 are connected in series between the third terminal of the driving unit 110 and the first electrode of the OLED light-emitting device, and the first storage unit 150 and the second storage unit 160 are connected to the first node N1. The gating unit 170 is connected between the first reference signal line Vini1 and the first node N1, and the gating unit 170 is configured to control the on / off state between the first reference signal line Vini1 and the first node N1.

[0081] For example, the second electrode of the OLED is connected to the second power line ELVSS. The driving unit 110 may include a driving transistor DT, which can provide a driving current to the OLED in response to the voltage of its gate.

[0082] For example, the first light-emitting control unit 120, the second light-emitting control unit 130, the threshold compensation unit 140, and the gating unit 170 may include components with switching functions. At least one of the first light-emitting control unit 120, the second light-emitting control unit 130, the threshold compensation unit 140, and the gating unit 170 includes at least a first terminal, a second terminal, and a control terminal, wherein the control terminal is used to control the on / off state of the first terminal and the second terminal. For example, at least one of the first light-emitting control unit 120, the second light-emitting control unit 130, the threshold compensation unit 140, and the gating unit 170 may include a transistor. The first electrode of the transistor may be formed as the first terminal described above, the second electrode of the transistor may be formed as the second terminal described above, and the gate of the transistor may be formed as the control terminal described above.

[0083] For example, the transistor described herein includes a gate, a first terminal, and a second terminal. The first and second terminals can be switched on and off by controlling the voltage of the gate. The first terminal can be the source, and the second terminal can be the drain; of course, the first terminal can also be the drain, and the second terminal can also be the source. The source and drain can be interchanged as needed. For a P-type transistor, a valid signal is a low-level signal, and an invalid signal is a high-level signal. For example, when the gate receives a high level, the first and second terminals are off; when the gate receives a low level, the first and second terminals are on. For an N-type transistor, a valid signal is a high-level signal, and an invalid signal is a low-level signal. For example, when the gate receives a high level, the first and second terminals are on; when it receives a low level, the first and second terminals are off.

[0084] For clarity, unless otherwise specified, the pixel circuit DR of this disclosure embodiment will be described below using an example where all transistors are N-type transistors. Accordingly, in the following text, a valid signal refers to a high-level signal and an invalid signal refers to a low-level signal.

[0085] For example, the second terminal of the first light-emitting control unit 120 is connected to the first terminal of the driving unit 110. For instance, the second terminal of the first light-emitting control unit 120 is connected to the first terminal of the driving transistor DT at the fourth node N4. The first terminal of the first light-emitting control unit 120 is connected to the first power line ELVDD, and the control terminal of the first light-emitting control unit 120 is connected to the first light-emitting control line EM1. Thus, by selectively providing a valid / invalid signal to the first light-emitting control line EM1, the connection and disconnection between the first power line ELVDD and the fourth node N4 can be controlled, thereby controlling the connection and disconnection between the first power line ELVDD and the first terminal of the driving unit 110. For example, a frame period includes a threshold compensation phase and a light-emitting phase. During the threshold compensation phase, an invalid signal is provided to the first light-emitting control line EM1 to disconnect the first power line ELVDD from the first terminal of the driving unit 110. During the light-emitting phase, a valid signal is provided to the first light-emitting control line EM1 to connect the first power line ELVDD to the fourth node N4.

[0086] For example, the first terminal of the second light-emitting control unit 130 is connected to the second terminal of the driving unit 110. For instance, the first terminal of the second light-emitting control unit 130 is connected to the second electrode of the driving transistor DT at the second node N2. The second terminal of the second light-emitting control unit 130 is connected to the first electrode of the light-emitting device OLED at the third node N3, and the control terminal of the second light-emitting control unit 130 is connected to the second light-emitting control line EM2. Thus, by selectively providing valid / invalid signals to the second light-emitting control line EM2, the on / off state of the second node N2 and the third node N3 can be controlled, thereby controlling the on / off state of the second terminal of the driving unit 110 and the first electrode of the light-emitting device OLED. For example, during the threshold compensation stage, an invalid signal is provided to the second light-emitting control line EM2 to disconnect the second terminal of the driving unit 110 from the first electrode of the light-emitting device OLED; during the light-emitting stage, a valid signal is provided to the second light-emitting control line EM2 to connect the second terminal of the driving unit 110 to the first electrode of the light-emitting device OLED.

[0087] For example, the first end of the threshold compensation unit 140 is connected to the third node N3, thereby connecting to the first electrode of the OLED. The second end of the threshold compensation unit 140 is connected to the fourth node N4, thereby connecting to the first end of the driving unit 110. The control end of the threshold compensation unit 140 is connected to the threshold compensation control line G3. Thus, by selectively providing a valid / invalid signal to the threshold compensation control line G3, the connection and disconnection between the fourth node N4 and the third node N3 can be controlled, that is, the connection and disconnection between the first end of the driving unit 110 and the first electrode of the OLED can be controlled. For example, during the threshold compensation stage, a valid signal is provided to the threshold compensation control line G3 to enable the threshold compensation unit 140 to conduct the connection between the first end of the driving unit 110 and the first electrode of the OLED; during the light emission stage, an invalid signal is provided to the threshold compensation control line G3 to disable the connection between the first end of the driving unit 110 and the first electrode of the OLED.

[0088] For example, both the first storage cell 150 and the second storage cell 160 may include capacitors. For instance, the first storage cell 150 includes a first capacitor C1, and the second storage cell 160 may include a second capacitor C2. The first plate of the first capacitor C1 is connected to the third terminal of the driving unit 110 at the fifth node N5. The second plate of the second capacitor C2 is connected to the third node N3, thereby connecting to the first electrode of the light-emitting device OLED. The second plate of the first capacitor C1 and the first plate of the second capacitor C2 are connected to the first node N1. Through the first capacitor C1 and the second capacitor C2, the driving current output by the driving transistor DT can be proportional to [(C3′+C2′) / (C1′+C2′+C3′)], thereby improving the attenuation of the driving current. Here, C1′ represents the capacitance of the first capacitor C1, C2′ represents the capacitance of the second capacitor C2, and C3′ represents the capacitance of the light-emitting capacitor (not shown in the figure) connected in parallel with the light-emitting device OLED.

[0089] For example, the first terminal of the gating unit 170 is connected to the first reference signal line Vini1, which can provide a constant DC signal. The second terminal of the gating unit 170 is connected to the first node N1, and the control terminal of the gating unit 170 is connected to the gating control line G4. Thus, by selectively providing a valid / invalid signal to the gating control line G4, the connection between the first reference signal line Vini1 and the first node N1 can be controlled. For example, during the threshold compensation stage, a valid signal is provided to the gating control line G4 to enable the gating unit 170 to conduct the first reference signal line Vini1 and the first node N1; during the light emission stage, an invalid signal is provided to the gating control line G4 to disable the first reference signal line Vini1 and the first node N1.

[0090] Figure 5 schematically illustrates one of the driving timing diagrams of an embodiment of the present disclosure. The operation of the pixel circuit DR of an embodiment of the present disclosure will be described exemplarily below with reference to Figures 4 and 5.

[0091] For example, one frame cycle is used to display one frame of an image. One frame cycle may include: a reset phase (Reset), a threshold compensation phase (Comp), a data writing phase (WD), and an emission phase (Emission). It should be noted that in the embodiments of this disclosure, the phrase "providing a valid / invalid signal to a certain signal line at a certain stage" and similar expressions can refer to providing a valid / invalid signal to a certain signal line during a certain time period of that stage. Whether the valid / invalid signal is provided simultaneously with entering that stage or after a period of time following entering that stage is not limited in the embodiments of this disclosure.

[0092] During the reset phase (Reset), an invalid signal is provided to the first light-emitting control line EM1, an valid signal is provided to the second light-emitting control line EM2, and an valid signal is provided to the threshold compensation control line G3. This causes the first light-emitting control unit 120 to disconnect the first power line ELVDD from the fourth node N4, the second light-emitting control unit 130 to connect the second node N2 and the third node N3, and the threshold compensation unit 140 to connect the fourth node N4 and the third node N3. At this time, a second reference signal V2 can be provided to the second node N2 (e.g., through the first reset unit mentioned below), and a reset signal Vr can be provided to the fifth node N5 (e.g., through the input unit mentioned below). This resets the potential of the fifth node N5 to Vr and the potentials of the fourth node N4, the second node N2, and the third node N3 to V2.

[0093] During the threshold compensation phase Comp, an invalid signal is provided to the second light-emitting control line EM2, and an valid signal is provided to the gating control line G4. This allows the second light-emitting control unit 130 to disconnect the second node N2 from the third node N3, and the gating unit 170 to connect the first reference signal line Vini1 to the first node N1. At this time, a reset signal Vr can continue to be provided to the fifth node N5, while simultaneously connecting the first reference signal line Vini1 to the second node N2 (for example, this can be achieved through the first reset unit mentioned below), where the voltage value of the electrical signal provided on the first reference signal line Vini1 at this time (hereinafter also referred to as the first reference signal V1) is less than the voltage value of the reset signal Vr. This allows the potential of the third node N3 to be Vr-Vth, and the potential of the first node N1 to be V1. Here, Vth is the threshold voltage of the driving transistor DT.

[0094] During the data writing phase WD, an invalid signal is provided to the threshold compensation control line G3. This causes the threshold compensation unit 140 to disconnect the fourth node N4 from the third node N3. At this time, a data voltage signal Data can be provided to the fifth node N5 (e.g., through an input unit mentioned below), while the first reference signal line Vini1 remains connected to the second node N2. This allows the data voltage signal Data to be written to the gate of the driving transistor DT, while the first node N1 remains at V1. This prevents the transition of the fifth node N5 from interfering with the third node N3, thus maintaining the potential of the third node N3 at Vr-Vth.

[0095] During the emission phase, an invalid signal is provided to the gating control line G4, while valid signals are provided to the first emission control line EM1 and the second emission control line EM2. This causes the gating unit 170 to disconnect the first node N1 from the first reference signal line Vini1, the first emission control unit 120 to connect the first power line ELVDD to the fourth node N4, and the second emission control unit 130 to connect the second node N2 to the third node N3. At this time, the supply of the data voltage signal Data to the fifth node N5 is stopped, and the first reference signal line Vini1 is disconnected from the second node N2. Therefore, the driving transistor DT can provide a driving current to the OLED device, where the driving current I = K*(Vgs - Vth). 2 That is, I = K * (Data - Vr) 2 Where Vgs represents the gate-source voltage of the driving transistor. Therefore, the magnitude of the driving current I is independent of the threshold voltage Vth of the driving transistor DT, thus achieving threshold compensation. Simultaneously, since the first reference signal line Vini1 is disconnected from the first node N1, interference from the external DC power supply to the fifth node N5 (or the third node N3) during the emission stage can be avoided.

[0096] Compared to the pixel circuit shown in Figure 2, the pixel circuit DR of this embodiment can also achieve threshold compensation and reduce the attenuation of the driving current. Furthermore, in the pixel circuit DR of this embodiment, the gating unit 170 prevents the first storage unit 150 and the second storage unit 160 from being constantly connected to an external DC power supply. This avoids the external DC power supply affecting the driving current during the emission phase, thereby improving the display effect.

[0097] The pixel circuit DR of the present disclosure embodiment will be further described below with reference to Figures 3 to 20.

[0098] In some specific embodiments, the driving unit 110 includes a driving transistor DT, which is an oxide thin-film transistor (OTFT) with advantages such as low leakage current. In the embodiments of this disclosure, the first terminal of the driving transistor DT is formed as the first terminal of the driving unit 110, the second terminal of the driving transistor DT is formed as the second terminal of the driving unit 110, and the gate of the driving transistor DT is formed as the third terminal of the driving unit 110.

[0099] In some specific embodiments, the pixel circuit DR further includes a first reset unit 180, which is connected between the gating unit 170 and the first reference signal line Vini1. The second terminals of the first reset unit 180, the gating unit 170, and the driving unit 110 are connected to the second node N2. The first reset unit 180 is configured to control the connection and disconnection between the first reference signal line Vini1 and the second node N2.

[0100] Exemplarily, the first terminal of the first reset unit 180 is connected to the first reference signal line Vini1. The second terminal of the first reset unit 180 is connected to the second node N2, thereby connecting to the second terminal of the driving unit 110 and the first terminal of the gating unit 170. The control terminal of the first reset unit 180 is connected to the first reset control line G5. Thus, by selectively providing a valid / invalid signal to the first reset control line G5, the connection and disconnection between the first reference signal line Vini1 and the second terminal of the driving unit 110 and the first terminal of the gating unit 170 can be controlled. For example, in the threshold compensation stage Comp, a valid signal is provided to the first reset control line G5 to enable the first reset unit 180 to conduct the first reference signal line Vini1 to the second terminal of the driving unit 110 and the first terminal of the gating unit 170; in the emission stage Emission, an invalid signal is provided to the first reset control line G5 to enable the first reset unit 180 to disconnect the first reference signal line Vini1 from the second terminal of the driving unit 110 and the first terminal of the gating unit 170.

[0101] For example, the first terminal of the gating unit 170 can be connected to the second node N2. When the first reference signal line Vini1 is connected to the second terminal of the driving unit 110 and the first terminal of the gating unit 170, the gating unit 170 can further connect the second node N2 to the first node N1. At this time, the first reference signal line Vini1 can be connected to the first node N1 to charge the first node N1. Simultaneously, the first reference signal line Vini1 also charges the second terminal of the driving transistor DT to control the driving transistor DT to write a threshold voltage to the third node N3. Thus, the charging of the first node N1 and the second terminal of the driving transistor DT can be achieved through a single signal line, thereby saving the number of signal lines.

[0102] In some specific embodiments, the first reset unit 180 includes a first reset transistor T7. The first terminal of the first reset transistor T7 is connected to the first reference signal line Vini1, the second terminal of the first reset transistor T7 is connected to the second node N2, and the gate of the first reset transistor T7 is connected to the first reset control line G5. The first reference signal line Vini1 is configured to provide a second reference signal V2 during the reset phase (Reset), and a first reference signal V1 during the threshold compensation phase (Comp) and the data writing phase (WD).

[0103] For example, during the reset phase (Reset), a valid signal is provided to the first reset control line G5, and a second reference signal V2 is provided to the first reference signal line Vini1. At this time, the first reset transistor T7 is turned on, and the second reference signal V2 is transmitted to the second node N2, used to reset the second node N2. During the threshold compensation phase (Comp) and the data writing phase (WD), a valid signal is provided to the first reset control line G5, and a first reference signal V1 is provided to the first reference signal line Vini1. At this time, the first reset transistor T7 is turned on, and the first reference signal V1 is transmitted to the second node N2, used to implement the aforementioned interference suppression and threshold compensation functions. During the emission phase (Emission), an invalid signal is provided to the first reset control line G5. At this time, the first reset transistor T7 is turned off. Therefore, the second node N2 can be disconnected from the first reference signal line Vini1, and the driving transistor DT can provide driving current to the OLED device via the second node N2.

[0104] In the embodiments of this disclosure, by providing the second reference signal V2 and the first reference signal V1 to the second node N2 in a time-division manner through a transistor (i.e., the first reset transistor T7), the number of transistors in the pixel circuit DR can be reduced, thereby facilitating the miniaturization design of the pixel circuit DR.

[0105] In some specific embodiments, the gating unit 170 includes a gating transistor T6, the first terminal of the gating transistor T6 is connected to the second node N2, the second terminal of the gating transistor T6 is connected to the first node N1, and the gate of the gating transistor T6 is connected to the gating control line G4.

[0106] For example, during the reset phase (Reset), a valid signal is provided to the gating control line G4. At this time, the gating transistor T6 is turned on, and the second reference signal V2 is transmitted to the first node N1. This allows the first node N1 to be reset. During the threshold compensation phase (Comp) and the data writing phase (WD), a valid signal is provided to the gating control line G4. At this time, the gating transistor T6 is turned on, and the first reference signal V1 is transmitted to the first node N1. This suppresses mutual interference between the fifth node N5 and the third node N3 during charging. During the emission phase (Emission), an invalid signal is provided to the gating control line G4. At this time, the gating transistor T6 is turned off, and the first node N1 is disconnected from the second node N2. This prevents external DC power supply interference to the fifth node N5 (or the third node N3).

[0107] For example, the gating control line G4 and the first reset control line G5 are configured in one of the following ways:

[0108] The gating control line G4 and the first reset control line G5 are integrated into a single structure. Therefore, the gating transistor T6 and the first reset transistor T7 can share the same control line, thus reducing the number of traces.

[0109] The gating control line G4 and the first reset control line G5 are separated by an insulated gap. Therefore, the gating transistor T6 and the first reset transistor T7 can be controlled independently, thereby improving drive flexibility.

[0110] In some specific embodiments, the pixel circuit DR further includes an input unit 190, which is connected between the data line Vdata and the third terminal of the driving unit 110. The input unit 190 is configured to control the on / off state of the data line Vdata and the third terminal of the driving unit 110. The input unit 190 is also connected between the reset signal line Vref and the third terminal of the driving unit 110, and is further configured to control the on / off state of the reset signal line Vref and the third terminal of the driving unit 110.

[0111] For example, the first end of the input unit 190 is connected to the data line Vdata, the second end of the input unit 190 is connected to the third end of the drive unit 110 at the fifth node N5, and the control end of the input unit 190 is connected to the input control line G1 and the third reset control line G2. Thus, by selectively providing a valid / invalid signal to the input control line G1, the connection / disconnection between the data line Vdata and the fifth node N5 can be controlled, thereby controlling the connection / disconnection between the data line Vdata and the third end of the drive unit 110. For example, during the reset phase (Reset), threshold compensation phase (Comp), and emission phase (Emission), an invalid signal is provided to the input control line G1 to cause the first reset unit 180 to disconnect the data line Vdata from the third end of the drive unit 110. During the data writing phase (WD), a valid signal is provided to the input control line G1 to cause the first reset unit 180 to connect the data line Vdata to the third end of the drive unit 110.

[0112] For example, the input unit 190 further includes a third terminal connected to the reset signal line Vref. The control terminal of the input unit 190 can also control the connection and disconnection between its third terminal and the second terminal. Thus, by selectively providing a valid / invalid signal to the third reset control line G2, the connection and disconnection between the reset signal line Vref and the fifth node N5 can be controlled, thereby controlling the connection and disconnection between the reset signal line Vref and the third terminal of the drive unit 110. For example, during the reset phase (Reset), a valid signal is provided to the third reset control line G2 so that the first reset unit 180 connects the reset signal line Vref to the third terminal of the drive unit 110. During the data writing phase (WD), an invalid signal is provided to the input control line G1 so that the first reset unit 180 connects the reset signal line Vref to the third terminal of the drive unit 110. For example, when the reset signal line Vref is connected to the fifth node N5, the fifth node N5 can be reset; when the data line Vdata is connected to the fifth node N5, the data voltage signal Data can be written to the fifth node N5.

[0113] In some specific embodiments, the input unit 190 includes an input transistor T1 and a third reset transistor T2. The first terminal of the input transistor T1 is connected to the third terminal of the driving unit 110, the second terminal of the input transistor T1 is connected to the data line Vdata, and the gate of the input transistor T1 is connected to the input control line G1. The first terminal of the third reset transistor T2 is connected to the third terminal of the driving unit 110, the second terminal of the third reset transistor T2 is connected to the reset signal line Vref, and the gate of the third reset transistor T2 is connected to the third reset control line G2.

[0114] For example, during the Reset phase and the threshold compensation phase Comp, a valid signal is provided to the third reset control line G2, and an invalid signal is provided to the input control line G1. At this time, the input transistor T1 is off, the third reset transistor T2 is on, and the reset signal line Vref is connected to the fifth node N5, thereby resetting the fifth node N5. During the data writing phase WD, an invalid signal is provided to the third reset control line G2, and a valid signal is provided to the input control line G1. At this time, the input transistor T1 is on, the third reset transistor T2 is off, and the data line Vdata is connected to the fifth node N5, thereby writing the data voltage signal Data to the fifth node N5. Thus, embodiments of this disclosure independently control the on / off states of the fifth node N5, the data line Vdata, and the reset signal line Vref using two transistors. The control of the two transistors does not affect each other, thereby improving drive flexibility.

[0115] In some specific embodiments, the threshold compensation unit 140 includes a threshold compensation transistor T4. The first terminal of the threshold compensation transistor T4 is connected to the first terminal of the light-emitting device OLED, the second terminal of the threshold compensation transistor T4 is connected to the first terminal of the driving unit 110, and the gate of the threshold compensation transistor T4 is connected to the threshold compensation control line G3.

[0116] For example, during the Reset phase and the threshold compensation phase Comp, a valid signal is provided to the threshold compensation control line G3. At this time, the threshold compensation transistor T4 is turned on, and the fourth node N4 is connected to the third node N3. When a suitable voltage is applied to the first terminal and gate of the driving transistor DT, the third node N3 can be written with the threshold voltage Vth of the driving transistor DT. During the data writing phase WD and the emission phase, an invalid signal is provided to the threshold compensation control line G3. At this time, the threshold compensation transistor T4 is turned off, and the fourth node N4 is disconnected from the third node N3.

[0117] For example, the third reset control line G2 and the threshold compensation control line G3 are configured in one of the following ways:

[0118] The third reset control line G2 and the threshold compensation control line G3 are integrated into a single structure. Therefore, the gating transistor T6 and the first reset transistor T7 can share the same control line, thus reducing the number of traces.

[0119] The third reset control line G2 is insulated from the threshold compensation control line G3. Therefore, the third reset transistor T2 and the threshold compensation transistor T4 can be controlled independently, thereby improving drive flexibility.

[0120] In some specific embodiments, the first light-emitting control unit 120 includes a first light-emitting control transistor T3. The first terminal of the first light-emitting control transistor T3 is connected to the first power line ELVDD, the second terminal of the first light-emitting control transistor T3 is connected to the first terminal of the driving unit 110, and the gate of the first light-emitting control transistor T3 is connected to the first light-emitting control line EM1. The second light-emitting control unit 130 includes a second light-emitting control transistor T5. The first terminal of the second light-emitting control transistor T5 is connected to the second terminal of the driving unit 110, the second terminal of the second light-emitting control transistor T5 is connected to the first terminal of the light-emitting device OLED, and the gate of the second light-emitting control transistor T5 is connected to the second light-emitting control line EM2.

[0121] For example, during the Reset phase, an invalid signal is provided to the first light-emitting control line EM1, and a valid signal is provided to the second light-emitting control line EM2. At this time, the first light-emitting control transistor T3 is off, and the second light-emitting control transistor T5 is on. As described above, during this phase, the first reference signal line Vini1 is connected to the second node N2, and a second reference signal V2 is provided to the second node N2. This allows the third node N3 to be reset. During the threshold compensation phase Comp and the data writing phase WD, invalid signals are provided to both the first light-emitting control line EM1 and the second light-emitting control line EM2. At this time, both the first light-emitting control transistor T3 and the second light-emitting control transistor T5 are off. As described above, during this phase, the fourth node N4 is connected to the third node N3. This allows the threshold voltage of the driving transistor DT to be written to the third node N3. During the Emission phase, valid signals are provided to both the first light-emitting control line EM1 and the second light-emitting control line EM2. At this time, both the first light-emitting control transistor T3 and the second light-emitting control transistor T5 are turned on, and the fourth node N4 is connected to the first power line ELVDD. The driving transistor DT provides driving current to the light-emitting device OLED based on the voltage of its gate. Since the threshold voltage Vth was previously written to the third node N3, the magnitude of the driving current is independent of the threshold voltage Vth, thus achieving threshold compensation. For details, please refer to the aforementioned embodiment, which will not be repeated here.

[0122] The first storage unit 150 includes a first capacitor C1, the first plate of which is connected to the third terminal of the driving unit 110, and the second plate of which is connected to the first node N1. The second storage unit 160 includes a second capacitor C2, the first plate of which is connected to the first node N1, and the second plate of the first capacitor C1, the second light-emitting control unit 130, the threshold compensation unit 140, and the first electrode of the light-emitting device OLED are connected to the third node N3.

[0123] By using the first capacitor C1 and the second capacitor C2, the drive current output by the driving transistor DT can be made proportional to [(C3′+C2′) / (C1′+C2′+C3′)], thereby improving the attenuation of the drive current. During the threshold compensation stage Comp and the data writing stage WD, since the first node N1 is connected to the first reference signal V1, the mutual interference between the fifth node N5 and the third node N3 during the charging process can be suppressed, thus maintaining both at the expected potential.

[0124] In some specific embodiments, the pixel circuit DR includes the aforementioned input transistor T1, third reset transistor T2, first light-emitting control transistor T3, threshold compensation transistor T4, second light-emitting control transistor T5, gating transistor T6, first reset transistor T7, first capacitor C1, and second capacitor C2.

[0125] Referring to Figure 5, during the Reset phase, an invalid signal is provided to the first light-emitting control line EM1 and the input control line G1, an valid signal is provided to the second light-emitting control line EM2, and valid signals are provided to the third reset control line G2, the threshold compensation control line G3, the gating control line G4, and the first reset control line G5. A second reference signal V2 is provided to the first reference signal line Vini1. At this time, the input transistor T1 and the first light-emitting control transistor T3 are turned off, while the third reset transistor T2, the threshold compensation transistor T4, the second light-emitting control transistor T5, the gating transistor T6, and the first reset transistor T7 are turned on. Therefore, the potential of the fifth node N5 can be reset to Vr, and the potentials of the fourth node N4, the second node N2, the third node N3, and the first node N1 can be reset to V2.

[0126] During the threshold compensation phase Comp, an invalid signal is provided to the second light-emitting control line EM2, and a first reference signal V1 is provided to the first reference signal line Vini1. At this time, the second light-emitting control transistor T5 is turned off. As a result, the fifth node N5 can be maintained at Vr, the second node N2 and the first node N1 can be charged to V1, and the fourth node N4 and the third node N3 can be Vr-Vth.

[0127] During the data writing phase WD, an invalid signal is provided to the third reset control line G2 and the threshold compensation control line G3, while a valid signal is provided to the input control line G1. At this time, the third reset transistor T2 and the threshold compensation transistor T4 are turned off, and the input transistor T1 is turned on. Thus, the data voltage signal Data can be written to the fifth node N5, while the first node N1 remains V1. Therefore, the third node N3 can be maintained at Vr-Vth.

[0128] During the emission phase, invalid signals are provided to the input control line G1, the gating control line G4, and the first reset control line G5, while valid signals are provided to the first emission control line EM1 and the second emission control line EM2. At this time, the input transistor T1, the gating transistor T6, and the first reset transistor T7 are turned off, while the first emission control transistor T3 and the second emission control transistor T5 are turned on. Therefore, the driving transistor DT can provide a driving current to the OLED device, where the driving current I = K*(Vgs - Vth). 2 That is, I = K * (Data - Vr) 2 The magnitude of the driving current I is independent of the threshold voltage of the driving transistor DT, thus achieving threshold compensation. Simultaneously, since the first reference signal line Vini1 is disconnected from the first node N1, interference from the external DC power supply to the fifth node N5 (or the third node N3) during the emission stage can be avoided.

[0129] The planar structure of the pixel circuit DR according to an embodiment of the present disclosure will be described below with reference to Figures 7 to 14.

[0130] Referring to Figures 7 to 14, in some specific embodiments, the pixel circuit DR further includes a first substrate (not shown in the figures), the driving unit 110 includes a driving transistor DT, the first light-emitting unit includes a first light-emitting control transistor T3, the second light-emitting control unit 130 includes a second light-emitting control transistor T5, the threshold compensation unit 140 includes a threshold compensation transistor T4, the gating unit 170 includes a gating transistor T6, and the first storage unit 150 includes a first capacitor C1. The orthographic projections of the first light-emitting control transistor T3 and the threshold compensation transistor T4 on the first substrate are arranged along a first direction X. The orthographic projections of the driving transistor DT, the first capacitor C1, the second light-emitting control transistor T5, and the gating transistor T6 on the first substrate are located between the orthographic projections of the first light-emitting control transistor T3 and the threshold compensation transistor T4 on the first substrate.

[0131] For example, the first direction X can refer to the vertical direction in Figure 14. For instance, in the same pixel circuit DR, the first light-emitting control transistor T3 and the threshold compensation transistor T4 are located on the upper and lower sides of other transistors, respectively. This facilitates the connection of the first light-emitting control transistor T3 and the threshold compensation transistor T4 without affecting other transistors.

[0132] For example, the pixel circuit DR includes: a first metal layer LS, a first gate layer Gate1, a semiconductor layer ACT, a second gate layer Gate2, and a first source / drain metal layer SD1, sequentially disposed along a direction away from the first substrate. It should be noted that an insulating layer is disposed between any two of the first metal layer LS, the first gate layer Gate1, the semiconductor layer ACT, the second gate layer Gate2, and the first source / drain metal layer SD1, such as the first insulating layer JY1 and the second insulating layer JY2 shown in Figures 11 and 12. The insulating layer can be a single film layer or a composite film layer; the embodiments of this disclosure are not limited in this regard. The material of the semiconductor layer ACT may include indium gallium zinc oxide (IGZO).

[0133] Exemplarily, each transistor in the embodiments of this disclosure may include an active portion located in the semiconductor layer ACT, the active portion including a first electrode connection portion, a second electrode connection portion, and a channel portion located between the first electrode connection portion and the second electrode connection portion. Each transistor also includes a gate located in the second gate layer. For example, the input transistor T1 includes a gate T1_GC, the third reset transistor T2 includes a gate T2_GC, the first light-emitting control transistor T3 includes a gate T3_GC, the threshold compensation transistor T4 includes a gate T4_GC, the second light-emitting control transistor T5 includes a gate T5_GC, the gating transistor T6 includes a gate T6_GC, and the first reset transistor T7 includes a gate T7_GC. The orthogonal projection of the transistor's gate onto the first substrate covers the orthogonal projection of the channel portion onto the first substrate. Each transistor also includes a first terminal and a second terminal. For example, the input transistor T1 includes a first terminal T1_S1 and a second terminal T1_S2, the third reset transistor T2 includes a first terminal T2_S1 and a second terminal T2_S2, the first light-emitting control transistor T3 includes a first terminal T3_S1 and a second terminal T3_S2, the threshold compensation transistor T4 includes a first terminal T4_S1 and a second terminal T4_S2, the second light-emitting control transistor T5 includes a first terminal T5_S1 and a second terminal T5_S2, the gating transistor T6 includes a first terminal T6_S1 and a second terminal T6_S2, and the first reset transistor T7 includes a first terminal T7_S1 and a second terminal T7_S2.

[0134] For example, in the same transistor, a first electrode connection portion is used to connect to the first electrode of the transistor, and a second electrode connection portion is used to connect to the second electrode of the transistor.

[0135] For example, the first and second electrodes of the transistor can be located in the first source / drain metal layer SD1. Alternatively, in the semiconductor layer ACT, several conductive regions can be formed by doping with a metallic conductive material, and some or all of the first and second electrodes of the transistor can be located in these conductive regions. In the embodiments of this disclosure, the specific film layers containing the first and second electrodes of the transistor can be determined according to actual needs, and the embodiments of this disclosure do not limit this. For clarity, the first and second electrodes of the transistor in the following text can refer to the portions of the first and second electrodes located in the conductive regions of the semiconductor layer ACT.

[0136] For example, the first power line ELVDD is located in the first source-drain metal layer SD1 and extends along the second direction Y, which intersects the first direction X. For example, the second direction Y can be the horizontal direction shown in Figure 14. The orthographic projection of the first light-emitting control transistor T3 on the first substrate is located between the orthographic projection of the first power line ELVDD on the first substrate and the orthographic projection of the driving transistor DT on the first substrate. The first electrode T3_S1 of the first light-emitting control transistor T3 is connected to the first power line ELVDD through the first via H1. The first via H1 penetrates the insulating layer between the first source-drain metal layer SD1 and the semiconductor layer ACT. The orthographic projection of the first via H1 on the first substrate overlaps with the orthographic projection of the first power line ELVDD on the first substrate.

[0137] For example, the first light-emitting control line EM1 is located in the first source-drain metal layer SD1 and extends along the second direction Y. The orthographic projection of the first light-emitting control line EM1 on the first substrate overlaps with the orthographic projection of the first light-emitting control transistor T3 on the first substrate. The gate T3_GC of the first light-emitting control transistor T3 is connected to the first light-emitting control line EM1 through a second via H2. The second via H2 penetrates the insulating layer between the first source-drain metal layer SD1 and the second gate layer Gate2. The orthographic projection of the second via H2 on the first substrate overlaps with the orthographic projection of the first light-emitting control line EM1 on the first substrate.

[0138] For example, the threshold compensation control line G3 is located in the first source-drain metal layer SD1 and extends along the second direction Y. The orthographic projection of the threshold compensation control line G3 on the first substrate overlaps with the orthographic projection of the threshold compensation transistor T4 on the first substrate. The gate T4_GC of the threshold compensation transistor T4 is connected to the threshold compensation control line G3 through a third via H3, which penetrates the insulating layer between the second gate layer Gate2 and the first source-drain metal layer SD1. Optionally, a first transition portion ZJ1 is provided on the threshold compensation control line G3. For example, the orthographic projection of the first transition portion ZJ1 on the first substrate is located on the side of the orthographic projection of the threshold compensation control line G3 on the first substrate that is opposite to the orthographic projection of the driving transistor DT on the first substrate. The gate T4_GC of the threshold compensation transistor T4 is connected to the first transition portion ZJ1 through the third via H3, and the orthographic projection of the third via H3 on the first substrate overlaps with the orthographic projection of the first transition portion ZJ1 on the first substrate.

[0139] In some specific embodiments, the second terminal T3_S2 of the first light-emitting control transistor T3 and the second terminal T4_S2 of the threshold compensation transistor T4 are connected through the first connection portion LJ1. The orthographic projections of the first light-emitting control transistor T3, the driving transistor DT, the first capacitor C1, the second light-emitting control transistor T5, the gating transistor T6, and the threshold compensation transistor T4 on the first substrate are located on the same side of the orthographic projection of the first connection portion LJ1 on the first substrate.

[0140] For example, the first connection portion LJ1 extends along the first direction X and is located in the semiconductor layer ACT. The first light-emitting control transistor T3, the driving transistor DT, the first capacitor C1, the second light-emitting control transistor T5, the gating transistor T6, and the threshold compensation transistor T4 are all located to the right of the first connection portion LJ1. Thus, the first connection portion LJ1 can avoid the connection structure between the aforementioned transistors.

[0141] For example, the orthographic projection of the second electrode T4_S2 of the threshold compensation transistor T4 on the first substrate is located on the side where the orthographic projection of the first electrode T4_S1 on the first substrate is opposite to the orthographic projection of the driving transistor DT on the first substrate. In this way, the connection position of the first connection part LJ1 and the threshold compensation transistor T4 can be set on the side away from the above-mentioned transistors, thereby reducing the impact of the new trace on the existing circuit.

[0142] In some specific embodiments, the orthographic projection of the driving transistor DT onto the first substrate overlaps with the orthographic projection of the first capacitor C1 onto the first substrate. This reduces the area occupied by the driving transistor DT and the first capacitor C1.

[0143] For example, the first plate C1_1 of the first capacitor C1 is located in the light-shielding layer, the second plate C1_2 of the first capacitor C1 is located in the first gate layer Gate1, and the gate DT_GC of the driving transistor DT is located in the second gate layer Gate2. The orthographic projections of the first plate C1_1 and the second plate C1_2 on the first substrate overlap, and a first notch QK1 is provided on the second plate C1_2, exposing the second plate C1_2.

[0144] For example, the gate DT_GC of the driving transistor DT can be connected to the second transition part ZJ2 first, and then the second transition part ZJ2 is connected to the first plate C1_1 of the first capacitor C1 through the first notch QK1.

[0145] For example, the second transition portion ZJ2 is located in the first source-drain metal layer SD1. The second transition portion ZJ2 includes a first portion extending along the first direction X and a second portion extending along the second direction Y. The gate DT_GC of the driving transistor DT is connected to the first portion, and the second portion is connected to the first plate C1_1 of the first capacitor C1 through the first notch QK1.

[0146] For example, the second electrode DT_S2 of the driving transistor DT is connected to the second electrode plate C1_2 of the first capacitor C1 through the second adapter ZJ2. The second adapter ZJ2 is located in the first source-drain metal layer SD1. The orthographic projection of the second adapter ZJ2 on the first substrate overlaps with the orthographic projection of the driving transistor DT on the first substrate and the orthographic projection of the first capacitor C1 on the first substrate.

[0147] In some specific embodiments, the second storage cell 160 includes a second capacitor C2. The orthographic projections of the first capacitor C1 and the second capacitor C2 on the first substrate are arranged along a first direction X. The orthographic projections of the second light-emitting control transistor T5 and the gating transistor T6 on the first substrate are located between the orthographic projections of the first capacitor C1 and the second capacitor C2 on the first substrate. Therefore, the second light-emitting control transistor T5 and the gating transistor T6 can be placed together between the first capacitor C1 and the second capacitor C2, thereby improving space utilization.

[0148] For example, the orthographic projection of the second light-emitting control transistor T5 on the first substrate lies between the orthographic projections of the gating transistor T6 on the first substrate. Both the second light-emitting control line EM2 and the gating control line G4 are located in the first source-drain metal layer SD1 and extend along the second direction Y. The gating control line G4 is connected to the gate T6_GC of the gating transistor T6 through a fourth via H4, which penetrates the insulating layer between the second gate layer Gate2 and the first source-drain metal layer SD1. The orthographic projection of the fourth via H4 on the first substrate overlaps with the orthographic projection of the gating control line G4 on the first substrate. The second light-emitting control line EM2 is connected to the gate T5_GC of the second light-emitting control transistor T5 through a fifth via H5, which penetrates the insulating layer between the second gate layer Gate2 and the first source-drain metal layer SD1. The orthographic projection of the fifth via H5 on the first substrate overlaps with the orthographic projection of the second light-emitting control line EM2 on the first substrate.

[0149] In some specific embodiments, the orthographic projection of the threshold compensation transistor T4 onto the first substrate overlaps with the orthographic projection of the second capacitor C2 onto the first substrate. This reduces the area occupied by the threshold compensation transistor T4 and the second capacitor C2.

[0150] For example, the orthographic projection of the third via H3 on the first substrate does not overlap with the orthographic projection of the second capacitor C2 on the first substrate, so that the connection position of the gate T4_GC of the threshold compensation transistor T4 and the threshold compensation control line G3 avoids the second capacitor C2.

[0151] In some specific embodiments, the orthographic projection of the selection transistor T6 on the first substrate lies between the orthographic projection of the second light-emitting control transistor T5 on the first substrate and the orthographic projection of the driving transistor DT on the first substrate. The second terminal DT_S2 of the driving transistor DT, the first terminal T5_S1 of the second light-emitting control transistor T5, and the second terminal DT_S2 of the driving transistor DT are connected through the second connection portion LJ2. The orthographic projection of the selection transistor T6 on the first substrate lies between the orthographic projection of the second connection portion LJ2 on the first substrate and the orthographic projection of the first connection portion LJ1 on the first substrate. The first terminal T6_S1 of the selection transistor T6 is connected to the second connection portion LJ2 through the third connection portion LJ3.

[0152] For example, the second connection portion LJ2 is located in the conductor region of the semiconductor layer ACT. The second connection portion LJ2 extends along the first direction X. Referring to FIG9, the first terminal T6_S1 of the selection transistor T6 extends to the right and is connected to the second connection portion LJ2. In this way, the selection transistor T6 and the second light-emitting control transistor T5 can be better arranged between the driving transistor DT and the second capacitor C2, thereby improving space utilization.

[0153] For example, the second plate C1_2 of the first capacitor C1 and the first plate C2_1 of the second capacitor C2 are connected by a first connection structure ZJG1. The first connection structure ZJG1 extends along a first direction X, and its orthographic projection on the first substrate is located on the side of the orthographic projection of the second connection portion LJ2 on the first substrate that is opposite to the orthographic projection of the first connection portion LJ1 on the first substrate. The first connection structure ZJG1 is located in the first gate layer Gate1. The second electrode T6_S2 of the selection transistor T6 is connected to the second connection structure ZJG2 through a sixth via H6, and then to the first connection structure ZJG1 through the second connection structure ZJG2. The sixth via H6 penetrates the insulating layer between the first gate layer Gate1 and the semiconductor layer ACT. The second connection structure ZJG2 extends along a second direction Y and is located in the first gate layer Gate1. The orthographic projection of the sixth via H6 on the first substrate overlaps with the orthographic projection of the second connection structure ZJG2 on the first substrate.

[0154] In some specific embodiments, the pixel circuit DR further includes an input unit 190, which includes an input transistor T1. The orthographic projection of the input transistor T1 on the first substrate is located on the side where the orthographic projection of the first capacitor C1 on the first substrate is opposite to the orthographic projection of the first light-emitting control transistor T3 on the first substrate. The orthographic projection of the selection transistor T6 on the first substrate is located between the orthographic projection of the input transistor T1 on the first substrate and the orthographic projection of the first connection portion LJ1 on the first substrate. Thus, the input transistor T1, the second light-emitting control transistor T5, and the selection transistor T6 can be preferably arranged between the first capacitor C1 and the second capacitor C2.

[0155] For example, the input transistor T1 and the gating transistor T6 are arranged along the second direction Y. The input control line G1 is located in the first source-drain metal layer SD1. The orthographic projection of the input control line G1 on the first substrate is located between the orthographic projection of the first capacitor C1 on the first substrate and the orthographic projection of the gating control line G4 on the first substrate. The input control line G1 extends along the second direction Y, and the orthographic projection of the input control line G1 on the first substrate overlaps with the input transistor T1.

[0156] For example, the gate T1_GC of the input transistor T1 is connected to the input control line G1 through a seventh via H7, which penetrates the insulating layer between the second gate layer Gate2 and the first source / drain metal layer SD1. The orthographic projection of the seventh via H7 onto the first substrate overlaps with the orthographic projection of the input control line G1 onto the first substrate.

[0157] In some specific embodiments, the input unit 190 further includes a third reset transistor T2, the orthographic projection of the third reset transistor T2 on the first substrate being located on the side of the orthographic projection of the first capacitor C1 on the first substrate close to the orthographic projection of the first light-emitting control transistor T3 on the first substrate, and the orthographic projection of the first light-emitting control transistor T3 on the first substrate being located between the orthographic projection of the third reset transistor T2 on the first substrate and the orthographic projection of the first connection portion LJ1 on the first substrate.

[0158] For example, the third reset transistor T2 and the first light-emitting control transistor T3 are arranged along the second direction Y. The third reset control line G2 and the reset signal line Vref are both located in the first source-drain metal layer SD1, and both extend along the second direction Y. The orthographic projection of the third reset control line G2 on the first substrate lies between the orthographic projection of the first light-emitting control line EM1 on the first substrate and the orthographic projection of the first capacitor C1 on the first substrate. The orthographic projection of the reset signal line Vref on the first substrate lies between the orthographic projection of the first power line ELVDD on the first substrate and the orthographic projection of the first light-emitting control line EM1 on the first substrate. The gate T2_GC of the third reset transistor T2 is connected to the third reset control line G2 through the eighth via H8, and the second terminal T2_S2 of the third reset transistor T2 is connected to the reset signal line Vref through the ninth via H9. The eighth via H8 penetrates the insulating layer between the second gate layer Gate2 and the first source-drain metal layer SD1, and the ninth via H9 penetrates the insulating layer between the semiconductor layer ACT and the first source-drain metal layer SD1. The orthographic projection of the eighth via H8 on the first substrate overlaps with the orthographic projection of the third reset control line G2 on the first substrate, and the orthographic projection of the ninth via H9 on the first substrate overlaps with the orthographic projection of the reset signal line Vref on the first substrate. Optionally, the orthographic projection of the eighth via H8 on the first substrate is located on the side where the orthographic projection of the first capacitor C1 on the first substrate is opposite to the orthographic projection of the first connection portion LJ1 on the first substrate. Therefore, the third reset transistor T2 and the first light-emitting control transistor T3 can be preferably arranged between the first power line ELVDD and the first capacitor C1.

[0159] For example, the first terminal T2_S1 of the third reset transistor T2 is connected to the second transition section ZJ2 described above, and then connected to the gate DT_GC of the driving transistor DT through the second transition section ZJ2.

[0160] In some specific embodiments, the second capacitor C2 includes a first plate C2_1 and a second plate C2_2. The second plate C2_2 is located on the side of the first plate C2_1 closest to the first substrate. A first opening K1 is provided on the first plate C2_1 of the second capacitor C2, exposing the second plate C2_2. The orthographic projection of the first opening K1 onto the first substrate and the orthographic projection of the threshold compensation transistor T4 onto the first substrate are aligned along a second direction Y, which intersects the first direction X. After the first electrode T4_S1 of the threshold compensation transistor T4 is connected to the second electrode T5_S2 of the second light-emitting control transistor T5, it is connected to a fourth connecting part LJ4. The second connecting part LJ2 is located on the side of the first plate C2_1 of the second capacitor C2 away from the first substrate. A portion of the fourth connecting part LJ4 passes through the first opening K1 and connects to the second plate C2_2 of the second capacitor C2.

[0161] For example, the fourth connection portion LJ4 is located in the conductive region of the semiconductor layer ACT, and the orthographic projection of the fourth connection portion LJ4 on the first substrate is on the side opposite to the orthographic projection of the second light-emitting control line EM2 on the first substrate. Referring to FIG9, the fourth connection portion LJ4 extends downward to the left side of the first opening K1, and then extends to the right side into the first opening K1, thereby connecting with the second plate C2_2 of the second capacitor C2 through the first opening K1.

[0162] In some specific embodiments, the pixel circuit DR further includes a first reset unit 180, which also includes a first reset transistor T7. The orthographic projection of the first reset transistor T7 on the first substrate is located on the side of the orthographic projection of the second capacitor C2 on the first substrate that is close to the orthographic projection of the first light-emitting control transistor T3 on the first substrate. Furthermore, the orthographic projection of the first reset transistor T7 on the first substrate and the orthographic projection of the first opening K1 on the first substrate are arranged along the first direction X.

[0163] Exemplarily, the orthographic projection of the first reset transistor T7 on the first substrate lies between the orthographic projection of the second light-emitting control line EM2 on the first substrate and the orthographic projection of the first opening K1 on the first substrate. Exemplarily, the first reset control line G5 is located in the first source-drain metal layer SD1, and the gate T7_GC of the first reset transistor T7 is located in the second gate layer Gate2. The gate T7_GC of the first reset transistor T7 is connected to the first reset control line G5 through a tenth via H10. The tenth via H10 penetrates the insulating layer between the first source-drain metal layer SD1 and the second gate layer Gate2. The orthographic projection of the tenth via H10 on the first substrate overlaps with the orthographic projection of the first reset control line G5 on the first substrate. Exemplarily, a portion of the first reference signal line Vini1 is located in the conductive region of the semiconductor layer ACT, and it is formed as an integral structure with the first electrode of the first reset transistor T7.

[0164] For example, the fourth connection part LJ4 can be connected to the third adapter part ZJ3 through the eleventh via H11. The third adapter part ZJ3 is located in the first source and drain electrode layer SD1. The third adapter part ZJ3 can be connected to the second plate C2_2 of the second capacitor C2 through the twentieth via H20 and the first opening K1.

[0165] For example, the fourth connection part LJ4 can also be connected to the fourth adapter part ZJ4 through the twelfth via H12. The fourth adapter part ZJ4 is located in the first source and drain electrode layer SD1, and is then connected to the first electrode of the light-emitting device OLED through the fourth adapter part ZJ4.

[0166] For example, the second electrode T1_S2 of the input transistor T1 can also be connected to the fifth adapter ZJ5 through the thirteenth via H13. The fifth adapter ZJ5 is located in the first source-drain electrode layer SD1, and is then connected to the data line Vdata through the fifth adapter ZJ5.

[0167] For example, the first terminal T2_S1 of the third reset transistor T2 can be connected to the second transition part ZJ2 through the fourteenth via H14, and the second transition part ZJ2 can be connected to the gate DT_GC of the driving transistor DT through the fifteenth via H15. The second transition part ZJ2 can be connected to the first plate C1_1 of the first capacitor C1 through the eighteenth via H18 and the first notch QK1.

[0168] For example, the second electrode DT_S2 of the driving transistor DT can be connected to the sixth adapter ZJ6 through the sixteenth via H16. The sixth adapter ZJ6 is located in the first source-drain electrode layer SD1. The sixth adapter ZJ6 can be connected to the second electrode C1_2 of the first capacitor C1 through the seventeenth via H17.

[0169] For example, the second terminal T7_S2 of the first reset transistor T7 can be connected to the second terminal DT_S2 of the drive transistor DT through the nineteenth via H19.

[0170] Referring to Figures 15, 17, 18 and 19, in other embodiments of this disclosure, the pixel circuit DR shown in Figure 6 can be modified to adapt the pixel circuit DR to the needs of different display substrates.

[0171] In some specific embodiments, the first reset unit 180 is also connected to the second reference signal line Vini2, and the first reset unit 180 is also configured to control the connection and disconnection between the second reference signal line Vini2 and the second node N2.

[0172] Unlike the embodiment shown in Figure 6, in this embodiment, the second reference signal V2 is provided through the second reference signal line Vini2, and the first reference signal V1 is provided through the first reference signal line Vini1, so that the second reference signal V2 and the first reference signal V1 are transmitted independently.

[0173] In some specific embodiments, the first reset unit 180 includes a first reset transistor T7 and a second reset transistor T8. The first terminal of the first reset transistor T7 is connected to the first reference signal line Vini1, the second terminal of the first reset transistor T7 is connected to the second node N2, and the gate of the first reset transistor T7 is connected to the first reset control line G5. The first terminal of the second reset transistor T8 is connected to the second reference signal line Vini2, the second terminal of the second reset transistor T8 is connected to the second node N2, and the gate of the second reset transistor T8 is connected to the second reset control line G6.

[0174] For example, in this embodiment, the pixel circuit DR includes the aforementioned driving transistor DT, input transistor T1, third reset transistor T2, first light-emitting control transistor T3, threshold compensation transistor T4, second light-emitting control transistor T5, gating transistor T6, first reset transistor T7, second reset transistor T8, first capacitor C1, and second capacitor C2.

[0175] Figure 16 is a driving timing diagram corresponding to Figure 15. Referring to Figure 16, the driving timing in this embodiment differs from that shown in Figure 5. Specifically, in this embodiment, during the reset phase (Reset), an invalid signal is provided to the first reset control line G5, and an valid signal is provided to the second reset control line G6. At this time, the first reset transistor T7 is turned off, and the second reset transistor T8 is turned on, thereby resetting the fourth node N4, the second node N2, the third node N3, and the first node N1 to V2. During the threshold compensation phase (Comp), a valid signal is provided to the first reset control line G5, and an invalid signal is provided to the second reset control line G6. At this time, the first reset transistor T7 is turned on, and the second reset transistor T8 is turned off, thereby charging the fourth node N4, the second node N2, the third node N3, and the first node N1 to V1. Apart from this, the driving timing of the remaining transistors is similar to that shown in Figure 5, and therefore will not be described again here.

[0176] Referring to Figure 17, in some other embodiments, the input unit 190 includes an input transistor T1. The first terminal of the input transistor T1 is connected to the third terminal of the driving unit 110, the second terminal of the input transistor T1 is connected to the reset signal line Vref and the data line Vdata, and the gate T1_GC of the input transistor T1 is connected to the input control line G1. The reset signal line Vref and the data line Vdata are formed as a single unit.

[0177] Unlike the embodiment shown in Figure 6, in this embodiment, the input unit 190 uses only one transistor, and the data line Vdata and the reset signal line Vref are provided to the input transistor T1 in a time-division manner.

[0178] For example, in this embodiment, the pixel circuit DR includes the aforementioned driving transistor DT, input transistor T1, first light-emitting control transistor T3, threshold compensation transistor T4, second light-emitting control transistor T5, gating transistor T6, first reset transistor T7, first capacitor C1, and second capacitor C2.

[0179] Regarding the driving timing, this embodiment differs from the driving timing shown in Figure 5. Specifically, in this embodiment, during the reset phase (Reset), a valid signal is provided to the input control line G1. At this time, the input transistor T1 is turned on, and the fifth node N5 is reset to vref via the reset signal Vr. During the data write phase (WD), a valid signal continues to be provided to the input control line G1. At this time, the input transistor T1 is turned on, thereby writing the data voltage signal Data to the fifth node N5. Apart from this, the driving timing of the remaining transistors is similar to that shown in Figure 5, and therefore will not be described again here.

[0180] Referring to Figure 18, in some other specific embodiments, the pixel circuit DR includes the aforementioned driving transistor DT, input transistor T1, first light-emitting control transistor T3, threshold compensation transistor T4, second light-emitting control transistor T5, gating transistor T6, first reset transistor T7, second reset transistor T8, first capacitor C1, and second capacitor C2.

[0181] Regarding the driving timing, this embodiment differs from the driving timing shown in Figure 5. Specifically, in this embodiment, during the reset phase (Reset), a valid signal is provided to the input control line G1 and the second reset control line G6, while an invalid signal is provided to the first reset control line G5. At this time, the input transistor T1 and the second reset transistor T8 are turned on, and the first reset transistor T7 is turned off. Thus, the fifth node N5 can be reset to Vr by the reset signal Vr, and the fourth node N4, the second node N2, the third node N3, and the first node N1 can be reset to V2 by the second reference signal V2.

[0182] During the threshold compensation phase Comp, an invalid signal is provided to the second reset control line G6, and an valid signal is provided to the first reset control line G5. At this time, the first reset transistor T7 is turned on, and the second reset transistor T8 is turned off, thereby charging the fourth node N4, the second node N2, the third node N3, and the first node N1 to V1.

[0183] During the data writing phase, WD continues to provide a valid signal to the input control line G1. At this time, the input transistor T1 turns on, thereby writing the data voltage signal Data to the fifth node N5. Apart from this, the driving timing of the remaining transistors is similar to that shown in Figure 5, so it will not be described again here.

[0184] Referring to FIG19, in some other specific embodiments, the pixel circuit DR further includes a third light emission control unit 111, which is connected between the third node N3 and the first electrode of the light-emitting device OLED. The third light emission control unit 111 is configured to control the on / off state of the third node N3 and the first electrode of the light-emitting device OLED.

[0185] Unlike the embodiment shown in Figure 6, this embodiment adds a third light-emitting control unit 111, which controls the connection and disconnection between the third node N3 and the first electrode of the OLED. Therefore, during the threshold compensation and data writing phase WD, the first electrode of the OLED can be disconnected from the third node N3, thus maintaining the voltage of the first electrode of the OLED at its initial potential. This initial potential can refer to the potential reset to during the reset phase. Additionally, the first reset unit 180 includes a first reset transistor T7 and a second reset transistor T8.

[0186] In some specific embodiments, the third light-emitting control unit 111 includes a third light-emitting control transistor T9, the first electrode of the third light-emitting control transistor T9 is connected to the third node N3, the second electrode of the third light-emitting control transistor T9 is connected to the first electrode of the light-emitting device OLED, and the gate of the third light-emitting control transistor T9 is connected to the third light-emitting control line EM3.

[0187] For example, in this embodiment, the pixel circuit DR includes the aforementioned driving transistor DT, input transistor T1, third reset transistor T2, first light-emitting control transistor T3, threshold compensation transistor T4, second light-emitting control transistor T5, gating transistor T6, first reset transistor T7, second reset transistor T8 and third light-emitting control transistor T9, first capacitor C1 and second capacitor C2.

[0188] Figure 20 is a timing diagram corresponding to Figure 19. Referring to Figure 20, the driving timing in this embodiment differs from that shown in Figure 5. Specifically, in this embodiment, during the reset phase (Reset), an invalid signal is provided to the first reset control line G5, while valid signals are provided to the third light-emitting control line EM3 and the second reset control line G6. At this time, the first reset transistor T7 is turned off, and the third light-emitting control transistor T9 and the second reset transistor T8 are turned on, thereby resetting the fourth node N4, the second node N2, the third node N3, the first node N1, and the first electrode of the OLED to V2. During the threshold compensation phase (Comp), a valid signal is provided to the first reset control line G5, while an invalid signal is provided to the third light-emitting control line EM3 and the second reset control line G6. At this time, the first reset transistor T7 is turned on, and the third light-emitting control transistor T9 and the second reset transistor T8 are turned off, thereby charging the fourth node N4, the second node N2, the third node N3, and the first node N1 to V1. Apart from this, the driving timing of the remaining transistors is similar to that shown in Figure 16, and therefore will not be described further here.

[0189] At least some embodiments of this disclosure also provide a display substrate, which includes the pixel circuit DR in the foregoing embodiments. Detailed structure of the display substrate can be found in the foregoing embodiments, and therefore will not be repeated here.

[0190] At least some embodiments of this disclosure also provide a display device, which may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0191] At least some embodiments of this disclosure also provide a driving method for a pixel circuit DR, the driving method being applied to the pixel circuit DR in the foregoing embodiments, the driving method comprising:

[0192] During the threshold compensation stage Comp, an invalid signal is provided to the first light-emitting control unit 120 so that the first light-emitting control unit 120 disconnects the first power line ELVDD from the first end of the driving unit 110. An invalid signal is provided to the second light-emitting control unit 130 so that the second light-emitting control unit 130 disconnects the second end of the driving unit 110 from the first electrode of the light-emitting device OLED. An valid signal is provided to the threshold compensation unit 140 so that the threshold compensation unit 140 conducts the first end of the driving unit 110 to the first electrode of the light-emitting device OLED. An valid signal is provided to the gating unit 170 so that the gating unit 170 conducts the first reference signal line Vini1 to the first node N1.

[0193] During the data writing phase, WD provides an invalid signal to the threshold compensation unit 140 so that the threshold compensation unit 140 disconnects the first terminal of the driving unit 110 from the first electrode of the light-emitting device OLED.

[0194] During the emission phase, a valid signal is provided to the first emission control unit 120 so that the first emission control unit 120 connects the first power line ELVDD to the first end of the driving unit 110, a valid signal is provided to the second emission control unit 130 so that the second emission control unit 130 connects the second end of the driving unit 110 to the first electrode of the OLED, and an invalid signal is provided to the gating unit 170 so that the first reference signal line Vini1 is disconnected from the first node N1.

[0195] For details not described in the embodiments of this disclosure, please refer to the foregoing embodiments, and therefore will not be repeated here.

[0196] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0197] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A pixel circuit, wherein, include: A driving unit, comprising a first end, a second end, and a third end, wherein the second end of the driving unit is connected to the first electrode of a light-emitting device, and the driving unit is configured to provide a driving current to the light-emitting device during the light-emitting phase. A first light-emitting control unit is connected between a first power line and a first end of the driving unit. The first light-emitting control unit is configured to control the connection and disconnection between the first power line and the first end of the driving unit. The second light-emitting control unit is connected between the second end of the driving unit and the first electrode of the light-emitting device. The second light-emitting control unit is configured to control the on / off state between the second end of the driving unit and the first electrode of the light-emitting device. A threshold compensation unit is connected between the first end of the driving unit and the first electrode of the light-emitting device. The threshold compensation unit is configured to control the on / off state between the first end of the driving unit and the first electrode of the light-emitting device. A first storage unit and a second storage unit are connected in series between the third end of the driving unit and the first electrode of the light-emitting device, and the first storage unit and the second storage unit are connected to a first node; A gating unit is connected between a first reference signal line and a first node, and the gating unit is configured to control the connection and disconnection between the first reference signal line and the first node.

2. The pixel circuit according to claim 1, wherein, The pixel circuit further includes a first reset unit, which is connected between the gating unit and the first reference signal line, and the second ends of the first reset unit, the gating unit, and the driving unit are connected to a second node; The first reset unit is configured to control the connection and disconnection between the first reference signal line and the second node.

3. The pixel circuit according to claim 2, wherein, The first reset unit includes: A first reset transistor, wherein the first terminal of the first reset transistor is connected to the first reference signal line, the second terminal of the first reset transistor is connected to the second node, and the gate of the first reset transistor is connected to the first reset control line; The first reference signal line is configured to provide a second reference signal during the reset phase, and at a threshold value... The compensation phase and the data writing phase provide the first reference signal.

4. The pixel circuit according to claim 2, wherein, The first reset unit is also connected to the second reference signal line, and the first reset unit is further configured to control the connection and disconnection between the second reference signal line and the second node.

5. The display substrate according to claim 4, wherein, The first reset unit includes: A first reset transistor, wherein the first terminal of the first reset transistor is connected to the first reference signal line, the second terminal of the first reset transistor is connected to the second node, and the gate of the first reset transistor is connected to the first reset control line; The second reset transistor has its first terminal connected to the second reference signal line, its second terminal connected to the second node, and its gate connected to the second reset control line.

6. The pixel circuit according to claim 3 or 5, wherein, The gating unit includes a gating transistor, the first terminal of which is connected to the second node, the second terminal of which is connected to the first node, and the gate of which is connected to a gating control line. The gating control line and the first reset control line are configured in one of the following ways: The gating control line and the first reset control line form an integral structure; The gating control line is insulated from the first reset control line by a distance.

7. The pixel circuit according to claim 1, wherein, The pixel circuit further includes an input unit connected between the data line and the third terminal of the driving unit. The input unit is configured to control the connection and disconnection between the data line and the third terminal of the driving unit. The input unit is also connected between the reset signal line and the third terminal of the drive unit, and the input unit is further configured to control the connection and disconnection between the reset signal line and the third terminal of the drive unit.

8. The pixel circuit according to claim 7, wherein, The input unit includes: An input transistor is provided, with its first terminal connected to the third terminal of the driving unit, its second terminal connected to the data line, and its gate connected to the input control line. catch; The third reset transistor has its first terminal connected to the third terminal of the driving unit, its second terminal connected to the reset signal line, and its gate connected to the third reset control line.

9. The pixel circuit according to claim 8, wherein, The threshold compensation unit includes: A threshold compensation transistor, wherein the first terminal of the threshold compensation transistor is connected to the first terminal of the light-emitting device, the second terminal of the threshold compensation transistor is connected to the first terminal of the driving unit, and the gate of the threshold compensation transistor is connected to the threshold compensation control line; The third reset control line and the threshold compensation control line are configured in one of the following ways: The third reset control line and the threshold compensation control line are formed as an integral structure; The third reset control line is insulated from the threshold compensation control line by a distance.

10. The pixel circuit according to claim 7, wherein, The input unit includes: An input transistor is provided, wherein the first terminal of the input transistor is connected to the third terminal of the driving unit, the second terminal of the input transistor is connected to the reset signal line and the data line, and the gate of the input transistor is connected to the input control line.

11. The pixel circuit according to claim 1, wherein, The first light-emitting control unit includes: a first light-emitting control transistor, the first electrode of the first light-emitting control transistor being connected to the first power line, the second electrode of the first light-emitting control transistor being connected to the first end of the driving unit, and the gate of the first light-emitting control transistor being connected to the first light-emitting control line; The second light-emitting control unit includes: a second light-emitting control transistor, the first terminal of the second light-emitting control transistor being connected to the second terminal of the driving unit, the second terminal of the second light-emitting control transistor being connected to the first terminal of the light-emitting device, and the gate of the second light-emitting control transistor being connected to the second light-emitting control line.

12. The pixel circuit according to claim 1, wherein, The first storage unit includes: a first capacitor, the first plate of the first capacitor being connected to the third terminal of the driving unit, and the second plate of the first capacitor being connected to the first node; The second storage unit includes: a second capacitor, the first plate of the second capacitor being connected to the first node, and the second plate of the first capacitor, the second light-emitting control unit, the threshold compensation unit, and the first electrode of the light-emitting device being connected to the third node.

13. The pixel circuit according to claim 12, wherein, The pixel circuit also includes: A third light-emitting control unit is connected between the third node and the first electrode of the light-emitting device, and the third light-emitting control unit is configured to control the on / off state between the third node and the first electrode of the light-emitting device.

14. The pixel circuit according to claim 13, wherein, The third light-emitting control unit includes: The third light-emitting control transistor has its first electrode connected to the third node, its second electrode connected to the first electrode of the light-emitting device, and its gate connected to the third light-emitting control line.

15. The pixel circuit according to claim 1, wherein, The driving unit includes a driving transistor, which includes an oxide thin-film transistor. The first electrode of the driving transistor is formed as the first terminal of the driving unit, the second electrode of the driving transistor is formed as the second terminal of the driving unit, and the gate of the driving transistor is formed as the third terminal of the driving unit.

16. The pixel circuit according to claim 1, wherein, The pixel circuit further includes a first substrate, the driving unit includes a driving transistor, the first light-emitting unit includes a first light-emitting control transistor, the second light-emitting control unit includes a second light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the gating unit includes a gating transistor, and the first storage unit includes a first capacitor. The orthographic projection of the first light-emitting control transistor on the first substrate and the orthographic projection of the threshold compensation transistor on the first substrate are arranged along a first direction. The orthographic projections of the driving transistor, the first capacitor, the second light-emitting control transistor, and the gating transistor on the first substrate are located between the orthographic projection of the first light-emitting control transistor on the first substrate and the orthographic projection of the threshold compensation transistor on the first substrate.

17. The pixel circuit according to claim 16, wherein, The second electrode of the first light-emitting control transistor is connected to the second electrode of the threshold compensation transistor through a first connection portion. The orthographic projections of the first light-emitting control transistor, the driving transistor, the first capacitor, the second light-emitting control transistor, the gating transistor, and the threshold compensation transistor on the first substrate are located on the same side of the orthographic projection of the first connection portion on the first substrate.

18. The pixel circuit according to claim 16, wherein, The orthographic projection of the driving transistor on the first substrate overlaps with the orthographic projection of the first capacitor on the first substrate.

19. The pixel circuit according to claim 16, wherein, The second storage cell includes a second capacitor, the orthographic projections of the first capacitor on the first substrate and the orthographic projections of the second capacitor on the first substrate are arranged along the first direction, and the orthographic projections of the second light-emitting control transistor and the gating transistor on the first substrate are located between the orthographic projections of the first capacitor on the first substrate and the orthographic projections of the second capacitor on the first substrate.

20. The pixel circuit according to claim 19, wherein, The orthographic projection of the threshold compensation transistor on the first substrate overlaps with the orthographic projection of the second capacitor on the first substrate.

21. The pixel circuit according to claim 16, wherein, The orthographic projection of the gating transistor on the first substrate is located between the orthographic projection of the second light-emitting control transistor on the first substrate and the orthographic projection of the driving transistor on the first substrate; The second terminal of the driving transistor, the first terminal of the second light-emitting control transistor, and the second terminal of the driving transistor are connected by a second connection portion. The orthographic projection of the gating transistor on the first substrate is located between the orthographic projection of the second connection portion on the first substrate and the orthographic projection of the first connection portion on the first substrate. The first terminal of the gating transistor is connected to the second connection portion through a third connection portion.

22. The pixel circuit according to claim 16, wherein, The pixel circuit further includes an input unit, which in turn includes an input transistor. The orthographic projection of the input transistor on the first substrate is located on the side where the orthographic projection of the first capacitor on the first substrate is opposite to the orthographic projection of the first light-emitting control transistor on the first substrate. The orthographic projection of the gating transistor on the first substrate is located between the orthographic projection of the input transistor on the first substrate and the orthographic projection of the first connection portion on the first substrate.

23. The pixel circuit according to claim 22, wherein, The input unit further includes a third reset transistor, the orthographic projection of the third reset transistor on the first substrate being located on the side of the orthographic projection of the first capacitor on the first substrate close to the orthographic projection of the first light-emitting control transistor on the first substrate, and the orthographic projection of the first light-emitting control transistor on the first substrate being located between the orthographic projection of the third reset transistor on the first substrate and the orthographic projection of the first connection portion on the first substrate.

24. The pixel circuit according to claim 18, wherein, The second capacitor includes a first plate and a second plate. The second plate is located on the side of the first plate close to the first substrate. A first opening is provided on the first plate of the second capacitor, and the first opening exposes the second plate of the second capacitor. The orthographic projection of the first opening on the first substrate and the orthographic projection of the threshold compensation transistor on the first substrate are arranged along a second direction, which intersects the first direction. After the first electrode of the threshold compensation transistor is connected to the second electrode of the second light-emitting control transistor, it is connected to the fourth connection part. The second connection part is located on the side of the first plate of the second capacitor away from the first substrate. A portion of the fourth connection passes through the first opening and connects to the second plate of the second capacitor.

25. The pixel circuit according to claim 24, wherein, The pixel circuit further includes a first reset unit, which includes a first reset transistor. The orthographic projection of the first reset transistor on the first substrate is located on the side where the orthographic projection of the second capacitor on the first substrate is close to the orthographic projection of the first light-emitting control transistor on the first substrate. Furthermore, the orthographic projection of the first reset transistor on the first substrate and the orthographic projection of the first opening on the first substrate are aligned along the first direction.

26. A display substrate, wherein, Includes the pixel circuitry as described in any one of claims 1 to 25.

27. A display device, wherein, Includes the display substrate as described in claim 26.

28. A driving method for a pixel circuit, wherein, Applied to a pixel circuit as described in any one of claims 1-25, the driving method includes: During the threshold compensation phase, an invalid signal is provided to the first light-emitting control unit to cause the first light-emitting control unit to disconnect the first power line from the first end of the driving unit; an invalid signal is provided to the second light-emitting control unit to cause the second light-emitting control unit to disconnect the second end of the driving unit from the first electrode of the light-emitting device; an valid signal is provided to the threshold compensation unit to cause the threshold compensation unit to connect the first end of the driving unit to the first electrode of the light-emitting device; and an valid signal is provided to the gating unit to cause the gating unit to connect the first reference signal line to the first node. During the data writing phase, an invalid signal is provided to the threshold compensation unit so that the threshold compensation unit disconnects the first end of the driving unit from the first electrode of the light-emitting device. During the light-emitting phase, a valid signal is provided to the first light-emitting control unit so that the first light-emitting control unit connects the first power line to the first end of the driving unit, and a valid signal is provided to the second light-emitting control unit so that the second light-emitting control unit connects the second end of the driving unit to the first electrode of the light-emitting device. An invalid signal is provided to the gating unit so that the gating unit disconnects the first reference signal line from the first node.

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