Array substrate and display panel

Abstract

An array substrate, comprising a substrate, and a plurality of first signal lines and a plurality of second signal lines located on one side of the substrate. The plurality of first signal lines and the plurality of second signal lines intersect to define a plurality of pixel regions. The plurality of first signal lines are arranged at intervals in a first direction and are partially bent in a second direction, wherein each first signal line comprises a first portion and a second portion; and one side of each pixel region is the first portion of one first signal line, and another side of the pixel region is the second portion of another first signal line, and the length of the first portion is greater than the length of the second portion. The array substrate further comprises a plurality of first electrodes corresponding to the pixel regions, and at least a part of each first electrode is located within the corresponding pixel region. For at least one pixel region, in the orthographic projections of the first electrode, the first portion, and the second portion on the substrate, the distance in the first direction between at least a part of the first electrode and the first portion is not equal to the distance in the first direction between the first electrode and the second portion.

Description

Array substrate and display panel Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the continuous development of display technology, display panels have been widely used, and people's requirements for display panels are becoming increasingly demanding. Among these, high pixel density (Pixels Per Inch; PPI) is an important development direction for display panels. Common display panels include Liquid Crystal Display (LCD) panels and Organic Light-Emitting Diode (OLED) panels. Thanks to the simpler pixel circuit structure of LCD panels (which can contain fewer thin-film transistors and capacitors), LCD panels have a greater advantage in ultra-high pixel densities (such as greater than or equal to 1000 PPI). As pixel density increases, the risk of pixel circuit interference (signal crosstalk) increases. How to improve the stability of pixel circuits is a crucial technical problem faced in further increasing the pixel density of LCD panels.

[0003] Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate includes a substrate and a plurality of first signal lines and a plurality of second signal lines located on one side of the substrate. The plurality of first signal lines and the plurality of second signal lines intersect to define a plurality of pixel regions. The plurality of first signal lines are spaced apart along a first direction and partially bent along a second direction. Each first signal line includes a first portion and a second portion. One side of each pixel region is a first portion of a first signal line, and the other side of the pixel region is a second portion of another first signal line. The length of the first portion is greater than the length of the second portion. The first direction and the second direction intersect. The array substrate also includes a plurality of first electrodes corresponding to the pixel regions, at least a portion of each first electrode being located within the pixel region. For at least one pixel region, in the orthographic projection of the first electrode, the first portion, and the second portion onto the substrate, the distance between at least a portion of the first electrode and the first portion in the first direction, and the distance between the first electrode and the second portion in the first direction, are not equal.

[0005] In some embodiments, in the orthographic projection of the first electrode, the first portion, and the second portion onto the substrate, the boundary length between the first electrode and the first portion is greater than the boundary length between the first electrode and the second portion, and the distance between at least a portion of the first electrode and the first portion in the first direction is greater than the distance between the first electrode and the second portion in the first direction.

[0006] In some embodiments, the first signal line includes a plurality of alternately connected first extension segments and a plurality of second extension segments; the plurality of first extension segments all extend along the first direction and are spaced apart along the second direction; the plurality of second extension segments all extend along the second direction and are alternately connected to the two ends of the first extension segments along the first direction. The first portion includes one second extension segment and two first extension segments connected to the second extension segment. The second portion includes one second extension segment adjacent to the first portion. The second extension segment included in the first portion is a first sub-segment, and the second extension segment included in the second portion is a second sub-segment. In the orthographic projection of the first electrode, the first sub-segment, and the second sub-segment onto the substrate, at least a portion of the first electrode is at a distance from the first sub-segment along the first direction that is greater than the distance from the second sub-segment along the first direction that is also from the first sub-segment.

[0007] In some embodiments, the array substrate further includes a plurality of first transistors, each first transistor being electrically connected to a first electrode, and a first terminal of the first transistor being electrically connected to the first signal line, and a second terminal being electrically connected to the first electrode. The first electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode disposed along a direction away from the substrate. The first sub-electrode is electrically connected to the second terminal of the first transistor, the second sub-electrode is electrically connected to the first sub-electrode, and the third sub-electrode is electrically connected to the second sub-electrode. The distance between the orthographic projection of at least a portion of at least one of the first sub-electrode, the second sub-electrode, and the third sub-electrode along the first direction and the orthographic projection of the first sub-segment onto the substrate is greater than the distance along the first direction between the orthographic projection of the second sub-segment onto the substrate.

[0008] In some embodiments, the first sub-electrode includes a third portion and a fourth portion; the fourth portion is located on one side of the third portion along the second direction and is connected to the third portion. Wherein, in the orthographic projection of the third portion, the first sub-segment, and the second sub-segment onto the substrate, the distance between the third portion and the first sub-segment in the first direction is greater than the distance between the third portion and the second sub-segment in the first direction. The fourth portion and the third portion are flush with the ends of the third portion near the first sub-segment, and the end of the fourth portion near the second sub-segment extends beyond the edge of the third portion.

[0009] In some embodiments, the orthographic projection of the fourth portion onto the substrate at least partially overlaps with the orthographic projection of the second sub-segment onto the substrate.

[0010] In some embodiments, the orthographic projections of the first sub-electrode and the first sub-segment onto the substrate are spaced 0.5 μm to 1.5 μm apart along the first direction. And / or, the orthographic projections of the third portion and the second sub-segment onto the substrate are spaced 0.2 μm to 1 μm apart along the first direction. And / or, the portion of the fourth portion whose orthographic projection onto the substrate coincides with the orthographic projection of the second sub-segment onto the substrate has a dimension of 0.1 μm to 1 μm along the first direction.

[0011] In some embodiments, the second sub-electrode includes a fifth portion and a sixth portion. The sixth portion is located on one side of the fifth portion along the second direction and is connected to the fifth portion, with both ends of the sixth portion extending beyond the edge of the fifth portion along the first direction. In the orthographic projections of the fifth portion, the first sub-segment, and the second sub-segment onto the substrate, the distance between the fifth portion and the first sub-segment in the first direction is equal to the distance between the fifth portion and the second sub-segment in the first direction. The distance between the orthographic projection of the sixth portion onto the substrate and the orthographic projection of the first sub-segment onto the substrate along the first direction is greater than the distance between the orthographic projection of the second sub-segment onto the substrate along the first direction.

[0012] In some embodiments, in the orthographic projections of the fifth portion, the first sub-segment, and the second sub-segment onto the substrate, the spacing between the fifth portion and the first sub-segment along the first direction, and the spacing between the fifth portion and the second sub-segment along the first direction, are both 1 μm to 2 μm. And / or, the spacing between the orthographic projections of the sixth portion and the first sub-segment onto the substrate along the first direction is 0.2 μm to 1 μm. And / or, the spacing between the orthographic projections of the sixth portion and the second sub-segment onto the substrate along the first direction is 0 to 1 μm.

[0013] In some embodiments, in the orthographic projection of the third sub-electrode, the first sub-segment, and the second sub-segment onto the substrate, the boundaries of the third sub-electrode and the first sub-segment approaching each other are substantially parallel, and the boundaries of the third sub-electrode and the second sub-segment approaching each other are substantially parallel; the distance between the third sub-electrode and the first sub-segment along the first direction is greater than the distance between the third sub-electrode and the second sub-segment along the first direction.

[0014] In some embodiments, the orthographic projections of the third sub-electrode and the first sub-segment onto the substrate are spaced 0.2 μm to 1 μm apart along the first direction. And / or, the orthographic projections of the third sub-electrode and the second sub-segment onto the substrate are spaced 0 to 1 μm apart along the first direction.

[0015] In some embodiments, the array substrate further includes a first semiconductor layer, a first insulating layer, a first gate conductive layer, a second insulating layer, a source / drain conductive layer, a third insulating layer, a first planarization layer, and a second planarization layer disposed in a direction away from the substrate. The array substrate also includes a first via penetrating the first insulating layer and the second insulating layer, and a second via penetrating the first insulating layer, the second insulating layer, and the third insulating layer. The first transistor includes a first semiconductor pattern located on the first semiconductor layer and a gate pattern located on the first gate conductive layer. A first signal line is disposed on the source / drain conductive layer and is electrically connected to the first semiconductor pattern through the first via. A first sub-electrode is electrically connected to the first semiconductor pattern through the second via. The first planarization layer is disposed between the first sub-electrode and the second sub-electrode, and includes a third via that exposes a portion of the first sub-electrode; the second sub-electrode is electrically connected to the first sub-electrode through the third via. The second planarization layer is disposed on the side of the second sub-electrode away from the substrate, covering the portion of the second sub-electrode located within the third via, and exposing at least a portion of the second sub-electrode located on the first planarization layer. The third sub-electrode covers the second planarization layer and at least a portion of the second sub-electrode.

[0016] In some embodiments, the voltage signals transmitted on two adjacent first signal lines are of opposite electrical polarity.

[0017] In some embodiments, the array substrate further includes a first auxiliary layer. The first auxiliary layer is disposed between the film layer containing the first signal line and the film layer containing the first electrode. In the orthographic projection of the first auxiliary layer, the first signal line, and the first electrode onto the substrate, the first auxiliary layer at least partially overlaps with the first signal line, and / or the first auxiliary layer at least partially overlaps with the first electrode.

[0018] In some embodiments, the orthographic projection of the first auxiliary layer on the substrate covers the orthographic projection of the first signal line on the substrate, and at least partially does not coincide with the orthographic projection of the first electrode on the substrate.

[0019] In some embodiments, the first signal line includes a plurality of alternately connected first extensions and a plurality of second extensions. The first auxiliary layer is a mesh structure, and includes a plurality of first sub-parts, a plurality of second sub-parts, and a plurality of mesh holes. The plurality of first sub-parts extend along the second direction, and the orthographic projection of one first sub-part onto the substrate covers the orthographic projection of one of the second extensions onto the substrate. The plurality of second sub-parts extend along the first direction, and the orthographic projection of one second sub-part onto the substrate covers the orthographic projection of the plurality of first extensions arranged along the first direction onto the substrate. In the plurality of mesh holes, one mesh hole corresponds to one pixel region, and the mesh hole exposes at least a portion of the pixel region corresponding to the mesh hole.

[0020] In some embodiments, the array substrate further includes a second electrode. The second electrode is disposed on the side of the first electrode away from the substrate, and a storage capacitor is formed between the second electrode and the first electrode. The first auxiliary layer and the second electrode transmit the same voltage signal.

[0021] In some embodiments, the orthographic projection of the first auxiliary layer onto the substrate at least partially overlaps with the orthographic projection of the second electrode onto the substrate.

[0022] In some embodiments, in the orthographic projections of the second electrode and the first sub-part onto the substrate, the second electrode covers the first sub-part, and the boundary of the second electrode is spaced apart from the boundary of the first sub-part. The orthographic projection of the second electrode onto the substrate partially coincides with the orthographic projection of the second sub-part onto the substrate.

[0023] In some embodiments, the linewidth of the first signal line is 1 μm to 2 μm. And / or, the dimension of the first sub-part along the first direction is 1 μm to 2.5 μm. And / or, the dimension of the second sub-part along the second direction is 1 μm to 2 μm.

[0024] In some embodiments, the array substrate further includes a plurality of first transistors. Each first transistor is electrically connected to a first electrode, and a first terminal of the first transistor is electrically connected to the first signal line, and a second terminal is electrically connected to the first electrode. The first electrode includes a fourth sub-electrode and a fifth sub-electrode sequentially disposed along a direction away from the substrate. The fourth sub-electrode is electrically connected to the second terminal of the first transistor, and the fifth sub-electrode is electrically connected to the fourth sub-electrode.

[0025] In some embodiments, the array substrate further includes a first semiconductor layer, a first insulating layer, a first gate conductive layer, a second insulating layer, a source / drain conductive layer, a third insulating layer, a first planarization layer, a fourth insulating layer, and a second planarization layer disposed along a direction away from the substrate; and a first via penetrating the first insulating layer and the second insulating layer, and a fourth via penetrating the first insulating layer, the second insulating layer, the third insulating layer, the first planarization layer, and the fourth insulating layer. The first transistor includes a first semiconductor pattern located on the first semiconductor layer and a gate pattern located on the first gate conductive layer, and a first signal line disposed on the source / drain conductive layer. The first signal line passes through the first via and is electrically connected to the first semiconductor pattern. The fourth sub-electrode passes through the fourth via and is electrically connected to the first semiconductor pattern. The second planarization layer is disposed on the side of the fourth sub-electrode away from the substrate, covering the portion of the fourth sub-electrode located within the fourth via, and exposing at least a portion of the fourth sub-electrode located on the fourth insulating layer. The first auxiliary layer is disposed between the first planarization layer and the fourth insulating layer; the fifth sub-electrode covers the second planarization layer and at least a portion of the fourth sub-electrode.

[0026] In some embodiments, the array substrate further includes a plurality of first transistors, each first transistor being electrically connected to a first electrode, and a first electrode of the first transistor being electrically connected to the first signal line, and a second electrode being electrically connected to the first electrode. The array substrate further includes a plurality of compensation capacitors, at least a portion of which is disposed on the side of the first transistor near the substrate, and a first plate of the compensation capacitor being electrically connected to the second plate of the first transistor, and the second plate being electrically connected to a constant voltage signal terminal.

[0027] In some embodiments, the array substrate further includes a second electrode. The second electrode is disposed on the side of the first electrode away from the substrate, forming a capacitor with the first electrode. The second plate of the compensation capacitor transmits the same voltage signal as the second electrode.

[0028] In some embodiments, the array substrate includes a display area and a peripheral area, and the first transistor is disposed in the display area. The array substrate further includes a second semiconductor layer and a second gate layer disposed along a path away from the substrate, the second semiconductor layer and the second gate layer being located on the side of the first transistor closer to the substrate. The array substrate also includes a second transistor. The second transistor is disposed in the peripheral area and includes a second semiconductor pattern located in the second semiconductor layer and a second gate pattern located in the second gate layer. The first electrode of the compensation capacitor is located in the second semiconductor layer, and the second electrode is located in the second gate layer.

[0029] In some embodiments, the first transistor is an oxide thin-film transistor; and / or, the second transistor is a low-temperature polycrystalline silicon thin-film transistor.

[0030] In some embodiments, the second plate of the compensation capacitor extends along the first direction, and the orthographic projection of the second plate on the substrate at least partially coincides with the orthographic projection of the second signal line on the substrate.

[0031] In some embodiments, the dimension of the second signal line along the second direction is 1 μm to 2 μm. And / or, the dimension of the second electrode along the second direction is 1 μm to 3 μm.

[0032] On the other hand, a display panel is provided. The display panel includes an opposing substrate, a liquid crystal layer, and an array substrate as described in any of the above embodiments. The opposing substrate is disposed opposite to the array substrate; the liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0033] In another aspect, a display device is provided. The display device includes an array substrate as described in any of the above embodiments, or a display panel as described in the above embodiments. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0035] Figure 1 is a structural diagram of a display device according to some embodiments;

[0036] Figure 2 is another structural diagram of a display device according to some embodiments;

[0037] Figure 3 is a structural layout of an array substrate according to some embodiments;

[0038] Figure 4 is a structural layout of a first signal line, a second signal line, and a first electrode according to some embodiments;

[0039] Figure 5 is a magnified view of a portion of region A in Figure 4;

[0040] Figure 6 is an equivalent circuit diagram of an array substrate according to some embodiments;

[0041] Figure 7 is a structural diagram of a pixel region according to some embodiments;

[0042] Figure 8 is a cross-sectional view along section line AA in Figure 3;

[0043] Figure 9 is a structural diagram of a first sub-electrode according to some embodiments;

[0044] Figure 10 is another structural diagram of the first sub-electrode according to some embodiments;

[0045] Figure 11 is a structural diagram of a second sub-electrode according to some embodiments;

[0046] Figure 12 is a structural diagram of a third sub-electrode according to some embodiments;

[0047] Figure 13 is a structural layout of an array substrate according to some embodiments;

[0048] Figure 14 is a cross-sectional view along section line BB in Figure 13;

[0049] Figure 15 is a structural diagram of a first auxiliary layer, a first signal line, and a first electrode according to some embodiments;

[0050] Figure 16 is a magnified view of a portion of region C in Figure 15;

[0051] Figure 17 is a cross-sectional view along section line CC in Figure 13;

[0052] Figure 18 is a cross-sectional view along section line DD in Figure 13;

[0053] Figure 19 is a cross-sectional view along section line EE in Figure 13;

[0054] Figure 20 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0055] Figure 21 is another cross-sectional view of the array substrate according to some embodiments;

[0056] Figure 22 is a structural diagram of a compensation capacitor and a first transistor according to some embodiments. Detailed Implementation

[0057] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0058] Unless the context otherwise requires, throughout the specification and claims, the term “comprise” and its other forms, such as the third-person singular “comprises” and the present participle “comprising”, are interpreted as open and encompassing, that is, “including, but not limited to”.

[0059] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0060] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0061] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0062] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0063] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0064] In describing some embodiments, the terms "coupling" and "connection" and their derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "coupling" indicates, for example, that two or more components have direct physical or electrical contact, or it may refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0065] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0066] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0067] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0068] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0069] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0070] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0071] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0072] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0073] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0074] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD). From the perspective of the shape of the display device 1000, the display device 1000 can be a flat panel display device or a curved panel display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The following uses a rectangular and flat liquid crystal display device as an example to illustrate some embodiments of this disclosure. However, the embodiments of this disclosure are not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0075] In some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board. The driving circuit board may include, for example, a timing controller (TCON), a DC / DC power management chip, and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch control, photography, video recording, or fingerprint recognition; specific limitations are not specified here.

[0076] In some embodiments, referring to FIG2, when the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight 1200 disposed on the backlight side of the display panel 1100. Exemplarily, the backlight 1200 may be a direct-lit backlight or an edge-lit backlight, etc. The backlight 1200 is used to provide light to the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display panel 1100, thereby enabling each sub-pixel to display the same or different gray levels to achieve the purpose of image display.

[0077] Referring again to Figure 2, when the display panel 1100 is a liquid crystal display panel, the display panel 1100 may include an array substrate 100 and a counter substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200. The counter substrate 200 may also be referred to as a color filter substrate or an encapsulation substrate. The counter substrate 200 can filter the light incident on it, so that each sub-pixel emits light of a certain color (e.g., red, green, or blue). Different sub-pixels can emit the same or different colors of light, thereby enabling the display panel 1100 to achieve color display. Of course, the structure of the display panel 1100 is not limited to this; it may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the counter substrate 200 near the liquid crystal layer 300, etc.

[0078] In some embodiments, referring to Figures 3 and 4, the array substrate 100 further includes a plurality of first signal lines 10 and a plurality of second signal lines 20, which intersect to define a plurality of pixel regions 102. The plurality of first signal lines 10 are spaced apart along a first direction X, and the plurality of second signal lines 20 are spaced apart along a second direction Y. The plurality of first signal lines 10 and the plurality of second signal lines 20 may be located in different conductive layers to insulate them from each other and prevent short circuits. The orthographic projections of the plurality of first signal lines 10 and the plurality of second signal lines 20 onto the substrate 101 intersect to form a plurality of grids, each grid defining a pixel region 102.

[0079] For example, the first signal line 10 can be a data line for transmitting data signals, and the second signal line 20 can be a scan signal line for transmitting scan signals (for controlling whether the first transistor T1 is turned on). Of course, the embodiments of this disclosure are not limited to this, and the first signal line 10 and the second signal line 20 can both be used to transmit other signals, as long as the same technical concept is adopted.

[0080] As shown in Figure 4, multiple first signal lines 10 are spaced apart along the first direction X and partially bent along the second direction Y. In other words, the first signal lines 10 extend along a broken line, and the first signal lines 10 are broken lines. Thus, the centers Q of two adjacent pixel regions 102 located between the same two first signal lines 10 and along the second direction Y are staggered along the first direction X. For example, the line connecting the centers of the three closest pixel regions 102 forms a triangle; that is, multiple pixel regions 102 are arranged in a delta-staggered arrangement. This helps to increase the density of pixel regions 102 on the array substrate 100, thereby improving the pixel density of the display panel.

[0081] Referring to Figures 4 and 5, the first signal line 10 includes a first part 11 and a second part 12. One side of each pixel region 102 is the first part 11 of a first signal line 10, and the other side of the pixel region 102 is the second part 12 of another first signal line 10. In other words, the first part 11 and the second part 12 of two adjacent first signal lines 10 surround a pixel region 102. Because the first signal line 10 bends along the second direction Y, the length of the first part 11 is greater than the length of the second part 12. That is, the lengths of the portions of the two first signal lines 10 that enclose the same pixel region 102 are different.

[0082] In some embodiments, referring to FIG6, the array substrate 100 further includes a plurality of pixel circuits, each pixel circuit including at least one thin film transistor and at least one capacitor. Exemplarily, the pixel circuit can be a "1T1C" circuit, a "2T1C" circuit, or a "3T1C" circuit, etc. Here, "T" refers to a thin film transistor, and the number preceding "T" indicates the number of thin film transistors; "C" refers to a capacitor, and the number preceding "C" indicates the number of capacitors.

[0083] In the following embodiments of this disclosure, a "1T1C" pixel circuit is used as an example to illustrate the embodiments of this disclosure. However, the embodiments of this disclosure are not limited to this, and any other pixel circuit can be considered as long as the same technical concept is applied. In the case of a "1T1C" pixel circuit, the pixel circuit includes a first transistor T1 and a storage capacitor C1.

[0084] In this configuration, the control electrode of the first transistor T1 is connected to the second signal line 20, or the second signal line 20 directly forms the control electrode of the first transistor T1. The first electrode (one of the source and drain) of the first transistor T1 is electrically connected to the first signal line 10, and the second electrode (the other of the source and drain) of the first transistor T1 is electrically connected to one plate of the storage capacitor C1. For example, referring to FIG3, the second signal line 20 extends along a first direction X and is configured to form the gates of a plurality of first transistors T1 arranged along the first direction X.

[0085] In some embodiments, the first transistor T1 can be an oxide thin-film transistor (OTFT). This helps to reduce the leakage current of the first transistor T1 and increase the aperture ratio of the pixel area, thereby improving the light transmittance of the array substrate 100. Exemplarily, the first transistor T1 includes a first semiconductor pattern 103, the material of which may include indium gallium zinc oxide (IGZO).

[0086] Referring to Figures 3 and 6, the array substrate 100 further includes a plurality of first electrodes 30 and second electrodes 40. At least a portion of the first electrodes 30 and second electrodes 40 are disposed opposite to each other to form a storage capacitor C1, with the first electrode 30 forming one plate of the storage capacitor C1 and the second electrode 40 forming the other plate of the storage capacitor C1. Exemplarily, one of the first electrode 30 and the second electrode 40 may be a pixel electrode, and the other may be a common electrode. For example, the first electrode 30 may be a pixel electrode, and the second electrode 40 may be a common electrode.

[0087] For example, the second electrode of the first transistor T1 is electrically connected to the plate of the storage capacitor C1 formed by the first electrode 30, and the plate of the storage capacitor C1 formed by the second electrode 40 can be electrically connected to a constant voltage signal terminal (such as a common voltage signal terminal). The first transistor T1 is configured to transmit the data signal from the first signal line 10 to the first electrode 30 under the control of the second signal line 20, that is, to transmit the data signal to one plate of the storage capacitor C1.

[0088] In some embodiments, referring to Figures 5 and 6, at least a portion of the first electrode 30 is disposed within the pixel region 102, that is, at least a portion of the first electrode 30 is disposed between the first portion 11 and the second portion 12. As the pixel density of the display panel increases, the area of ​​the pixel region 102 in the array substrate 100 gradually decreases, and the spacing between the first electrode 30 and the adjacent first portion 11 and second portion 12 becomes smaller and smaller, resulting in the formation of parasitic capacitances between the first electrode 30 and the first portion 11 and the second portion 12. In embodiments of this disclosure, the parasitic capacitance formed between the first electrode 30 and the first portion 11 is designated as the first parasitic capacitance Cpd1, and the parasitic capacitance formed between the first electrode 30 and the second portion 12 is designated as the second parasitic capacitance Cpd2.

[0089] In some embodiments, the array substrate provided in this disclosure can be used to form a display panel with a pixel density greater than or equal to 1000 PPI. Exemplarily, the array substrate 100 can be used to form a display panel with a pixel density of 1000 PPI, 1200 PPI, 2000 PPI, or 2117 PPI or higher. Of course, the application scope of the array substrate 100 provided in the embodiments of this disclosure is not limited to this, and display panels with other pixel densities can be considered, as long as the same technical approach is adopted. Exemplarily, in the following embodiments of this disclosure, the array substrate 100 is configured to form a 2117 PPI display panel as an example to illustrate the embodiments of this disclosure. For example, when describing the dimensions of the array substrate 100 structure and the distance between two structures, the example is based on a 2117 PPI display panel.

[0090] The voltage ΔV1 generated by the coupling between the first parasitic capacitance Cpd1 and the first electrode 30 is given by this voltage. Vdata1, the voltage generated by the coupling between the second parasitic capacitance Cpd1 and the first electrode 30 is ΔV2. ΔVdata1 refers to the voltage change of the first signal line 10 (the first signal line 10 where the first part 11 is located) that forms the first parasitic capacitance Cpd1; ΔVdata2 refers to the voltage change of the first signal line 10 (the first signal line 10 where the second part 12 is located) that forms the first parasitic capacitance Cpd1. The voltage generated by the coupling of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 with the first electrode 30 is ΔV, where ΔV = ΔV1 + ΔV2. It can be seen that the voltage ΔV generated by the coupling of two adjacent first signal lines 10 (the first part 11 and the second part 12) with the first electrode 30 is positively correlated with the magnitude of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2, and negatively correlated with the magnitude of the storage capacitor C1.

[0091] In some embodiments, the voltage signals (e.g., data signals) transmitted by two adjacent first signal lines 10 are electrically opposite; that is, the voltage value of the data signal transmitted by one of the two adjacent first signal lines 10 is positive, and the voltage value of the data signal transmitted by the other is negative. In other words, multiple first signal lines 10 employ a column-inverting driving method. Thus, ΔV1 and ΔV2, one positive and one negative, help reduce the voltage ΔV generated by the coupling between the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 and the first electrode 30, thereby reducing voltage fluctuations in the first electrode 30; that is, it helps improve the voltage stability of the first electrode 30. This further reduces fluctuations in the electric field formed between the first electrode 30 and the second electrode 40, which helps reduce the risk of changes in the deflection direction of liquid crystal molecules in the liquid crystal layer during the same display stage (within one frame), ensuring the stability of the optical rotation direction of liquid crystal molecules within the pixel area, thereby reducing fluctuations in the light transmittance of the display panel, improving the stability of grayscale display in sub-pixels, and enhancing the display quality of the display panel.

[0092] In related technologies, the first electrode 30 is typically positioned midway between two adjacent first signal lines 10. This means the distance between the first electrode 30 and the first part 11 and the second part 12 in the first direction is approximately equal. Since the length of the first part 11 is greater than the length of the second part 12, and the side length of the portion of the first electrode 30 adjacent to the first part 11 is greater than the side length of the portion of the first electrode 30 adjacent to the second part 12, when the distance between the first electrode 30 and the first part 11 and the second part 12 is equal, the first parasitic capacitance Cpd1 formed between the first electrode 30 and the first part 11 is greater than the second parasitic capacitance Cpd2 formed between the first electrode 30 and the second part 12, i.e., Cpd1 > Cpd2. At this time, the voltage generated by the coupling of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 with the first electrode 30 is ΔV = ΔV1 + ΔV2 ≠ 0. In other words, the voltage signal transmitted on the first signal line 10 will cause crosstalk to the voltage on the first electrode 30, resulting in voltage fluctuations on the first electrode 30. Furthermore, voltage fluctuations in the first electrode 30 will affect the voltage difference between the first electrode 30 and the second electrode 40, which in turn will cause the deflection direction of the liquid crystal molecules in the liquid crystal layer to change within a display cycle, and cause the grayscale of the sub-pixel display to deviate, thus reducing the display quality of the display panel.

[0093] To address the aforementioned technical problems, the array substrate provided in the embodiments of this disclosure, referring to Figures 4 and 5, shows that for at least one pixel region 102, in the orthographic projection of the first electrode 30, the first portion 11, and the second portion 12 onto the substrate 101, the distance D1 between at least a portion of the first electrode 30 and the first portion 11 in the first direction X, and the distance D2 between the first electrode 30 and the second portion 12 in the first direction X, are not equal. This facilitates the balancing of the first parasitic capacitance Cpd1 formed between the first electrode 30 and the first portion 11, and the second parasitic capacitance Cpd2 formed between the first electrode 30 and the second portion 12, reducing the capacitance difference between the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2, and reducing the voltage ΔV generated by the coupling of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 together with the first electrode 30. Based on this, it is beneficial to reduce the voltage fluctuation of the first electrode 30 within a display cycle, improve the stability of the voltage difference between the first electrode 30 and the second electrode 40 within a display cycle, make the electric field formed between the first electrode 30 and the second electrode 40 more stable, reduce the change in the deflection direction of the liquid crystal molecules in the liquid crystal layer in the same display stage (within one frame), ensure the stability of the optical rotation direction of the liquid crystal molecules in the pixel area, reduce the fluctuation of the light transmittance of the display panel, and improve the display quality of the display panel.

[0094] For example, for each pixel region 102, in the orthographic projection of the first electrode 30, the first part 11 and the second part 12 on the substrate 101, the distance D1 between at least a portion of the first electrode 30 and the first part 11 in the first direction X, and the distance D2 between the first electrode 30 and the second part 12 in the first direction X are not equal.

[0095] In some embodiments, referring to Figures 4 and 5, the length of the first part 11 is greater than the length of the second part 12. In the orthographic projection of the first electrode 30, the first part 11, and the second part 12 onto the substrate 101, the boundary length between the first electrode 30 and the first part 11 is greater than the boundary length between the first electrode 30 and the second part 12. Based on this, the area directly opposite the first electrode 30 and the first part 11 is greater than the area directly opposite the first electrode 30 and the second part 12.

[0096] For example, as shown in FIG5, the boundary between the first electrode 30 and the first part 11 includes the left boundary, a portion of the upper boundary, and a portion of the lower boundary of the first electrode 30, and the boundary between the first electrode 30 and the second part 12 includes the right boundary of the first electrode 30. Obviously, the length of the boundary between the first electrode 30 and the first part 11 is greater than the length of the boundary between the first electrode 30 and the second part 12.

[0097] The magnitude of the parasitic capacitance formed between the first electrode 30 and the first part 11 and the second part 12 is positively correlated with the area of ​​the first electrode 30 facing the first part 11 and the second part 12, and negatively correlated with the distance between the first electrode 30 and the first part 11 and the second part 12. When the length of the first part 11 is greater than the length of the second part 12, the area of ​​the first electrode 30 facing the first part 11 is greater than the area of ​​the first electrode 30 facing the second part 12. The distance D1 between at least a portion of the first electrode 30 and the first part 11 in the first direction X is greater than the distance D2 between the first electrode 30 and the second part 12 in the first direction X. This helps to balance the first parasitic capacitance Cpd1 formed between the first electrode 30 and the first part 11 and the second parasitic capacitance Cpd2 formed between the first electrode 30 and the second part 12, reducing the capacitance difference between the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2, thereby reducing the voltage ΔV generated by the coupling of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 with the first electrode 30, and reducing the voltage fluctuation of the first electrode 30. This helps to improve the stability of the voltage difference between the first electrode 30 and the second electrode 40, so as to provide a more stable electric field. It also helps to reduce the change in the deflection direction of the liquid crystal molecules in the liquid crystal layer during the same display stage (within one frame), reduce the fluctuation of the light transmittance (grayscale) of the display panel, and improve the display quality of the display panel.

[0098] In some embodiments, referring to Figures 4 and 5, the first signal line 10 includes a plurality of alternating first extension segments 13 and a plurality of second extension segments 14. The plurality of first extension segments 13 extend along a first direction X and are spaced apart along a second direction Y; the plurality of second extension segments 14 extend along the second direction Y and are alternately connected to the two ends of the first extension segments 13 along the first direction X.

[0099] For the same pixel region 102, the first part 11 includes a second extension segment 14 and two first extension segments 13 connected to the second extension segment 14, and the second part 12 includes a second extension segment 14 adjacent to the first part 11. In the following embodiments of this disclosure, for ease of description, the second extension segment 14 included in the first part 11 is referred to as the first sub-segment 141, and the second extension segment 14 included in the second part 12 is referred to as the second sub-segment 142.

[0100] It should be noted that, as shown in Figure 4, the second extension segment 14 includes a pixel area 102 on each side along the first direction X. For two adjacent pixel areas 102 along the first direction X, the second extension segment 14 located between the two pixel areas 102 can serve as the first sub-segment 141 and the second sub-segment 142 of the two pixel areas 102, respectively. For example, for the first row of pixel areas 102 in Figure 4, the second extension segment 14 located between the two pixel areas 102 serves as both the second sub-segment 142 of the left pixel area 102 and the first sub-segment 141 of the right pixel area 102. For the second row of pixel areas 102 in Figure 4, the second extension segment 14 located between the two pixel areas 102 serves as both the first sub-segment 141 of the left pixel area 102 and the second sub-segment 142 of the left pixel area 102. In the following embodiments of this disclosure, unless otherwise specified, the description of the first electrode 30, the first sub-segment 141 and the second sub-segment 142 is based on the first electrode 30, the first sub-segment 141 and the second sub-segment 142 of the same pixel area 102.

[0101] Referring to Figures 4 and 5, for the same pixel area 102, in the orthogonal projections of the first electrode 30, the first sub-segment 141, and the second sub-segment 142 onto the substrate 101, at least a portion of the first electrode 30 is at a distance D1 from the first sub-segment 141 along the first direction X, which is greater than the distance D2 from the second sub-segment 142 along the first direction X. This is beneficial for increasing the spacing between the first electrode 30 and the first portion 11, thereby reducing the capacitance difference between the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2, reducing the voltage ΔV generated by the coupling of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 with the first electrode 30, reducing the voltage fluctuation of the first electrode 30, and reducing the change in the electric field between the first electrode 30 and the second electrode 40, which is beneficial for improving the display quality of the display panel.

[0102] In some embodiments, referring to Figures 3, 7, and 8, the first electrode 30 includes a first sub-electrode 31, a second sub-electrode 32, and a third sub-electrode 33 disposed along a direction away from the substrate 101. The first sub-electrode 31 is electrically connected to the second electrode of the first transistor T1, the second sub-electrode 32 is electrically connected to the first sub-electrode 31, and the third sub-electrode 33 is electrically connected to the second sub-electrode 32.

[0103] In some embodiments, referring to FIG8, the array substrate 100 may include a first semiconductor layer ACT1, a first insulating layer GI, a first gate conductive layer Gate1, a second insulating layer ILD, a source / drain conductive layer SD, a third insulating layer PVX1, a first planarization layer PLN1, and a second planarization layer PLN2 disposed along a direction away from the substrate 101 (from bottom to top in FIG8). The array substrate 100 also includes a first via K1 penetrating the first insulating layer GI and the second insulating layer ILD; a second via K2 penetrating the first insulating layer GI, the second insulating layer ILD, and the third insulating layer PVX1; and a third via K3 penetrating the first planarization layer PLN1.

[0104] The material of the first semiconductor layer ACT1 may include one or more of amorphous silicon, polycrystalline silicon, metal oxide materials, and metal oxide nitrides. Among them, the metal oxide materials include, but are not limited to, one or more of: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0105] Metal oxynitride materials include, but are not limited to, at least one of: zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, and silicon oxynitride. Polycrystalline silicon may include low-temperature polycrystalline silicon (LTPS).

[0106] The material of the first semiconductor layer ACT1 can be amorphous, partially crystalline, single-crystal, or polycrystalline, and can also be a single-layer or multi-layer structure.

[0107] The first transistor T1 includes a first semiconductor pattern 103 located in the first semiconductor layer ACT1 and a first gate pattern 104 located in the first gate conductive layer Gtae1. The first semiconductor pattern 103 may include a channel region and a first electrode region and a second electrode region located on both sides of the channel region. The orthographic projection of the channel region on the substrate 101 coincides with the orthographic projection of the first gate pattern 104 on the substrate 101. One of the first electrode region and the second electrode region is configured to form the first electrode of the first transistor T1, and the other is configured to form the second electrode of the first transistor T1. For example, as shown in FIG8, the first electrode region is located on the left side of the channel region, used to form the first electrode of the first transistor T1, and used to be electrically connected to the first signal line 10; the second electrode region is located on the right side of the channel region, used to form the second electrode of the first transistor T1, and used to be electrically connected to the first electrode 30.

[0108] A first signal line 10 is disposed on the source / drain conductive layer SD, and the first signal line 10 passes through a first via K1 and is electrically connected to the first semiconductor pattern 103 (first polar region). At least a portion of the first sub-electrode 31 is disposed between the third insulating layer PVX1 and the first planarization layer PLN1, and a portion of the first sub-electrode 31 passes through a second via K2 and is electrically connected to the first semiconductor pattern 103 (second polar region). The orthographic projection of the third via K3 on the substrate 101 does not coincide with the orthographic projection of the second via K2 on the substrate 101, thereby reducing the depth of the third via K3 and improving the flatness of the second sub-electrode 32. The third via K3 exposes a portion of the first sub-electrode 31, and the second sub-electrode 32 passes through the third via K3 and is electrically connected to the first sub-electrode 31.

[0109] The array substrate 100 further includes a second planarization layer PLN2, which is disposed on the side of the second sub-electrode 32 away from the substrate 101. The second planarization layer PLN2 covers the portion of the second sub-electrode 32 located within the third via K3 and exposes at least a portion of the second sub-electrode 32 located on the first planarization layer PLN1. A third sub-electrode 33 covers the second planarization layer PLN2 and at least a portion of the second sub-electrode 32 for electrical connection with the second sub-electrode 32. The second planarization layer PLN2 increases the flatness of the surface of the third sub-electrode 33. For example, the surface of the second planarization layer PLN2 away from the substrate 101 is flush or substantially flush with the surface of the second sub-electrode 32 away from the substrate 101, thus greatly improving the flatness of the surface of the third sub-electrode 33. This facilitates the formation of a storage capacitor C1 between the third sub-electrode 33 and the second electrode 40.

[0110] In some embodiments, continuing to refer to FIG8, the first gate conductive layer Gate1 can be a stacked structure. Exemplarily, the first gate conductive layer Gate1 may include a first material layer G1 and a second material layer G2 stacked together. The material of the first material layer G1 may include a transparent conductive material, and the material of the second material layer G2 may include a metallic material. Exemplarily, the transparent conductive material may include, for example, indium tin oxide (ITO); the second material layer G2 may include a single metallic material, or may include a metallic stack. For example, the metallic stack may include one of the following: titanium-aluminum-titanium (Ti / Al / Ti) stack, molybdenum-aluminum (Mo / Al) stack, molybdenum-aluminum-molybdenum (Mo / Al / Mo) stack, molybdenum-niobium-titanium (MoNb / Ti) stack, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stack, molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) stack, molybdenum-neodymium-copper stack, MoNb-copper-MoNb stack, and AlNb-molybdenum-AlNd stack.

[0111] In some embodiments, referring to FIG8, the array substrate 100 may further include a fifth insulating layer PVX3 disposed between the third sub-electrode 33 and the fourth electrode 40. The fifth insulating layer PVX3 is used to isolate the third sub-electrode 33 and the fourth electrode 40, preventing a short circuit between the third sub-electrode 33 and the fourth electrode 40. The array substrate 100 may further include a sixth insulating layer 110 covering the fourth electrode 40, the sixth insulating layer 110 being used to protect the fourth electrode 40.

[0112] In some embodiments of this disclosure, as shown in FIG8, the first electrode 30 includes a first sub-electrode 31, a second sub-electrode 32, and a third sub-electrode 33. On the one hand, this can reduce the depth of the second via K2 and the third via K3, reduce the difficulty of the first sub-electrode 31 climbing the sidewall of the second via K2, and improve the connection reliability between the first sub-electrode 31 and the semiconductor pattern 103. On the other hand, it can reduce the difficulty of the second sub-electrode 31 climbing the sidewall of the third via K3, and improve the connection reliability between the second sub-electrode 32 and the first sub-electrode 31. The third sub-electrode 33 is filled with a second planarization layer PLN2 between it and the second sub-electrode 32, which helps to improve the flatness of the third sub-electrode 33.

[0113] The distance between the orthographic projection of at least a portion of at least one of the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 onto the substrate 101 and the orthographic projection of the first sub-segment 141 onto the substrate 101 along the first direction X is greater than the distance between the orthographic projection of the second sub-segment 142 onto the substrate 101 along the first direction X. This reduces the parasitic capacitance formed between at least one of the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 and the first sub-segment 141. This helps to reduce the capacitance difference between the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2, and reduces the voltage ΔV generated by the coupling of the first parasitic capacitance Cpd1 and the second parasitic capacitance Cpd2 with the first electrode 30. This improves the stability of the voltage difference between the first electrode 30 and the second electrode 40, thereby enhancing the display quality of the display panel.

[0114] For example, in the orthogonal projection of the first sub-segment 141, the second sub-segment 142, the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 onto the substrate 101, a portion or all of one of the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 (e.g., the first sub-electrode 31, the second sub-electrode 32, or the third sub-electrode 33) may be at a distance greater than the distance to the second sub-segment 142 from the first sub-segment 141, and the other two may be at a distance equal to the distance to the second sub-segment 142 from the first sub-segment 141. Alternatively, a portion or all of two of the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 (e.g., the first sub-electrode 31 and the second sub-electrode 32, or the first sub-electrode 31 and the third sub-electrode 33, or the second sub-electrode 32 and the third sub-electrode 33) may be at a distance greater than the distance to the second sub-segment 142 from the first sub-segment 141, and the other may be at a distance equal to the distance to the second sub-segment 142 from the first sub-segment 141. Alternatively, the distances between the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 and the first sub-segment 141 may be partially or completely greater than the distances between them and the second sub-segment 142.

[0115] In some embodiments, referring to FIG9, the first sub-electrode 31 includes a third portion 311 and a fourth portion 312. The fourth portion 312 is located on one side of the third portion 311 along the second direction Y and is connected to the third portion 311. Exemplarily, the fourth portion 312 is located above the third portion 311. In the orthographic projection of the third portion 311, the first sub-segment 141, and the second sub-segment 142 onto the substrate 101, the distance D3 between the third portion 311 and the first sub-segment 141 in the first direction X is greater than the distance D4 between the third portion 311 and the second sub-segment 142 in the first direction X. The ends of the fourth portion 312 and the third portion 311 near the first sub-segment 141 are flush, and the end of the fourth portion 312 near the second sub-segment 142 extends beyond the edge of the third portion 311. The distance between the fourth portion 312 and the first sub-segment 141 in the first direction X is also D3, and the distance between the fourth portion 312 and the second sub-segment 142 is less than D4. In this way, the two parasitic capacitances generated between the first sub-electrode 31 and the first part 11 and the second part 12 can be balanced to a great extent, reducing the capacitance difference between the parasitic capacitances generated between the first sub-electrode 31 and the first part 11 and the second part 12, reducing the voltage generated by the coupling of the two parasitic capacitances with the first sub-electrode 31, which is beneficial to improving the voltage stability of the first electrode 30.

[0116] For example, the orthographic projections of the fourth portion 312 and the third via K3 on the substrate 101 coincide, and the fourth portion 312 is configured to connect to the semiconductor pattern 103 through the third via K3. Along the first direction X, the size of the fourth portion 312 is larger than the size of the third portion 312, which helps reduce the difficulty of aligning the fourth portion 312 with the third via K3, allowing the fourth portion 312 to cover the third via K3 and connect to the semiconductor pattern 103 through the third via K3, thereby improving the connection reliability between the first sub-electrode 312 and the semiconductor pattern 103.

[0117] In some embodiments, referring to FIG10, the orthographic projection of the fourth portion 312 on the substrate 101 at least partially overlaps with the orthographic projection of the second sub-segment 142 on the substrate 101. This is beneficial to further increase the size of the parasitic capacitance formed between the fourth portion 312 and the second sub-segment 142, further balance the two parasitic capacitances between the first sub-electrode 31 and the first portion 11 and the second portion 12 (second sub-segment 142), reduce the capacitance difference between the two parasitic capacitances formed between the first sub-electrode 31 and the first portion 11 and the second portion 12, reduce the voltage generated by the coupling of the two parasitic capacitances with the first sub-electrode 31, and help reduce the voltage fluctuation of the first electrode 30 and improve the voltage stability of the first electrode 30.

[0118] In some embodiments, referring to Figures 9 and 10, the orthogonal projections of the first sub-electrode 31 and the first sub-segment 141 on the substrate 101 have a spacing D3 of 0.5 μm to 1.5 μm along the first direction X. This is beneficial for increasing the spacing between the first sub-electrode 31 and the first sub-segment 141 and reducing the size of the parasitic capacitance generated between the first sub-electrode 31 and the first sub-segment 141.

[0119] For example, the value of D3 can range from 0.5μm to 0.8μm, such as 0.5μm, 0.6μm, 0.7μm, or 0.8μm. Alternatively, the value of D3 can range from 0.8μm to 1.2μm, such as 0.8μm, 0.95μm, 1μm, or 1.2μm. Or, the value of D3 can range from 1.2μm to 1.5μm, such as 1.2μm, 1.3μm, 1.4μm, or 1.15μm. Of course, the value of D3 is not limited to these, and the embodiments of this disclosure will not list them all.

[0120] The orthographic projection of the third part 311 and the second sub-segment 142 onto the substrate 101 has a spacing D4 of 0.2 μm to 1 μm along the first direction X. This helps to reduce the spacing between the third part 311 and the first sub-segment 141, thereby reducing the size of the parasitic capacitance generated between the third part 311 and the first sub-segment 141.

[0121] For example, the value of D4 can range from 0.2μm to 0.4μm, such as 0.2μm, 0.3μm, 0.35μm, or 0.4μm. Alternatively, the value of D4 can range from 0.4μm to 0.7μm, such as 0.4μm, 0.55μm, 0.6μm, or 0.7μm. Or, the value of D4 can range from 0.7μm to 1μm, such as 0.7μm, 0.8μm, 0.85μm, or 1μm. Of course, the value of D4 is not limited to these, and the embodiments of this disclosure will not list them all.

[0122] The portion of the fourth part 312 whose orthographic projection on the substrate 101 coincides with the orthographic projection of the second sub-segment 142 on the substrate 101 has a dimension D5 of 0.1 μm to 1 μm along the first direction X. This increases the facing area between the fourth part 312 and the second sub-segment 142, thereby increasing the parasitic capacitance between them. This balances the two parasitic capacitances generated between the first sub-electrode 31 and the first part 11 and the second part 12, reducing the capacitance difference between them and lowering the voltage generated by the coupling of these two parasitic capacitances with the first sub-electrode 31. This improves the voltage stability of the first electrode 30.

[0123] For example, the value of D5 can range from 0.1 μm to 0.4 μm, such as 0.1 μm, 0.2 μm, 0.35 μm, or 0.4 μm. Alternatively, the value of D5 can range from 0.4 μm to 0.7 μm, such as 0.4 μm, 0.5 μm, 0.65 μm, or 0.7 μm. Or, the value of D5 can range from 0.7 μm to 1 μm, such as 0.7 μm, 0.85 μm, 0.9 μm, or 1 μm. Of course, the value of D5 is not limited to these, and the embodiments of this disclosure will not list them all.

[0124] It should be noted that, in addition to forming a parasitic capacitance with the first sub-segment 141 of the first part 11, the fourth part 312 can also form a parasitic capacitance with the first extension segment 13 of the first part 11. Increasing or decreasing the size of the parasitic capacitance between the fourth part 312 and the second sub-segment 142 helps to reduce the capacitance difference between the two parasitic capacitances formed between the fourth part 312 and the first part 11 and the second part 12, respectively.

[0125] In one example, the orthographic projections of the first sub-electrode 31 and the first sub-segment 141 onto the substrate 101 have a spacing D3 of 0.95 μm along the first direction X. The orthographic projections of the third portion 311 and the second sub-segment 142 onto the substrate 101 have a spacing D4 of 0.55 μm along the first direction X. The portion of the fourth portion 312 whose orthographic projection onto the substrate 101 overlaps with the orthographic projection of the second sub-segment 142 onto the substrate 101 has a dimension D5 of 0.25 μm along the first direction X. This significantly reduces the capacitance difference between the two parasitic capacitors formed between the first sub-electrode 31 and the first portion 11 and the second portion 12, for example, making the capacitances of the two parasitic capacitors formed between the first sub-electrode 31 and the first portion 11 and the second portion 12 equal.

[0126] In some embodiments, referring to FIG11, the second sub-electrode 32 includes a fifth portion 321 and a sixth portion 322. The sixth portion 322 is located on one side of the fifth portion 321 along the second direction Y and is connected to the fifth portion 321. Exemplarily, the sixth portion 322 may be located above the fifth portion 321.

[0127] As shown in Figure 11, the distance D7 between the orthographic projection of the sixth part 322 on the substrate 101 and the orthographic projection of the first sub-segment 141 on the substrate 101 along the first direction X is greater than the distance D8 between the orthographic projection of the sixth part 322 on the substrate 101 and the orthographic projection of the second sub-segment 142 on the substrate 101 along the first direction X, i.e., D7 > D8. This can greatly balance the two parasitic capacitances generated between the second sub-electrode 32 and the first part 11 and the second part 12, respectively, reducing the capacitance difference between the two parasitic capacitances generated between the second sub-electrode 32 and the first part 11 and the second part 12, and reducing the voltage fluctuations caused by the coupling of the two parasitic capacitances with the second sub-electrode 32. This is beneficial to improving the stability of the first electrode 30, thereby improving the display quality of the display panel.

[0128] Referring again to Figure 11, in the orthographic projection of the fifth portion 321, the first sub-segment 141, and the second sub-segment 142 onto the substrate 101, the distance D6 between the fifth portion 321 and the first sub-segment 141 in the first direction X is equal to the distance D6 between the fifth portion 321 and the second sub-segment 142 in the first direction X. That is, the fifth portion 321 of the second sub-electrode 32 is located at the midpoint between the first sub-segment 141 and the second sub-segment 142.

[0129] In some embodiments, the orthographic projection of the fifth portion 321 onto the substrate 101 partially coincides with the orthographic projection of the third via K3 onto the substrate 101, and the fifth portion 321 is electrically connected to the first sub-electrode 31 through the third via K3. That is, the fifth portion 321 is configured to be electrically connected to the first sub-electrode 31. The sixth portion 322 is in direct contact with the third sub-electrode 33, and the sixth portion 322 is configured to be electrically connected to the third sub-electrode 33.

[0130] The sixth portion 322 extends beyond the edges of the fifth portion 321 at both ends along the first direction X. That is, the dimension L1 of the fifth portion 321 along the first direction X is smaller than the dimension L2 of the sixth portion 322 along the first direction X, i.e., L1 < L2. In other words, the distance D6 between the fifth portion 321 and the first sub-segment 141 (or the second sub-segment 142) along the first direction X is smaller than the distance D7 between the orthographic projections of the sixth portion 322 and the first sub-segment 141 onto the substrate 101 along the first direction X, and smaller than the distance D8 between the orthographic projections of the sixth portion 322 and the second sub-segment 142 onto the substrate 101 along the first direction X. That is, D6 < D7 and D6 < D8.

[0131] Based on this, on the one hand, the distance D6 between the fifth part 321 and the first sub-segment 141 and the second sub-segment 142 in the first direction X can be greatly reduced, thereby reducing the two parasitic capacitances formed between the fifth part 321 and the first sub-segment 141 and the second sub-segment 142, reducing the capacitance of the two parasitic capacitances formed between the second sub-electrode 32 and the first part 11 and the second part 12, and thus reducing the capacitance difference between the two parasitic capacitances formed between the second sub-electrode 31 and the first part 11 and the second part 12, and reducing the voltage generated by the coupling of the two parasitic capacitances with the second sub-electrode 32. On the other hand, it is beneficial to increase the area of ​​the sixth part 322. The sixth part 322 is configured to contact and connect with the third sub-electrode 33, which is beneficial to increase the contact area between the sixth part 322 and the third sub-electrode 33 and reduce the contact resistance between the sixth part 322 and the third sub-electrode 33.

[0132] In some embodiments, referring to FIG11, the orthographic projection of the fifth portion 321 on the substrate 101 and the orthographic projections of the first sub-segment 141 and the second sub-segment 142 on the substrate 101 are spaced apart by a distance D6 along the first direction X by 1 μm to 2 μm. This significantly reduces the capacitance of the two parasitic capacitances formed between the fifth portion 321 and the first sub-segment 141 and the second sub-segment 142, respectively.

[0133] For example, the value range of D6 can be 1μm to 1.3μm; for example, the value of D6 can be 1μm, 1.1μm, 1.25μm, or 1.3μm, etc. Alternatively, the value range of D6 can be 1.3μm to 1.7μm; for example, the value of D6 can be 1.3μm, 1.4μm, 1.55μm, or 1.7μm, etc. Alternatively, the value range of D6 can be 1.7μm to 2μm; for example, the value of D6 can be 1.7μm, 1.85μm, 1.9μm, or 2μm, etc. Of course, the value of D6 is not limited to these, and the embodiments of this disclosure will not be listed one by one.

[0134] Referring again to Figure 11, the spacing D7 between the orthographic projections of the sixth portion 322 and the first sub-segment 141 onto the substrate 101 along the first direction X is 0.2 μm to 1 μm. This helps to reduce the capacitance of the parasitic capacitance formed between the sixth portion 322 and the first sub-segment 141, and helps to balance the capacitance difference between the two parasitic capacitances formed between the sixth portion 322 and the first portion 11 and the second portion 12, respectively.

[0135] For example, the value range of D7 can be 0.2μm to 0.5μm; for example, the value of D7 can be 0.2μm, 0.35μm, 0.4μm, or 0.5μm, etc. Alternatively, the value range of D7 can be 0.5μm to 0.8μm; for example, the value of D7 can be 0.5μm, 0.55μm, 0.6μm, or 0.8μm, etc. Alternatively, the value range of D7 can be 0.8μm to 1μm; for example, the value of D7 can be 0.8μm, 0.85μm, 0.9μm, or 1μm, etc. Of course, the value of D7 is not limited to these, and the embodiments of this disclosure will not be listed one by one.

[0136] The distance D8 between the orthographic projections of the sixth part 322 and the second sub-segment 142 onto the substrate 101 along the first direction X is 0 to 1 μm. This is beneficial for increasing the capacitance of the parasitic capacitance formed between the sixth part 322 and the second sub-segment 142, and for balancing the capacitance difference between the two parasitic capacitances formed between the sixth part 322 and the first part 11 and the second part 12, respectively.

[0137] For example, the value range of D8 can be 0μm to 0.3μm; for example, the value of D8 can be 0μm, 0.15μm, 0.2μm, or 0.3μm, etc. Alternatively, the value range of D8 can be 0.3μm to 0.7μm; for example, the value of D8 can be 0.3μm, 0.55μm, 0.6μm, or 0.7μm, etc. Alternatively, the value range of D8 can be 0.7μm to 1μm; for example, the value of D8 can be 0.7μm, 0.85μm, 0.9μm, or 1μm, etc. Of course, the value of D8 is not limited to these, and the embodiments of this disclosure will not be listed one by one.

[0138] It should be noted that, in addition to forming a parasitic capacitance with the first sub-segment 141 of the first part 11, the sixth part 322 can also form a parasitic capacitance with the first extension segment 13 of the first part 11. Increasing or decreasing the size of the parasitic capacitance between the sixth part 322 and the second sub-segment 142 helps to reduce the capacitance difference between the two parasitic capacitances formed between the sixth part 322 and the first part 11 and the second part 12, respectively.

[0139] In one example, the orthographic projection of the fifth portion 321 onto the substrate 101 is 1.45 μm apart along the first direction X with the orthographic projections of the first sub-segment 141 and the second sub-segment 142 onto the substrate 101; the orthographic projection of the sixth portion 322 and the first sub-segment 141 onto the substrate 101 is 0.55 μm apart along the first direction X with the first direction X with the first direction X with the first direction X with the first direction X with the first direction X with the first direction X with the second ... first direction X with the second direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second direction X with the first direction X with the second

[0140] In some embodiments, referring to FIG12, in the orthographic projection of the third sub-electrode 33, the first sub-segment 141, and the second sub-segment 142 onto the substrate 101, the boundaries of the third sub-electrode 33 and the first sub-segment 141 that approach each other are approximately parallel, and the boundaries of the third sub-electrode 33 and the second sub-segment 142 that approach each other are also approximately parallel. That is, the spacing between different portions of the third sub-electrode 33 along the second direction Y and the first sub-segment 141 is uniformly equal, and the spacing between the third sub-electrode 33 and the second sub-segment 142 is uniformly equal. This facilitates the formation of a regular morphology for the third sub-electrode 33, and since the shape of the third sub-electrode 33 is similar to that of the pixel region 102, it is beneficial to form a regularly shaped pixel region 102.

[0141] Referring to Figure 12, the distance D9 between the third sub-electrode 33 and the first sub-segment 141 along the first direction X is greater than the distance D10 between the third sub-electrode 33 and the second sub-segment 142 along the first direction X. This helps to balance the capacitance of the two parasitic capacitors formed between the third sub-electrode 33 and the first part 11 and the second part 12 (second sub-segment 142), reduce the capacitance difference between the two parasitic capacitors formed between the third sub-electrode 33 and the first part 11 and the second part 12, reduce the voltage fluctuations caused by the coupling of the two parasitic capacitors with the third sub-electrode 33, and improve the stability of the voltage difference between the first electrode 30 and the second electrode 40, thereby improving the display quality of the display panel.

[0142] In some embodiments, referring to FIG12, the orthographic projections of the third sub-electrode 33 and the first sub-segment 141 on the substrate 101 have a spacing D9 of 0.2 μm to 1 μm along the first direction X. This is beneficial for increasing the spacing between the third sub-electrode 33 and the first sub-segment 141, reducing the capacitance of the parasitic capacitance formed between the third sub-electrode 33 and the first sub-segment 141, and thereby balancing the capacitance difference between the two parasitic capacitances formed between the third sub-electrode 33 and the first part 11 and the second part 12, respectively.

[0143] For example, the value range of D9 can be 0.2μm to 0.5μm; for example, the value of D9 can be 0.2 μm, 0.35μm, 0.4μm, or 0.5μm, etc. Alternatively, the value range of D9 can be 0.5μm to 0.8μm; for example, the value of D9 can be 0.5μm, 0.55μm, 0.7μm, or 0.8μm, etc. Alternatively, the value range of D9 can be 0.8μm to 1μm; for example, the value of D9 can be 0.8μm, 0.9μm, 0.95μm, or 1μm, etc. Of course, the value of D9 is not limited to these, and the embodiments of this disclosure will not list them all.

[0144] The orthographic projections of the third sub-electrode 33 and the second sub-segment 142 onto the substrate 101 have a spacing D10 of 0–1 μm along the first direction X. This is beneficial for reducing the spacing between the third sub-electrode 33 and the second sub-segment 142, increasing the capacitance of the parasitic capacitance formed between the third sub-electrode 33 and the second sub-segment 142, and thereby balancing the capacitance difference between the two parasitic capacitances formed between the third sub-electrode 33 and the first part 11 and the second part 12, respectively.

[0145] For example, the value range of D10 can be 0μm to 0.4μm; for example, the value of D10 can be 0μm, 0.15μm, 0.2μm, or 0.4μm, etc. Alternatively, the value range of D10 can be 0.4μm to 0.7μm; for example, the value of D10 can be 0.4μm, 0.55μm, 0.6μm, or 0.7μm, etc. Alternatively, the value range of D10 can be 0.7μm to 1μm; for example, the value of D10 can be 0.7μm, 0.85μm, 0.9μm, or 1μm, etc. Of course, the value of D10 is not limited to these, and the embodiments of this disclosure will not list them all.

[0146] It should be noted that, in addition to forming a parasitic capacitance with the first sub-segment 141 of the first part 11, the third sub-electrode 33 can also form a parasitic capacitance with the first extension segment 13 of the first part 11. Increasing or decreasing the size of the parasitic capacitance between the third sub-electrode 33 and the second sub-segment 142 is beneficial for reducing the capacitance difference between the two parasitic capacitances formed between the third sub-electrode 33 and the first part 11 and the second part 12, respectively.

[0147] In one example, the orthographic projections of the third sub-electrode 33 and the first sub-segment 141 onto the substrate 101 have a spacing D9 of 0.55 μm along the first direction X, and the orthographic projections of the third sub-electrode 33 and the second sub-segment 142 onto the substrate 101 have a spacing D10 of 0.15 μm along the first direction X. This significantly reduces the capacitance difference between the two parasitic capacitors formed between the third sub-electrode 33 and the first part 11 and the second part 12, for example, making the capacitances of the two parasitic capacitors formed between the third sub-electrode 33 and the first part 11 and the second part 12 equal.

[0148] It should be noted that the above-described embodiments regarding the structures of the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33, as well as their relative positions to the first part 11 and the second part 12, can be implemented individually or in any suitable combination, as long as the same technical concept is adopted. For example, one or both of the first sub-electrode 31, the second sub-electrode 32, and the third sub-electrode 33 can adopt the implementation methods described in the above embodiments, while the remaining two or one can adopt other suitable implementation methods. For instance, the structures of the first sub-electrode 31 and the second sub-electrode 32, and their relative positions to the first part 11 and the second part 12, can adopt the embodiments described above, and the orthographic projection of the third sub-electrode 33 on the substrate 101 can be located in the middle of the orthographic projections of the first sub-segment 141 and the second sub-segment 142 on the substrate 101. Of course, the embodiments of this disclosure are not limited to these, and any combination of the above-described embodiments can be used, which will not be elaborated upon here.

[0149] In some embodiments, referring to Figures 13, 14, and 15, the array substrate 100 further includes a first auxiliary layer 50, which is disposed between the film layer (source / drain conductive layer SD) containing the first signal line 10 and the film layer containing the first electrode 30. In other words, during the fabrication of the array substrate 100, the first signal line 10 is formed first, then the first auxiliary layer 50 is formed, and finally the first electrode 30 is formed. The first auxiliary layer 50 is not necessarily located between the first signal line 10 and the first electrode 30 along a direction perpendicular to the substrate 101. For example, at the location where the first electrode 30 is connected to the first transistor T1, a portion of the first electrode 30 is closer to the substrate 101 than the first auxiliary layer 50.

[0150] Referring to Figures 14 and 15, in the orthographic projection of the first auxiliary layer 50, the first signal line 10, and the first electrode 30 onto the substrate 101, the first auxiliary layer 50 at least partially overlaps with the first signal line 10, and / or the first auxiliary layer 50 at least partially overlaps with the first electrode 30. Thus, the first auxiliary layer 50 can shield at least a portion of the first signal line 10, and / or at least a portion of the first electrode 30, thereby reducing the capacitance of the parasitic capacitance formed between the first signal line 10 and the first electrode 30, and reducing the capacitance of the two parasitic capacitances (first parasitic capacitance Cpd1 and second parasitic capacitance Cpd2) generated between the first electrode 30 and the first part 11 and the second part 12, respectively. This reduces the capacitance difference between the two parasitic capacitances, which helps to reduce voltage fluctuations of the first electrode 30, improves the voltage stability of the first electrode 30, and ultimately improves the display quality of the display panel.

[0151] For example, in the orthographic projection of the first auxiliary layer 50, the first signal line 10, and the first electrode 30 onto the substrate 101, the first auxiliary layer 50 at least partially overlaps with the first signal line 10, and the first auxiliary layer 50 does not overlap with the first electrode 30. Alternatively, the first auxiliary layer 50 does not overlap with the first signal line 10, but the first auxiliary layer 50 at least partially overlaps with the first electrode 30. Alternatively, the first auxiliary layer 50 at least partially overlaps with the first signal line 10, and the first auxiliary layer 50 at least partially overlaps with the first electrode 30.

[0152] In some embodiments, referring to Figures 14 and 15, the orthographic projection of the first auxiliary layer 50 on the substrate 101 covers the orthographic projection of the first signal line 10 on the substrate 101. This significantly reduces the capacitance of the parasitic capacitance generated between the first signal line 10 and the first electrode 30, thereby reducing the capacitance difference between the two parasitic capacitances (first parasitic capacitance Cpd1 and second parasitic capacitance Cpd2) generated between the first electrode 30 and two adjacent first signal lines 10. This helps reduce voltage fluctuations in the first electrode 30, improves voltage stability, and ultimately enhances the display quality of the display panel. The orthographic projection of the first auxiliary layer 50 on the substrate 101 does not at least partially overlap with the orthographic projection of the first electrode 30 on the substrate 101. This reduces the area of ​​the first auxiliary layer 50 within the pixel region 102, reducing the occlusion of light within the pixel region 102 by the first auxiliary layer 50. This helps improve the light transmittance of the array substrate and thus enhances the light extraction efficiency of the display panel.

[0153] For example, referring to FIG15, the orthographic projection of the first auxiliary layer 50 on the substrate 101 does not coincide with the orthographic projection of the first electrode 30 on the substrate 101. In this way, the area of ​​the first auxiliary layer 50 in the pixel area 102 can be greatly reduced, and the occlusion of the first auxiliary layer 50 in the pixel area 102 can be greatly reduced, which is beneficial to improving the light extraction efficiency of the array substrate.

[0154] In some embodiments, referring to Figures 15 and 16, the first signal line 10 includes a plurality of alternately connected first extensions 13 and a plurality of second extensions 14. The first auxiliary layer 50 has a mesh structure and includes a plurality of first sub-parts 51, a plurality of second sub-parts 52, and a plurality of mesh holes 53.

[0155] Multiple first sub-sections 51 extend along the second direction Y, and the orthographic projection of one first sub-section 51 on the substrate 101 covers the orthographic projection of one second extension segment 14 on the substrate 101. Multiple second sub-sections 52 extend along the first direction X, and the orthographic projection of one second sub-section 52 on the substrate 101 covers the orthographic projection of multiple first extension segments 13 arranged along the first direction X on the substrate 101. For example, the second sub-sections 52 can extend continuously along the first direction X, and the second sub-sections 52 can cover the gap between two adjacent first extension segments 13 along the first direction X. In this way, the orthographic projection of the first auxiliary layer 50 on the substrate 101 can completely cover the orthographic projection of multiple first signal lines 10 on the substrate 101, thereby greatly shielding the influence of the first signal lines 10 on the first electrode 30.

[0156] A mesh hole 53 corresponds to a pixel area 102, and the mesh hole 53 exposes at least a portion of the pixel area 102 corresponding to the mesh hole 53. The mesh hole 53 helps to reduce the occlusion of the pixel area 102 by the first auxiliary layer 50, thereby reducing the impact of the first auxiliary layer 50 on the light extraction efficiency of the pixel area 102.

[0157] In some embodiments, as shown in FIG14, the array substrate 100 further includes a first semiconductor layer ACT1, a first insulating layer GI, a first gate conductive layer Gate1, a second insulating layer ILD, a source / drain conductive layer SD, a third insulating layer PVX1, and a first planarization layer PLN1 disposed along a direction away from the substrate 101, and a first via K1 penetrating the first insulating layer GI and the second insulating layer ILD. A first signal line 10 passes through the first via K1 and is electrically connected to a first semiconductor pattern 103. A first transistor T1 includes a first semiconductor pattern 103 located on the first semiconductor layer ACT1 and a first gate pattern 104 located on the first gate conductive layer Gate1, and the first signal line 10 is disposed on the source / drain conductive layer SD.

[0158] Unlike the embodiment shown in Figure 8, in this embodiment, referring to Figure 14, when the array substrate 100 is provided with a first auxiliary layer 50, the first electrode 30 can be provided with two sub-electrodes. The first electrode 30 includes a fourth sub-electrode 34 and a fifth sub-electrode 35 sequentially disposed along a direction away from the substrate 101. The fourth sub-electrode 34 is electrically connected to the second electrode of the first transistor T1, and the fifth sub-electrode 35 is electrically connected to the fourth sub-electrode 34. In this way, the number of conductive film layers included in the array substrate 100 remains unchanged, which is beneficial to reducing the thickness of the array substrate 100 and the manufacturing cost.

[0159] As shown in Figure 14, the array substrate 100 further includes a fourth insulating layer PVX2 and a second planarization layer PVX2, as well as a fourth via K4 that penetrates the first insulating layer GI, the second insulating layer ILD, the third insulating layer PVX1, the first planarization layer PLN1 and the fourth insulating layer PVX2. The fourth sub-electrode 34 is disposed on the side of the fourth insulating layer PVX2 away from the substrate 101, and the fourth sub-electrode 34 passes through the fourth via K4 and is electrically connected to the first semiconductor pattern 103.

[0160] A first auxiliary layer 50 is disposed between the first planarization layer PLN1 and the fourth insulating layer PVX2. A second planarization layer PVX2 is disposed on the side of the fourth sub-electrode 34 away from the substrate 101, covering the portion of the fourth sub-electrode 34 located within the fourth via K4, and exposing at least a portion of the fourth sub-electrode 34 located on the fourth insulating layer PVX2. Exemplarily, the surface of the second planarization layer PVX2 away from the substrate 101 is substantially flush with the surface of the fourth sub-electrode 34 away from the substrate 101, which helps to improve the flatness of the fifth sub-electrode 35. The fifth sub-electrode 35 covers the second planarization layer PLN2 and at least a portion of the fourth sub-electrode 34 for electrical connection with the fourth sub-electrode 34. The second planarization layer PLN2 increases the flatness of the surface of the fifth sub-electrode 35, which facilitates the formation of a storage capacitor C1 between the fifth sub-electrode 35 and the second electrode 40. Exemplarily, the fifth sub-electrode 35 covers the surface of the fourth sub-electrode 34 away from the substrate 101.

[0161] In some embodiments, referring to FIG14, the array substrate 100 may further include a fifth insulating layer PVX3 disposed between the fifth sub-electrode 34 and the fourth electrode 40. The fifth insulating layer PVX3 is used to isolate the fifth sub-electrode 34 and the fourth electrode 40, preventing a short circuit between the third sub-electrode 33 and the fourth electrode 40. The array substrate 100 may further include a sixth insulating layer 110 covering the fourth electrode 40, the sixth insulating layer 110 being used to protect the fourth electrode 40.

[0162] Some embodiments of this disclosure also provide a method for fabricating an array substrate 100 as shown in Figures 13 and 14. The method for fabricating the array substrate includes: sequentially fabricating a first semiconductor layer ACT1, a first insulating layer GI, a first gate conductive layer Gate1, and a second insulating layer ILD on a substrate 101. Then, a first via K1 is formed penetrating the first insulating layer GI and the second insulating layer ILD, exposing a portion of the first semiconductor layer ACT1. Then, a source / drain conductive layer SD, a third insulating layer PVX1, a first planarization layer PLN1, a first auxiliary layer 50, and a fourth insulating layer PVX2 are sequentially formed. Next, a first sub-via K41 penetrating the fourth insulating layer PVX2 and the first planarization layer PLN1 is formed using a photolithography process (one mask). Then, using the first planarization layer PLN1 as a mask, a second sub-via K42 penetrating the third insulating layer PVX1, the second insulating layer ILD, and the first insulating layer GI is etched. The second sub-via K42 communicates with the first sub-via K41 to form a fourth via K4. Then, the fourth sub-electrode 34, the second planarization layer PLN2, the fifth sub-electrode 35, the fifth insulating layer PVX3, the second electrode 40, and the sixth insulating layer 110 are formed sequentially. In the above fabrication method, although the fourth via K4 undergoes two etching processes, it can reduce the mask required in the formation of the second sub-via K42, which helps to simplify the fabrication process of the array substrate and reduce the fabrication cost of the array substrate 100.

[0163] In some embodiments, referring to FIG14, the fourth via K4 may include a first sub-via K41 penetrating the first planarization layer PLN1 and the fourth insulating layer PVX2, and a second sub-via K42 penetrating the first insulating layer GI, the second insulating layer ILD, and the third insulating layer PVX1. A stepped structure may be formed at the connection between the first sub-via K41 and the second sub-via K42. This reduces the depth of the fourth via K4, lowers the difficulty for the fourth sub-electrode 34 to climb the sidewall of the fourth via K4, and improves the linearity of the fourth sub-electrode 34 within the fourth via K4.

[0164] In some embodiments, referring to Figures 13 and 17, the array substrate 100 further includes a second electrode 40, which is disposed on the side of the first electrode 30 away from the substrate 101. The first auxiliary layer 50 and the second electrode 40 transmit the same voltage signal; that is, the first auxiliary layer 50 transmits a constant voltage signal. Thus, even if parasitic capacitance is generated between the first auxiliary layer 50 and the first signal line 10, this parasitic capacitance will not affect the voltage of the first auxiliary layer 50, which is beneficial for maintaining the voltage stability of the first auxiliary layer 50. Parasitic capacitance is also formed between the first auxiliary layer 50 and the first electrode 30. Since the voltage stability of the first auxiliary layer 50 is relatively high (compared to the first signal line 10), this parasitic capacitance will not affect the voltage of the first electrode 30, or its effect on the first electrode 30 is slight and negligible.

[0165] In some embodiments, referring to FIG17, the orthographic projection of the first auxiliary layer 50 on the substrate 101 at least partially overlaps with the orthographic projection of the second electrode 40 on the substrate 101. This is beneficial to reduce the influence of the first auxiliary layer 50 on the electric field generated between the first electrode 30 and the second electrode 40, thereby reducing the influence of the first auxiliary layer 50 on the shape and position of the second electrode 40.

[0166] In some embodiments, referring to Figures 13 and 17, in the orthographic projection of the second electrode 40 and the first sub-part 51 onto the substrate 101, the second electrode 40 covers the first sub-part 51, and the boundary of the second electrode 40 is spaced from the boundary of the first sub-part 51. This greatly reduces the influence of the first sub-part 51 on the electric field formed between the first electrode 30 and the second electrode 40.

[0167] Referring to Figures 13, 18, and 19, the orthographic projection of the second electrode 40 onto the substrate 101 partially overlaps with the orthographic projection of the second sub-part 52 onto the substrate 101. Specifically, the portion of the second electrode 40 and the second sub-part 52 that overlaps on the substrate 101 (as shown in Figures 13 and 18) facilitates the continuity of the second electrode 40 in the second direction Y and facilitates the connection of the second electrode 40 with corresponding signal lines in the surrounding area. The portion of the second electrode 40 that does not overlap with the second sub-part 52 (as shown in Figures 13 and 19) facilitates the formation of slits 42 on the second electrode 40 for patterning.

[0168] For example, as shown in FIG13, the second electrode 40 includes sixth sub-electrodes 41 spaced apart along the first direction X, with an opening 42 between adjacent sixth sub-electrodes 41. The extension direction of the sixth sub-electrodes 41 forms a certain angle with the second direction Y, and along the extension direction of the sixth sub-electrodes 41, the sixth sub-electrodes 41 are successively offset to the same side of the first direction X. For example, as shown in FIG13, along the extension direction of the sixth sub-electrodes 41, the sixth sub-electrodes 41 are offset to the left by a certain distance for each row of pixel area extended downwards. The orthographic projection of a sixth sub-electrode 41 on the substrate 101 coincides with the orthographic projection portions of two adjacent first electrodes 30 on the substrate 101 along the first direction X, and forms a storage capacitor C1 with the two first electrodes 30 respectively. The orthographic projection of the opening 42 on the substrate 101 partially coincides with the orthographic projection of the first electrode 30 on the substrate 101; for example, the orthographic projection of the middle region of the first electrode 30 along the first direction X on the substrate 101 coincides with the orthographic projection of the opening 42 on the substrate 101, that is, the opening 42 exposes a part of the middle region of the first electrode 30 along the first direction X.

[0169] In some embodiments, referring to FIG17, the linewidth D11 of the first signal line 10 is 1μm to 2μm. This can greatly reduce the linewidth of the first signal line 10, which is beneficial to improving the pixel density of the array substrate. Here, the linewidth of the first signal line 10 is the dimension of the first extension 13 along the second direction Y and the dimension of the second extension 14 along the first direction X.

[0170] For example, the linewidth D11 of the first signal line 10 can range from 1 μm to 1.3 μm, such as 1 μm, 1.1 μm, 1.25 μm, or 1.3 μm. Alternatively, the linewidth D11 of the first signal line 10 can range from 1.3 μm to 1.7 μm, such as 1.3 μm, 1.45 μm, 1.6 μm, or 1.7 μm. Or, the linewidth D11 of the first signal line 10 can range from 1.7 μm to 2 μm, such as 1.7 μm, 1.85 μm, 1.9 μm, or 2 μm. Of course, the linewidth D11 of the first signal line 10 is not limited to these values, and the embodiments of this disclosure will not list them all.

[0171] Referring to Figure 17, the dimension D12 of the first sub-part 51 along the first direction X is 1μm to 2.5μm. This is beneficial for the first sub-part 51 to completely cover the second extension 13 of the first signal line 10, greatly improving the shielding effect of the first sub-part 51 on the second extension 14 and reducing the capacitance of the parasitic capacitance between the second extension 14 and the first electrode 30.

[0172] For example, the dimension D12 of the first sub-part 51 along the first direction X can range from 1 μm to 1.5 μm, such as 1 μm, 1.25 μm, 1.4 μm, or 1.5 μm. Alternatively, the dimension D12 of the first sub-part 51 along the first direction X can range from 1.5 μm to 2 μm, such as 1.5 μm, 1.65 μm, 1.8 μm, or 2 μm. Or, the dimension D12 of the first sub-part 51 along the first direction X can range from 2 μm to 2 μm, such as 2 μm, 2.25 μm, 2.4 μm, or 2.5 μm. Of course, the value of the dimension D12 of the first sub-part 51 along the first direction X is not limited, and the embodiments disclosed herein will not be listed one by one.

[0173] Referring to Figures 18 and 19, the dimension D13 of the second sub-part 52 along the second direction Y is 1μm to 2μm. In this way, the line width of the second sub-part 52 is small, which helps to reduce the size of the second sub-part 52 within the pixel area 102 and greatly reduces the influence of the second sub-part 52 on the light emission rate of the pixel area 102.

[0174] For example, the dimension D13 of the second sub-part 52 along the second direction Y can range from 1 μm to 1.3 μm, such as 1.1 μm, 1.2 μm, or 1.3 μm. Alternatively, the dimension D13 of the second sub-part 52 along the second direction Y can range from 1.3 μm to 1.7 μm, such as 1.3 μm, 1.4 μm, 1.5 μm, or 1.7 μm. Alternatively, the dimension D13 of the second sub-part 52 along the second direction Y can range from 1.7 μm to 2 μm, such as 1.7 μm, 1.8 μm, 1.9 μm, or 2 μm. The embodiments of this disclosure will not be listed in detail here.

[0175] In some embodiments, referring to FIG20, the array substrate 100 further includes a plurality of first transistors T1 and a plurality of compensation capacitors C2. One compensation capacitor C2 corresponds to one first transistor T1, and at least a portion of the compensation capacitor C2 is disposed on the side of the first transistor T1 near the substrate 101.

[0176] In this configuration, a first transistor T1 is electrically connected to a first electrode 30, with its first terminal electrically connected to the first signal line 10 and its second terminal electrically connected to the first electrode 30. The first plate C21 of the compensation capacitor C2 is electrically connected to the second terminal of the first transistor T1, meaning that the first plate C21 of the compensation capacitor C2 is also electrically connected to the first electrode 30. The second plate C22 of the compensation capacitor C2 is electrically connected to the constant voltage signal terminal. The compensation capacitor C2 maintains the voltage stability of the first electrode 30, which helps reduce voltage fluctuations at the first electrode 30 and reduces fluctuations in the electric field between the first electrode 30 and the second electrode 40, thus improving the display quality of the display panel.

[0177] In some embodiments, continuing to refer to FIG20, the array substrate 100 further includes a second electrode 40. The second plate C22 of the compensation capacitor C2 transmits the same voltage signal as the second electrode 40. Thus, the compensation capacitor C2 and the storage capacitor C1 are connected in parallel, which can increase the total capacitance of the storage capacitor C1. From the above... It can be seen that the voltage generated by the coupling between the first signal line 10 and the first electrode 30 is ΔV, which is negatively correlated with the capacitance of the storage capacitor C1. The parallel connection of the compensation capacitor C2 and the storage capacitor C1 helps to reduce the voltage ΔV generated by the coupling between two adjacent first signal lines 10 and the first electrode 30, thereby reducing the voltage fluctuation of the first electrode 30. In other words, it can improve the voltage stability of the first electrode 30, which is beneficial to improving the display quality of the display panel.

[0178] In some embodiments, referring to FIG21, the array substrate 100 includes a display area AA and a peripheral area BB, and a first transistor T1 and a compensation capacitor C2 are both disposed in the display area AA. The array substrate 100 also includes a second semiconductor layer ACT2 and a second gate layer Gate2 disposed sequentially along a direction away from the substrate 101, and the second semiconductor layer ACT2 and the second gate layer Gate2 are both located on the side of the film layer where the first transistor T1 is located, closer to the substrate 101.

[0179] The material of the second semiconductor layer ACT2 may include one or more of amorphous silicon, polycrystalline silicon, metal oxide materials, and metal oxide nitrides. Among them, metal oxide materials include, but are not limited to, one or more of: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0180] Metal oxynitride materials include, but are not limited to, at least one of: zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, and silicon oxynitride. Polycrystalline silicon may include low-temperature polycrystalline silicon (LTPS).

[0181] The material of the first semiconductor layer ACT1 can be amorphous, partially crystalline, single-crystal, or polycrystalline, and can also be a single-layer or multi-layer structure.

[0182] The array substrate 100 also includes a plurality of second transistors T2 disposed in the peripheral region BB. Exemplarily, the plurality of second transistors T2 are configured to form a gate on array (GOA) circuit. The second transistors T2 include a second semiconductor pattern 105 located in the second semiconductor layer ACT2 and a second gate pattern 106 located in the second gate layer Gate2.

[0183] In this design, the first electrode C21 of the compensation capacitor C2 is located in the second semiconductor layer ACT2, and the second electrode C22 is located in the second gate layer Gate2. Therefore, the first electrode C21 of the compensation capacitor C2 can be formed simultaneously during the fabrication of the second semiconductor layer ACT2, and the second electrode C22 can be formed simultaneously during the fabrication of the second gate layer Gate2. This greatly simplifies the fabrication process of the compensation capacitor C2 and reduces its manufacturing cost.

[0184] Of course, the embodiments provided in this disclosure are not limited to these, as long as the same technical concept is used. For example, at least one of the first plate C21 and the second plate C22 of the compensation capacitor C2 can also be prepared by other film layers. For example, one or two new film layers can be added to the side of the first transistor T1 near the substrate 101 to prepare the first plate C21 and / or the second plate C22.

[0185] In some embodiments, the second transistor T2 can be a low-temperature polysilicon thin-film transistor (LTPS TFT). LTPS TFTs have advantages such as high mobility and high response speed, which are beneficial for improving the response speed of the gate drive circuit.

[0186] In some embodiments, referring to FIG22, the second electrode C22 of the compensation capacitor C2 extends along the first direction X, and the orthographic projection of the second electrode C22 on the substrate 101 at least partially coincides with the orthographic projection of the second signal line 20 on the substrate 101. On the one hand, the extension of the second electrode C22 along the first direction X facilitates the extension of the second electrode C22 to the peripheral region BB and its electrical connection with the constant voltage signal terminal (common voltage signal terminal). On the other hand, the fact that the orthographic projection of the second electrode C22 on the substrate 101 at least partially coincides with the orthographic projection of the second signal line 20 on the substrate 101 helps to reduce the area of ​​the second electrode C22 within the pixel region 102, thereby reducing the impact of the second electrode C22 on the light transmittance of the pixel region 102 and improving the light transmittance of the array substrate.

[0187] In some embodiments, the dimension D14 of the second signal line 20 along the second direction is 1μm to 2μm. This can greatly reduce the linewidth of the second signal line 20, which is beneficial to improving the aperture ratio of the pixel area 102 and thus improving the pixel density of the array substrate.

[0188] For example, the value of the dimension D14 of the second signal line 20 along the second direction can range from 1 μm to 1.3 μm. For instance, the value of the dimension D14 of the second signal line 20 along the second direction can be 1 μm, 1.1 μm, 1.2 μm, or 1.3 μm. Alternatively, the value of the dimension D14 of the second signal line 20 along the second direction can range from 1.3 μm to 1.7 μm. For instance, the value of the dimension D14 of the second signal line 20 along the second direction can be 1.3 μm, 1.5 μm, 1.6 μm, or 1.7 μm. Alternatively, the value of the dimension D14 of the second signal line 20 along the second direction can range from 1.7 μm to 2 μm. For instance, the value of the dimension D14 of the second signal line 20 along the second direction can be 1.7 μm, 1.8 μm, 1.9 μm, or 2.0 μm. Of course, the value of the dimension D14 of the second signal line 20 along the second direction is not limited to these values, and the embodiments of this disclosure will not list them all.

[0189] In some embodiments, the dimension D15 of the second electrode plate C22 along the second direction Y is 1 μm to 3 μm.

[0190] For example, the dimension D15 of the second electrode C22 along the second direction Y can be 1μm to 2μm. In this case, the second electrode C22 has a small linewidth, which can greatly reduce the linewidth of the second electrode C22, which is beneficial to improving the aperture ratio of the pixel area 102, thereby improving the pixel density of the array substrate. For example, the dimension D15 of the second electrode C22 along the second direction Y can be 1μm, 1.3μm, 1.5μm, 1.8μm or 2μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0191] For example, the dimension D15 of the second electrode C22 along the second direction Y is 2μm to 3μm. In this case, the orthogonal projection of the second electrode C22 on the substrate 101 covers the orthogonal projection of the second signal line 20 on the substrate 101, and also covers the orthogonal projection of the channel region of the first semiconductor pattern 103 of the first transistor T1 on the substrate 101. That is, the second electrode C22 can block the channel region of the first semiconductor pattern 103 of the first transistor T1, reducing the light entering the channel region of the first semiconductor pattern 103 of the first transistor T1, and improving the stability of the first transistor T1 under backlight illumination. For example, the dimension D15 of the second electrode C22 along the second direction Y can be 2μm, 2.4μm, 2.5μm, 2.7μm, or 3μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0192] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: A substrate, and multiple first signal lines and multiple second signal lines located on one side of the substrate, the first signal lines and the second signal lines intersecting to define multiple pixel regions; wherein, the multiple first signal lines are spaced apart along a first direction and partially bent along a second direction, each first signal line comprising a first portion and a second portion; one side of each pixel region is a first portion of a first signal line, and the other side of the pixel region is a second portion of another first signal line, the length of the first portion being greater than the length of the second portion; wherein, the first direction and the second direction intersect; A plurality of first electrodes corresponding to the pixel region, at least a portion of the first electrode being located within the pixel region; for at least one pixel region, in the orthographic projection of the first electrode, the first portion, and the second portion onto the substrate, the distance between at least a portion of the first electrode and the first portion in the first direction, and the distance between the first electrode and the second portion in the first direction are not equal.

2. The array substrate according to claim 1, wherein, In the orthographic projection of the first electrode, the first part, and the second part onto the substrate, the boundary length between the first electrode and the first part is greater than the boundary length between the first electrode and the second part, and the distance between at least a portion of the first electrode and the first part in the first direction is greater than the distance between the first electrode and the second part in the first direction.

3. The array substrate according to claim 1 or 2, wherein, The first signal line includes a plurality of alternating first extension segments and a plurality of second extension segments; the plurality of first extension segments all extend along the first direction and are spaced apart along the second direction; the plurality of second extension segments all extend along the second direction and are alternately connected to the two ends of the first extension segments along the first direction. The first part includes a second extension segment and two first extension segments connected to the second extension segment, and the second part includes a second extension segment close to the first part; the second extension segment included in the first part is a first sub-segment, and the second extension segment included in the second part is a second sub-segment. In the orthographic projection of the first electrode, the first sub-segment, and the second sub-segment onto the substrate, at least a portion of the first electrode is at a distance from the first sub-segment along the first direction that is greater than the distance from the second sub-segment along the first direction.

4. The array substrate according to claim 3, further comprising: Multiple first transistors, each first transistor is electrically connected to a first electrode, and the first electrode of the first transistor is electrically connected to the first signal line, and the second electrode is electrically connected to the first electrode; The first electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode disposed along a direction away from the substrate; the first sub-electrode is electrically connected to the second electrode of the first transistor, the second sub-electrode is electrically connected to the first sub-electrode, and the third sub-electrode is electrically connected to the second sub-electrode. The distance between the orthographic projection of at least a portion of at least one of the first sub-electrode, the second sub-electrode, and the third sub-electrode on the substrate and the orthographic projection of the first sub-segment on the substrate along the first direction is greater than the distance between the orthographic projection of the second sub-segment on the substrate along the first direction.

5. The array substrate according to claim 3, wherein, The first sub-electrode includes: In the third part, in the orthographic projection of the third part, the first sub-segment, and the second sub-segment onto the substrate, the distance between the third part and the first sub-segment in the first direction is greater than the distance between the third part and the second sub-segment in the first direction; The fourth part is located on one side of the third part along the second direction and is connected to the third part; the fourth part and the third part are flush with the ends of the first sub-segment, and the end of the fourth part near the second sub-segment extends beyond the edge of the third part.

6. The array substrate according to claim 5, wherein, The orthographic projection of the fourth portion onto the substrate at least partially overlaps with the orthographic projection of the second sub-segment onto the substrate.

7. The array substrate according to claim 5 or 6, wherein, The orthographic projections of the first sub-electrode and the first sub-segment onto the substrate are spaced 0.5 μm to 1.5 μm apart along the first direction; and / or, The orthographic projections of the third portion and the second sub-segment onto the substrate are spaced 0.2 μm to 1 μm apart along the first direction; and / or, The portion of the fourth part whose orthographic projection on the substrate coincides with the orthographic projection of the second sub-segment on the substrate has a dimension of 0.1 μm to 1 μm along the first direction.

8. The array substrate according to any one of claims 4 to 7, wherein, The second sub-electrode includes: In the fifth part, the distance between the fifth part and the first sub-segment in the first direction in the orthographic projection of the fifth part, the first sub-segment, and the second sub-segment on the substrate is equal to the distance between the fifth part and the second sub-segment in the first direction; The sixth part is located on one side of the fifth part along the second direction and is connected to the fifth part; the two ends of the sixth part extend beyond the edge of the fifth part along the first direction, and the distance between the orthographic projection of the sixth part on the substrate and the orthographic projection of the first sub-segment on the substrate along the first direction is greater than the distance between the orthographic projection of the second sub-segment on the substrate along the first direction.

9. The array substrate according to claim 8, wherein, In the orthographic projection of the fifth portion, the first sub-segment, and the second sub-segment onto the substrate, the spacing between the fifth portion and the first sub-segment, and between the fifth portion and the second sub-segment along the first direction, is 1 μm to 2 μm; and / or, The orthographic projections of the sixth portion and the first sub-segment onto the substrate are spaced 0.2 μm to 1 μm apart along the first direction; and / or, The orthographic projections of the sixth portion and the second sub-segment onto the substrate are spaced 0 to 1 μm apart along the first direction.

10. The array substrate according to any one of claims 4 to 9, wherein, In the orthographic projection of the third sub-electrode, the first sub-segment, and the second sub-segment onto the substrate, the boundaries of the third sub-electrode and the first sub-segment that approach each other are approximately parallel, and the boundaries of the third sub-electrode and the second sub-segment that approach each other are also approximately parallel; the distance between the third sub-electrode and the first sub-segment along the first direction is greater than the distance between the third sub-electrode and the second sub-segment along the first direction.

11. The array substrate according to claim 10, wherein, The orthographic projections of the third sub-electrode and the first sub-segment onto the substrate are spaced 0.2 μm to 1 μm apart along the first direction; and / or, The orthographic projections of the third sub-electrode and the second sub-segment onto the substrate are spaced 0–1 μm apart along the first direction.

12. The array substrate according to any one of claims 4 to 11, further comprising: A first semiconductor layer, a first insulating layer, a first gate conductive layer, a second insulating layer, a source / drain conductive layer, and a third insulating layer are disposed along a direction away from the substrate; wherein, the first transistor includes a first semiconductor pattern located on the first semiconductor layer and a gate pattern located on the first gate conductive layer, and the first signal line is disposed on the source / drain conductive layer; A first via penetrating the first insulating layer and the second insulating layer; the first signal line passes through the first via and is electrically connected to the first semiconductor pattern; A second via extends through the first insulating layer, the second insulating layer, and the third insulating layer, and the first sub-electrode passes through the second via and is electrically connected to the first semiconductor pattern; A first planarization layer is disposed between the first sub-electrode and the second sub-electrode. The first planarization layer includes a third via, which exposes a portion of the first sub-electrode. The second sub-electrode passes through the third via and is electrically connected to the first sub-electrode. A second planarization layer is disposed on the side of the second sub-electrode away from the substrate, covering the portion of the second sub-electrode located within the third via, and exposing at least a portion of the second sub-electrode located on the first planarization layer; The third sub-electrode covers the second planarization layer and at least a portion of the second sub-electrode.

13. The array substrate according to any one of claims 1 to 12, wherein, The voltage signals transmitted by two adjacent first signal lines are of opposite electrical polarity.

14. The array substrate according to any one of claims 1 to 3, further comprising: A first auxiliary layer is disposed between the film layer where the first signal line is located and the film layer where the first electrode is located; Wherein, in the orthographic projection of the first auxiliary layer, the first signal line, and the first electrode onto the substrate, the first auxiliary layer at least partially overlaps with the first signal line, and / or the first auxiliary layer at least partially overlaps with the first electrode.

15. The array substrate according to claim 14, wherein, The orthographic projection of the first auxiliary layer on the substrate covers the orthographic projection of the first signal line on the substrate, and at least partially does not coincide with the orthographic projection of the first electrode on the substrate.

16. The array substrate according to claim 15, wherein, The first signal line includes a plurality of alternating first extension segments and a plurality of second extension segments; The first auxiliary layer is a mesh structure, and the first auxiliary layer includes: Multiple first sub-sections extend along the second direction, and the orthographic projection of one first sub-section on the substrate covers the orthographic projection of one second extension on the substrate; Multiple second sub-parts extend along the first direction, and the orthographic projection of one second sub-part on the substrate covers the orthographic projection of multiple first extension segments arranged along the first direction on the substrate. Multiple mesh holes, each mesh hole corresponding to a pixel area, and the mesh hole exposes at least a portion of the pixel area corresponding to the mesh hole.

17. The array substrate according to claim 16, further comprising: The second electrode is disposed on the side of the first electrode away from the substrate; The first auxiliary layer transmits the same voltage signal as the second electrode.

18. The array substrate according to claim 17, wherein, The orthographic projection of the first auxiliary layer on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate.

19. The array substrate according to claim 18, wherein, In the orthographic projection of the second electrode and the first sub-part on the substrate, the second electrode covers the first sub-part, and the boundary of the second electrode is spaced from the boundary of the first sub-part; The orthographic projection of the second electrode onto the substrate coincides with the orthographic projection of the second sub-part onto the substrate.

20. The array substrate according to any one of claims 16 to 17, wherein, The linewidth of the first signal line is 1μm to 2.0μm; and / or, The first sub-part has a dimension of 1 μm to 2.5 μm along the first direction; and / or, The second sub-part has a dimension of 1 μm to 2 μm along the second direction.

21. The array substrate according to any one of claims 14 to 20, further comprising: Multiple first transistors, each first transistor is electrically connected to a first electrode, and the first electrode of the first transistor is electrically connected to the first signal line, and the second electrode is electrically connected to the first electrode; The first electrode includes a fourth sub-electrode and a fifth sub-electrode arranged sequentially along a direction away from the substrate. The fourth sub-electrode is electrically connected to the second electrode of the first transistor, and the fifth sub-electrode is electrically connected to the fourth sub-electrode.

22. The array substrate according to claim 21, further comprising: A first semiconductor layer, a first insulating layer, a first gate conductive layer, and a second insulating layer are disposed along a direction away from the substrate. The transistor comprises a first semiconductor layer, a source / drain conductive layer, a third insulating layer, a first planarization layer, and a fourth insulating layer; wherein the first transistor includes a first semiconductor pattern located on the first semiconductor layer and a gate pattern located on the first gate conductive layer, and the first signal line is disposed on the source / drain conductive layer. A first via penetrating the first insulating layer and the second insulating layer; the first signal line passes through the first via and is electrically connected to the first semiconductor pattern; A fourth via extends through the first insulating layer, the second insulating layer, the third insulating layer, the first planarization layer, and the fourth insulating layer. The fourth sub-electrode passes through the fourth via and is electrically connected to the first semiconductor pattern. The second planarization layer is disposed on the side of the fourth sub-electrode away from the substrate, covering the portion of the fourth sub-electrode located within the fourth via, and exposing at least a portion of the fourth sub-electrode located on the fourth insulating layer; The first auxiliary layer is disposed between the first planarization layer and the fourth insulating layer; the fifth sub-electrode covers the second planarization layer and at least a portion of the fourth sub-electrode.

23. The array substrate according to any one of claims 1 to 22, wherein, The array substrate further includes a plurality of first transistors, each first transistor being electrically connected to a first electrode, and the first electrode of the first transistor being electrically connected to the first signal line, and the second electrode being electrically connected to the first electrode. Multiple compensation capacitors are at least partially disposed on the side of the first transistor near the substrate, and the first plate of the compensation capacitor is electrically connected to the second plate of the first transistor, and the second plate is electrically connected to the constant voltage signal terminal.

24. The array substrate according to claim 23, further comprising: The second electrode is disposed on the side of the first electrode away from the substrate; The second plate of the compensation capacitor transmits the same voltage signal as the second electrode.

25. The array substrate according to claim 24, wherein, The array substrate includes a display area and a peripheral area, wherein the first transistor is disposed in the display area; the array substrate further includes: A second semiconductor layer and a second gate layer are disposed away from the substrate, the second semiconductor layer and the second gate layer being located on the side of the first transistor closer to the substrate; The second transistor is disposed in the peripheral region and includes a second semiconductor pattern located in the second semiconductor layer and a second gate pattern located in the second gate layer; The first electrode of the compensation capacitor is located in the second semiconductor layer, and the second electrode is located in the second gate layer.

26. The array substrate according to claim 25, wherein, The first transistor is an oxide thin-film transistor; and / or, The second transistor is a low-temperature polycrystalline silicon thin-film transistor.

27. The array substrate according to any one of claims 23 to 26, wherein, The second plate of the compensation capacitor extends along the first direction, and the orthographic projection of the second plate on the substrate at least partially coincides with the orthographic projection of the second signal line on the substrate.

28. The array substrate according to claim 27, wherein, The second signal line has a dimension of 1 μm to 2 μm along the second direction; and / or, The second electrode plate has a dimension of 1 μm to 3 μm along the second direction.

29. A display panel, comprising: The array substrate as described in any one of claims 1 to 28; The opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

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