Pixel circuit, driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a driving method and a display apparatus. The pixel circuit comprises a light-emitting element, a driving circuit, an external compensation control circuit, a control circuit and a data writing circuit, wherein the display period of the pixel circuit comprises a first active level stage and a second active level stage, which are sequentially set, and a third active level stage, which is set between the first active level stage and the second active level stage; the control circuit writes a bias voltage signal into a first node at the third active level stage; and the data writing circuit controls the connection between a data line and a control node under the control of a third scanning signal at the first active level stage and the second active level stage. By means of the present disclosure, the hysteresis phenomenon of a driving transistor comprised in a driving circuit is mitigated.

Description

Pixel circuits, driving methods, and display devices

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410504741.7, filed in China on April 24, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0004] In the display field, especially in OLED (Organic Light Emitting Diode) displays, oxides are currently widely used in medium and large-sized OLED displays due to their good uniformity. However, existing 3T1C external compensation pixel circuits often suffer from poor display uniformity and even image retention defects due to differences in the characteristics of the driving transistors. Summary of the Invention

[0005] The main objective of this disclosure is to provide a pixel circuit, driving method, and display device that solves the problem that existing pixel circuits cannot improve the hysteresis of the driving transistors included in the driving circuit while performing external threshold voltage compensation.

[0006] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a driving circuit, an external compensation control circuit, a control circuit, and a data writing circuit; the display cycle of the pixel circuit includes a first effective level phase and a second effective level phase set sequentially, and a third effective level phase set between the first effective level phase and the second effective level phase;

[0007] The control terminal of the driving circuit is electrically connected to the control node, the first terminal of the driving circuit is electrically connected to the first node, and the second terminal of the driving circuit is electrically connected to the light-emitting element through the second node. The driving circuit is used to generate a driving current to drive the light-emitting element under the potential control of the control node.

[0008] The external compensation control circuit is electrically connected to the first scanning end, the external compensation line and the second node respectively, and is used to control the connection or disconnection between the external compensation line and the second node under the control of the first scanning signal provided by the first scanning end;

[0009] The control circuit is electrically connected to the first node and is used to write the bias voltage signal into the first node during the third effective level phase.

[0010] The data writing circuit is electrically connected to the third scanning terminal, the data line, and the control node, respectively, and is used to control the connection between the data line and the control node under the control of the third scanning signal provided by the third scanning terminal during the first effective level stage and the second effective level stage.

[0011] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit; the control circuit is a bias control circuit.

[0012] The bias control circuit is electrically connected to the second scanning terminal, the bias voltage terminal and the first node respectively, and is used to write the bias voltage provided by the bias voltage terminal into the first node under the control of the second scanning signal provided by the second scanning terminal during the third effective level stage.

[0013] The first light-emitting control circuit is connected to the first light-emitting control terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the first node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0014] Optionally, the control circuit is a first light-emitting control circuit; the display cycle further includes a light-emitting phase set after the second effective level phase;

[0015] The first light-emitting control circuit is connected to the first light-emitting control terminal, the first voltage terminal and the first node respectively. Under the control of the first light-emitting control signal provided by the first light-emitting control terminal, during the third effective level stage, the circuit writes the bias voltage signal provided by the first voltage terminal into the first node. During the light-emitting stage, the circuit controls the connection between the first voltage terminal and the first node.

[0016] The first voltage terminal is used to provide a bias voltage signal during the third effective level phase and a power supply voltage signal during the light emission phase.

[0017] Optionally, the second valid level phase includes a detection phase and a data write-back phase set sequentially; the first valid level phase is a data write phase.

[0018] The external compensation control circuit is used to control the connection between the external compensation line and the second node under the control of the first scan signal during the detection phase. The compensation voltage can be calculated based on the electrical signal on the external compensation line during the detection phase.

[0019] The external compensation control circuit is also used in the data writing stage and the data write-back stage, under the control of the first scan signal, to control the connection between the external compensation line and the second node, and to write the reference voltage provided by the external compensation line into the second node.

[0020] Optionally, the detection phase lasts longer than the data write-back phase.

[0021] Optionally, the duration of the second effective level phase is longer than the duration of the first effective level phase.

[0022] Optionally, the third effective level phase is a bias phase, and the display cycle further includes a first floating phase set between the write data phase and the bias phase, and a second floating phase set between the bias phase and the detection phase.

[0023] During the first floating phase and the second floating phase, the transistors included in the pixel circuit are turned off.

[0024] Optionally, the duration of the first floating phase is longer than the duration of the data writing phase.

[0025] Optionally, the duration of the first floating phase is longer than the duration of the second floating phase.

[0026] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second light-emitting control circuit and an energy storage circuit; the second node is electrically connected to the first electrode of the light-emitting element through the second light-emitting control circuit;

[0027] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal and is used to control the connection or disconnection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0028] The first end of the energy storage circuit is electrically connected to the control node, and the second end of the energy storage circuit is electrically connected to the second node. The energy storage circuit is used to store electrical energy.

[0029] Optionally, the bias control circuit includes a first transistor;

[0030] The gate of the first transistor is electrically connected to the second scan terminal, the first terminal of the first transistor is electrically connected to the bias voltage terminal, and the second terminal of the first transistor is electrically connected to the first node.

[0031] Optionally, the first light-emitting control circuit includes a second transistor;

[0032] The gate of the second transistor is electrically connected to the first light-emitting control terminal, the first terminal of the second transistor is electrically connected to the first voltage terminal, and the second terminal of the second transistor is electrically connected to the first node.

[0033] Optionally, the external compensation control circuit includes a third transistor;

[0034] The gate of the third transistor is electrically connected to the first scanning terminal, the first electrode of the third transistor is electrically connected to the external compensation line, and the second electrode of the third transistor is electrically connected to the second node.

[0035] The data writing circuit includes a fourth transistor;

[0036] The gate of the fourth transistor is electrically connected to the third scan terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the control node.

[0037] Optionally, the second light-emitting control circuit includes a fifth transistor;

[0038] The gate of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0039] The energy storage circuit includes a storage capacitor;

[0040] The first end of the storage capacitor is electrically connected to the control node, and the second end of the storage capacitor is electrically connected to the second node.

[0041] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, wherein the display cycle of the pixel circuit includes a first effective level phase and a second effective level phase configured sequentially, and a third effective level phase configured between the first effective level phase and the second effective level phase; the driving method includes:

[0042] During the third effective level phase, the control circuit writes the bias voltage signal into the first node;

[0043] During the first effective level phase and the second effective level phase, the data writing circuit controls the connection between the data line and the control node under the control of the third scan signal provided by the third scan terminal.

[0044] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0045] This embodiment adds a control circuit. During the bias stage, the control circuit writes a bias voltage signal to the first node, so that the driving transistor in the driving circuit is in a forward bias state, which improves the hysteresis phenomenon of the driving transistor included in the driving circuit, can perform stress recovery of the driving transistor, and can eliminate the image retention problem in the display panel. Attached Figure Description

[0046] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0047] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0048] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0050] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0051] Figure 6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0052] Figure 7 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 6;

[0053] Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0054] Figure 9 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0055] Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0056] Figure 11 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 10. Detailed Implementation

[0057] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0058] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0059] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0060] The pixel circuit described in this embodiment includes a light-emitting element, a driving circuit, an external compensation control circuit, a control circuit, and a data writing circuit; the display cycle of the pixel circuit includes a first effective level stage and a second effective level stage set sequentially, and a third effective level stage set between the first effective level stage and the second effective level stage;

[0061] The control terminal of the driving circuit is electrically connected to the control node, the first terminal of the driving circuit is electrically connected to the first node, and the second terminal of the driving circuit is electrically connected to the light-emitting element through the second node. The driving circuit is used to generate a driving current to drive the light-emitting element under the potential control of the control node.

[0062] The external compensation control circuit is electrically connected to the first scanning end, the external compensation line and the second node respectively, and is used to control the connection or disconnection between the external compensation line and the second node under the control of the first scanning signal provided by the first scanning end;

[0063] The control circuit is electrically connected to the first node and is used to write the bias voltage signal into the first node during the third effective level phase.

[0064] The data writing circuit is electrically connected to the third scanning terminal, the data line, and the control node, respectively, and is used to control the connection between the data line and the control node under the control of the third scanning signal provided by the third scanning terminal during the first effective level stage and the second effective level stage.

[0065] The pixel circuit described in this embodiment is equipped with a control circuit. During the third effective level stage, the control circuit writes a bias voltage signal to the first node, so that the driving transistor in the driving circuit is in a forward bias state, which improves the hysteresis phenomenon of the driving transistor included in the driving circuit, can perform stress recovery of the driving transistor, and can eliminate the image retention problem in the display panel.

[0066] The above biasing process allows the driving transistors at different locations across the screen to be forward biased, enabling areas with long periods of black screen to also be forward biased, thereby reducing the threshold voltage differences of the driving transistors in different areas and eliminating image retention.

[0067] In at least one embodiment of this disclosure, the third effective level stage may be a bias stage, the first effective level stage may be a write data stage, and the second effective level stage may include a detection stage and a data write-back stage set sequentially.

[0068] In at least one embodiment of this disclosure, during the bias phase, the control circuit writes a bias voltage signal to the first node, so that the driving transistor included in the driving circuit is in a forward bias state; during the bias phase,

[0069] When the driving transistor is an n-type transistor, the gate-source voltage of the driving transistor is greater than the threshold voltage of the driving transistor;

[0070] When the driving transistor is a p-type transistor, the gate-source voltage of the driving transistor is less than the threshold voltage of the driving transistor.

[0071] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit; the control circuit is a bias control circuit.

[0072] The bias control circuit is electrically connected to the second scanning terminal, the bias voltage terminal and the first node respectively, and is used to write the bias voltage provided by the bias voltage terminal into the first node under the control of the second scanning signal provided by the second scanning terminal during the third effective level stage.

[0073] The first light-emitting control circuit is connected to the first light-emitting control terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the first node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0074] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, which may be a bias control circuit. During the bias stage, the bias control circuit writes a bias voltage to the first node under the control of the second scanning signal. Under the control of the first light-emitting control signal, the first light-emitting control circuit controls the first voltage terminal to disconnect from the first node. During the light-emitting stage, the first light-emitting control circuit controls the first voltage terminal to connect with the first node under the control of the first light-emitting control signal.

[0075] As shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, an external compensation control circuit 11, a bias control circuit 12, a first light-emitting control circuit 13, and a data writing circuit 31; the display cycle of the pixel circuit includes a first effective level stage and a second effective level stage set sequentially, and a third effective level stage set between the first effective level stage and the second effective level stage.

[0076] The control terminal of the driving circuit 10 is electrically connected to the control node NC, the first terminal of the driving circuit 10 is electrically connected to the first node N1, and the second terminal of the driving circuit 10 is electrically connected to the light-emitting element E1 through the second node N2. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the potential control of the control node NC.

[0077] The external compensation control circuit 11 is electrically connected to the first scanning terminal G1, the external compensation line SL and the second node N2 respectively, and is used to control the connection or disconnection between the external compensation line SL and the second node N2 under the control of the first scanning signal provided by the first scanning terminal G1.

[0078] The bias control circuit 12 is electrically connected to the second scan terminal G2, the bias voltage terminal REF and the first node N1 respectively, and is used to write the bias voltage Vref provided by the bias voltage terminal REF into the first node N1 under the control of the second scan signal provided by the second scan terminal G2 during the third effective level stage.

[0079] The first light-emitting control circuit 13 is connected to the first light-emitting control terminal EM1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the first node M1 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0080] The data writing circuit 31 is electrically connected to the third scanning terminal G3, the data line DT, and the control node NC, respectively, and is used to control the connection between the data line DT and the control node NC under the control of the third scanning signal provided by the third scanning terminal G3 during the first effective level stage and the second effective level stage.

[0081] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, the display cycle may include a first effective level stage, a third effective level stage, and a second effective level stage set sequentially; the third effective level stage is a bias stage, the first effective level stage is a data writing stage, and the second effective level stage includes a detection stage and a data write-back stage set sequentially.

[0082] During the first effective level phase and the second effective level phase, the data writing circuit 31 controls the connection between the data line DT and the control node NC under the control of the third scan signal;

[0083] During the bias phase, under the control of the second scanning signal, the bias control circuit 12 writes the bias voltage Vref into the first node N1, so that the driving transistor included in the driving circuit is in a forward bias state; under the control of the first light emission control signal, the first light emission control circuit 13 controls the first voltage terminal V1 to disconnect from the first node N1.

[0084] During the detection phase, the external compensation control circuit 11, under the control of the first scan signal, controls the connection between the external compensation line SL and the second node N2, and the compensation voltage can be calculated based on the electrical signal on the external compensation line SL.

[0085] In at least one embodiment of this disclosure, the control circuit is a first light-emitting control circuit; the display cycle further includes a light-emitting phase disposed after the second effective level phase;

[0086] The first light-emitting control circuit is connected to the first light-emitting control terminal, the first voltage terminal and the first node respectively. Under the control of the first light-emitting control signal provided by the first light-emitting control terminal, during the third effective level stage, the circuit writes the bias voltage signal provided by the first voltage terminal into the first node. During the light-emitting stage, the circuit controls the connection or disconnection between the first voltage terminal and the first node.

[0087] The first voltage terminal is used to provide a bias voltage signal during the third effective level phase and a power supply voltage signal during the light emission phase.

[0088] As shown in Figure 2, the pixel circuit described in at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, an external compensation control circuit 11, a first light-emitting control circuit 13, and a data writing circuit 31; the display cycle also includes a light-emitting phase set after the second effective level phase;

[0089] The control terminal of the driving circuit 10 is electrically connected to the control node NC, the first terminal of the driving circuit 10 is electrically connected to the first node N1, and the second terminal of the driving circuit 10 is electrically connected to the light-emitting element through the second node N2. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the potential control of the control node NC.

[0090] The external compensation control circuit 11 is electrically connected to the first scanning terminal G1, the external compensation line SL and the second node N2 respectively, and is used to control the connection or disconnection between the external compensation line SL and the second node N2 under the control of the first scanning signal provided by the first scanning terminal G1.

[0091] The data writing circuit 31 is electrically connected to the third scanning terminal G3, the data line DT, and the control node NC, respectively, and is used to control the connection between the data line DT and the control node NC under the control of the third scanning signal provided by the third scanning terminal G3 during the first effective level stage and the second effective level stage.

[0092] The first light-emitting control circuit 13 is connected to the first light-emitting control terminal EM1, the first voltage terminal V1 and the first node N1 respectively. Under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1, during the third effective level stage, the bias voltage signal provided by the first voltage terminal V1 is written into the first node N1. During the light-emitting stage, the circuit controls the connection between the first voltage terminal V1 and the first node N1.

[0093] The first voltage terminal V1 is used to provide a bias voltage signal during the third effective level phase and a power supply voltage signal during the light emission phase.

[0094] At least one embodiment of the pixel circuit shown in FIG2 of this disclosure, during operation, includes a first effective level stage, a third effective level stage, and a second effective level stage; the third effective level stage is a bias stage, the first effective level stage is a data write stage, and the second effective level stage includes a detection stage and a data write-back stage set sequentially.

[0095] During the first effective level phase and the second effective level phase, the data writing circuit 31 controls the connection between the data line DT and the control node NC under the control of the third scan signal;

[0096] During the bias phase, the first voltage terminal V1 provides a bias voltage signal. Under the control of the first light emission control signal, the first light emission control circuit 13 writes the bias voltage signal into the first node N1, so that the driving transistor included in the driving circuit 10 is in a forward bias state, thereby improving the hysteresis phenomenon of the driving transistor.

[0097] During the detection phase, the external compensation control circuit 11, under the control of the first scan signal, controls the connection between the external compensation line SL and the second node N2, and the compensation voltage can be calculated based on the electrical signal on the external compensation line SL.

[0098] In at least one embodiment of this disclosure, the second effective level phase may include a detection phase and a data write-back phase that are set sequentially; the first effective level phase is a data write phase;

[0099] The external compensation control circuit is used to control the connection between the external compensation line and the second node under the control of the first scan signal during the detection phase. The compensation voltage can be calculated based on the electrical signal on the external compensation line during the detection phase.

[0100] The external compensation control circuit is also used in the data writing stage and the data write-back stage. Under the control of the first scan signal, the external compensation control circuit controls the connection between the external compensation line and the second node, and writes the reference voltage provided by the external compensation line into the second node to control the light-emitting element not to emit light.

[0101] In at least one embodiment of this disclosure, the duration of the detection phase is longer than the duration of the data write-back phase.

[0102] In practice, the duration of the detection phase can be set to be longer than the duration of the data write-back phase, so that there is enough time to detect the electrical signal on the external compensation line and to calculate the accurate compensation voltage based on the electrical signal.

[0103] In at least one embodiment of this disclosure, the duration of the second effective level phase is longer than the duration of the first effective level phase.

[0104] In practical implementation, since detection and data writing are required during the second effective level phase, while only data writing is required during the first effective level phase, the duration of the second effective level phase can be set to be longer than the duration of the first effective level phase.

[0105] Optionally, the third effective level phase is a bias phase, and the display cycle further includes a first floating phase set between the write data phase and the bias phase, and a second floating phase set between the bias phase and the detection phase.

[0106] During the first floating phase and the second floating phase, the transistors included in the pixel circuit are turned off.

[0107] In at least one embodiment of this disclosure, the duration of the first floating phase is longer than the duration of the write data phase.

[0108] In practice, the duration of the first floating phase can be set to be longer than the duration of the write data phase, so as to separate the write data phase and the bias phase through the first floating phase.

[0109] In at least one embodiment of this disclosure, the duration of the first levitation phase is longer than the duration of the second levitation phase.

[0110] In practical implementation, since the duration of the second effective level phase is longer than the duration of the first effective level phase, the duration of the first floating phase can be set to be longer than the duration of the second floating phase.

[0111] The pixel circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0112] The first end of the energy storage circuit is electrically connected to the control node, and the second end of the energy storage circuit is electrically connected to the second node. The energy storage circuit is used to store electrical energy.

[0113] In a specific implementation, the pixel circuit may further include an energy storage circuit, which can control the potential of the second node under the control of the potential of the control node.

[0114] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit described in at least one embodiment of this disclosure may further include an energy storage circuit 30.

[0115] The first end of the energy storage circuit 30 is electrically connected to the control node NC, and the second end of the energy storage circuit 30 is electrically connected to the second node N2. The energy storage circuit 30 is used to store electrical energy.

[0116] The pixel circuit described in at least one embodiment of this disclosure further includes a second light-emitting control circuit; the second node is electrically connected to the first electrode of the light-emitting element through the second light-emitting control circuit; the second electrode of the light-emitting element is electrically connected to a second voltage terminal;

[0117] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal and is used to control the connection or disconnection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0118] Optionally, the second voltage terminal can be a ground terminal or a low voltage terminal, but is not limited thereto.

[0119] In a specific implementation, the pixel circuit may further include a second light-emitting control circuit. Under the control of the second light-emitting control signal, the second light-emitting control circuit controls the connection or disconnection between the second node and the first pole of the light-emitting element to perform light-emitting control.

[0120] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a second light-emitting control circuit 41; the second node N2 is electrically connected to the first electrode of the light-emitting element E1 through the second light-emitting control circuit 41; the second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0121] The second light-emitting control circuit 41 is electrically connected to the second light-emitting control terminal EM2, and is used to control the connection or disconnection between the second node N2 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0122] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit described in at least one embodiment of this disclosure may further include an energy storage circuit 30 and a second light emission control circuit 41.

[0123] The first end of the energy storage circuit 30 is electrically connected to the control node NC, and the second end of the energy storage circuit 30 is electrically connected to the second node N2. The energy storage circuit 30 is used to store electrical energy.

[0124] The second node N2 is electrically connected to the first electrode of the light-emitting element E1 through the second light-emitting control circuit 41; the second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0125] The second light-emitting control circuit 41 is electrically connected to the second light-emitting control terminal EM2, and is used to control the connection or disconnection between the second node N2 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0126] Optionally, the bias control circuit includes a first transistor;

[0127] The gate of the first transistor is electrically connected to the second scanning terminal, the first terminal of the first transistor is electrically connected to the bias voltage terminal, and the second terminal of the first transistor is electrically connected to the first node.

[0128] Optionally, the first light-emitting control circuit includes a second transistor;

[0129] The gate of the second transistor is electrically connected to the first light-emitting control terminal, the first terminal of the second transistor is electrically connected to the first voltage terminal, and the second terminal of the second transistor is electrically connected to the first node.

[0130] Optionally, the external compensation control circuit includes a third transistor;

[0131] The gate of the third transistor is electrically connected to the first scanning terminal, the first electrode of the third transistor is electrically connected to the external compensation line, and the second electrode of the third transistor is electrically connected to the second node.

[0132] Optionally, the data writing circuit includes a fourth transistor;

[0133] The gate of the fourth transistor is electrically connected to the third scan terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the control node.

[0134] Optionally, the second light-emitting control circuit includes a fifth transistor;

[0135] The gate of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0136] Optionally, the energy storage circuit includes a storage capacitor;

[0137] The first end of the storage capacitor is electrically connected to the control node, and the second end of the storage capacitor is electrically connected to the second node.

[0138] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 3, the bias control circuit includes a first transistor T1; the light-emitting element is an organic light-emitting diode O1; and the driving circuit includes a driving transistor T0.

[0139] The gate of the driving transistor T0 is electrically connected to the control node NC, the drain of the driving transistor T0 is electrically connected to the first node N1, and the source of the driving transistor T0 is electrically connected to the second node N2; the second node N2 is electrically connected to the anode of the organic light-emitting diode O1; and the cathode of O1 is electrically connected to the low-voltage terminal ELVSS.

[0140] The gate of the first transistor T1 is electrically connected to the second scan terminal G2, the drain of the first transistor T1 is electrically connected to the bias voltage terminal REF, and the source of the first transistor T1 is electrically connected to the first node N1.

[0141] The first light-emitting control circuit includes a second transistor T2;

[0142] The gate of the second transistor T2 is electrically connected to the first light-emitting control terminal EM1, the drain of the second transistor EM1 is electrically connected to the power supply voltage terminal ELVDD, and the source of the second transistor T2 is electrically connected to the first node N1.

[0143] The external compensation control circuit includes a third transistor T3;

[0144] The gate of the third transistor T3 is electrically connected to the first scan terminal G1, the drain of the third transistor T3 is electrically connected to the external compensation line SL, and the source of the third transistor T3 is electrically connected to the second node N2.

[0145] The data writing circuit includes a fourth transistor T4;

[0146] The gate of the fourth transistor T4 is electrically connected to the third scan terminal G3, the drain of the fourth transistor T4 is electrically connected to the data line DT, and the source of the fourth transistor T4 is electrically connected to the control node NC.

[0147] The energy storage circuit includes a storage capacitor C1;

[0148] The first end of the storage capacitor C1 is electrically connected to the control node NC, and the second end of the storage capacitor C1 is electrically connected to the second node N2.

[0149] In at least one embodiment of the pixel circuit shown in Figure 6, the first voltage terminal is the power supply voltage terminal ELVDD, the second voltage terminal is the low voltage terminal ELVSS, all transistors are n-type transistors, and all transistors are oxide transistors, but not limited thereto.

[0150] As shown in Figure 7, when at least one embodiment of the pixel circuit shown in Figure 6 is working, the display cycle may include a data writing stage S1, a first floating stage SF1, a bias stage S2, a second floating stage SF2, a detection stage S3, a data write-back stage S4, and a light emission stage S5, which are set sequentially.

[0151] During the data writing phase S1, DT provides the compensated data voltage Vd', G3 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a low voltage signal, T4 is turned on, T3 is turned on, Vd' is written to the gate of T0, and the reference voltage Vj provided by SL is written to the second node N2. By controlling the voltage value of Vj, O1 is prevented from emitting light. The compensated data voltage Vd' is the sum of the original data voltage and the compensated voltage obtained based on the detection result of the detection phase in the previous display cycle.

[0152] During the first floating phase SF1 and the second floating phase SF2, G3, G1, G2 and EM1 all provide low voltage signals, and T0, T1, T2, T3 and T4 are all turned off.

[0153] During the biasing phase S2, G3 provides a low voltage signal, G1 provides a high voltage signal, G2 provides a high voltage signal, EM1 provides a low voltage signal, T1 is turned on, REF provides a bias voltage Vref to N1, controlling T0 to be in a forward bias state and improving the hysteresis of T0; T3 is turned on, SL provides a reference voltage Vj to the second node N2, and by controlling the voltage value of Vj, O1 is prevented from emitting light;

[0154] During the detection phase S3, DT provides the raw data voltage, G3 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, T4 and T3 are turned on, T0 is turned on, and the compensation voltage can be calculated based on the electrical signal on SL.

[0155] During the data write-back phase S4, DT provides the compensated data voltage Vd', G3 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a low voltage signal, T4 is turned on, T3 is turned on, Vd' is written to the gate of T0, and the reference voltage Vj provided by SL is written to the second node N2. By controlling the voltage value of Vj, O1 is prevented from emitting light. The compensated data voltage Vd' is the sum of the original data voltage and the compensated voltage obtained based on the detection result of the detection phase in the previous display cycle.

[0156] During the light-emitting phase S5, EM1 provides a high-voltage signal, G1, G2 and G3 provide low-voltage signals, T2 is turned on, and T0 drives O1 to emit light.

[0157] In at least one embodiment of the pixel circuit shown in FIG6 of this disclosure, during operation, the operation of the bias stage S2 causes the driving transistors at different positions of the screen to be forward biased, so that areas of the screen that have been black for a long time can also be forward biased, thereby reducing the threshold voltage difference of the driving transistors in different areas and eliminating image retention.

[0158] In at least one embodiment of this disclosure, the first effective level stage is a write data stage S1, the third effective level stage is a bias stage, and the second effective level stage includes a detection stage S3 and a data write-back stage S4.

[0159] The detection phase S3 lasts longer than the data write-back phase S4, allowing sufficient time to detect the electrical signal on the external compensation line SL, so that an accurate compensation voltage can be calculated based on the electrical signal.

[0160] In at least one embodiment of this disclosure, since detection and data writing are required during the second effective level phase, while only data writing is required during the first effective level phase, the duration of the second effective level phase can be set to be longer than the duration of the first effective level phase.

[0161] In at least one embodiment of this disclosure, the duration of the first floating phase SF1 is longer than the duration of the write data phase S1.

[0162] In specific implementation, the duration of the first floating phase SF1 can be set to be longer than the duration of the write data phase S1, so as to separate the write data phase S1 and the bias phase S2 through the first floating phase SF1.

[0163] In at least one embodiment of this disclosure, the duration of the first levitation phase SF1 is longer than the duration of the second levitation phase SF2.

[0164] In specific implementation, since the duration of the second effective level phase is longer than the duration of the first effective level phase, the duration of the first floating phase SF1 can be set to be longer than the duration of the second floating phase SF2.

[0165] The difference between at least one embodiment of the pixel circuit shown in FIG8 of this disclosure and at least one embodiment of the pixel circuit shown in FIG6 of this disclosure is that: it further includes a second light-emitting control circuit;

[0166] The second light-emitting control circuit includes a fifth transistor T5;

[0167] The gate of the fifth transistor T5 is electrically connected to the second light-emitting control terminal EM2, the drain of the fifth transistor T5 is electrically connected to the second node N2, and the source of the fifth transistor T5 is electrically connected to the anode of the organic light-emitting diode O1.

[0168] As shown in FIG9, when at least one embodiment of the pixel circuit shown in FIG8 of this disclosure is in operation, the display cycle may include a data writing stage S1, a first floating stage SF1, a bias stage S2, a second floating stage SF2, a detection stage S3, a data write-back stage S4, and a light emission stage S5 arranged sequentially.

[0169] During the data writing phase S1, DT provides the compensated data voltage Vd', G3 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a low voltage signal, T4 is turned on, T3 is turned on, Vd' is written to the gate of T0, and the reference voltage Vj provided by SL is written to the second node N2; T5 is turned off; the compensated data voltage Vd' is the sum of the original data voltage and the compensated voltage obtained according to the detection result of the detection phase in the previous display cycle;

[0170] During the first floating phase SF1 and the second floating phase SF2, G3, G1, G2 and EM1 all provide low voltage signals, and T0, T1, T2, T3 and T4 are all turned off.

[0171] During the biasing phase S2, G3 provides a low voltage signal, G1 provides a high voltage signal, G2 provides a high voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, T1 is turned on, REF provides a bias voltage Vref to N1, controlling T0 to be in a forward bias state and improving the hysteresis of T0; T3 is turned on, SL provides a reference voltage Vj to the second node N2; T5 is turned off.

[0172] During the detection phase S3, DT provides the raw data voltage, G3 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, and EM2 provides a low voltage signal. T4 and T3 are turned on, and T0 is turned on. The compensation voltage can be calculated based on the electrical signal on SL. T5 is turned off.

[0173] During the data write-back phase S4, DT provides the compensated data voltage Vd', G3 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, T4 and T3 are turned on, Vd' is written to the gate of T0, and the reference voltage Vj provided by SL is written to the second node N2; T5 is turned off; the compensated data voltage Vd' is the sum of the original data voltage and the compensated voltage obtained according to the detection result in the detection phase of the previous display cycle;

[0174] During the light-emitting stage S5, EM1 provides a high voltage signal, G1, G2 and G3 provide low voltage signals, EM2 provides a high voltage signal, T2 is turned on, T5 is turned on, and T0 drives O1 to emit light.

[0175] The difference between at least one embodiment of the pixel circuit shown in FIG. 10 of this disclosure and at least one embodiment of the pixel circuit shown in FIG. 8 of this disclosure is that the first transistor T1 is not included, and the drain of T2 is electrically connected to the first voltage terminal V1.

[0176] In at least one embodiment of the pixel circuit shown in Figures 8 and 10 of this disclosure, all transistors may be n-type transistors and all transistors may be oxide transistors.

[0177] As shown in FIG11, when at least one embodiment of the pixel circuit shown in FIG10 of this disclosure is in operation, the display cycle may include a data writing stage S1, a first floating stage SF1, a bias stage S2, a second floating stage SF2, a detection stage S3, a data write-back stage S4, and a light emission stage S5 arranged sequentially.

[0178] During the data writing phase S1, DT provides the compensated data voltage Vd', G3 provides a high voltage signal, G1 provides a high voltage signal, EM1 provides a low voltage signal, T4 is turned on, T3 is turned on, Vd' is written to the gate of T0, and the reference voltage Vj provided by SL is written to the second node N2; T5 is turned off, and the compensated data voltage Vd' is the sum of the original data voltage and the compensation voltage obtained according to the detection result of the detection phase in the previous display cycle;

[0179] During the first floating phase SF1 and the second floating phase SF2, G3, G1, G2 and EM1 all provide low voltage signals, and T0, T1, T2, T3 and T4 are all turned off.

[0180] During the biasing phase S2, G3 provides a low voltage signal, G1 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, T2 is turned on, V1 provides a bias voltage to the second node N2, controlling T0 to be in a positive bias state and improving the hysteresis of T0; T3 is turned on, SL provides a reference voltage Vj to the second node N2; T5 is turned off.

[0181] During the detection phase S3, DT provides the raw data voltage, G3 provides a high voltage signal, G1 provides a high voltage signal, EM1 provides a high voltage signal, and EM2 provides a low voltage signal. T4 and T3 are turned on, and T0 is turned on. The compensation voltage can be calculated based on the electrical signal on SL. T5 is turned off.

[0182] During the data write-back phase S4, DT provides the compensated data voltage Vd', G3 provides a high voltage signal, G1 provides a high voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, T4 is turned on, T3 is turned on, Vd' is written to the gate of T0, and the reference voltage Vj provided by SL is written to the second node N2; T5 is turned off; the compensated data voltage Vd' is the sum of the original data voltage and the compensated voltage obtained according to the detection result in the detection phase of the previous display cycle;

[0183] During the light-emitting stage S5, V1 provides the power supply voltage signal, EM1 provides the high voltage signal, G1 and G3 provide the low voltage signal, EM2 provides the high voltage signal, T2 is turned on, T5 is turned on, and T0 drives O1 to emit light.

[0184] The driving method described in this embodiment is applied to the pixel circuit described above. The display cycle of the pixel circuit includes a first effective level phase and a second effective level phase set sequentially, and a third effective level phase set between the first effective level phase and the second effective level phase. The driving method includes:

[0185] During the third effective level phase, the control circuit writes the bias voltage signal into the first node;

[0186] During the first effective level phase and the second effective level phase, the data writing circuit controls the connection between the data line and the control node under the control of the third scan signal provided by the third scan terminal.

[0187] The display device described in this disclosure includes the pixel circuit described above.

[0188] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a driving circuit, an external compensation control circuit, a control circuit, and a data writing circuit; the display cycle of the pixel circuit includes a first effective level phase and a second effective level phase set sequentially, and a third effective level phase set between the first effective level phase and the second effective level phase; The control terminal of the driving circuit is electrically connected to the control node, the first terminal of the driving circuit is electrically connected to the first node, and the second terminal of the driving circuit is electrically connected to the light-emitting element through the second node. The driving circuit is used to generate a driving current to drive the light-emitting element under the potential control of the control node. The external compensation control circuit is electrically connected to the first scanning end, the external compensation line and the second node respectively, and is used to control the connection or disconnection between the external compensation line and the second node under the control of the first scanning signal provided by the first scanning end; The control circuit is electrically connected to the first node and is used to write the bias voltage signal into the first node during the third effective level phase. The data writing circuit is electrically connected to the third scanning terminal, the data line, and the control node, respectively, and is used to control the connection between the data line and the control node under the control of the third scanning signal provided by the third scanning terminal during the first effective level stage and the second effective level stage.

2. The pixel circuit as described in claim 1, wherein, It also includes a first light-emitting control circuit; the control circuit is a bias control circuit. The bias control circuit is electrically connected to the second scanning terminal, the bias voltage terminal and the first node respectively, and is used to write the bias voltage provided by the bias voltage terminal into the first node under the control of the second scanning signal provided by the second scanning terminal during the third effective level stage. The first light-emitting control circuit is connected to the first light-emitting control terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the first node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

3. The pixel circuit as described in claim 1, wherein, The control circuit is a first light-emitting control circuit; the display cycle also includes a light-emitting phase set after the second effective level phase; The first light-emitting control circuit is connected to the first light-emitting control terminal, the first voltage terminal and the first node respectively. Under the control of the first light-emitting control signal provided by the first light-emitting control terminal, during the third effective level stage, the circuit writes the bias voltage signal provided by the first voltage terminal into the first node. During the light-emitting stage, the circuit controls the connection between the first voltage terminal and the first node. The first voltage terminal is used to provide a bias voltage signal during the third effective level phase and a power supply voltage signal during the light emission phase.

4. The pixel circuit according to any one of claims 1 to 3, wherein, The second valid level phase includes a detection phase and a data write-back phase set sequentially; the first valid level phase is the data write-back phase. The external compensation control circuit is used to control the connection between the external compensation line and the second node under the control of the first scan signal during the detection phase. The compensation voltage can be calculated based on the electrical signal on the external compensation line during the detection phase. The external compensation control circuit is also used in the data writing stage and the data write-back stage, under the control of the first scan signal, to control the connection between the external compensation line and the second node, and to write the reference voltage provided by the external compensation line into the second node.

5. The pixel circuit as described in claim 4, wherein, The detection phase lasts longer than the data write-back phase.

6. The pixel circuit according to any one of claims 1 to 3, wherein, The duration of the second effective level phase is longer than the duration of the first effective level phase.

7. The pixel circuit as described in claim 4, wherein, The third effective level phase is a bias phase. The display cycle also includes a first floating phase set between the write data phase and the bias phase, and a second floating phase set between the bias phase and the detection phase. During the first floating phase and the second floating phase, the transistors included in the pixel circuit are turned off.

8. The pixel circuit as described in claim 7, wherein, The duration of the first floating phase is longer than the duration of the data writing phase.

9. The pixel circuit as described in claim 7, wherein, The duration of the first floating phase is longer than the duration of the second floating phase.

10. The pixel circuit as claimed in claim 2 or 3, wherein, It also includes a second light-emitting control circuit and an energy storage circuit; the second node is electrically connected to the first electrode of the light-emitting element through the second light-emitting control circuit. The second light-emitting control circuit is electrically connected to the second light-emitting control terminal and is used to control the connection or disconnection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; The first end of the energy storage circuit is electrically connected to the control node, and the second end of the energy storage circuit is electrically connected to the second node. The energy storage circuit is used to store electrical energy.

11. The pixel circuit as claimed in claim 2, wherein, The bias control circuit includes a first transistor; The gate of the first transistor is electrically connected to the second scan terminal, the first terminal of the first transistor is electrically connected to the bias voltage terminal, and the second terminal of the first transistor is electrically connected to the first node.

12. The pixel circuit as described in claim 2 or 3, wherein, The first light-emitting control circuit includes a second transistor; The gate of the second transistor is electrically connected to the first light-emitting control terminal, the first terminal of the second transistor is electrically connected to the first voltage terminal, and the second terminal of the second transistor is electrically connected to the first node.

13. The pixel circuit as claimed in claim 1, wherein, The external compensation control circuit includes a third transistor; The gate of the third transistor is electrically connected to the first scanning terminal, the first electrode of the third transistor is electrically connected to the external compensation line, and the second electrode of the third transistor is electrically connected to the second node. The data writing circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the third scan terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the control node.

14. The pixel circuit as claimed in claim 10, wherein, The second light-emitting control circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element. The energy storage circuit includes a storage capacitor; The first end of the storage capacitor is electrically connected to the control node, and the second end of the storage capacitor is electrically connected to the second node.

15. A driving method applied to a pixel circuit as described in any one of claims 1 to 14, wherein the display cycle of the pixel circuit includes a first effective level phase and a second effective level phase configured sequentially, and a third effective level phase configured between the first effective level phase and the second effective level phase; the driving method includes: During the third effective level phase, the control circuit writes the bias voltage signal into the first node; During the first effective level phase and the second effective level phase, the data writing circuit controls the connection between the data line and the control node under the control of the third scan signal provided by the third scan terminal.

16. A display device comprising a pixel circuit as claimed in any one of claims 1 to 14.

Images