Method for the production of an electronic component, and electronic component

Abstract

A method for producing an electronic component comprises steps of: providing a carrier, in which conductor tracks and a contact structure are positioned on a top side of the carrier; removing part of the material of the carrier on the top side of the carrier in order to create a cavity with a recessed top side in a vicinity of the contact structure, such that the contact structure is raised above the recessed top side; positioning a semiconductor chip above the contact structure; and establishing an electrically conductive connection between the contact structure and the semiconductor chip.

Description

[0001] METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT

[0002] DESCRIPTION

[0003] The present invention relates to a method for manufacturing an electronic component and to an electronic component.

[0004] The patent application claims priority from German patent application 10 2024 111 163 . 1 , the disclosure content of which is hereby incorporated by reference.

[0005] State of the art

[0006] Electronic components with semiconductor chips arranged on substrates, as well as associated manufacturing processes, are known in various forms.

[0007] One object of the present invention is to provide a method for manufacturing an electronic component. A further object of the invention is to provide an electronic component. These objects are achieved by a method for manufacturing an electronic component and by an electronic component having the features of the independent claims. Various embodiments are specified in the dependent claims.

[0008] A method for manufacturing an electronic component comprises steps for providing a support in which conductive traces and a contact structure are arranged on a top side of the support, for removing a portion of the support material on the top side of the support to create a cavity with a recessed top side in a region of the contact structure so that the contact structure is raised above the recessed top side, for placing a semiconductor chip over the contact structure, and for creating an electrically conductive connection between the contact structure and the semiconductor chip.

[0009] By placing the cavity in the vicinity of the contact structure, this manufacturing process ensures good accessibility to the contact structure. This allows the semiconductor chip to be positioned over the contact structure in a simple and reliable manner and electrically connected to it.

[0010] In one variant of the process, the cavity is created by sputter etching, plasma etching, wet etching, or laser ablation. These processes advantageously allow for the selective removal of a portion of the substrate material on the top surface of the substrate in the vicinity of the contact structure.

[0011] In one variant of the process, a blackening layer applied to the contact structure is removed simultaneously with the removal of part of the substrate material. Removing the blackening layer can advantageously enable a more reliable creation of an electrically conductive connection between the contact structure and the semiconductor chip. The simultaneous removal of part of the substrate material and the blackening layer applied to the contact structure allows for a particularly efficient execution of the process.

[0012] In one variant of the process, the blackening layer comprises copper nitride, a copper oxide, palladium or palladium oxide, rhodium, platinum, another dark metal or metal oxide, carbon, or silicon. Such a blackening layer can reduce the visibility of the conductor tracks on the top surface of the substrate, thereby contributing to a more favorable external appearance of the electronic component. In another variant of the process, the placement of the semiconductor chip over the contact structure includes steps for placing a trap material on the contact structure in the cavity area and for placing the semiconductor chip on the trap material. Advantageously, placing the trap material allows for particularly simple assembly of the semiconductor chip.In this process, the semiconductor chip is held by the trapping material after it has been arranged on the trapping material, which enables a simple and reliable production of the electrically conductive connection between the contact structure and the semiconductor chip.

[0013] In one variation of the process, the trapping material contains a flux, hydrocarbon, or solder paste. Advantageously, such trapping materials facilitate the creation of the electrically conductive connection between the contact structure and the semiconductor chip.

[0014] In one variation of the process, the electrically conductive connection is created by soldering or gluing. Advantageously, these methods enable a simple and reliable creation of the electrically conductive connection between the semiconductor chip and the contact structure.

[0015] In one variant of the process, arranging the semiconductor chip over the contact structure and establishing the electrically conductive connection includes steps for applying an anisotropically conductive adhesive film to the contact structure in the cavity area and for arranging the semiconductor chip on the anisotropically conductive adhesive film. The use of an anisotropically conductive adhesive film is made possible by the fact that the contact structure is readily accessible through the cavity located on the top side of the substrate. The use of an anisotropically conductive adhesive film enables a simple, cost-effective, and reliable fabrication of the electrically conductive connection between the contact structure and the semiconductor chip.In one variant of the process, arranging the semiconductor chip over the contact structure and establishing the electrically conductive connection includes steps for providing a soft metal protrusion on the contact structure or on the semiconductor chip and pressing the semiconductor chip onto the contact structure such that the metal protrusion is positioned between the contact structure and the semiconductor chip. The use of a soft metal protrusion to establish the electrically conductive connection is also made possible by the good accessibility of the contact structure, which is achieved by placing the cavity on the top side of the substrate.

[0016] In one variation of the process, the semiconductor chip is pressed onto the substrate using a cover film containing an adhesive layer. The semiconductor chip is embedded in the adhesive layer. Advantageously, this also allows for cost-effective embedding of the semiconductor chip and the conductor tracks arranged on the top surface of the substrate.

[0017] In one variant of the process, providing the carrier comprises steps for providing a base carrier with a molded layer arranged on one top side of the base carrier, wherein an embossing defining the conductor tracks and contact structure is provided on one top side of the molded layer, for applying a metallic coating to the top side of the molded layer, and for back-grinding the metallic coating to form the conductor tracks and contact structure. Advantageously, this enables cost-effective manufacturing of the carrier.

[0018] In one variant of the process, the mold layer comprises an acrylate or an epoxy resin. Advantageously, the embossing defining the conductor tracks and the contact structure can be provided with high precision in such a mold layer. In another variant of the process, the preparation of the substrate includes steps for providing a base substrate with a metallization layer arranged on one top side of the base substrate and for structuring the metallization layer to form the conductor tracks and the contact structure. Advantageously, this also enables simple and cost-effective fabrication of the substrate.

[0019] In one variation of the process, the substrate is made of a transparent material, in particular PET, polycarbonate, or PMMA. Advantageously, this allows for the production of a transparent substrate.

[0020] An electronic component comprises a substrate with a top surface on which conductive traces and a contact structure are arranged. A cavity with a recessed top surface is formed on the substrate's top surface, surrounding the contact structure. The contact structure protrudes above this recessed top surface. A semiconductor chip is positioned above the contact structure and electrically connected to it.

[0021] In this electronic component, the cavity formed on the top of the carrier in the vicinity of the contact structure ensures good accessibility of the contact structure, thereby guaranteeing a reliable electrically conductive connection between the contact structure and the semiconductor chip.

[0022] In one variant of the electronic component, the conductor tracks form a grid. This allows the conductor tracks to be designed in such a way that they cover only a small part of the top surface of the substrate.

[0023] In one variant of the electronic component, less than 20% of the substrate's top surface is covered by the conductor tracks and the contact structure. This advantageously results in low visibility of the conductor tracks. In another variant of the electronic component, the conductor tracks have a blackening layer, at least in some sections. The contact structure, however, does not have this blackening layer. The blackening layer can reduce the visibility of the conductor tracks on the substrate's top surface, thus giving it a more aesthetically pleasing appearance. The absence of a blackening layer on the contact structure increases the reliability of the electrically conductive connection between the semiconductor chip and the contact structure.

[0024] In one variant of the electronic component, several contact structures are arranged on the top surface of the substrate. Each contact structure has a separate cavity. These contact structures can, for example, each be designed to accommodate a semiconductor chip.

[0025] The properties, features, and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more readily understandable in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the drawings. These drawings show, in each case, a schematic representation.

[0026] Fig. 1 shows a cutaway side view of a first variant of a carrier with an embossing provided in a mold layer;

[0027] Fig. 2 shows the carrier with a metallic coating applied to the mold layer;

[0028] Fig. 3 shows the carrier after back-grinding of the metallic coating to form conductor tracks and a contact structure; Fig. 4 shows the carrier during the removal of part of the carrier material from the top of the carrier;

[0029] Fig. 5 shows the carrier with a cavity formed on the upper side;

[0030] Fig. 6 shows the carrier with a trapping material arranged on the contact structure in the area of ​​the cavity;

[0031] Fig. 7 shows the carrier with a semiconductor chip arranged on the capture material;

[0032] Fig. 8 shows a first variant of an electronic component obtained after establishing an electrically conductive connection between the contact structure and the semiconductor chip;

[0033] Fig. 9 shows a top view of part of the electronic component;

[0034] Fig. 10 shows a cutaway side view of a second variant of the support with a metallization layer arranged on the top side of a base support;

[0035] Fig. 11 shows the carrier with a mask arranged on the metallization layer;

[0036] Fig. 12 shows the carrier after structuring the metallization layer to form conductor tracks and a contact structure;

[0037] Fig. 13 shows the support during the removal of part of the material from the top of the support;

[0038] Fig. 14 shows the carrier with a cavity formed on the upper side in the vicinity of the contact structure; Fig. 15 shows the carrier after a capturing material has been arranged on the contact structure in the area of ​​the cavity;

[0039] Fig. 16 shows the carrier with a semiconductor chip arranged on the capture material;

[0040] Fig. 17 shows a second variant of the electronic component obtained after establishing an electrically conductive connection between the contact structure and the semiconductor chip;

[0041] Fig. 18 shows a third variant of the electronic component; and

[0042] Fig. 19 shows a fourth variant of the electronic component.

[0043] Fig. 1 shows a schematic cutaway side view of part of a support 100. The support 100 has a flat and essentially planar shape with a top surface 101. The support 100 can also be referred to as a substrate.

[0044] The support 100 comprises a base support 110 and a molded layer 120 arranged on a top surface 111 of the base support 110. A top surface 121 of the molded layer 120 facing away from the base support 110 forms the top surface 101 of the support 100.

[0045] The base carrier 110 can be made of a transparent material, for example PET, polycarbonate or PMMA. The mold layer 120 can be made of, for example, an acrylate or an epoxy.

[0046] The upper surface 121 of the mold layer 120 has an embossing 130. The embossing 130 may, for example, have been introduced into the mold layer 120 by means of a stamp during the curing of the material of the mold layer 120. Fig. 2 shows a schematic cutaway side view of the carrier 100 in a processing stage subsequent to that shown in Fig. 1. A lower blackening layer 140 and a metallic coating 150s have been applied to the upper surface 121 of the mold layer 120.

[0047] The lower blackening layer 140 is directly adjacent to the upper surface 121 of the mold layer 120 and is so thin that it essentially replicates the embossing 130 on the upper surface 121 of the mold layer 120. The lower blackening layer 140 can advantageously comprise a dark material such as carbon or silicon, or a dark metal or metal oxide, for example, copper nitride, a copper oxide, palladium or palladium oxide, rhodium, or platinum. However, the lower blackening layer 140 can also be omitted.

[0048] The metallic coating 150 borders the lower blackening layer 140 and is thick enough to essentially level the embossing 130. Thus, the metallic coating 150 forms a continuous coating on the top surface 101 of the substrate 100. The metallic coating 150 can, for example, contain copper.

[0049] Fig. 3 shows a schematic cutaway side view of the carrier 100 in a processing stage that follows the representation in Fig. 2. The metallic coating 150 has been thinned by back-grinding to such an extent that sections of the metallic coating 150 remain only in the recessed areas of the embossing 130 on the upper surface 121 of the mold layer 120.

[0050] These remaining parts of the metallic coating 150 form conductive tracks 250 and a contact structure 200 on the top surface 101 of the substrate 100. The position, shape, and size of the conductive tracks 250 and the contact structure 200 are defined by the embossing 130. The remaining parts of the metallic coating 150 forming the contact structure 200 and the conductive tracks 250 have a thickness 151 measured perpendicular to the top surface 101 of the substrate 100, which may, for example, be approximately 2 pm.

[0051] The back-grinding process can create indentations 170 on the upper surfaces of the conductor tracks 250 and the contact structure 200. These indentations 170 can, for example, have a depth of several hundred nm.

[0052] After re-grinding the metallic coating 150, an upper blackening layer 160 was applied to the contact structure 200 and to the conductor tracks 250. This could have been done, for example, by electroless deposition. The upper blackening layer 160 can have a similar thickness to the lower blackening layer 140 and comprises one of the materials specified for the lower blackening layer 140.

[0053] In the illustrated example, the contact structure 200 comprises a first contact surface 210 and a second contact surface 220 separated from the first contact surface 210. The first contact surface 210 and the second contact surface 220 are arranged laterally adjacent to each other on the top surface 101 of the carrier 100. The first contact surface 210 and the second contact surface 220 are each electrically connected to one or more conductor tracks 250. However, the first contact surface 210 and the second contact surface 220 are electrically separated from each other. In other variants, the contact structure 200 can comprise more than two contact surfaces 210, 220.

[0054] Fig. 4 shows a schematic cutaway side view of a processing step that follows the representation in Fig. 3. In this step, a portion of the material of the carrier 100 is removed from the top surface 101 of the carrier 100 in the vicinity of the contact structure 200 to create a cavity 300 with a recessed top surface 301. The cavity 300 can be created, for example, by sputter etching or by a dry etching process using a reactive or non-reactive plasma (e.g., argon, oxygen, or nitrogen). Alternatively, the cavity 300 can also be created by wet etching with an organic or inorganic acid (e.g., acetic acid, citric acid, sulfuric acid, or hydrogen peroxide). The acid can be applied, for example, as etching droplets using a metering process.It is also possible to create the cavity 300 by laser ablation, for example using a UV or IR laser.

[0055] The cavity 300 can be formed using a mask 310. The mask 310 can, for example, be a metal mask, which can be produced using a laser or by etching and must first be aligned over the carrier 100. Alternatively, the mask 310 can be made of a photoresist. In this case, the mask 310 can optionally remain on the top surface 101 of the carrier 100 after the cavity 300 has been formed.

[0056] The upper blackening layer 160 on the contact structure 200 can be removed simultaneously with the creation of the cavity 300. It is advantageous if this is done concurrently with the creation of the cavity 300 by the process that removes part of the carrier 100's material. Alternatively, a separate process can be used for removing the upper blackening layer 160. In the areas located laterally outside the cavity 300 on the top surface 101 of the carrier 100, the upper blackening layer 160 remains on the conductor tracks 250.

[0057] After creating cavity 300, a wet cleaning step can optionally be performed.

[0058] Fig. 5 shows a schematic representation of a processing stage that follows the representation in Fig. 4 in time.

[0059] The cavity 300 has a depth 302 measured perpendicular to the top surface 101 of the support 100, which can be, for example, approximately 0.5 pm. In a lateral direction parallel to the top surface 101 of the support 100, the cavity 300 has a diameter 303, which can be, for example, between 0.1 mm and 1 mm.

[0060] The contact structure 200 is raised above the recessed upper surface 301 of the cavity 300. Thus, the contact surfaces 210, 220 of the contact structure 200 are easily accessible on the upper surface 101 of the support 100, despite any recesses 170 that may be present.

[0061] Fig. 6 shows a schematic cutaway side view of a processing stage that follows the representation in Fig. 5. In the area of ​​the cavity 300, a retaining material 320 has been arranged on the contact structure 200. The retaining material 320 can cover parts of the first contact surface 210 and the second contact surface 220, as well as parts of the recessed upper surface 301 of the cavity 300 between the first contact surface 210 and the second contact surface 220.

[0062] The catch material 320 may, for example, contain a flux, a hydrocarbon, or a solder paste.

[0063] The application of the trapping material 320 may, for example, have been carried out by a printing process.

[0064] Fig. 7 shows a schematic cutaway side view of a processing stage that follows the representation in Fig. 6. A semiconductor chip 400 has been arranged over the contact structure 200. For this purpose, the semiconductor chip 400 has been arranged on the holding material 320 such that the holding material 320 at least lightly holds the semiconductor chip 400 in its position.

[0065] The semiconductor chip 400 has a top surface 401 and a contact surface 402 opposite the top surface 401. The contact surface 402 of the semiconductor chip 400 is oriented towards the contact structure 200 on the top surface 101 of the carrier 100, such that the top surface 401 of the semiconductor chip 400 points away from the carrier 100.

[0066] On its contact side 402, the semiconductor chip 400 has contact areas 410, which are provided for electrical contacting the semiconductor chip 400. In the example shown, the semiconductor chip 400 has two contact areas 410, which correspond to the two contact surfaces 210, 220 of the contact structure 200. However, the semiconductor chip 400 could also have more than two contact areas 410. In this case, the contact structure 200 can comprise more than two contact surfaces 210, 220.

[0067] A connecting material 420 is arranged at each of the contact areas 410 of the semiconductor chip 400. The connecting material 420 can be, for example, a solder or an electrically conductive adhesive.

[0068] The arrangement of the semiconductor chip 400 over the contact structure 200 can be carried out, for example, by a laser-induced forward transfer (LI FT).

[0069] The semiconductor chip 400 can, for example, be an optoelectronic semiconductor chip, such as a light-emitting optoelectronic semiconductor chip, for example, a light-emitting diode (LED) chip or a laser chip. In this case, the top surface 401 of the semiconductor chip 400 can be a light-emitting surface of the semiconductor chip 400. The semiconductor chip 400 can, for example, be an LED chip with dimensions in the pm range. However, the semiconductor chip 400 can also be any other semiconductor chip that can have dimensions in the pm or mm range.

[0070] Fig. 8 shows a schematic cutaway side view of a processing stage that follows the representation in Fig. 7. An electrically conductive connection has been established between the semiconductor chip 400 and the contact structure 200. This may have been done, for example, by soldering or gluing. The connecting material 420 provided at the contact areas 410 of the semiconductor chip 400 now establishes electrically conductive connections between the contact surfaces 210, 220 of the contact structure 200 and the contact areas 410 of the semiconductor chip 400. The trapping material 320 may have assisted in establishing the electrically conductive connection.

[0071] In the processing stage shown in Fig. 8, the production of an electronic component 10 can be completed. The electronic component 10 comprises the carrier 100 with the conductor tracks 250 arranged on the top surface 101 of the carrier 100 and the contact structure 200. In the vicinity of the contact structure 200, the cavity 300 is formed on the top surface 101 of the carrier 100. The contact structure 200 is raised above the recessed top surface 301 of the cavity 300. The semiconductor chip 400 is arranged above the contact structure 200 and electrically connected to the contact structure 200.

[0072] Fig. 9 shows a schematic view of a portion of the top surface 101 of the carrier 100 of the electronic component 10. It can be seen that the conductor tracks 250 form a grid 260 in the illustrated example. In this example, less than 20% of the top surface 101 of the carrier 100 is covered by the conductor tracks 250 and the contact structure 200. Parts of the conductor tracks 250 located laterally outside the cavity 300 have the upper blackening layer 160. The contact structure 200 located in the region of the cavity 300 and the sections of the conductor tracks 250 located in the region of the cavity 300 do not have the upper blackening layer 160. In the lateral areas outside the cavity 300, the conductor tracks 250 are embedded in the mold layer 120 of the carrier 100.

[0073] The optoelectronic component 10 can have several contact structures 200 arranged at different lateral positions on the top surface 101 of the carrier 100. In this case, a separate cavity 300 can be provided in the vicinity of each contact structure 200 and configured as described above. A semiconductor chip 400 is then arranged at each contact structure 200.

[0074] In the manufacturing process described above with reference to Figures 1 to 9, the carrier 100 with the conductive tracks 250 and the contact structure 200 arranged on the top surface 101 of the carrier 100 was provided by the process steps described with reference to Figures 1 to 3. An alternative variant of the process for manufacturing the electronic component 10 is described below with reference to Figures 10 to 17. In this variant, the steps for providing the carrier 100 with the conductive tracks 250 and the contact structure 200 arranged on the top surface 101 of the carrier 100, as described with reference to Figures 10 to 12, differ in particular from the variant described above.Furthermore, the variant of the manufacturing process described below shows a high degree of similarity to the variant of the manufacturing process described above, so that the above description also applies to the second variant of the manufacturing process, unless deviations are explicitly described.

[0075] As schematically shown in Fig. 10, in the second variant of the manufacturing process, the carrier 100 comprises the base carrier 110 and a metallization layer 180 arranged on the upper surface 111 of the base carrier 110. The metallization layer 180 forms a continuous layer and can, for example, have a thickness of approximately 2 pm. The metallization layer 180 can, for example, consist of copper. On a side of the metallization layer 180 facing away from the base carrier 110, an upper blackening layer 160 is arranged. In this case, the upper blackening layer 160 can, for example, consist of copper nitride.

[0076] Fig. 11 shows a schematic cutaway side view of a processing stage that follows the representation in Fig. 10. A mask 190 has been arranged on the metallization layer 180 and the upper blackening layer 160 above the top surface 101 of the carrier 100. The mask 190 can, for example, be made of a photoresist.

[0077] Fig. 12 shows a schematic cutaway side view of a processing stage that follows the representation in Fig. 11. The metallization layer 180 and the upper blackening layer 160 arranged on the metallization layer 180 have been structured to form the conductor tracks 250 and the contact structure 200. Sections of the metallization layer 180 not protected by the mask 190 have been removed. The mask 190 thus defines the position, shape, and size of the contact structure 200 and the conductor tracks 250.

[0078] The structuring of the metallization layer 180 may, for example, have been carried out by a wet chemical etching process.

[0079] In the processing state shown in Fig. 12, the carrier 100 is provided with the conductive tracks 250 and the contact structure 200 arranged on the top surface 101 of the carrier 100. This variant of the carrier 100 differs from the variant shown in Fig. 3 in that the conductive tracks 250 and the contact structure 200 on the top surface 101 of the carrier 100 are not embedded in the material of the carrier 100, but are raised above the top surface 101 of the carrier 100. In Fig. In step 13, shown schematically, a portion of the material of the carrier 100 is removed from the top surface 101 of the carrier 100 in order to create the cavity 300 with the recessed top surface 301 in the vicinity of the contact structure 200. This is done as described above with reference to Fig. 4.In particular, in this processing step the upper blackening layer 160 arranged on the contact structure 200 is also removed.

[0080] Fig. 14 shows a schematic cutaway side view of the cavity 300 thus formed. The contact structure 200 is raised above the recessed top surface 301 of the cavity 300.

[0081] In the processing state shown schematically in Fig. 15, the trapping material 320 has been arranged in the area of ​​the cavity 300 on the contact structure 200, as described above with reference to Fig. 6.

[0082] In the processing station shown schematically in Fig. 16, the semiconductor chip 400 is arranged above the contact structure 200 on the holding material 320. This corresponds to the processing station described above with reference to Fig. 7.

[0083] In the processing stage shown schematically in Fig. 17, an electrically conductive connection has been established between the semiconductor chip 400 and the contact structure 200. This completes the production of the second variant of the optoelectronic component 10.

[0084] Fig. 18 shows another variant of the optoelectronic component 10, which can be produced by a further variant of the manufacturing process described above. In the example shown in Fig. 18, the carrier 100 is designed as in the variant shown in Fig. 8. Alternatively, the carrier 100 can also be designed in this variant as in the variant of Fig. 17. In the production of the variant of the optoelectronic component 10 shown in Fig. 18, a section of an anisotropically conductive adhesive film 500 was arranged on the contact structure 200 in the area of ​​the cavity 300 instead of the trapping material 320, according to the processing stage shown in Fig. 5. The semiconductor chip 400 was then arranged on the anisotropically conductive adhesive film 500, thus creating an electrically conductive connection between the semiconductor chip 400 and the contact structure 200. The connecting material 420 could be omitted.

[0085] Fig. 19 shows a schematic cutaway side view of another variant of the optoelectronic component 10, which can be manufactured using a further variant of the manufacturing process described above. In the example shown in Fig. 19, the carrier 100 of the electronic component 10 is designed like the carrier 100 of the variant of the electronic component 10 shown in Fig. 8. Alternatively, the carrier 100 of the variant of the electronic component 10 shown in Fig. 19 can be designed like the carrier 100 of the variant of the electronic component 10 shown in Fig. 17.

[0086] In the production of the variant of the electronic component 10 shown in Fig. 19, no capping material 320 was arranged on the contact structure 200 according to the processing stage shown in Fig. 5. The semiconductor chip 400 was not provided with the connecting material 420 arranged on the contact areas 410, but with soft metal protrusions 600 arranged on the contact areas 410. Alternatively, the metal protrusions 600 could be provided on the contact surfaces 210, 220 of the contact structure 200. The metal protrusions 600 comprise a soft metal, for example gold. The semiconductor chip 400 was then pressed onto the contact structure 200 in such a way that the metal protrusions 600 are arranged between the contact structure 200 and the semiconductor chip 400 and create an electrically conductive connection between the contact structure 200 and the semiconductor chip 400.

[0087] In the illustrated example, the semiconductor chip 400 is pressed onto the substrate using a cover 700, which comprises a cover film 710 and an adhesive layer 720 arranged on the cover film 710. The cover 700 was positioned over the top surface 101 of the substrate 100 such that the adhesive layer 720 faces the top surface 101 of the substrate 100. The cover 700 was pressed onto the top surface 101 of the substrate 100 such that the semiconductor chip 400 was embedded in the adhesive layer 720 and pressed onto the contact structure 200 in the manner described. The cover 700 can remain attached to the electronic component 10.

[0088] The cover film 710 of the cover 700 can, for example, be made of PET, a polycarbonate, or PMMA. The adhesive layer 720 can, for example, be made of an acrylate-based adhesive.

[0089] The invention has been illustrated and described in more detail with reference to preferred embodiments. However, the invention is not limited to the obvious examples. Other variations can be derived by a person skilled in the art.

[0090] REFERENCE SYMBOL LIST electronic component carrier top surface base carrier top surface molded layer top surface embossing bottom blackening layer metallic coating thickness top blackening layer recess metallization layer mask contact structure first contact surface second contact surface conductor track grid cavity recessed top surface depth diameter mask trap material semiconductor chip top surface contact side contact area interconnect material anisotropic conductive adhesive film metal bump cover cover film adhesive layer

Claims

PATENT CLAIMS 1. Method for manufacturing an electronic component (10) with the following steps: - Providing a carrier (100) wherein conductor tracks (250) and a contact structure (200) are arranged on a top side (101) of the carrier (100); - Removing part of the material of the support (100) on the top surface (101) of the support (100) to create a cavity (300) with a recessed top surface (301) in a environment of the contact structure (200), such that the contact structure (200) is raised above the recessed top surface (301); - Arranging a semiconductor chip (400) over the contact structure (200) ; - Establishing an electrically conductive connection between the contact structure (200) and the semiconductor chip (400) .

2. Method according to claim 1, wherein the cavity (300) is created by sputtering, plasma etching, wet etching or by laser ablation.

3. Method according to one of the preceding claims, wherein a blackening layer (160) arranged on the contact structure (200) is removed simultaneously with the removal of the part of the material of the carrier (100).

4. Method according to claim 3, wherein the blackening layer (160) comprises copper nitride, a copper oxide, palladium or a palladium oxide, rhodium, platinum or another dark metal or metal oxide, carbon or silicon.

5. A method according to any of the preceding claims, wherein the arrangement of the semiconductor chip (400) over the contact structure (200) comprises the following steps: - Arranging a catch material (320) on the contact structure (200) in the area of ​​the cavity (300) ; - Arranging the semiconductor chip (400) on the trapping material (320) .

6. The method of claim 5, wherein the trapping material (320) comprises a flux, a hydrocarbon or a solder paste.

7. Method according to one of the preceding claims, wherein the electrically conductive connection is made by soldering or gluing.

8. A method according to any one of claims 1 to 4, wherein arranging the semiconductor chip (400) over the contact structure (200) and establishing the electrically conductive connection comprises the following steps: - Arranging an anisotropically conductive adhesive film (500) on the contact structure (200) in the area of ​​the cavity (300) ; - Arranging the semiconductor chip (400) on the anisotropically conductive adhesive film (500) .

9. A method according to any one of claims 1 to 4, wherein arranging the semiconductor chip (400) over the contact structure (200) and establishing the electrically conductive connection comprises the following steps: - Providing a soft metal bump (600) on the contact structure (200) or on the semiconductor chip (400) ; - Pressing the semiconductor chip (400) onto the contact structure (200) such that the metal bump (600) is positioned between the contact structure (200) and the semiconductor chip (400).

10. Method according to claim 9, wherein the semiconductor chip (400) is pressed on using a cover film (710) having an adhesive layer (720), wherein the semiconductor chip (400) is embedded in the adhesive layer (720).

11. Method according to any of the preceding claims, wherein the provision of the carrier (100) comprises the following steps: - Providing a base carrier (110) with a molded layer (120) arranged on a top side (111) of the base carrier (110), wherein an embossing (130) defining the conductor tracks (250) and the contact structure (200) is provided on a top side (121) of the molded layer (120); - Applying a metallic coating (150) to the top surface (121) of the mold layer (120) ; - Grinding back the metallic coating (150) to form the conductor tracks (250) and the contact structure (200).

12. Method according to claim 11, wherein the mold layer (120) comprises an acrylate or an epoxy.

13. Method according to any one of claims 1 to 10, wherein the provision of the carrier (100) comprises the following steps: - Providing a base carrier (110) with a metallization layer (180) arranged on a top side (111) of the base carrier (110); - Structuring the metallization layer (180) to form the conductor tracks (250) and the contact structure (200).

14. Method according to any one of claims 11 to 13, wherein the base carrier (110) comprises a transparent material, in particular a PET, a polycarbonate or PMMA.

15. Electronic component (10) with a carrier (100) , wherein conductors are arranged on a top surface (101) of the carrier (100) tracks (250) and a contact structure (200) are arranged, wherein a cavity (300) with a recessed top surface (301) is formed on the top surface (101) of the carrier (100) in a region of the contact structure (200), wherein the contact structure (200) is raised above the recessed top surface (301), and wherein a semiconductor chip (400) is arranged above the contact structure (200) and is electrically connected to the contact structure (200).

16. Electronic component (10) according to claim 15, wherein the conductor tracks (250) form a grid (260).

17. Electronic component (10) according to one of claims 15 and 16, wherein less than 20% of the top surface (101) of the carrier (100) is covered by the conductor tracks (250) and the contact structure (200).

18. Electronic component (10) according to one of claims 15 to 17, wherein the conductor tracks (250) have at least a blackening layer (160) in sections, wherein the contact structure (200) does not have a blackening layer (160).

19. Electronic component (10) according to one of claims 15 to 18, wherein several contact structures (200) are arranged on the top side (101) of the carrier (100), wherein a separate cavity (300) is formed in the area of ​​each contact structure (200).

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