Semiconductor device

Abstract

The present invention provides a semiconductor device having reduced power consumption. This semiconductor device includes an operation cell and a drive cell. The operation cell has a first capacitive element and a second capacitive element that hold respective first terminals at a potential corresponding to first data w. The drive cell has a third capacitive element and a fourth capacitive element that hold the respective first terminals at a potential corresponding to reference data r. By supplying a current corresponding to second data x1 to the wiring connected to respective second terminals of the first capacitive element and the third capacitive element, the potential of the first terminal of the first capacitive element is, due to capacitive coupling, a potential corresponding to w × x1 / r. Similarly, by supplying a current corresponding to third data x2 to the wiring connected to respective second terminals of the second capacitive element and the fourth capacitive element, the potential of the first terminal of the second capacitive element is, due to capacitive coupling, a potential corresponding to w × x2 / r.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] There are also attempts to use a computing device that configures an artificial neural network, for example, to correct an image displayed on a display device. For example, Patent Document 1 discloses a display device that uses a computing device that configures an artificial neural network to adjust the brightness, color tone, etc. of a displayed image to suit the preferences of the viewer.

[0006] JP 2018-36639 A

[0007] M. Kang et al., "IEEE Journal of Solid-State Circuits", 2018, Volume 53, No. 2, pp. 642-655. J. Zhang et al., "IEEE Journal of Solid-State Circuits", 2017, Volume 52, No. 4, pp. 915-924. Takashi Koida, "High-Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0008] There are various models of artificial neural networks. For example, a model called a convolutional neural network (CNN) is used in image analysis. A convolutional neural network is a type of neural network that exhibits excellent performance in the field of image recognition, but the amount of calculation is determined by factors such as the image resolution and the filter size. Specifically, for example, the higher the image resolution, the larger the filter size, or the smaller the stride, the greater the amount of calculation in the convolutional neural network, which tends to result in longer processing times by the computing device. Furthermore, the greater the amount of calculation, the higher the power consumption of the computing device.

[0009] Furthermore, in a convolutional neural network, feature extraction is performed for each of the divided images using the same filter. Therefore, the filter is repeatedly used for each calculation, resulting in frequent read operations of the filter from a memory circuit or the like. Because the power consumption of both the read operation and the data transmission operation of the filter and the like is high, it is desirable for the calculation circuit that performs the calculation of the convolutional neural network to have a configuration called in-memory computing, which has a function of retaining the filter value, which is a multiplier, for a long period of time in addition to the calculation function. It is also desirable to have a configuration that reduces the number of data transmission operations such as files.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device that can hold a multiplier used in an operation for a long period of time.An object of one embodiment of the present invention is to provide a semiconductor device that can multiply one multiplier by each of a plurality of multiplicands at once.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide an electronic device including the above-described semiconductor device.

[0011] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0012] In the convolution process used in a convolutional neural network, each of the divided images is used as input data and multiplied by the same filter value. Therefore, in one aspect of the present invention, multiple retention nodes that retain the same filter value as a potential are required to perform the multiplication with each input data. Furthermore, by inputting a potential corresponding to the input data to each retention node via a capacitive element, the potential of the retention node becomes the sum of the potential of the filter value and the potential corresponding to the input data due to capacitive coupling.

[0013] When an n-channel transistor operates in the subthreshold region, the source-drain current (called the subthreshold current in this case) is calculated by multiplying the gate-source voltage by V ＧＳ As a result, exp[V ＧＳ -V ｔｈ ] is proportional to V ｔｈ is the threshold voltage of the transistor. At this time, the gate potential is set to a potential V Ｆ and the potential V corresponding to the input data ＩＮ The source potential is V ＧＮＤ When this is done, exp[V ＧＳ -V ｔｈ ] is exp[V Ｆ ]exp[V ＩＮ ]exp[V ＧＮＤ -V ｔｈ ] and the subthreshold current is Ｆ ] and exp[V ＩＮ ].

[0014] As described above, a semiconductor device according to one embodiment of the present invention includes a circuit in which one of a pair of electrodes of a capacitor and a gate of a transistor are connected to each other. Note that the connection point is a storage node. Furthermore, since each of a plurality of input data items is multiplied by the same filter, it is preferable that the number of such circuits is equal to the number of input data items. Furthermore, since a potential corresponding to the same filter value is held in each of the storage nodes of the plurality of such circuits, it is more preferable that the storage nodes are connected via a switch or the like. For example, by turning on the switch, the storage nodes are brought into a conductive state, and thus a potential corresponding to the same filter value can be written. Furthermore, by turning off the switch, the storage nodes are brought into a non-conductive state, and thus the potential of each storage node can be held.

[0015] In addition, in a semiconductor device according to one embodiment of the present invention, the potential written to each retention node can be determined by flowing a current corresponding to a filter value between the source and drain of the transistor. For example, in a configuration in which the gate and drain of a transistor are connected, a source potential is applied to the source of the transistor and a current of an amount I corresponding to the filter value is flowed to the drain of the transistor, so that the gate-source voltage of the transistor is determined according to the amount I. In other words, when the source potential is a fixed potential, the gate potential of the transistor (the potential of the retention node) is determined according to the amount I. Here, the amount I is the amount of source-drain current in the subthreshold region of the transistor.

[0016] As described above, by writing the potential of the retention node by passing a current of an amount I according to the filter value, multiplication can be performed more accurately than by writing the potential directly to the retention node. In the case of writing the potential directly to the retention node, the amount of current in the subthreshold region of the transistor is, as described above, exp[V ＧＳ -V ｔｈ], even a slight deviation in the potential to be written can result in a large deviation in the amount of current flowing between the source and drain of the transistor. For the above reasons, it is preferable to write the potential of the retention node by passing a current of an amount I corresponding to the filter value.

[0017] A specific configuration of one embodiment of the present invention will be described below.

[0018] (1) One embodiment of the present invention is a semiconductor device including a first cell and a second cell. The first cell includes first to sixth transistors, a first capacitor, and a second capacitor. The second cell includes seventh to twelfth transistors, a third capacitor, and a fourth capacitor.

[0019] One of the source or drain of the first transistor is electrically connected to the gate of the third transistor and the first terminal of the first capacitor, and the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, the gate of the fifth transistor, and the first terminal of the second capacitor. One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, and one of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor. The other of the source or drain of the second transistor and the other of the source or drain of the fourth transistor are each electrically connected to a first wiring, and the other of the source or drain of the sixth transistor is electrically connected to a second wiring.

[0020] One of the source or drain of the seventh transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitor, and the other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor, the gate of the eleventh transistor, and the first terminal of the fourth capacitor. One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor, and one of the source or drain of the eleventh transistor is electrically connected to one of the source or drain of the twelfth transistor. The other of the source or drain of the eighth transistor, the other of the source or drain of the tenth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are each electrically connected to a third wiring, and the other of the source or drain of the twelfth transistor, the second terminal of the second capacitor, and the second terminal of the fourth capacitor are each electrically connected to a fourth wiring.

[0021] The gate of the first transistor, the gate of the second transistor, the gate of the seventh transistor, and the gate of the eighth transistor are each electrically connected to a fifth wiring.

[0022] (2) Alternatively, in one aspect of the present invention, in the above (1), the channel length of one selected from the first transistor, the second transistor, the seventh transistor, and the eighth transistor may be longer than the channel lengths of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor. Also, in the above (1), the channel width of one selected from the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor may be longer than the channel widths of the first transistor, the second transistor, the seventh transistor, and the eighth transistor.

[0023] (3) Another embodiment of the present invention is a semiconductor device different from the semiconductor device described above in (1), which includes a first cell and a second cell. The first cell includes first to third transistors, a fifth transistor, a first capacitor, and a second capacitor. The second cell includes seventh to ninth transistors, an eleventh transistor, a third capacitor, and a fourth capacitor.

[0024] One of the source or drain of the first transistor is electrically connected to the gate of the third transistor and the first terminal of the first capacitance element, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, the gate of the fifth transistor, and the first terminal of the second capacitance element, the other of the source or drain of the second transistor and one of the source or drain of the third transistor are each electrically connected to a first wiring, and the one of the source or drain of the fifth transistor is electrically connected to a second wiring.

[0025] One of the source or drain of the seventh transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitance element, the other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor, the gate of the eleventh transistor, and the first terminal of the fourth capacitance element. The other of the source or drain of the eighth transistor, one of the source or drain of the ninth transistor, the second terminal of the first capacitance element, and the second terminal of the third capacitance element are each electrically connected to a third wiring, and one of the source or drain of the eleventh transistor, the second terminal of the second capacitance element, and the second terminal of the fourth capacitance element are each electrically connected to a fourth wiring.

[0026] The gate of the first transistor, the gate of the second transistor, the gate of the seventh transistor, and the gate of the eighth transistor are each electrically connected to a fifth wiring.

[0027] (4) Alternatively, in one aspect of the present invention, in the above (3), the channel length of one selected from the first transistor, the second transistor, the seventh transistor, and the eighth transistor may be longer than the channel lengths of the third transistor, the fifth transistor, the ninth transistor, the eleventh transistor, and the twelfth transistor. Also, in the above (3), the channel width of one selected from the third transistor, the fifth transistor, the ninth transistor, and the eleventh transistor may be longer than the channel widths of the first transistor, the second transistor, the seventh transistor, and the eighth transistor.

[0028] (5) In another embodiment of the present invention, in any one of (1) to (4), the transistors included in the first cell and the second cell each may have a channel formation region containing an oxide semiconductor. In particular, the oxide semiconductor preferably contains indium.

[0029] (6) Alternatively, one embodiment of the present invention can have a structure in which the oxide semiconductor further contains one or both of zinc and an element M in the above structure (5).

[0030] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0031] (7) Alternatively, one embodiment of the present invention can have a structure in the above (5) or (6) including first to fourth driver circuits.

[0032] In particular, it is preferable that the first driving circuit has a function of supplying a first current corresponding to the first data w to the first cell via the first wiring. Also, the second driving circuit has a function of supplying a second current corresponding to the second data x to the second cell via the third wiring. １or a reference current according to the reference data r to the second cell via the fourth wiring, ２ Preferably, the third driving circuit has a function of transmitting a selection signal to the fifth wiring in order to write the first data w to the first cell and the reference data r to the second cell. Furthermore, the fourth driving circuit has a function of transmitting a selection signal to the fifth wiring in order to write the first data w to the first cell and the reference data r to the second cell. Furthermore, the fourth driving circuit has a function of transmitting a selection signal to the fifth wiring in order to write the first data w to the first cell and the reference data r to the second cell. Furthermore, the fourth driving circuit has a function of transmitting a selection signal to the fifth wiring in order to write the first data w to the first cell and the reference data r to the second cell. １ / r, and outputting a result of calculation of a first function in which the amount of the fourth current is substituted as a variable; and a function of calculating w×x ２ / r, and outputting the result of calculation of a second function in which the amount of the fifth current is substituted as a variable.

[0033] The amounts of the first to fifth currents and the reference current are the amounts of source-drain currents in the subthreshold regions of the third, fifth, ninth, and eleventh transistors, respectively.

[0034] As in the configurations (1) and (3) above, the connection point between the first terminal of the first capacitance element and the gate of the third transistor is the first holding node, the connection point between the first terminal of the second capacitance element and the gate of the fifth transistor is the second holding node, and the first holding node and the second holding node are connected via the first transistor.By doing so, when the first transistor is in the on state, it is possible to write the same filter value to each of the first holding node and the second holding node, and when the first transistor is in the off state, it is possible to hold the filter values ​​of the first holding node and the second holding node.

[0035] Furthermore, when the third transistor and the fifth transistor are operated in the subthreshold region and the first hold node and the second hold node respectively hold the same filter value, by applying potentials corresponding to different input data to the second terminal of the first capacitance element and the second terminal of the second capacitance element, respectively, a subthreshold current corresponding to the multiplication result of the input data and the filter value flows in each of the third transistor and the fourth transistor. In this way, the configurations of (1) and (3) make it possible to multiply one multiplier by each of multiple multiplicands at once.

[0036] In the above (1) and (3), the first transistor, the second transistor, the seventh transistor, and the eighth transistor each function as a switching transistor. In the above (1), the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor each function as an amplifying transistor. In the above (3), the third transistor, the fifth transistor, the ninth transistor, and the eleventh transistor each function as an amplifying transistor. In the above (2) and (4), the amount of source-drain current of the amplifying transistor can be made larger than the amount of source-drain current of the switching transistor in the on state. By increasing the amount of current of the amplifying transistor, the driving speed of the semiconductor device can be increased. In other words, the multiplication speed can be increased. In the above (2) and (4), the off-state current of the switching transistor can be made smaller than the off-state current of the amplifying transistor. This allows the same multiplier written to the first retention node and the second retention node to be held for a long period of time.

[0037] Furthermore, the configuration (5) above can reduce the off-state current of each transistor. This allows the potentials written to the first and second retention nodes to be held for a long period of time. This allows the same multipliers written to the first and second retention nodes to be held for a long period of time, enabling continuous calculations.

[0038] According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device capable of holding a multiplier used in an arithmetic operation for a long period of time can be provided. According to one embodiment of the present invention, a semiconductor device capable of multiplying a single multiplier by each of a plurality of multiplicands at once can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, an arithmetic device including the above-described semiconductor device can be provided.

[0039] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0040] FIG. 1 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIGS. 2A to 2C are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIGS. 3A to 3D are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 4 is a circuit diagram illustrating an example of the configuration of a circuit included in the arithmetic device. FIGS. 5A to 5C are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 6 is a circuit diagram illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 7 is a timing chart showing an example of the operation of the arithmetic device. FIG. 8 is a circuit diagram illustrating an example of the configuration of an arithmetic circuit. FIG. 9 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIGS. 10A and 10B are circuit diagrams illustrating an example of the configuration of an arithmetic circuit. FIGS. 11A and 11B are circuit diagrams illustrating an example of the configuration of an arithmetic circuit. FIGS. 12A and 12B are circuit diagrams illustrating an example of the configuration of an arithmetic circuit. FIG. 13 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 14 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 15 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 16 is a circuit diagram illustrating an example of the configuration of a computing device. FIG. 17 is a schematic perspective view illustrating an example of the configuration of a computing device. FIG. 18 is a block diagram illustrating an example of the configuration of a computing device. FIG. 19 is a schematic cross-sectional view illustrating an example of the configuration of a computing device. FIGS. 20A and 20B are schematic cross-sectional views illustrating an example of the configuration of a transistor. FIG. 21 is a schematic cross-sectional view illustrating an example of the configuration of a computing device. FIG. 22A is a schematic plan view illustrating an example of the configuration of a transistor, and FIGS. 22B and 22C are schematic cross-sectional views illustrating an example of the configuration of a transistor. FIG. 23 is a schematic perspective view illustrating an example of the configuration of a transistor. FIG. 24A is a schematic cross-sectional view illustrating an example of the configuration of a capacitive element, and FIG. 24B is a schematic plan view illustrating an example of the configuration of a capacitive element. FIGS. 25A and 25B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 25C is a cross-sectional view illustrating an indium oxide film. FIGS. 26A to 26D are diagrams illustrating examples of electronic components. Fig. 27A and Fig. 27B are diagrams showing an example of electronic equipment, and Fig. 27C is a diagram showing an example of a mainframe computer. Fig. 28 is a diagram showing an example of space equipment. Fig. 29 is a diagram showing an example of a storage system applicable to a data center.30A1 to 30A7 and 30B1 to 30B6 are circuit diagrams for explaining electrical connections.

[0041] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0042] In this specification, "connection" includes, for example, "electrical connection."

[0043] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0045] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 30A1 and 30A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 30A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0046] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 30A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 30A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0047] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 30A6 and 30A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 30A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 30A6 and 30A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0048] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0049] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 30B1, 30B2, and 30B3. Note that, when A and B are connected to a power supply that supplies a constant potential V or GND without any circuit element between them, as shown in FIGS. 30B4 and 30B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that, as shown in FIG. 30B6, it can also be said that "A and B are directly connected" when A (or B) is connected to a constant potential V via the source and drain of a transistor. Note that, because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0050] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0051] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0052] Generally, examples of a "resistance element" include a circuit element having a resistance value higher than 0Ω, wiring having a resistance value higher than 0Ω, etc. Therefore, the "resistance element" described in this specification includes wiring, diodes, or coils having a resistance value. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0053] Generally, examples of a "capacitive element" include a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, and a region between a gate or back gate and a source or drain in a transistor having a capacitance value higher than 0 F. Furthermore, the terms "capacitive element," "parasitic capacitance," and "gate capacitance" may sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" may sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance."

[0054] Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitor" can be rephrased as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Furthermore, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The value of the electrostatic capacitance of a capacitor can be, for example, 0.05 fF or more and 10 pF or less. Furthermore, it can be, for example, 1 pF or more and 10 μF or less.

[0055] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0056] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0057] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0058] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0059] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive state and non-conductive state.

[0060] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0061] For example, an example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. The multi-gate structure allows the channel formation regions to be connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the source-drain current does not change significantly even when the source-drain voltage changes when operating in the saturation region. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0062] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id (source-drain current) - Vgs (gate-source voltage) characteristics. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0063] In this specification, the term "operation in the subthreshold region" in a transistor refers to a case where the gate-source voltage of the transistor is lower than the threshold voltage, more preferably a case where the drain current of the transistor increases exponentially with the gate-source voltage. In this case, the term also refers to a case where the gate potential, source potential, and drain potential applied to the transistor are appropriately set within a range where the transistor operates in the subthreshold region.

[0064] In this specification, the subthreshold region refers to a region in a graph showing the Id-Vgs characteristics of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to a region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to a region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described above.

[0065] In this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the “subthreshold current.” The subthreshold current increases exponentially with the gate-source voltage, regardless of the drain potential.

[0066] In general, the off-state current of a transistor may refer to a source-drain current that flows when the gate-source voltage Vgs of the transistor is lower than the threshold voltage. Therefore, the off-state current may include a subthreshold current. Note that, in this specification, since a circuit driven by a subthreshold current is described, the off-state current will be described as a current lower than the subthreshold current unless otherwise specified.

[0067] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0068] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0069] Furthermore, the selector described in this specification may be, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the selector described in this specification may be a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the selector described in this specification may be, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the selector may be a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, the selector may refer to an analog multiplexer or an analog demultiplexer.

[0070] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0071] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0072] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0073] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component referred to with the ordinal number "first" in one embodiment of this specification may be referred to with a different ordinal number, such as "second" or "third," in other embodiments or claims. Furthermore, for example, a component referred to with the ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0074] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0075] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0076] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0077] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" can be replaced with other terms without being used. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator".

[0078] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0079] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0080] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0081] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0082] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides, and nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0083] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0084] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0085] In this specification, unless otherwise specified, the expression "A and B are equal" means that the ratio of one of A and B to the other is 0.9 or more and 1.1 or less. For example, the case where the ratio of B to A is 0.9 or more and 1.1 or less and the ratio of A to B is not 0.9 or more and 1.1 or less is also considered to be "A and B are equal." Furthermore, unless otherwise specified, the expression "A and B are approximately equal" means that the ratio of one of A and B to the other is 0.8 or more and 1.2 or less, is also considered to be "A and B are approximately equal." For example, the case where the ratio of B to A is 0.8 or more and 1.2 or less and the ratio of A to B is not 0.8 or more and 1.2 or less is also considered to be "A and B are approximately equal."

[0086] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0087] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0088] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0089] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0090] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0091] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0092] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0093] Embodiment 1 In this embodiment, an arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0094] <Configuration Example 1 of Arithmetic Device> One embodiment of the present invention is an arithmetic circuit capable of multiplying a multiplier of one positive number or 0 by a multiplicand of multiple positive numbers or 0. Specifically, for example, when a multiplier of one positive number or 0 is w and a multiplicand of multiple positive numbers or 0 is x, １ , x ２ When this is done, the arithmetic circuit １ ×w and x ２ Each multiplication by xw can be performed simultaneously.

[0095] As described above, a convolutional neural network, which is a type of artificial neural network, is an example of a case in which one multiplier is multiplied by each of multiple multiplicands. In a convolutional neural network, for example, a filter including a certain feature is multiplied by image data. In particular, a convolutional neural network multiplies the feature of one filter as a multiplier by multiple image data as multiplicands, so it is preferable to use the above-described arithmetic cell to perform this multiplication.

[0096] In this specification, the multiplier is referred to as the first data, and each of the multiple multiplicands is referred to as the second data. Note that the multiplier and the multiplicand can be interchangeable due to the commutative law of products. For example, the multiplier can be referred to as the second data, and each of the multiple multiplicands can be interchangeable as the first data.

[0097] FIG. 1 is a circuit diagram illustrating a configuration example of an arithmetic circuit CC, which is a semiconductor device according to one embodiment of the present invention. The arithmetic circuit CC includes, as an example, an arithmetic cell IM and a driver cell IMd. FIG. 1 illustrates circuit configuration examples of the arithmetic cell IM and the driver cell IMd. In addition, in order to describe an operation example of the arithmetic circuit CC later, FIG. 1 also illustrates a driver circuit WCD, a driver circuit XCD, a driver circuit WSD, and a driver circuit ITS for driving the arithmetic circuit CC. Therefore, in this specification and the like, a circuit including the arithmetic circuit CC and the above-listed driver circuits may be referred to as an arithmetic device CDV. In this specification, the arithmetic device CDV may also be referred to as a semiconductor device.

[0098] The arithmetic circuit CC in Fig. 1 is an arithmetic circuit that can perform multiplication of one piece of first data by one of two pieces of second data, and multiplication of one piece of first data by the other of the two pieces of second data. Furthermore, as will be described in detail later, by changing the circuit configuration of the arithmetic circuit CC in Fig. 1, it is possible to perform multiplication of one piece of first data by three or more pieces of second data.

[0099] 1, the calculation cell IM includes, for example, transistors M1_1, M1_2, M2_1, M2_2, M3_1, M3_2, and capacitors CP_1 and CP_2. The driving cell IMd includes, for example, transistors M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, M3d_2, and capacitors CPd_1 and CPd_2.

[0100] In the operation cell IM, the transistors M1_1 and M1_2 each function as a write transistor (sometimes called a hold transistor). The transistors M2_1 and M2_2 each function as a transistor (sometimes called an amplifying transistor) for outputting the multiplication result of a multiplier and a multiplicand. The transistor M3_1 functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M2_1 due to drain-induced barrier lowering (DIBL). Similarly, the transistor M3_2 functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M2_2 due to DIBL.

[0101] In the driving cell IMd, the transistors M1d_1 and M1d_2 each function as a write transistor. The transistors M2d_1 and M2d_2 each function as a transistor for outputting the multiplication result of a multiplier and a multiplicand. The transistor M3d_1, like the transistors M3_1 and M3_2, also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M2d_1 due to DIBL. The transistor M3d_2 also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M2d_2 due to DIBL.

[0102] 1, the transistors M1_1, M1_2, M2_1, M2_2, M3_1, M3_2, M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2 are preferably OS transistors, for example. In particular, examples of metal oxides for channel formation regions of OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from the group consisting of indium, the element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0103] As the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) can be used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc can be used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) can be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) can be used. Note that an OS transistor will be described in detail in Embodiment 2.

[0104] Furthermore, the metal oxide included in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer having a two-layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main metal element in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to the main metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the second layer. This structure can suppress diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0105] In the metal oxide used for the second layer, the atomic ratio of In to the element M is preferably larger than that of In to the element M in the metal oxide used for the first layer. With this structure, the OS transistor can have large on-state current and high frequency characteristics.

[0106] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0107] Incidentally, in order to reduce the off-state current of a transistor, it is preferable to use, for example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) as the metal oxide used in the semiconductor layer of the transistor. When the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the amount of source-drain current of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (e.g., 25° C.). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of source-drain current is extremely small when the gate-source voltage of a transistor is 0 V is referred to as normally-off.

[0108] As described above, in a transistor in which a semiconductor layer contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), when the gate-source voltage is lower than the threshold voltage, the amount of current flowing per 1 μm of channel width is 1×10 −１６ A or less, preferably 1 x 10 −１８ A or less, more preferably 1×10 −２０ In some cases, the amount of current flowing per 1 μm of channel width may be 1×10 −２０ A or less, more preferably 1×10 −２２ A or less, more preferably 1×10 −２４ In this specification, the operation of the transistor in this region may be referred to as an off state. In this case, the current flowing through the transistor may be referred to as an off-state current.

[0109] In particular, by using transistors including the oxide in semiconductor layers for the transistors M1_1, M1_2, M1d_1, and M1d_2, the off-state current of each of the transistors M1_1, M1_2, M1d_1, and M1d_2 can be extremely small. As described above, the transistors M1_1 and M1_2 each function as a write transistor in the calculation cell IM, and the transistors M1d_1 and M1d_2 each function as a write transistor in the driver cell IMd. Therefore, it is preferable to use OS transistors with extremely low off-state current for each of the transistors M1_1, M1_2, M1d_1, and M1d_2.

[0110] Furthermore, by using transistors including the above oxide in semiconductor layers as the transistors M2_1, M2_2, M2d_1, and M2d_2, these transistors can operate in a wide subthreshold region, thereby reducing current consumption.

[0111] By using transistors including the oxide in semiconductor layers for the transistors M3_1, M3_2, M3d_1, and M3d_2 in addition to the transistors M1_1, M1_2, M1d_1, M1d_2, M2_1, M2_2, M2d_1, and M2d_2, the transistors included in the calculation cell IM and the driver cell IMd can be manufactured simultaneously. Therefore, the manufacturing process of the calculation device CDV can be shortened in some cases.

[0112] In addition, in the semiconductor layers of the transistors M1_1, M1_2, M1d_1, M1d_2, M2_1, M2_2, M2d_1, and M2d_2, indium oxide (sometimes referred to as indium oxide) can be used as a metal oxide. By using indium oxide as a metal oxide in the semiconductor layers of the transistors listed above, the frequency characteristics of the transistors can be improved. Furthermore, the on-state current of the transistors can be increased. Furthermore, the off-state current of the transistors can be reduced. Note that indium oxide will be described in detail in Embodiment 3.

[0113] Furthermore, the transistors M1_1, M1_2, M2_1, M2_2, M3_1, M3_2, M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2 can be, other than OS transistors, transistors whose channel formation regions contain silicon (hereinafter referred to as Si transistors). Si transistors have a larger on-state current than OS transistors and are therefore suitable for passing a large current.

[0114] Furthermore, for each of the transistors M1_1, M1_2, M2_1, M2_2, M3_1, M3_2, M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2, other than an OS transistor or a Si transistor, a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region can be used.

[0115] In the calculation cell IM, the first terminal of the transistor M1_1 is connected to the gate of the transistor M2_1 and the first terminal of the capacitor CP_1, and the second terminal of the transistor M1_1 is connected to the first terminal of the transistor M1_2, the gate of the transistor M2_2, and the first terminal of the capacitor CP_2. The first terminal of the transistor M2_1 is connected to the first terminal of the transistor M3_1, and the second terminal of the transistor M2_1 is connected to the wiring VE1. The first terminal of the transistor M2_2 is connected to the first terminal of the transistor M3_2, and the second terminal of the transistor M2_2 is connected to the wiring VE1. The gates of the transistors M3_1 and M3_2 are each connected to the wiring VE2.

[0116] In the driving cell IMd, the first terminal of the transistor M1d_1 is connected to the gate of the transistor M2d_1 and the first terminal of the capacitor CPd_1, and the second terminal of the transistor M1d_1 is connected to the first terminal of the transistor M1d_2, the gate of the transistor M2d_2, and the first terminal of the capacitor CPd_2. The first terminal of the transistor M2d_1 is connected to the first terminal of the transistor M3d_1, and the second terminal of the transistor M2d_1 is connected to the wiring VE1. The first terminal of the transistor M2d_2 is connected to the first terminal of the transistor M3d_2, and the second terminal of the transistor M2d_2 is connected to the wiring VE1. The gates of the transistors M3d_1 and M3d_2 are each connected to the wiring VE2.

[0117] The second terminal of the transistor M1_2 and the second terminal of the transistor M3_1 are connected to the wiring WCL_1, and the second terminal of the transistor M3_2 is connected to the wiring WCL_2.

[0118] The second terminal of the transistor M1d_2, the second terminal of the transistor M3d_1, the second terminal of the capacitor CP_1, and the second terminal of the capacitor CPd_1 are connected to the wiring XCL_1. The second terminal of the transistor M3d_2, the second terminal of the capacitor CP_2, and the second terminal of the capacitor CPd_2 are connected to the wiring XCL_2.

[0119] The gates of the transistors M1_1, M1_2, M1d_1, and M1d_2 are connected to the wiring WSL.

[0120] 1, in the calculation cell IM, the connection point between the first terminal of the transistor M1_1, the gate of the transistor M2_1, and the first terminal of the capacitor CP_1 is shown as node N_1. Also, the connection point between the second terminal of the transistor M1_1, the first terminal of the transistor M1_2, the gate of the transistor M2_2, and the first terminal of the capacitor CP_2 is shown as node N_2. In the driving cell IMd, the connection point between the first terminal of the transistor M1d_1, the gate of the transistor M2d_1, and the first terminal of the capacitor CPd_1 is shown as node Nd_1. Also, the connection point between the second terminal of the transistor M1d_1, the first terminal of the transistor M1d_2, the gate of the transistor M2d_2, and the first terminal of the capacitor CPd_2 is shown as node Nd_2.

[0121] The driver circuit WCD is connected to the wiring WCL_1. The driver circuit XCD is connected to the wirings XCL_1 and XCL_2. The driver circuit WSD is connected to the wiring WSL. The driver circuit ITS is connected to the wirings WCL_1, WCL_2, OL_1, and OL_2.

[0122] The wiring WCL_1, for example, functions as a wiring for passing a current corresponding to one piece of first data between the driving circuit WCD and the calculation cell IM. Note that, as will be described in detail later, this current is generated by the driving circuit WCD. The wiring WCL_1, for example, functions as a wiring for passing a current corresponding to the result of multiplication of one piece of first data by one of two pieces of second data performed in the calculation cell IM between the driving circuit ITS and the calculation cell IM.

[0123] As an example, the wiring WCL_2 functions as a wiring for passing a current corresponding to the result of multiplication of one first data and the other of two second data performed in the calculation cell IM between the driving circuit ITS and the calculation cell IM.

[0124] For example, the wiring XCL_1 functions as a wiring for passing a current corresponding to reference data between the driving circuit XCD and the driving cell IMd. Details of the reference data will be described later. The wiring XCL_1 also functions as a wiring for passing a current corresponding to one of two second data between the driving circuit XCD and the driving cell IMd.

[0125] For example, the wiring XCL_2 functions as a wiring for passing a current corresponding to the reference data between the driving circuit XCD and the driving cell IMd. The wiring XCL_2 also functions as a wiring for passing a current corresponding to the other of the two second data between the driving circuit XCD and the driving cell IMd.

[0126] As will be described in more detail later, the current corresponding to the reference data, the current corresponding to one of the two second data, and the current corresponding to the other of the two second data are each generated by the drive circuit XCD.

[0127] The wiring WSL functions as a wiring for transmitting a selection signal for selecting a computing cell IM to which a first data item is to be written and a driving cell IMd to which a reference data item is to be written. The selection signal is generated by the driving circuit WSD.

[0128] For example, the wiring VE1 functions as a wiring that applies a fixed potential. Specifically, the wiring VE1 functions as a wiring that applies the fixed potential to the second terminals of the transistors M2_1, M2_2, M2d_1, and M2d_2. In particular, the fixed potential is a potential at which the transistors M2_1, M2_2, M2d_1, and M2d_2 operate in the subthreshold region. Specifically, the fixed potential is, for example, a V ｇ (1) and V ｇｍThe fixed potential may be a potential lower than (1), a low-level potential, a ground potential, a negative potential, or the like. Alternatively, depending on the situation, the fixed potential may be a high-level potential, a positive potential, or the like. Alternatively, depending on the situation, the wiring VE1 may function as a wiring that applies a variable potential, such as a pulse potential (which may be called a pulse signal) or a clock potential (which may be called a clock signal), for example.

[0129] For example, the wiring VE2 functions as a wiring that applies a fixed potential. Note that the fixed potential can be, for example, a high-level potential or a positive potential. As a result, the clamp transistors, that is, the transistors M3_1, M3_2, M3d_1, and M3d_2, are turned on. Note that, depending on the situation, the fixed potential applied by the wiring VE2 can be a low-level potential, a ground potential, a negative potential, or the like. For example, the wiring VE2 may also function as a wiring that applies a variable potential instead of a fixed potential.

[0130] Each of the wirings OL_1 and OL_2 functions as a wiring for outputting the result of the multiplication performed by the arithmetic unit CDV to the outside as digital data.

[0131] As an example, the calculation cell IM has the function of retaining the first data transmitted from the drive circuit WCD, and the function of acquiring two second data transmitted from the drive circuit XCD and multiplying the first data by one of the two second data, and multiplying the first data by the other of the two second data.

[0132] The driving cell IMd has a function of holding reference data transmitted from the driving circuit XCD, for example, and a function of keeping constant a current corresponding to second data flowing from the driving circuit XCD to the wiring XCL_1 or the wiring XCL_2.

[0133] The driving circuit WCD has a function of generating a current according to the first data. Specifically, for example, the driving circuit WCD has a function of acquiring the first data w, which is digital data, from the outside, converting the first data w into an analog current, and outputting the analog current to the wiring WCL.

[0134] 1 , the driver circuit WCD includes, for example, a circuit WCDa and a circuit SWCA. The circuit SWCA includes a switch SA. An input terminal of the circuit WCDa is connected to a wiring IWL, and an output terminal of the circuit WCDa is connected to a first terminal of the switch SA. A second terminal of the switch SA is connected to a wiring WCL_1, and a control terminal of the switch SA is connected to a wiring SWLA.

[0135] The circuit SWCA has a function of bringing the output terminal of the circuit WCDa and the wiring WCL_1 into a conductive state or a non-conductive state, and therefore, a switch SA included in the circuit SWCA switches the conductive state and the non-conductive state between the output terminal of the circuit WCDa and the wiring WCL_1.

[0136] The switch SA can be, for example, an electrical switch such as an analog switch or a transistor. In particular, the above-described transistor is preferably used as the electrical switch for the switch SA, and an OS transistor is more preferably used. When an electrical switch is used for the switch SA, a Si transistor or the like can be used as the electrical switch other than an OS transistor. Alternatively, a mechanical switch, for example, can be used for the switch SA.

[0137] In this specification, the switch SA shown in FIG. 1 is assumed to be in an on state when a high-level potential is applied as a signal to the control terminal, and to be in an off state when a low-level potential is applied as a signal to the control terminal.

[0138] For example, the wiring SWLA functions as a wiring for transmitting a signal for controlling switching between an on state and an off state of the switch SA.

[0139] For example, the circuit WCDa has a function of converting digital data input to an input terminal into an analog current and outputting the analog current to an output terminal, and therefore preferably includes a digital potential-analog current converter circuit (also referred to as a current DAC or IDAC).

[0140] For example, the wiring IWL has a function as a wiring for transmitting first data, which is digital data, from the outside of the calculation device CDV to the driver circuit WCD.

[0141] In particular, the analog current output from the circuit WCDa is a current in the subthreshold region of each of the transistors M2_1 and M2_2. Therefore, in the circuit WCDa, the first data is w as the digital data input to the input terminal, and the current output from the output terminal is wI. ＵＴ =I ｗ When the current I flows between the source and drain of the transistor M2_1, for example, ｗ and the gate potential V of the transistor M2_1. ｇ The relationship between (w) and satisfies the following formula (1.1). ｗ is exp[V ｇ (w)]. Note that I ＵＴ is the amount of current output from the output terminal of the digital potential-analog current conversion circuit when w is 1. In this specification, the current may be referred to as a current according to reference data or a reference current.

[0142]

[0143] When w is set to 0, the circuit WCDa outputs V ｇ (1) and V ｇｍ It is preferable to output a potential lower than (1), a ground potential, or a negative potential. Alternatively, a potential approximately equal to the potential applied by the wiring VE1 may be output. The circuit WCDa also outputs a current I that satisfies w=0.001 or less, preferably w=0.0001 or less, more preferably w=0.00001 or less, even more preferably w=0.000001 or less, and even more preferably w=0.0000001 or less, as an approximation of w=0.ｗ may be broadcast.

[0144] When the first data w is stored in the operation cell IM, the circuit WCDa first acquires the first data w, which is digital data, from the outside and converts the first data w into an analog current. Then, by applying a high-level potential to the wiring SWLA to turn on the switch SA, an analog current I corresponding to the first data w is output from the output terminal of the circuit WCDa. ｗ flows to the operation cell IM via the wiring WCL.

[0145] As will be described later in detail, when a high-level potential is applied to the wiring WSL to turn on the transistors M1_1 and M1_2, the potentials of the nodes N_1 and N_2 of the calculation cell IM are increased by the analog current I Ｗ The potential V ｇ (w). This allows the first data w to be written to the calculation cell IM. After that, a low-level potential is applied to the wiring WSL to turn off the transistors M1_1 and M1_2, thereby allowing the first data w to be held in the calculation cell IM.

[0146] After the first data w has been written to the computation cell IM, it is preferable to apply a low-level potential to the wiring SWLA to turn off the switch SA, thereby increasing the impedance of the output terminal of the circuit WCDa, stopping the transmission of the first data w from the output terminal of the circuit WCDa to the wiring WCL, and reducing the power consumption of the circuit WCDa.

[0147] The driving circuit XCD supplies two second data x １ and x ２ Specifically, for example, the driver circuit XCD receives two second data x １ and x ２ Obtain x １ Analog current I ｘ１ and the function to convert to x ２ Analog current I ｘ２The driving circuit XCD also has a function of converting the first data w and the second data x into １ When multiplying by the analog current I ｘ１ to the wiring XCL_1, and the first data w and the second data x ２ When multiplying by the analog current I ｘ２ to the wiring XCL_2.

[0148] Furthermore, when the first data w is written to the calculation cell IM, the driving circuit XCD supplies a current I corresponding to the reference data to each of the wiring XCL_1 and the wiring XCL_2. ＵＴ It has the function of giving

[0149] 1 , the driver circuit XCD includes, for example, a circuit XCDa_1 and a circuit XCDa_2. The input terminal of the circuit XCDa_1 is connected to a wiring IXL_1, and the output terminal of the circuit XCDa_1 is connected to a wiring XCL_1. The input terminal of the circuit XCDa_2 is connected to a wiring IXL_2, and the output terminal of the circuit XCDa_2 is connected to a wiring XCL_2.

[0150] For example, each of the circuits XCDa_1 and XCDa_2 has a function of converting digital data input to an input terminal into an analog current. Therefore, each of the circuits XCDa_1 and XCDa_2 preferably includes an IDAC, similar to the circuit WCDa.

[0151] As will be described in detail later, when the first data w is written to the calculation cell IM, the circuit XCDa_1 acquires the reference data r as digital data from the input terminal and outputs I as an analog current (reference current) according to the reference data r. ＵＴ is supplied to the wiring XCL_1 connected to the output terminal. In addition, a high-level potential is applied to the wiring WSL to turn on the transistors M1d_1 and M1d_2, thereby supplying a current I ＵＴ flows to the driving cell IMd, and the reference data r can be written to the driving cell IMd.

[0152] At this time, the potentials of the wiring XCL_1, the node Nd_1, and the node Nd_2 are respectively ＵＴ The potential V ｒ After that, a low-level potential is applied to the wiring WSL to turn off the transistors M1d_1 and M1d_2, thereby allowing the reference data r to be held in the driving cell IMd.

[0153] Furthermore, since the reference data r is held in the driving cell IMd, the potential difference V between the potential of the node N_1 and the potential of the wiring XCL_1 is applied to the capacitance element CP_1 of the computing cell IM. ｗ -V ｒ In this case, the reference data r is set to 1.

[0154] Similarly, when the first data w is written to the calculation cell IM, the circuit XCDa_2 acquires reference data as digital data from the input terminal and generates a current I ＵＴ is supplied to the wiring XCL_2 connected to the output terminal. The potentials of the gates of the transistors M2d_1 and M2d_2 are V ｒ and the potential of each gate of the transistor M3d_1 and the transistor M3d_2 is the potential provided by the wiring VE2. When the transistors M2d_1 and M2d_2 have the same structure and the same size (including, for example, the channel length and the channel width) and the transistors M3d_1 and M3d_2 have the same structure and the same size, the resistance values ​​of the transistors M3d_1 and M2d_1 on the path from the wiring XCL_1 to the wiring VE1 are approximately equal to the resistance values ​​of the transistors M3d_2 and M2d_2 on the path from the wiring XCL_2 to the wiring VE1. In addition, a current I ＵＴ flows, the potential of the wiring XCL_2 is lower than the potential V of the wiring XCL_1 ｒ Therefore, the potential difference V between the potential of the node N_2 and the potential of the wiring XCL_2 is also applied to the capacitor CP_2 of the processing cell IM. ｗ -Vｒ is maintained.

[0155] After the first data w is stored in the operation cell IM, the circuit XCDa_1 receives the second data x, which is digital data, from the input terminal. １ Get x １ Analog current I according to ｘ１ is passed through the wiring XCL_1 connected to the output terminal. The circuit XCDa_1 generates an analog current I ｘ１ By passing the current through the wiring XCL_1, the potential of the node N_1 in the calculation cell IM can be varied by capacitive coupling through the capacitor CP_1. In particular, the potential of the node N_1 varied by the capacitive coupling of the capacitor CP_1 is set to the potential of the gate of the transistor M2_1 that is driven in the subthreshold region. Similarly, in the driver cell IMd, the potential of the node Nd_1 can be varied by capacitive coupling through the capacitor CPd_1. In particular, the potential of the node Nd_1 varied by the capacitive coupling of the capacitor CPd_1 is set to the potential of the gate of the transistor M2d_1 that is driven in the subthreshold region.

[0156] Similarly, after storing the first data w in the calculation cell IM, the circuit XCDa_2 receives the second data x, which is digital data, from the input terminal. ２ Get x ２ Analog current I according to ｘ２ is passed through the wiring XCL_2 connected to the output terminal. The circuit XCDa_2 generates an analog current I ｘ２ By passing the current through the wiring XCL_2, the potential of the node N_2 in the calculation cell IM can be changed by capacitive coupling through the capacitor CP_2. In particular, the potential of the node N_2 changed by the capacitive coupling of the capacitor CP_2 is set to the gate potential of the transistor M2_2 that operates in the subthreshold region. Similarly, in the driver cell IMd, the potential of the node Nd_2 can be changed by capacitive coupling through the capacitor CPd_2. In particular, the potential of the node Nd_2 changed by the capacitive coupling through the capacitor CPd_2 is set to the gate potential of the transistor M2d_2 that operates in the subthreshold region.

[0157] That is, while the first data w is being written to the operation cell IM, the circuit XCDa_1 acquires the reference data from the wiring IXL_1 and generates the reference current I ＵＴ to the wiring XCL_1, and when the first data w is held in the operation cell IM, the second data x is sent from the wiring IXL_1. １ Get x １ Analog current I according to ｘ１ The circuit XCDa_2 has a function of supplying a reference current I to the wiring XCL_1 while the first data w is being written to the operation cell IM. ＵＴ to the wiring XCL_2, and when the first data w is held in the operation cell IM, the second data x is sent from the wiring IXL_2. ２ Get x ２ Analog current I according to ｘ２ to the wiring XCL_2.

[0158] In the IDACs included in the circuits XCDa_1 and XCDa_2, the second data x (x １ or x ２ ) and the current I output from the output terminal ｘ (I ｘ１ or I ｘ２ ) is preferably proportional to the input terminal of each of the circuits XCDa_1 and XCDa_2. １ or x ２ ) is input, the output terminal outputs xI ＵＴ =I ｘ (x １ I ＵＴ =I ｘ１ or x ２ I ＵＴ =I ｘ２ It is preferable that a current that satisfies I ＵＴ is x (x １ or x ２) is 1. The analog currents I ｘ is the current in the subthreshold region of each of the transistors M2d_1 and M2d_2, I ｘ satisfies the following formula (1.2).

[0159]

[0160] In addition, V ｇｍ (x) is the potential of the gate of the transistor M2d_1 or the transistor M2d_2 according to the second data x.

[0161] Also, x １ When V is set to 0, the circuit XCDa_1 outputs V ｇ (1) and V ｇｍ It is preferable to output a potential lower than (1), a ground potential, or a negative potential. Alternatively, a potential equal to the potential applied by the wiring VE1 may be output. ２ When V is set to 0, the circuit XCDa_2 outputs V from the output terminal in the same manner as above. ｇ (1) and V ｇｍ It is preferable that the circuit XCDa_1 outputs a potential lower than (1), a ground potential, or a negative potential. Alternatively, the circuit XCDa_1 may output a potential approximately equal to the potential applied by the wiring VE1. １ = 0, x １ = 0.001 or less, preferably x １ = 0.0001 or less, more preferably x １ = 0.00001 or less, more preferably x １ = 0.000001 or less, more preferably x １ = 0.0000001 or less. ｘ１ The same applies to the circuit XCDa_2.

[0162] The driver circuit WSD has a function of applying a selection signal to the wiring WSL to turn on the transistors M1_1 and M1_2, which are write transistors, when selecting the calculation cell IM to which the first data w is to be written. When the first data w is not to be written, the driver circuit WSD has a function of applying a non-selection signal to the wiring WSL to turn off the transistors M1_1 and M1_2 in the calculation cell IM. In the circuit configuration of FIG. 1, the selection signal is preferably set to a high potential and the non-selection signal is preferably set to a low potential.

[0163] Furthermore, since the wiring WSL is also connected to the driving cell IMd, the driving circuit WSD transmits a selection signal or a non-selection signal to the driving cell IMd as well as to the processing cell IM. Therefore, when a selection signal is transmitted to the wiring WSL, the transistors M1d_1 and M1d_2 of the driving cell IMd are both turned on. Furthermore, for example, when a non-selection signal is transmitted to the wiring WSL, the transistors M1d_1 and M1d_2 are both turned off.

[0164] As an example, the driving circuit ITS controls the current flowing through the wiring WCL_1 (the first data w and the second data x output by the calculation cell IM). １ and the amount of current corresponding to the multiplication of １ The output data z １ =F １ (wxx １ Similarly, the driving circuit ITS has a function of outputting, for example, a current flowing through the wiring WCL_2 (the first data w and the second data x output by the calculation cell IM). ２ and the amount of current corresponding to the multiplication of ２ The output data z ２ =F ２ (wxx ２ ) output function.

[0165] The activation function may be a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. In particular, a configuration example of the driver circuit ITS that performs the calculation of the ReLU function will be described later.

[0166] In addition, in the calculation device CDV, when it is not necessary for the driving circuit ITS to calculate the activation function, the driving circuit ITS calculates the first data w and the second data x １ The current corresponding to the multiplication of z is obtained, and the value of the multiplication is z １ = w x x １ Similarly, the driving circuit ITS can output the first data w and the second data x ２ The current corresponding to the multiplication of z is obtained, and the value of the multiplication is z ２ = w x x ２ Alternatively, if it is not necessary to perform the calculation of the activation function by the driving circuit ITS, the calculation device CDV may be configured not to include the driving circuit ITS.

[0167] 1 , the driver circuit ITS includes, for example, a circuit ITSa_1, a circuit ITSa_2, a switch SB_1, and a switch SB_2. A first terminal of the switch SB_1 is connected to a wiring WCL_1, a second terminal of the switch SB_1 is connected to an input terminal of the circuit ITSa, and a control terminal of the switch SB_1 is connected to a wiring SWLB. An output terminal of the circuit ITSa_1 is connected to a wiring OL_1. A first terminal of the switch SB_2 is connected to a wiring WCL_2, a second terminal of the switch SB_2 is connected to an input terminal of the circuit ITSa, and a control terminal of the switch SB_2 is connected to a wiring SWLB. An output terminal of the circuit ITSa_2 is connected to a wiring OL_2.

[0168] For example, a switch applicable to the switch SA can be used as each of the switches SB_1 and SB_2. Therefore, the description of the switch SA can be referred to for each of the switches SB_1 and SB_2.

[0169] The wiring SWLB functions as a wiring for transmitting a signal for controlling the on / off switching of the switches SB_1 and SB_2. For example, a high-level potential or a low-level potential is supplied to the wiring SWLB.

[0170] For example, each of the circuits ITSa_1 and ITSa_2 has a function of performing a functional calculation using a value corresponding to the amount of current input to an input terminal as an input value, and also has a function of converting the result of the calculation into digital data, an analog potential, or an analog current and outputting the result to an output terminal.

[0171] Next, examples of the configurations of the drive circuits WCD, XCD, and ITS for driving the computation cells IM and the drive cells IMd will be described.

[0172] <<Driver Circuit WCD>> The driver circuit WCD shown in Fig. 1 can have, for example, the configuration shown in Fig. 2A. Note that Fig. 2A also illustrates wiring SWLA, wiring IWL, and wiring WCL_1 in order to show connection of the driver circuit WCD to peripheral circuits.

[0173] The circuit WCDa has a function of acquiring first data w, which is digital data, from the wiring IXL and supplying a signal of an amount corresponding to the first data w to the wiring WCL_1. Note that in the case of the arithmetic unit CDV in FIG. 1, the signal is a current. For this reason, the circuit WCDa preferably includes an IDAC.

[0174] The circuit WCDa shown in FIG. 2A includes, as an example, a switch SWW. The first terminal of the switch SWW is connected to the second terminal of the switch SA, and the second terminal of the switch SWW is connected to the wiring VINI1. The wiring VINI1 functions as a wiring that applies a fixed potential for initialization to the wiring WCL_1. The initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise. The initialization potential can be a potential applied when the first data w is 0, or a potential corresponding to the current that flows when the first data w is 0.

[0175] Note that the wiring VINI1 may have a function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0176] The switch SWW may be, for example, a switch that can be applied to the switch SA.

[0177] 2A includes a plurality of current sources CS. Ｋ value) (K is an integer of 1 or more) as a current amount. In this case, the circuit WCDa has a function of outputting the first data w of 2 Ｋ The circuit WCDa has, for example, one current source CS that outputs information corresponding to the value of the 0th bit as a current, two current sources CS that output information corresponding to the value of the 1st bit as a current, and two current sources CS that output information corresponding to the value of the (K-1)th bit as a current. Ｋ−１ There are individual ones.

[0178] 2A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to a first terminal of a switch SA included in the circuit SWCA. The terminal T2 of one current source CS is connected to a wiring DW[0], and each of the terminals T2 of two current sources CS is connected to a wiring DW[1]. Ｋ−１Each of the terminals T2 of the current sources CS is connected to a wiring DW[K-1].

[0179] In particular, the wirings DW[0] to DW[K-1] can be the wiring IWL shown in Fig. 1. That is, the wiring IWL can be a wiring group including the wirings DW[0] to DW[K-1].

[0180] The multiple current sources CS of the circuit WCDa each supply the same constant current I Ｗｕｔ from the terminal T1. In reality, during the manufacturing stage of the arithmetic unit CDV, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each of the terminals T1 of the multiple current sources CS is Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCDa is Ｗｕｔ The following explanation will be given assuming that there is no error.

[0181] The wirings DW[0] to DW[K-1] receive a constant current I from the connected current source CS. Ｗｕｔ This allows the circuit WCDa to pass a current corresponding to the K-bit data transmitted from the wirings DW[0] to DW[K-1] to the wiring WCL_1. Specifically, for example, when a high-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] supplies a constant current I Ｗｕｔ flows to the first terminal of the switch SA, and when a low level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] flows as follows: Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[1], the two current sources CS connected to the wiring DW[1] output a total of 2I Ｗｕｔ When a constant current of 2I flows through the first terminal of the switch SA and a low-level potential is applied to the wiring DW[1], the current source CS connected to the wiring DW[1] has a total of 2I ＷｕｔFor example, when a high-level potential is applied to the wiring DW[K-1], the constant current of the second Ｋ−１ The current sources CS are a total of 2 Ｋ−１ I Ｗｕｔ When a constant current of 2 flows through the second terminal of the switch SW3 and a low-level potential is applied to the wiring DW[K-1], the current source CS connected to the wiring DW[K-1] has a total of 2 Ｋ−１ I Ｗｕｔ It does not output a constant current.

[0182] 2 connected to wiring DW[0] ０ The current flowing from one current source CS corresponds to the value of the 0th bit, and is connected to the wiring DW[1]. １ The currents flowing from the two current sources CS correspond to the value of the first bit, and are connected to the wiring DW[K-1]. Ｋ−１ The amount of current flowing from the current sources CS corresponds to the value of the (K-1)th bit. Here, consider the circuit WCDa when K is 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high level potential is applied to the wiring DW[0] and a low level potential is applied to the wiring DW[1]. At this time, a constant current I is supplied from the circuit WCDa to the first terminal of the switch SA of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low level potential is applied to the wiring DW[0] and a high level potential is applied to the wiring DW[1]. At this time, a constant current of 2I flows from the circuit WCDa to the first terminal of the switch SA of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, a constant current of 3I flows from the circuit WCDa to the first terminal of the switch SA of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, no constant current flows from the circuit WCDa to the first terminal of the switch SA of the circuit SWCA.

[0183] 2A illustrates the circuit WCDa when K is an integer of 3 or more, but when K is 1, it is preferable that the circuit WCDa in FIG. 2A does not have a current source CS connected to the wirings DW[1] to DW[K-1]. When K is 2, it is preferable that the circuit WCDa in FIG. 2A does not have a current source CS connected to the wirings DW[2] to DW[K-1].

[0184] Next, a specific example of the configuration of the current source CS will be described.

[0185] The current source CS1 shown in FIG. 3A is a circuit that can be applied to the current source CS included in the circuit WCDa in FIG. 2A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0186] A first terminal of the transistor Tr1 is connected to the wiring VEH, and a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is connected to the terminal T1, and a gate of the transistor Tr2 is connected to the terminal T2. The terminal T2 is also connected to the wiring DW.

[0187] The wiring DW is any one of the wirings DW[0] to DW[K-1] in FIG. 2A.

[0188] The wiring VEH functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a high-level potential.

[0189] When the fixed potential applied by the wiring VEH is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate and the second terminal of the transistor Tr1 are connected to each other, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current in the subthreshold region (source-drain current, subthreshold current) flows between the first and second terminals of the transistor Tr1. The amount of the current flowing per 1 μm of channel width is, for example, 1.0×10 when the transistor Tr1 is an OS transistor. −８ A or less, and 1.0 × 10 −１２ A or less is more preferable, and 1.0 × 10 −１５ A or less is more preferable. Furthermore, for example, it is more preferable that the current is within a range in which it increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the subthreshold region. Note that the current is the current in the subthreshold region of each of the transistors M2_1 and M2_2 included in the processing cell IM and the transistors M2d_1 and M2d_2 included in the driving cell IMd. Furthermore, the current is the above-mentioned I Ｗｕｔ , or I described below Ｘｕｔ Corresponds to.

[0190] The transistor Tr2 functions as a switching transistor. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected to each other, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, the current in the subthreshold region described above flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0191] Note that a circuit applicable to the current source CS included in the circuit WCDa of FIG. 2A is not limited to the current source CS1 of FIG. 3A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 3B. In the current source CS2 shown in FIG. 3B, the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0192] Further, for example, the current source CS1 is configured such that the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected. However, a capacitor element may be used to hold the voltage between the back gate and the second terminal of the transistor Tr2. Such a configuration example is shown in FIG. 3C. The current source CS3 shown in FIG. 3C includes a transistor Tr3 and a capacitor element C6 in addition to the transistors Tr1 and Tr2. The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are connected via the capacitor element C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are connected. Also, the current source CS3 is configured such that the second terminal of the transistor Tr3 is connected to the wiring VTL and the gate of the transistor Tr3 is connected to the wiring VWL. By applying a high-level potential to the wiring VWL to turn on the transistor Tr3, the connection between the wiring VTL and the back gate of the transistor Tr1 can be made conductive. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the capacitor element C6 can hold the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1. That is, by determining the potential applied by the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor element C6.

[0193] Further, for example, as a circuit applicable to the current source CS included in the circuit WCDa of FIG. 2A, the current source CS4 shown in FIG. 3D may be used. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 3C, the back gate of the transistor Tr2 is connected to the wiring VTHL instead of the second terminal of the transistor Tr2. That is, similar to the current source CS2 of FIG. 3B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential applied by the wiring VTHL.

[0194] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0195] 2A includes the current source CS, and the circuit WCDa can output a current corresponding to the K-bit first data by using any one of the current sources CS1 to CS4 shown in FIGS. 3A to 3D. The amount of the current can be set to, for example, the amount of current flowing between the source and drain of the transistors M2_1 and M3_1 included in the operation cell IM within the range in which they operate in the subthreshold region.

[0196] 2B may be used as the circuit WCDa of Fig. 2A. The circuit WCDa of Fig. 2B has a configuration in which the current source CS of Fig. 3A is connected to each of the wirings DW[0] to DW[K-1]. When the channel width of the transistor Tr1[0] is w[0], the channel width of the transistor Tr1[1] is w[1], and the channel width of the transistor Tr1[K-1] is w[K-1], the ratio of the channel widths is w[0]:w[1]:w[K-1]=1:2:2. Ｋ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCDa shown in FIG. 2B can output a current corresponding to the K-bit first data w, similar to the circuit WCDa in FIG. 2A.

[0197] Note that the transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3 can be, for example, transistors that can be used for the transistors M1p, M6p, M1n, M6n, M1d, or M6d. In particular, OS transistors are preferably used for the transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3.

[0198] In particular, the circuits shown in FIGS. 2A and 2B are sometimes called K-bit current ladder type DACs (Digital to Analog Converters), which are a type of IDAC.

[0199] 2B may be modified to a CMOS circuit including n-channel transistors and p-channel transistors. For example, the circuit WCDa in FIG. 2A may be modified to a circuit configuration shown in FIG. 4.

[0200] The circuit WCDa shown in Figure 4 has a circuit configuration including n-channel transistors and p-channel transistors, and is an example of a configuration of a K-bit current-type ladder DAC. The circuit WCDa has K current sources CS and a current mirror circuit CRM. The current source CS shown in Figure 4 differs from each of the current sources CS1 to CS4 shown in Figures 3A to 3D in terms of connection configuration.

[0201] Next, each current source CS shown in FIG. 4 will be described.

[0202] A first terminal of the transistor Tr1[0] is connected to the wiring VSSL, a second terminal of the transistor Tr1[0] is connected to the first terminal of the transistor Tr2[0], and a gate of the transistor Tr1[0] is connected to the wiring BIS. Also, a gate of the transistor Tr2[0] is connected to the wiring DW[0].

[0203] Similarly, a first terminal of the transistor Tr1[1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[1] is connected to the first terminal of the transistor Tr2[1], and a gate of the transistor Tr1[1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[1] is connected to the wiring DW[1].

[0204] Similarly, a first terminal of the transistor Tr1[K-1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[K-1] is connected to the first terminal of the transistor Tr2[K-1], and a gate of the transistor Tr1[K-1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[K-1] is connected to the wiring DW[K-1].

[0205] Further, second terminals of the transistors Tr2[0] to Tr2[K-1] are connected to a terminal CTi of a current mirror circuit CRM, which will be described later.

[0206] In FIG. 4, the channel widths of the transistors Tr1[0] to Tr1[K-1] can be determined by referring to the description of the transistors Tr1[0] to Tr1[K-1] in FIG. 2B.

[0207] 4, the transistors Tr2[0] to Tr2[K-1] function as transistors capable of adjusting the amount of current flowing between the source and drain of each of the transistors Tr1[0] to Tr1[K-1]. Therefore, the wiring BIS functions as a wiring that applies a fixed potential. Note that the fixed potential may be a high-level potential, a positive potential, or the like. Depending on the situation, the fixed potential may also be a low-level potential, a ground potential, a negative potential, or the like.

[0208] For example, the wiring VSSL functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential. For example, the wiring VSSL may also function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0209] Each current source CS shown in FIG. 4 has the above-described connection configuration, and therefore functions as a current sink circuit that causes a current to flow from the terminal T1 of the current source CS to the wiring VSSL via the transistor Tr1 and the transistor Tr2.

[0210] Next, the current mirror circuit CRM will be described.

[0211] The current mirror circuit CRM has a terminal CTi that functions as an input terminal and a terminal CTo that functions as an output terminal. Ideally, the current mirror circuit CRM has a function of outputting a current to the terminal CTo that is equal to the amount of current flowing through the terminal CTi.

[0212] The current mirror circuit CRM includes a transistor Tr5, a transistor Tr5m, a transistor Tr6, and a transistor Tr6m.

[0213] The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and the wiring CPE. The second terminal of transistor Tr6 is connected to the wiring VEH. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to the wiring VEH.

[0214] For the wiring VEH, the description of the wiring VEH shown in FIG. 2A can be referred to.

[0215] For example, the wiring CPE functions as a wiring that applies a fixed potential. The fixed potential may be a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential, or the like. For example, the wiring CPE may also function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0216] In the current mirror circuit CRM, the second terminals of the transistors Tr6 and Tr6m are connected such that a potential is applied from the wiring VDDL, and the gates of the transistors Tr6 and Tr6m are connected such that a potential of the terminal CTi is applied. Ideally, therefore, equal amounts of current flow between the source and drain of the transistors Tr6 and Tr6m.

[0217] Furthermore, transistor Tr5 functions as a transistor cascode-connected to transistor Tr6. Similarly, transistor Tr5m functions as a transistor cascode-connected to transistor Tr6m. This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, this prevents the potential of the first terminal of transistor Tr6 from suddenly fluctuating, thereby stabilizing the operation of the current mirror circuit CRM.

[0218] <<Driver Circuit XCD>> The driver circuit XCD shown in FIG. 1 can have, for example, the configuration shown in FIG. 2C.

[0219] The circuit XCDa shown in Fig. 2C can be applied to each of the circuit XCDa_1 and the circuit XCDa_2 shown in Fig. 1. The wiring XCL shown in Fig. 2C can be the wiring XCL_1 or the wiring XCL_2 shown in Fig. 1, and the wiring IXL shown in Fig. 2C can be the wiring IXL_1 or the wiring IXL_2 shown in Fig. 1.

[0220] 2C has a function of supplying a signal of an amount corresponding to the second data x to the wiring XCL. In the case of the arithmetic unit CDV in FIG. 1, the signal can be a current.

[0221] The circuit XCDa shown in FIG. 2C includes, as an example, a switch SWX. A first terminal of the switch SWX is connected to the wiring XCL, and a second terminal of the switch SWX is connected to the wiring VINI2. The wiring VINI2 functions as a wiring that applies an initialization potential to the wiring XCL. The initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. The initialization potential applied by the wiring VINI2 may be approximately equal to the potential applied by the wiring VINI1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise. The initialization potential can be a potential applied when the second data x is 0, or a potential corresponding to the current flowing when the second data x is 0.

[0222] The switch SWX may be, for example, a switch that can be applied to the switch SA.

[0223] The circuit configuration of the circuit XCDa in Fig. 2C can be substantially the same as that of the circuit WCDa in Fig. 2A. Specifically, the circuit XCDa has a function of outputting reference data as a current amount and a function of outputting L bits (2 Ｌ and a function of outputting second data x of a value (L is an integer of 1 or more) as a current amount. In this case, the circuit XCDa has a function of outputting second data x of a value (L is an integer of 1 or more) as a current amount. Ｌ The circuit XCDa has one current source CS that outputs information corresponding to the value of the 0th bit as a current, two current sources CS that output information corresponding to the value of the 1st bit as a current, and two current sources CS that output information corresponding to the value of the (L-1)th bit as a current. Ｌ−１ There are individual ones.

[0224] When the reference data output as a current from the circuit XCDa is set to 1, for example, the value of the 0th bit can be set to "1" and the values ​​of the 1st and subsequent bits can be set to "0".

[0225] In FIG. 2C, the terminal T2 of one current source CS is connected to the wiring DX[0], and each of the terminals T2 of the two current sources CS is connected to the wiring DX[1]. Ｌ−１ Each of the terminals T2 of the current sources CS is connected to the wiring DX[L-1].

[0226] In particular, the wirings DX[0] to DX[L-1] can be the wiring IXL shown in Fig. 1. That is, the wiring IXL can be a wiring group including the wirings DX[0] to DX[L-1].

[0227] The multiple current sources CS of the circuit XCDa are each supplied with the same constant current I Ｘｕｔ from the terminal T1. The wirings DX[0] to DX[L-1] are connected to the current source CS and output I Ｘｕｔ This allows the circuit XCDa to pass, to the wiring XCL, an amount of current corresponding to the L-1-bit data transmitted from the wirings DX[0] to DX[L-1].

[0228] Specifically, consider the circuit XCDa when L is set to 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DX[0] and a low-level potential is applied to the wiring DX[1]. At this time, a constant current I is supplied from the circuit XCDa to the wiring XCL. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low level potential is applied to the wiring DX[0] and a high level potential is applied to the wiring DX[1]. At this time, a constant current of 2I flows from the circuit XCDa to the wiring XCL. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, a constant current of 3I flows from the circuit XCDa to the wiring XCL. Ｘｕｔflows. Also, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, no constant current flows from the circuit XCDa to the wiring XCL. Note that in this specification and the like, this may be rephrased as a current of zero amount flows from the circuit XCDa to the wiring XCL. Also, the current of zero amount, I, output from the circuit XCDa Ｘｕｔ , 2I Ｘｕｔ , 3I Ｘｕｔ etc. can be the second data output by the circuit XCDa, and in particular the amount of current I Ｘｕｔ can be the reference data output by the circuit XCDa.

[0229] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCDa, the amount of constant current I output from each of the terminals T1 of the multiple current sources CS is Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the amount of constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCDa is Ｘｕｔ In this embodiment, the amount of constant current I output from the terminal T1 of each of the plurality of current sources CS included in the circuit WCDa is Ｘｕｔ The following explanation will be given assuming that there is no error.

[0230] 3A to 3D can be applied as the current source CS of the circuit XCDa, similarly to the current source CS of the circuit WCDa. In this case, by replacing the wiring DW with the wiring DX in the description of the current sources CS1 to CS4 of FIGS. 3A to 3D, the description can be used as a description of the current source CS used in the circuit XCDa. As a result, the circuit XCDa can use any of the current sources CS1 to CS4 of FIGS. 3A to 3D to pass a current in the subthreshold region to the wiring XCL as reference data or L-bit second data.

[0231] 2C can be applied to the circuit XCDa of Fig. 2B. In this case, in the description of the circuit WCDa of Fig. 2B, by replacing the circuit WCDa with the circuit XCDa, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], the wiring DW[K-1] with the wiring DX[L-1], the switch SWW with the switch SWX, and the wiring VINI1 with the wiring VINI2, the description can be interpreted as a description of the circuit XCDa having the same circuit configuration as that of Fig. 2B.

[0232] 2C can have the same circuit configuration as the circuit WCDa shown in Fig. 4. In this case, in the description of the circuit WCDa in Fig. 4, by replacing the circuit WCDa with the circuit XCDa, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], and the wiring DW[K-1] with the wiring DX[L-1], the description can be interpreted as a description of the circuit XCDa having the same circuit configuration as that in Fig. 4.

[0233] <<Driver Circuit WSD>> The driver circuit WSD shown in FIG. 1 has a function of turning on the write transistor included in the computation cell IM by supplying a predetermined signal to the wiring WSL when writing first data w to the computation cell IM. Similarly, it also has a function of turning on the write transistor included in the driving cell IMd. That is, the driver circuit WSD functions as a write word line driver circuit for the computation cell IM and the driving cell IMd. For example, the driver circuit WSD can turn on the transistors M1_1 and M1_2 included in the computation cell IM and the transistors M1d_1 and M1d_2 included in the driving cell IMd by supplying a high-level potential as a select signal to the wiring WSL. Furthermore, the driver circuit WSD can turn off the transistors M1_1 and M1_2 included in the computation cell IM and the transistors M1d_1 and M1d_2 included in the driving cell IMd by supplying a low-level potential as a deselect signal to the wiring WSL. As described above, the driver circuit WSD transmits a selection signal or a non-selection signal to the wiring WSL, thereby allowing the computing cell IM and the driver cell IMd to select either data writing or data retention.

[0234] <<Driver Circuit ITS>> The driver circuit ITS shown in Fig. 1 can have, for example, the configuration shown in Fig. 5A. Note that Fig. 5A also illustrates wiring SWLB, wiring WCL, and wiring OL to show connection of the driver circuit ITS with peripheral circuits.

[0235] The circuit ITSa shown in Figure 5A can be applied to the circuit ITSa_1 and the circuit ITSa_2 shown in Figure 1. The wiring WCL shown in Figure 5A can be the wiring WCL_1 or the wiring WCL_2 shown in Figure 1. The wiring OL shown in Figure 5A can be the wiring OL_1 or the wiring OL_2 shown in Figure 1. The switch SB shown in Figure 5A can be the switch SB_1 or the switch SB_2 shown in Figure 1.

[0236] 5A includes a circuit that performs an activation function calculation as a function system (e.g., a nonlinear function system) and an analog-to-digital conversion circuit, as described above. In particular, the circuit that performs the function system calculation preferably has a function of performing the function system calculation using, as an input value, a value corresponding to the amount of input current, and outputting digital data (e.g., a digital potential) corresponding to the result of the calculation.

[0237] 5A includes, for example, a circuit RL and an analog-to-digital conversion circuit ATDC. The circuit RL includes, for example, a terminal RTi and a terminal RTo.

[0238] A second terminal of the switch SB is connected to a terminal RTi of the circuit RL via an input terminal of the circuit ITSa. A terminal RTo of the circuit RL is connected to an input terminal of the analog-to-digital conversion circuit ATDC, and an output terminal of the analog-to-digital conversion circuit ATDC is connected to a wiring OL via an output terminal of the circuit ITSa.

[0239] The circuit RL may be an arithmetic circuit of the above-described function system. The function system may be an activation function used in an artificial neural network model. Examples of the activation function include nonlinear functions such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. The circuit RL may also include a circuit that performs pooling processing instead of an arithmetic circuit of the function system. In the configuration of FIG. 5A, the circuit RL is preferably configured to output a potential from a terminal RTo.

[0240] The circuit RL may also be a current-voltage conversion circuit.

[0241] When the circuit RL is configured as a current-voltage conversion circuit, it is preferable that the circuit RL is configured to generate an analog potential corresponding to the current input to the terminal RTi of the circuit RL from the wiring WCL via the switch SB, and output the analog potential to the terminal RTo of the circuit RL.

[0242] The analog-to-digital converter circuit ATDC preferably converts an analog potential supplied from the terminal RTo of the circuit RL into a digital signal and outputs the digital signal to the wiring OL.

[0243] 5B shows an example of the configuration of the drive circuit ITS when the circuit RL is a current-voltage conversion circuit. The circuit RL shown in FIG. 5B includes, as an example, a load LE and an amplifier circuit OP.

[0244] The amplifier circuit OP has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, an operational amplifier or a differential amplifier circuit can be used as the amplifier circuit OP.

[0245] The inverting input terminal of the amplifier circuit OP is connected to the first terminal of the load LE and the second terminal of the switch SB. The non-inverting input terminal of the amplifier circuit OP is connected to the wiring VRL. The output terminal of the amplifier circuit OP is connected to the second terminal of the load LE and the terminal RTo.

[0246] The wiring VRL functions as a wiring that applies a fixed potential, which may be, for example, a ground potential (GND) or a low-level potential.

[0247] In particular, since the amplifier circuit OP is configured as a negative feedback, a virtual short circuit is formed between the inverting input terminal and the non-inverting input terminal of the amplifier circuit OP. Therefore, the potential of the non-inverting input terminal of the amplifier circuit OP can be regarded as a fixed potential provided by the wiring VRL. Therefore, by setting the fixed potential provided by the wiring VRL to the ground potential (GND), the analog voltage output from the output terminal of the amplifier circuit OP can be a voltage based on the ground potential (GND).

[0248] 5B, the drive circuit ITS can output to the terminal RTo an analog voltage corresponding to the amount of current flowing from the wiring WCL through the switch SB to the terminal RTi of the circuit RL. The analog voltage can then be converted into a digital signal by the analog-to-digital converter ATDC and output to the wiring OL.

[0249] Note that, when the drive circuit ITS outputs an analog voltage rather than a digital signal to the wiring OL, the circuit ITSa does not need to include an analog-digital conversion circuit ATDC, as in the drive circuit ITS shown in FIG. 5C . Also, in FIG. 5C , the circuit RL is preferably configured to perform a function calculation using a value corresponding to the amount of current flowing through the terminal RTi as an input value, and output the result of the calculation as an analog current to the terminal RTo. Furthermore, by passing the analog current resulting from the calculation output from the terminal RTo, for example, through the wiring XCL_1 or XCL_2 of another arithmetic unit CDV, another calculation can be performed using the calculation result. This corresponds to sending the calculation result to the next fully connected layer in a multilayer perceptron, a type of artificial neural network. By directly using the analog current resulting from the calculation for the next calculation, analog-to-digital conversion and digital-to-analog current conversion are not necessary, and these conversion circuits can be omitted. This reduces the circuit area of ​​the arithmetic unit CDV and the power consumption required for the conversion circuits.

[0250] Next, a specific configuration example of the circuit RL included in the circuit ITSa of FIG. 5A or FIG. 5C will be described.

[0251] FIG. 6 is a circuit diagram showing, as an example, a specific configuration of the circuit RL included in the circuit ITSa of FIG. 5A or FIG. 5C, and the circuit RL of FIG. 6 has a function of performing the calculation of the ReLU function.

[0252] The circuit RL shown in FIG. 6 includes, as an example, transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, MN2o, and a current source CNI.

[0253] 6, a first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o, a second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o, and a third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o.

[0254] Furthermore, since the circuit RL includes a first current mirror circuit to a third current mirror circuit, the circuit RL is sometimes called a three-stage current mirror circuit.

[0255] The drain of transistor MP1i is connected to terminal RTi, and the drain of transistor MP1o is connected to the input terminal of current source CNI and the drain of transistor MN2i. The drain of transistor MN2o is connected to the drain of transistor MP3i. Transistor MP3o is connected to the output terminal of circuit RL. The output terminal of current source CNI is connected to wiring VGE.

[0256] For example, the wiring VGE functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a low-level potential, a negative potential, or a ground potential. Depending on the situation, the fixed potential applied by the wiring VGE can be a high-level potential, a positive potential, or the like. The wiring VGE may also function as a wiring that applies not only a fixed potential but also a variable potential such as a pulse potential or a clock potential.

[0257] The first current mirror circuit ideally has the function of passing a current between the source and drain of transistor MP2o that is equal to the source-drain current corresponding to the gate-source voltage of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of passing a current between the source and drain of transistor MN1o that is equal to the source-drain current corresponding to the gate-source voltage of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of passing a current between the source and drain of transistor NP4o that is equal to the source-drain current corresponding to the gate-source voltage of transistor MP4i.

[0258] In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to DIBL. Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to DIBL. Therefore, wiring RSWL1 that applies a desired bias potential is connected to the gates of transistor MP1i and transistor MP1o.

[0259] In the second and third current mirror circuits, the transistors MN2i, MN2o, MP3i, and MP3o also function as clamp transistors to prevent a decrease in the threshold voltage of the transistors connected in series by DIBL. In this case, the wirings RSWL2 and RSWL3 each function as wirings that apply a desired bias potential.

[0260] Note that the bias potentials applied by the wirings RSWL1 to RSWL3 can be made equal to each other. Therefore, the wirings RSWL1 to RSWL3 can be the same wiring. The ratio of the bias potential applied by one selected from the wirings RSWL1 to RSWL3 to the bias potential applied by the remaining two is preferably 0.9 to 1.1, more preferably 0.95 to 1.05, and even more preferably 0.99 to 1.01.

[0261] Each of the transistors MP1i and MP1o can function as a switching transistor. In this case, the wiring RSWL1 preferably functions as a wiring for controlling the switching between the on state and the off state of each of the transistors MP1i and MP1o. Furthermore, by turning off each of the transistors MP1i and MP1o, the first current mirror circuit can be stopped, thereby reducing power consumption in the circuit RL.

[0262] Similarly, since the transistors MN2i and MN2o each function as a switching transistor, the second current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL2 function as a wiring for controlling the switching between the on state and the off state of the transistors MN2i and MN2o. Similarly, since the transistors MP3i and MP3o each function as a switching transistor, the third current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL3 function as a wiring for controlling the switching between the on state and the off state of the transistors MP3i and MP3o.

[0263] Note that the transistors MP1i and MP1o, and the transistors MP3i and MP3o can be simultaneously turned on or off. Therefore, the wiring RSWL1 and the wiring RSWL3 can be the same wiring.

[0264] In the first current mirror circuit, the source of the transistor MP2i and the source of the transistor MP2o are each connected to the wiring VDDL. The first current mirror circuit is configured with p-channel transistors, and therefore also functions as a current source circuit. Therefore, the wiring VDDL functions as a wiring that provides a high-level potential as a high power supply potential for the first current mirror circuit. Similarly, the third current mirror also functions as a current source circuit, and therefore, the high-level potential provided by the wiring VDDL also functions as a high power supply potential for the third current mirror circuit.

[0265] In the second current mirror circuit, the source of the transistor MN1i and the source of the transistor MN1o are connected to a wiring VSSL. The second current mirror circuit is configured with n-channel transistors, and therefore also functions as a current sink circuit. Therefore, the wiring VSSL functions as a wiring that applies a low-level potential as a low power supply potential of the second current mirror circuit.

[0266] The current source CNI is, for example, a quantity I ＩＢ The current flows from the drains of the transistors MP1o and MN2i to the wiring VGE.

[0267] When a high-level potential is applied to the wiring SWLB, the high-level potential is applied to the control terminal of the switch SB, and the switch SB is turned on. At this time, a quantity I corresponding to the value multiplied by the operation cell IM is applied to the wiring WCL. ＩＬ Therefore, a current of the amount I flows from the wiring VDDL to the wiring WCL. ＩＬ Therefore, the amount of the source-drain current of the transistor MP2o is also I ＩＬThis becomes:

[0268] Also, when the current source CNI is operating, I ＩＬ =I ＩＢ +I ＯＬ is established. Note that I ＯＬ is the amount of current flowing between the source and drain of the transistor MN1i. Therefore, the amount of source-drain current of the transistor MN1o is also I ＯＬ This becomes:

[0269] The amount of source-drain current of the transistor MN1o is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4i is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4o is also I ＯＬ and the terminal RTo is charged with the quantity I ＯＬ A current of flows.

[0270] The circuit RL is I ＩＬ Ga I Ｂ If it is greater than , the difference is the amount I ＯＬ A current of I flows through the terminal RTo. ＩＬ Ga I Ｂ When the following condition is satisfied, the current flowing between the input terminal and the output terminal of the current source CNI is I ＩＬ And also, I ＯＬ = 0. In this case, no current flows from the terminal RTo of the circuit RL. In other words, the circuit RL shown in FIG. 6 can perform the calculation of the ReLU function.

[0271] <Example of Operation Method of Calculation Device> Next, an example of operation of the calculation device CDV shown in FIG. 1 will be described.

[0272] 7 is a timing chart showing an example of an operation method of the computing device CDV. The timing chart shows changes in potentials of the wirings SWLA, SWLB, WSL, XCL_1, XCL_2, the node N_1, the node Nd_1, the node N_2, and the node Nd_2 during and around the periods T01 to T08. The timing chart also shows changes in potentials of the source-drain current I flowing through the transistor M2_1. Ｍ２＿１ and the source-drain current I flowing through the transistor M2d_1. Ｍ２ｄ＿１ and the source-drain current I flowing through the transistor M2_2. Ｍ２＿２ and the source-drain current I flowing through the transistor M2d_2. Ｍ２ｄ＿２ The amount of and the respective variations of are also shown.

[0273] 7, the types of wiring, nodes, etc. are shown on the left side, and the potential levels are shown on the right side. In particular, "High" in the timing chart means a high-level potential on the wiring, and "Low" means a low-level potential on the wiring.

[0274] In this operation example, the driving circuit WCD included in the calculation device CDV of FIG. 1 will be described as being applied to the driving circuit WCD of FIG. 2A, and the circuit XCDa_1 and circuit XCDa_2 included in the calculation device CDV of FIG. 1 will be described as being applied to the circuit XCDa of FIG. 2C.

[0275] The potentials applied by the wirings VE1, VINI1, and VINI2 are V Ｎ In addition, V Ｎ is V ｇ (1) and V ｇｍ (1) can be a lower potential, ground potential (GND), or a negative potential.

[0276] The wiring VE2 is supplied with a fixed potential that turns on the transistors M3_1, M3_2, M3d_1, and M3d_2. As described above, the transistors M3_1, M3_2, M3d_1, and M3d_2 each function as a clamp transistor for suppressing DIBL in the corresponding transistor.

[0277] Before the period T01, the wirings SWLA, SWLB, and WSL are applied with a low-level potential. The potentials of the nodes N_1 and N_2 of the processing cell IM and the nodes Nd_1 and Nd_2 of the driving cell IMd are initially set to V Ｎ It is assumed that I Ｍ２＿１ , I Ｍ２ｄ＿１ , I Ｍ２＿２ and I Ｍ２ｄ＿２ Each of these is initially set to 0.

[0278] Since the wiring WSL is supplied with a low-level potential, the gates of the transistors M1_1, M1_2, M1d_1, and M1d_2 are supplied with a low-level potential, turning off the transistors M1_1, M1_2, M1d_1, and M1d_2.

[0279] Also, before the period T01, the two second data x, which are digital data, are still received from the outside. １ , x ２ is not applied to the wiring VINI2 via the switch SWX. The amount of current generated by the circuit XCDa_1 and the circuit XCDa_2 of the driver circuit XCD is 0. Specifically, in each of the circuits XCDa_1 and XCDa_2, the switch SWX is on, and the potential V Ｎ is assumed to be given.

[0280] [Period T01] In the period T01, a high-level potential is applied to the wiring SWLA. Therefore, the high-level potential is applied to the control terminal of the switch SA, and the switch SA is turned on.

[0281] Also, during the period T01, the first data w, which is digital data, has not yet been provided from the outside. Therefore, the amount of current generated by the circuit WCDa of the drive circuit WCD is 0. Specifically, the switch SWW is in an on state, and the wiring WCL_1 is connected to the wiring VINI1 through the switch SWW and the switch SA. Ｎ is assumed to be given.

[0282] [Period T02] During the period T02, a high-level potential is applied to the wiring WSL. Therefore, a high-level potential is applied to the gates of the transistors M1_1, M1_2, M1d_1, and M1d_2. As a result, the transistors M1_1, M1_2, M1d_1, and M1d_2 are turned on.

[0283] In the calculation cell IM, when the transistors M1_1 and M1_2 are turned on, the potential V Ｎ is supplied to the gate of the transistor M2_1, the first terminal of the capacitor CP_1 (node ​​N_1), and the gate of the transistor M2_2, and the first terminal of the capacitor CP_2 (node ​​N_2) via the wiring WCL_1.

[0284] At this time, the potential V output from the circuit WCDa Ｎ is also applied to the first terminal of the transistor M2_1 through the wiring WCL_1 and the transistor M3_1. At this time, the second terminal of the transistor M2_1 receives the potential V Ｎ Therefore, no current flows between the source and drain of the transistor M2_1, and therefore, I Ｍ２＿１ will be 0.

[0285] In addition, in the period T02, a low-level potential is applied to the wiring SWLB. Therefore, the low-level potential is applied to the control terminal of the switch SB_2, and the switch SB_2 is in an off state. At this time, the potential of the wiring WCL_2 is V Ｎ When the voltage V sigma is set to 0, the source-drain voltage of the transistor M2_2 is V Ｎ -V Ｎ = 0, so the current I Ｍ２＿２ will be 0.

[0286] In the period T02, the current I Ｍ２＿２ is set to 0, current may flow between the source and drain of the transistor M2_2 depending on the potential of the wiring WCL_2 in an initial state.

[0287] Specifically, the gate-source voltage of the transistor M2_2 is V Ｎ -V Ｎ =0, when the threshold voltage of the transistor M2_2 is within an appropriate range, a current (source-drain current) in the subthreshold region flows between the first terminal and the second terminal of the transistor M2_2, and the potential of the wiring WCL_2 may fluctuate. Ｎ , positive charges of the wiring WCL_2 may flow to the wiring VE1 as a current in the subthreshold region of the transistor M2_2. Ｎ If the potential difference Vcc is lower than 1, positive charges on the wiring VE1 may flow to the wiring WCL_2 as a current in the subthreshold region of the transistor M2_2.

[0288] In addition, in the driving cell IMd, the transistors M1d_1 and M1d_2 are turned on, and thus the potential V Ｎis applied to the gate of the transistor M2d_1 and the first terminal of the capacitor CPd_1 (node ​​Nd_1), and to the gate of the transistor M2d_2 and the first terminal of the capacitor CPd_2 (node ​​Nd_2). Ｎ The second terminal of the transistor M2d_1 is supplied with a potential V Ｎ is given, no current flows between the source and drain of the transistor M2d_1, and therefore, I Ｍ２ｄ＿１ becomes 0.

[0289] Similarly, the potential V Ｎ The second terminal of the transistor M2d_2 is supplied with a potential V Ｎ is given, no current flows between the source and drain of the transistor M2d_2, and therefore, I Ｍ２ｄ＿２ also becomes 0.

[0290] [Period T03] During period T03, reference data r, which is digital data, is applied from the wiring IXL. Therefore, the amount of current generated by the circuit XCDa of the drive circuit XCD is determined according to r. Here, this amount of current is defined as rI. Ｘｕｔ In addition, I Ｘｕｔ is the amount of current that flows when r = 1. Also, the switch SWX is in the OFF state, and the amount rI generated by the circuit XCDa Ｘｕｔ A current of flows through the wiring XCL.

[0291] Also, in the driving cell IMd, the quantity rI Ｘｕｔ The current flows through the source-drain paths of the transistors M3d_1 and M2d_1 to the wiring VE1. At this time, since the transistors M1d_1 and M1d_2 are on, the potentials of the gate of the transistor M2d_1 and the first terminal of the capacitor CPd_1 (node ​​Nd_1), and the potentials of the gate of the transistor M2d_2 and the first terminal of the capacitor CPd_2 (node ​​Nd_2) are equal to or less than rI. ＸｕｔAt this time, the potential is V ｇｍ Let (r).

[0292] Furthermore, in a period T03, the calculation device CDV is provided with first data w, which is digital data, from the wiring IWL. Specifically, the first data w, which is digital data, is provided from the wiring IWL to a circuit WCDa included in the drive circuit WCD of the calculation device CDV. This causes the circuit WCDa of the drive circuit WCD to generate a current of an amount corresponding to the first data w. Here, the amount of current corresponding to the first data w is referred to as wI. Ｗｕｔ In addition, I Ｗｕｔ is the amount of current that flows when w=1. Also, assume that the switch SWW is in the OFF state. Since the switch SA is in the ON state, the amount wI generated by the circuit WCDa Ｗｕｔ A current of flows through the wiring WCL_1.

[0293] In addition, in the calculation cell IM, the quantity wI Ｗｕｔ The current flows through the source-drain paths of the transistors M3d_1 and M3d_2 to the wiring VE1. At this time, since the transistors M1_1 and M1_2 are on, the potentials of the gate of the transistor M2_1 and the first terminal of the capacitor CP_1 (node ​​N_1), and the potentials of the gate of the transistor M2_2 and the first terminal of the capacitor CP_2 (node ​​N_2) are equal to or greater than the potential of the transistor M1_1. Ｘｕｔ At this time, the potential is V ｇ Let's call it (w).

[0294] In addition, I Ｘｕｔ I Ｗｕｔ It is preferable that the value is equal to I. Ｘｕｔ and I Ｗｕｔ The ratio of one of the above to the other is preferably 0.9 or more and 1.1 or less, more preferably 0.95 or more and 1.05 or less, and even more preferably 0.99 or more and 1.01 or less. Ｘｕｔ and I Ｗｕｔ Each of these is I ＵＴ It will be explained as follows.

[0295] Furthermore, the amount of current generated by each of the circuits XCDa_1 and XCDa_2 is rI ＵＴ is the current in the subthreshold region of each of the transistors M2d_1 and M2d_2, and the gate-source voltage of each of the transistors M2d_1 and M2d_2 is V ｇｍ (r)-V Ｎ Therefore, rI ＵＴ can be expressed as the following equation (1.3).

[0296]

[0297] In addition, V ｔｈ is the threshold voltage of the transistor M2d_1 or the transistor M2d_2, and J is a correction coefficient determined by temperature, device structure, etc. ａ is the gate-source voltage of the transistor M2d_1 or the transistor M2d_2 is V ｔｈ is the amount of current that flows when

[0298] Also, the amount of current generated in the circuit WCDa is wI ＵＴ is the current in the subthreshold region of the transistor M2_1 or the transistor M2_2, and the gate-source voltage of each of the transistors M2_1 and M2_2 is V ｇ (w)-V Ｎ Therefore, wi ＵＴ can be expressed as the following equation (1.4).

[0299]

[0300] For the sake of simplicity, V ｔｈ are equal to each other, and the J in these transistors are equal to each other, and the I in these transistors ａ are assumed to be equal to each other.

[0301] Here, I ＵＴ can be expressed as the following equation (1.5).

[0302]

[0303] Therefore, by using equations (1.4) and (1.5), w can be expressed as in the following equation (1.6).

[0304]

[0305] [Period T04] During the period T04, a low-level potential is applied to the wiring WSL. Therefore, the low-level potential is applied to the gates of the transistors M1_1, M1_2, M1d_1, and M1d_2. As a result, the transistors M1_1, M1_2, M1d_1, and M1d_2 are turned off.

[0306] In the calculation cell IM, the transistors M1_1 and M1_2 are turned off, so that the potential V ｇ (w) is held by the capacitance element CP_1, and the potential V ｇ (w) is held by the capacitor CP_2. As a result, the nodes N_1 and N_2 are each in a floating state. Furthermore, since the potential of the node N_1 is held, the gate-source voltage of the transistor M2_1 is fixed, and therefore, the amount wI continues to flow between the source and drain of the transistor M2_1. ＵＴ Similarly, since the potential of the node N_2 is maintained, the gate-source voltage of the transistor M2_2 is fixed, and therefore a current of the amount wI continues to flow between the source and drain of the transistor M2_2. ＵＴ A current of flows.

[0307] Similarly, in the driving cell IMd, the transistors M1d_1 and M1d_2 are turned off, so that the potential V ｇｍ (r) is held by the capacitance element CPd_1, and the potential V ｇｍ(r) is held by the capacitor CPd_2. As a result, the nodes Nd_1 and Nd_2 are each in a floating state. Furthermore, since the potential of the node Nd_1 is held, the gate-source voltage of the transistor M2d_1 is fixed, and therefore, the quantity rI continues to flow between the source and drain of the transistor M2d_1. ＵＴ Similarly, since the potential of the node Nd_2 is maintained, the gate-source voltage of the transistor M2d_2 is fixed, and a current of the amount rI continues to flow between the source and drain of the transistor M2d_2. ＵＴ A current of flows.

[0308] As in the above-described transistors M2_1, M2_2, M2d_1, and M2d_2, by causing a current of the amount I to flow between the source and drain and holding a potential corresponding to the current at the gate, it is possible to continue to cause a current of the amount I to flow between the source and drain. In this specification, such an operation is referred to as "setting (programming) the amount of current flowing between the source and drain of a transistor to I."

[0309] [Period T05] In the period T05, the circuits XCDa_1 and XCDa_2 of the driver circuit XCD are stopped, and the amount of current generated by each of the circuits XCDa_1 and XCDa_2 is set to 0. In addition, in the circuit XCDa_1, the switch SWX is turned on, and the potential V Ｎ is applied via the switch SWX. In the circuit XCDa_2, the switch SWX is turned on, and the potential V Ｎ is applied via switch SWX.

[0310] The potential V Ｎ Consider the case where the potential V from the circuit XCDa_1 is given. Ｎis applied to the first terminal of the transistor M2d_1 of the driving cell IMd via the wiring XCL_1. Since the node Nd_1 is in a floating state, the potential of the node Nd_1 fluctuates in accordance with the change in the potential of the wiring XCL_1 due to capacitive coupling in the capacitor CPd_1. For example, the potential of the wiring XCL_1 is V ｇｍ (r) to V Ｎ The changed voltage is V ｇｍ (r)-V Ｎ In addition, from now on, V ｇｍ (r)-V Ｎ = ΔV ｇｍ Furthermore, when the capacitive coupling coefficient of the capacitor CPd_1 is p, the change in the potential of the node Nd_1 is pΔV ｇｍ (r) = p(V ｇｍ (r)-V Ｎ ) Therefore, the potential of the node Nd_1 in the period T05 is V ｇｍ (r)-pΔV ｇｍ (r).

[0311] At this time, the gate-source voltage of the transistor M2d_1 is V ｇｍ (r)-pΔV ｇｍ (r)-V Ｎ In this operation example, the amount of current I flowing through the transistor M2d_1 due to this gate-source voltage is Ｍ１＿１ is assumed to be 0.

[0312] In addition, the potential V from the circuit XCDa_1 Ｎ is also applied to the second terminal of the capacitor CP_1 of the processing cell IM via the wiring XCL_1. Since the node N_1 is also in a floating state, the potential of the node N_1 also fluctuates in accordance with the change in the potential of the wiring XCL_1 due to capacitive coupling in the capacitor CP_1. For example, the change in the potential of the wiring XCL_1 is ΔV ｇｍ (r), and when the capacitive coupling coefficient of the capacitor CP_1 is set to p, which is the same as that of the capacitor CPd_1, the change in potential of the node N_1 is pΔV ｇｍ (r) = p(V ｇｍ (r)-V Ｎ) Therefore, the potential of the node N_1 in the period T05 is V ｇ (w)-pΔV ｇｍ (r).

[0313] At this time, the gate-source voltage of the transistor M2_1 is V ｇ (r)-pΔV ｇｍ (r)-V Ｎ In this operation example, the amount of current I flowing through the transistor M2_1 due to this gate-source voltage is Ｍ２＿１ is also set to 0.

[0314] Next, the potential V Ｎ Consider the case where the potential V from the circuit XCDa_2 is given. Ｎ is applied to the first terminal of the transistor M2d_2 of the driving cell IMd via the wiring XCL_2. Since the node Nd_2 is in a floating state, the potential of the node Nd_2 fluctuates in accordance with the change in the potential of the wiring XCL_2 due to capacitive coupling in the capacitor CPd_2. For example, the potential of the wiring XCL_2 is V ｇｍ (r) to V Ｎ The changed voltage is V ｇｍ (r)-V Ｎ In addition, from now on, V ｇｍ (r)-V Ｎ = ΔV ｇｍ In addition, when the capacitive coupling coefficient of the capacitor CPd_2 is set to p, which is the same as that of the capacitors CP_1 and CPd_2, the change in the potential of the node Nd_2 is pΔV ｇｍ (r) = p(V ｇｍ (r)-V Ｎ ) during the period T05. Therefore, the potential of the node Nd_2 in the period T05 is V ｇｍ (r)-pΔV ｇｍ (r).

[0315] At this time, the gate-source voltage of the transistor M2d_2 is V ｇｍ (r)-pΔV ｇｍ (r)-V Ｎand the amount of current flowing through the transistor M2d_2 is I Ｍ２ｄ＿２ is assumed to be 0.

[0316] In addition, the potential V from the circuit XCDa_2 Ｎ is also supplied to the second terminal of the capacitor CP_2 of the processing cell IM via the wiring XCL_2. Since the node N_2 is also in a floating state, the potential of the node N_2 also fluctuates in accordance with the change in the potential of the wiring XCL_2 due to capacitive coupling in the capacitor CP_2. For example, the change in the potential of the wiring XCL_2 is ΔV ｇｍ (r), and when the capacitive coupling coefficient of the capacitor CP_2 is set to p, which is the same as that of the capacitors CP_1, CPd_1, and CPd_2, the change in potential of the node N_2 is pΔV ｇｍ (r) = p(V ｇｍ (r)-V Ｎ ) Therefore, the potential of the node N_2 in the period T05 is V ｇ (w)-pΔV ｇｍ (r).

[0317] At this time, the gate-source voltage of the transistor M2_1 is V ｇ (r)-pΔV ｇｍ (r)-V Ｎ In this operation example, the amount of current I flowing through the transistor M2_2 due to this gate-source voltage is Ｍ２＿２ is also set to 0.

[0318] [Period T06] In the period T06, a low-level potential is applied to the wiring SWLA, and therefore, the control terminal of the switch SA is supplied with a low-level potential, turning the switch SA off.

[0319] In period T06, the circuit WCDa of the driver circuit WCD stops, and the amount of current generated by the circuit WCDa becomes zero. The switch SWW may be turned on or off. In either case, because the switch SA is turned off, the terminal connected to the wiring WCL_1 of the driver circuit WCD has high impedance, and no current or potential is applied from the driver circuit WCD to the wiring WCL_1.

[0320] [Period T07] In the period T07, a high-level potential is applied to the wiring SWLB. Therefore, a high-level potential is applied to each of the control terminals of the switches SB_1 and SB_2, and the switches SB_1 and SB_2 are turned on.

[0321] At this time, the input terminal of the circuit ITSa_1 is electrically connected to the first terminal of the transistor M2_1 of the processing cell IM. Similarly, the input terminal of the circuit ITSa_2 is electrically connected to the first terminal of the transistor M2_2 of the processing cell IM.

[0322] [Period T08] During the period T08, the arithmetic device CDV receives the second data x １ Specifically, the second data x , which is digital data, is supplied from the wiring IXL_1 to the circuit XCDa_1 included in the driver circuit XCD of the arithmetic device CDV. １ As a result, the circuit XCDa_1 of the driving circuit XCD receives the second data x １ Here, the second data x １ The current amount according to x １ I Ｘｕｔ = x １ I ＵＴ In addition, the switch SWX is turned off, and the quantity x generated by the circuit XCDa_1 １ I ＵＴ A current of flows through the wiring XCL_1.

[0323] Amount x １ I ＵＴ The current flows through the transistor M2d_1 of the driving cell IMd to the wiring VE1. At this time, the potential of the wiring XCL_1 is V ＮFrom V ｇｍ (x １ ) because the node Nd_1 is in a floating state. The potential of the node Nd_1 varies in accordance with the change in the potential of the wiring XCL_1 due to capacitive coupling in the capacitor CPd_1. For example, the potential of the wiring XCL_1 is V Ｎ From V ｇｍ (x １ ) so the changed voltage is V ｇｍ (x １ ) -V Ｎ In addition, from now on, V ｇｍ (x １ ) -V Ｎ = ΔV ｇｍ (x １ ) Since the capacitive coupling coefficient of the capacitor CPd_1 is p, the change in the potential of the node Nd_1 is pΔV ｇｍ (x １ ) = p(V ｇｍ (x １ ) -V Ｎ ) Therefore, the potential of the node Nd_1 in the period T08 is V ｇｍ (r)-pΔV ｇｍ (r) + pΔV ｇｍ (x １ ) = V ｇｍ (r) + p(ΔV ｇｍ (x １ ) -ΔV ｇｍ (r)).

[0324] At this time, the gate-source voltage of the transistor M2d_1 is V ｇｍ (r) + p(ΔV ｇｍ (x １ ) -ΔV ｇｍ (r))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M2d_1 Ｍ２ｄ＿１ = x １ I ＵＴ is expressed as the following equation (1.7).

[0325]

[0326] In addition, in the calculation cell IM, the node N_1 is also in a floating state. Therefore, due to a change in the potential of the wiring XCL_1, the potential of the node N_1 fluctuates in accordance with the change in the potential of the wiring XCL_1 due to capacitive coupling in the capacitor CP_1. For example, the amount of change in the potential of the wiring XCL_1 is ΔV ｇｍ (x １ ), and since the capacitive coupling coefficient of the capacitor CP_1 is p, the change in the potential of the node N_1 is also pΔV ｇｍ (x １ ) = p(V ｇｍ (x １ ) -V Ｎ ) Therefore, the potential of the node N_1 in the period T08 is V ｇ (w)-pΔV ｇｍ (r) + pΔV ｇｍ (x １ ) = V ｇ (w)-p(ΔV ｇｍ (x １ ) -ΔV ｇｍ (r)).

[0327] At this time, the gate-source voltage of the transistor M2_1 is V ｇ (w)-p(ΔV ｇｍ (x １ ) -ΔV ｇｍ (r))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M2_1 Ｍ２＿１ is expressed as the following equation (1.8).

[0328]

[0329] Here, r and X are defined as in equations (1.9) and (1.10), respectively.

[0330]

[0331] By using equations (1.5), (1.6), (1.9) and (1.10), equation (1.8) becomes the following equation (1.11).

[0332]

[0333] In addition, in the period T08, the calculation device CDV receives the second data x ２ Specifically, the second data x , which is digital data, is supplied from the wiring IXL_2 to the circuit XCDa_2 included in the driver circuit XCD of the arithmetic device CDV. ２ As a result, the circuit XCDa_2 of the driving circuit XCD receives the second data x ２ Here, the second data x ２ The current amount according to x ２ I Ｘｕｔ = x ２ I ＵＴ In addition, the switch SWX is turned off, and the quantity x generated by the circuit XCDa_2 ２ I ＵＴ The current flows through the wiring XCL_2.

[0334] Amount x ２ I ＵＴ The current flows through the wiring VE1 via the transistor M2d_2 of the driving cell IMd. At this time, the potential of the wiring XCL_2 is V Ｎ From V ｇｍ (x ２ ) because the node Nd_2 is in a floating state. The potential of the node Nd_2 changes in accordance with the change in the potential of the wiring XCL_2 due to capacitive coupling in the capacitor CPd_2. For example, the potential of the wiring XCL_2 is V Ｎ From V ｇｍ (x ２ ) so the changed voltage is V ｇｍ (x ２ ) -V Ｎ In addition, from now on, V ｇｍ (x ２ ) -V Ｎ = ΔV ｇｍ (x ２ ) Since the capacitive coupling coefficient of the capacitor CPd_2 is p, the change in the potential of the node Nd_2 is pΔV ｇｍ (x ２ ) = p(V ｇｍ (x ２ ) -V Ｎ ) Therefore, the potential of the node Nd_2 in the period T08 is Vｇｍ (r)-pΔV ｇｍ (r) + pΔV ｇｍ (x ２ ) = V ｇｍ (r) + p(ΔV ｇｍ (x ２ ) -ΔV ｇｍ (r)).

[0335] At this time, the gate-source voltage of the transistor M2d_2 is V ｇｍ (r) + p(ΔV ｇｍ (x ２ ) -ΔV ｇｍ (r))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M2d_2 Ｍ２ｄ＿２ = x ２ I ＵＴ is expressed as the following equation (1.12).

[0336]

[0337] In addition, in the computation cell IM, the node N_2 is also in a floating state. Therefore, due to a change in the potential of the wiring XCL_2, the potential of the node N_2 fluctuates in accordance with the change in the potential of the wiring XCL_2 due to capacitive coupling in the capacitor CP_2. For example, the amount of change in the potential of the wiring XCL_2 is ΔV ｇｍ (x ２ ), and since the capacitive coupling coefficient of the capacitor CP_2 is p, the change in the potential of the node N_2 is also pΔV ｇｍ (x ２ ) = p(V ｇｍ (x ２ ) -V Ｎ ) Therefore, the potential of the node N_2 in the period T08 is V ｇ (w)-pΔV ｇｍ (r) + pΔV ｇｍ (x ２ ) = V ｇ (w)-p(ΔV ｇｍ (x ２ ) -ΔV ｇｍ (r)).

[0338] At this time, the gate-source voltage of the transistor M2_2 is V ｇ (w)-p(ΔVｇｍ (x ２ ) -ΔV ｇｍ (r))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M2_2 Ｍ２＿２ is expressed as the following equation (1.13).

[0339]

[0340] By using equations (1.5), (1.6), (1.9) and (1.10), equation (1.13) becomes the following equation (1.14).

[0341]

[0342] As shown in equations (1.11) and (1.14), the amount of current I flowing between the source and drain of the transistor M2_1 Ｍ２＿１ is w and x １ The amount of current I flowing between the source and drain of the transistor M2_2 is proportional to the product of Ｍ２＿２ is w and x ２ This means that the amount of current I Ｍ２＿１ The first data is w and x １ and the amount of current I Ｍ２＿２ The first data is w and x ２ Therefore, by using the arithmetic unit CDV of FIG. 1, it is possible to simultaneously obtain the multiplication result of two pieces of second data x １ , x ２ and each multiplication can be performed.

[0343] In particular, when multiplying the first data by the second data, it is preferable to set the reference data r to 1. That is, in the periods T03 and T04, the amount of current that the circuit XCDa_1 passes through the wiring XCL_1 is set to I ＵＴ The amount of current that the circuit XCDa_2 passes through the wiring XCL_2 is I ＵＴ It is preferable to set the following.

[0344] Further, from the above explanation, in the calculation device CDV of FIG. 1, by setting the reference data r to a positive number other than 1, r is used as the divisor, and w×x１ In other words, w and x １ Similarly, if r is the divisor, we can multiply by w x ２ In other words, w and x ２ Therefore, the calculation unit CDV can increase the resolution of the value that can be input as the second data. １ or x ２ When it is considered that the calculation device CDV performs a multiplication by the first data, it can be said that the calculation device CDV can increase the resolution of the value that can be input as the first data.

[0345] Furthermore, it is preferable that the capacitive coupling coefficient p of each of the capacitors CP_1, CP_2, CPd_1, and CPd_2 be as close to 1 as possible. Specifically, for example, p is preferably 0.8 to 1, more preferably 0.9 to 1, even more preferably 0.95 to 1, and even more preferably 0.99 to 1. For example, by setting p to 1, in the capacitive coupling of the node N_1 and the node Nd_1 caused by a change in the potential of the wiring XCL_1 in the periods T03, T04, and T08, the amount of change in the potential of the wiring XCL_1 can be made equal to the amount of change in the potential of the node N_1 and the node Nd_1. Similarly, in the capacitive coupling of the node N_2 and the node Nd_2 caused by a change in the potential of the wiring XCL_2, the amount of change in the potential of the wiring XCL_2 can be made equal to the amount of change in the potential of the node N_2 and the node Nd_2. Conversely, as p becomes smaller than 1, the amount of change in the potential of each of the nodes N_1, Nd_1, N_2, and Nd_2 due to capacitive coupling becomes smaller. Therefore, the second data x １ , x ２ Therefore, it is preferable that p is as close to 1 as possible.

[0346] Since the switch SA is in an off state and the switches SB_1 and SB_2 are in an on state, the amount I Ｍ２＿１ A current of I flows through the input terminal of the circuit ITSa_1 included in the driver circuit ITS and flows between the source and drain of the transistor M2_2. Ｍ２＿２ flows to the input terminal of the circuit ITSa_2 included in the drive circuit ITS.

[0347] In the circuit ITSa_1, the quantity I Ｍ２＿１ By obtaining the current, the quantity I Ｍ２＿１ The circuit ITSa_1 calculates a function in which a value according to I is substituted as a variable, and outputs a voltage or current according to the calculation result from an output terminal. Ｍ２＿１ The function with the input value is F １ (I Ｍ２＿１ ) and the result of the operation is z １ When this is the case, z １ can be expressed as the following equation (1.15). Ｍ２＿２ The function with the input value is F ２ (I Ｍ２＿２ ) and the result of the operation is z ２ When this is the case, z ２ can be shown as equation (1.16) below.

[0348]

[0349] Therefore, by using the arithmetic unit CDV of FIG. 1, the multiplication result of the first data and the second data w×x １ , wxx ２ In addition, the results of the calculations can be output to the wirings OL_1 and OL_2.

[0350] <Modification 1 of Arithmetic Circuit> Next, a modification of the arithmetic circuit CC included in the arithmetic device CDV shown in FIG. 1 will be described.

[0351] The arithmetic circuit CC shown in FIG. 8 has a circuit configuration in which the arithmetic cell IM shown in FIG. 1 does not include the transistors M3_1 and M3_2, and the driving cell IMd shown in FIG. 1 does not include the transistors M3d_1 and M3d_2.

[0352] 8, in the calculation cell IM, the second terminal of the transistor M1_2 and the first terminal of the transistor M2_1 are connected to the wiring WCL_1, and the first terminal of the transistor M2_2 is connected to the wiring WCL_2. In the driving cell IMd, the second terminal of the transistor M1d_2 and the first terminal of the transistor M2d_1 are connected to the wiring XCL_1, and the first terminal of the transistor M2d_2 is connected to the wiring XCL_2.

[0353] As described above, in the calculation circuit CC of FIG. 1 , transistor M3_1 functions as a clamp transistor for suppressing DIBL for transistor M2_1. Incidentally, if transistor M2_1 is a transistor that is not affected by DIBL, the calculation cell IM of the calculation circuit CC can be configured not to include transistor M3_1, which is a clamp transistor, as shown in FIG. 8 . Similarly, if transistor M2_2 is a transistor that is not affected by DIBL, the calculation cell IM of the calculation circuit CC can be configured not to include transistor M3_2, which is a clamp transistor, as shown in FIG. 8 . Similarly, if transistors M2d_1 and M2d_2 are both transistors that are not affected by DIBL, the driver cell IMd of the calculation circuit CC can be configured not to include transistors M3d_1 and M3d_2, which are clamp transistors, as shown in FIG. 8 .

[0354] The circuit area of ​​the arithmetic circuit CC can be reduced by changing the arithmetic circuit CC of Fig. 1 to the arithmetic circuit CC of Fig. 8. Specifically, the arithmetic circuit CC of Fig. 8 does not include the transistors M3_1, M3_2, M3d_1, and M3d_2, and does not include the wiring VE2. Therefore, the arithmetic circuit CC of Fig. 8 can have a smaller circuit area than the arithmetic circuit CC of Fig. 1. This can lead to a reduction in the circuit area of ​​the arithmetic device CDV.

[0355] Furthermore, since the wiring VE2 is not provided, there is no need to generate the fixed potential or variable potential provided by the wiring VE2. This reduces the power consumption required to generate the fixed potential or variable potential. This leads to a reduction in the power consumption of the calculation device CDV.

[0356] <Modification 2 of the Arithmetic Circuit> The arithmetic circuit CC shown in FIG. 9 is a modification of the arithmetic circuit CC shown in FIG. 1, and is configured to convert S (S is an integer of 3 or more) pieces of second data x to the first data w. １ 〜x Ｋ 9 is an arithmetic circuit that can perform multiplication by each of the arithmetic circuit CC and the driving circuit XCD, the driving circuit WSD, the driving circuit ITS, and the like, in order to explain the peripheral connection configuration with the arithmetic circuit CC. Therefore, the circuit configuration shown in FIG. 9 can be said to be a modified example of the circuit configuration of the arithmetic circuit CDV in FIG. 1.

[0357] 9, the calculation cell IM includes transistors M1_1 to M1_S, transistors M2_1 to M2_S, transistors M3_1 to M3_S, and capacitors CP_1 to CP_S. The driver cell IMd includes transistors M1d_1 to M1d_S, transistors M2d_1 to M2d_S, transistors M3d_1 to M3d_S, and capacitors CPd_1 to CPd_S.

[0358] Note that Figure 9 excerpts the transistors M1_1, M1_2, M1_S-1, M1_S, M2_1, M2_2, M2_S, M3_1, M3_2, M3_S, CP_1, CP_2, and CP_S from among the transistors M1_1 to M1_S, the transistors M2_1 to M2_S, the transistors M3_1 to M3_S, and the capacitors CP_1 to CP_S. 9 excerpts the transistors M1d_1, M1d_2, M1d_S-1, M1d_S, M2d_1, M2d_2, M2d_S, M3d_1, M3d_2, M3d_S, M3d_1, M3d_2, M3d_S, M1d_1, M1d_2, M1d_3, M1d_4, M1d_5, M1d_6, M1d_7, M1d_8, M1d_9, M1d_10, M1d_11, M1d_12, M1d_13, M1d_14, M1d_15, M1d_16, M1d_17, M1d_18, M1d_19, M1d_20, M1d_21, M1d_22, M1d_23, M1d_24, M1d_25, M1d_26, M1d_27, M1d_28, M1d_2 ...9, M1d_20, M1d_21, M1d_22, M1d_23, M1d_24, M1d_25, M1d_26, M1d_27, M1d_28, M1d_

[0359] 9, the transistors M1_1 to M1_S correspond to the transistors M1_1 and M1_2 in FIG. 1, the transistors M2_1 to M2_S correspond to the transistors M2_1 and M2_2 in FIG. 1, and the transistors M3_1 to M3_S correspond to the transistors M3_1 and M3_2 in FIG. 1. The capacitors CP_1 to CP_S correspond to the capacitors CP_1 and CP_2 in FIG. 1.

[0360] 9, the transistors M1d_1 to M1d_S correspond to the transistors M1d_1 and M1d_2 in FIG. 1, the transistors M2d_1 to M2d_S correspond to the transistors M2d_1 and M2d_2 in FIG. 1, and the transistors M3d_1 to M3d_S correspond to the transistors M3d_1 and M3d_2 in FIG. 1. The capacitors CPd_1 to CPd_S correspond to the capacitors CPd_1 and CPd_2 in FIG. 1.

[0361] 9, a first terminal of the transistor M1_1 is connected to the gate of the transistor M2_1 and the first terminal of the capacitor CP_1. A first terminal of the transistor M1_s (s is an integer between 2 and S) is connected to the second terminal of the transistor M1_s-1, the gate of the transistor M2_s, and the first terminal of the capacitor CP_s.

[0362] Note that a connection point between the first terminal of the transistor M1_1, the gate of the transistor M2_1, and the first terminal of the capacitor CP_1 is referred to as a node N_1, and a connection point between the first terminal of the transistor M1_s, the second terminal of the transistor M1_s-1, the gate of the transistor M2_s, and the first terminal of the capacitor CP_s is referred to as a node N_s. Note that, of the nodes N_1 to N_S, only the nodes N_1, N_2, and N_S are illustrated in FIG.

[0363] The first terminal of the transistor M2_1 is connected to the first terminal of the transistor M3_1. The second terminal of the transistor M1_S and the second terminal of the transistor M3_1 are connected to the wiring WCL_1. The first terminal of the transistor M2_s is connected to the first terminal of the transistor M3_s. The second terminal of the transistor M3_s is connected to the wiring WCL_s. The second terminals of the transistors M2_1 to M2_S are connected to the wiring VE1. The gates of the transistors M3_1 to M3_S are connected to the wiring VE2.

[0364] 9, a first terminal of the transistor M1d_1 is connected to the gate of the transistor M2d_1 and the first terminal of the capacitance element CPd_1, and a first terminal of the transistor M1d_s is connected to the second terminal of the transistor M1d_s-1, the gate of the transistor M2d_s, and the first terminal of the capacitance element CPd_s.

[0365] Note that a connection point between the first terminal of the transistor M1d_1, the gate of the transistor M2d_1, and the first terminal of the capacitor CPd_1 is referred to as a node Nd_1, and a connection point between the first terminal of the transistor M1d_s, the second terminal of the transistor M1d_s-1, the gate of the transistor M2d_s, and the first terminal of the capacitor CPd_s is referred to as a node Nd_s. Note that, of the nodes Nd_1 to Nd_S, only the nodes Nd_1, Nd_2, and Nd_S are illustrated in FIG.

[0366] The first terminal of the transistor M2d_1 is connected to the first terminal of the transistor M3d_1. The second terminal of the transistor M1d_S, the second terminal of the transistor M3d_1, the second terminal of the capacitor CP_1, and the second terminal of the capacitor CPd_1 are connected to the wiring XCL_1. The first terminal of the transistor M2_s is connected to the first terminal of the transistor M3_s. The second terminal of the transistor M3_s is connected to the wiring WCL_s. The second terminal of the transistor M3d_s, the second terminal of the capacitor CP_s, and the second terminal of the capacitor CPd_s are connected to the wiring XCL_s. The second terminals of the transistors M2d_1 to M2d_S are connected to the wiring VE1. The gates of the transistors M3d_1 to M3d_S are connected to the wiring VE2.

[0367] In the calculation cell IM and the driver cell IMd in FIG. 9, the gates of the transistors M1_1 to M1_S and the gates of the transistors M1d_1 to M1d_S are connected to the wiring WSL.

[0368] The wiring WCL_1 shown in Fig. 9 can be the wiring WCL_1 shown in Fig. 1. Therefore, in the arithmetic device CDV in Fig. 9 as well, the wiring WCL_1 is connected to the driver circuit WCD and the driver circuit ITS.

[0369] The wirings WCL_2 to WCL_S shown in Fig. 9 can be the wiring WCL_2 shown in Fig. 1. Therefore, in the arithmetic device CDV in Fig. 9, the wirings WCL_2 to WCL_S are also connected to the driver circuit ITS.

[0370] 9 can be the wirings XCL_1 and XCL_2 shown in FIG 1. Therefore, in the arithmetic device CDV in FIG 9, the wirings XCL_1 to WCL_S are also connected to the driver circuit XCD.

[0371] The wiring WSL shown in Fig. 9 can be the wiring WSL shown in Fig. 1. Therefore, in the arithmetic device CDV in Fig. 9 as well, the wiring WSL is connected to the driver circuit WSD.

[0372] The drive circuit WCD shown in Fig. 9 corresponds to the drive circuit WCD shown in Fig. 1. Therefore, the drive circuit WCD in Fig. 9 has the function of supplying a signal of an amount corresponding to first data w acquired from outside the calculation device CDV to the wiring WCL_1, similar to the drive circuit WCD in Fig. 1, for example. Furthermore, for the rest of the description, the description of the drive circuit WCD in Fig. 1 can be referred to.

[0373] The driving circuit XCD shown in Fig. 9 corresponds to the driving circuit XCD shown in Fig. 1. Therefore, the driving circuit XCD of Fig. 9, for example, like the driving circuit XCD of Fig. 1, １ a function of supplying a signal of an amount corresponding to the second data x acquired from the outside of the calculation device CDV to the wiring XCL_1; ｓ and a function of supplying a signal of an amount corresponding to the signal to the wiring XCL_s. Regarding other details, the description of the driver circuit XCD in FIG.

[0374] The drive circuit WSD shown in Fig. 9 corresponds to the drive circuit WSD shown in Fig. 1. Therefore, the drive circuit WSD in Fig. 9 has a function as a write word line driver circuit, for example, similar to the drive circuit WSD in Fig. 1.

[0375] 9 is connected to wirings OL_1 to OL_S, which correspond to the wirings OL_1 and OL_2 shown in FIG. 1. The driver circuit ITS shown in FIG. 9 corresponds to the driver circuit ITS shown in FIG. 1. Therefore, the driver circuit ITS in FIG. 9 converts the first data w and the second data x performed in the arithmetic cell IM. １ 8 has a function of obtaining from the wiring WCL_1 a current of an amount corresponding to the result of the multiplication of the first data w and the second data x performed in the operation cell IM, performing a calculation of a function in which the result of the multiplication is substituted as a variable, and outputting the result of the calculation to the wiring OL_1. ｓThe current calculation unit 100 has a function of obtaining from the wiring WCL_s an amount of current corresponding to the multiplication result of the above, executing a calculation of a function in which the multiplication result is substituted as a variable, and outputting the calculation result to the wiring OL_s.

[0376] For the operation method of the calculation device CDV in FIG. 9, the operation example of the timing chart in FIG. 7 described above can be referred to.

[0377] For example, in the period T02, a high-level potential is applied from the driver circuit WSD to the wiring WSL, and the high-level potential is applied to the gates of the transistors M1_1 to M1_S and the transistors M1d_1 to M1d_S, respectively, so that the transistors M1_1 to M1_S and the transistors M1d_1 to M1d_S can be turned on.

[0378] Furthermore, for example, in the period T03, the driver circuit XCD applies a voltage rI corresponding to the reference data r to each of the wirings XCL_1 to XCL_S. ＵＴ By passing a current of V, the potentials of the nodes Nd_1 to Nd_S of the driving cell IMd are set to V ｇｍ (r).

[0379] Also, for example, in a period T04, an amount wI corresponding to the first data w is supplied from the driving circuit WCD to the wiring XCL_1. ＵＴ By passing V, the potentials of the nodes N_1 to N_S of the processing cell IM are set to V ｇ (w).

[0380] Further, for example, in the period T05, the driver circuit WSD applies a low-level potential to the wiring WSL, and the low-level potential is applied to the gates of the transistors M1_1 to M1_S and the transistors M1d_1 to M1d_S. This can turn off the transistors M1_1 to M1_S and the transistors M1d_1 to M1d_S. As a result, the potential V ｇｍ(r), and the nodes N_1 to N_S of the operation cell IM are supplied with a potential V ｇ (w) can be held.

[0381] In addition, for example, in the period T08, the driver circuit XCD supplies the second data x １ 〜x Ｋ Specifically, a current of the amount x flows from the driver circuit XCD to each of the wirings XCL_1 to XCL_S. １ I ＵＴ ~Amount x Ｋ I ＵＴ By passing a current of w×x in the calculation cell IM, １ 〜w×x Ｋ Further, currents according to the results of the multiplications flow through the wirings WCL_1 to WCL_K.

[0382] By using the arithmetic circuit CC of FIG. 9, S (S is an integer of 3 or more) pieces of second data x are obtained for the first data w. １ 〜x Ｋ The results of these multiplications can be expressed as w×x １ 〜w×x Ｋ These are used as input values, and the drive circuit ITS performs function calculations to obtain the results of the calculations.

[0383] <Modification 3 of Arithmetic Circuit> The arithmetic circuit CC shown in FIG. 10A is a modification of the arithmetic circuit CC shown in FIG. 1, and has a circuit configuration in which the driving cell IMd in FIG. 1 is divided into driving cells IMda and IMdb.

[0384] The driving cell IMda includes a transistor M1a, a transistor M2a, a transistor M3a, and a capacitance element CPa, while the driving cell IMdb includes a transistor M1b, a transistor M2b, a transistor M3b, and a capacitance element CPb.

[0385] The transistors M1a and M1b function as write transistors, similar to the transistors M1d_1 and M1d_2 of the driver cell IMd in Fig. 1. The transistors M2a and M2b function as amplifier transistors, similar to the transistors M2d_1 and M2d_2 of the driver cell IMd in Fig. 1. The transistors M3a and M3b function as clamp transistors, similar to the transistors M3d_1 and M3d_2 of the driver cell IMd in Fig. 1.

[0386] In the driving cell IMda, the first terminal of the transistor M1a is connected to the gate of the transistor M2a and the first terminal of the capacitance element CPa, and the first terminal of the transistor M2a is connected to the first terminal of the transistor M3a. The second terminals of the transistors M1a and M3a are connected to the wiring XCL_1. The gate of the transistor M1a is connected to the wiring WSL, the second terminal of the transistor M2a is connected to the wiring VE1, the gate of the transistor M3a is connected to the wiring VE2, and the second terminal of the capacitance element CPa is connected to the wiring XCL_1.

[0387] In the driving cell IMdb, the first terminal of the transistor M1b is connected to the gate of the transistor M2b and the first terminal of the capacitance element CPb, and the first terminal of the transistor M2b is connected to the first terminal of the transistor M3b. The second terminals of the transistors M1b and M3b are connected to the wiring XCL_2. The gate of the transistor M1b is connected to the wiring WSL, the second terminal of the transistor M2b is connected to the wiring VE1, the gate of the transistor M3b is connected to the wiring VE2, and the second terminal of the capacitance element CPb is connected to the wiring XCL_2.

[0388] For the circuit configuration of the operation cell IM, the description of the operation cell IM in FIG. 1 can be referred to.

[0389] In addition, in Figure 10A, the connection point between the first terminal of transistor M1a, the gate of transistor M2a, and the first terminal of capacitance element CPa is shown as node Na, and the connection point between the first terminal of transistor M1b, the gate of transistor M2a, and the first terminal of capacitance element CPb is shown as node Nb.

[0390] The calculation circuit CC shown in FIG. 10A has a circuit configuration in which the driving cell IMd in FIG. 1 is divided into driving cells IMda and IMdb. １ / r operation and w×x ２ Note that when performing the calculation of / r, it is necessary to write the reference data r to each of the driving cells IMda and IMdb. Also, for the operation method of the calculation circuit CC in Figure 10A, the explanation of the operation method from period T05 onwards in the timing chart of Figure 7 can be referred to.

[0391] 10A, the driving cell IMd is divided into the driving cell IMda and the driving cell IMdb, so that different reference data can be written to the driving cell IMda and the driving cell IMdb. For example, in the periods T03 and T04 of the operation method of the timing chart of FIG. １ and writes the reference data r ２ By writing the value w×x in the operation method of the timing chart of FIG. 7, the operation cell IM １ / r １ Calculation and w×x ２ / r ２ The above calculations can be performed simultaneously.

[0392] Furthermore, if transistors M2_1, M2_2, M2a, and M2b are not affected by DIBL, the arithmetic circuit CC of FIG. 10A can be modified to a configuration in which transistors M3_1, M3_2, M3a, and M3b are not provided.

[0393] The arithmetic circuit CC shown in Figure 10B is a modified example of the arithmetic circuit CC of Figure 10A, and differs from the circuit configuration of the arithmetic circuit CC of Figure 10A in that transistors M3_1, M3_2, M3a, and M3b are not provided.

[0394] Specifically, the second terminal of the transistor M1_2 and the first terminal of the transistor M2_1 are connected to the wiring WCL_1, and the first terminal of the transistor M2_2 is connected to the wiring WCL_2. The second terminal of the transistor M1a and the first terminal of the transistor M2a are connected to the wiring XCL_1, and the second terminal of the transistor M1b and the first terminal of the transistor M2b are connected to the wiring XCL_2.

[0395] The arithmetic circuit CC shown in Fig. 10B can have a smaller circuit area than the arithmetic circuit CC of Fig. 10A. Specifically, the arithmetic circuit CC of Fig. 10B does not have transistors M3_1, M3_2, M3a, and M3b, and does not have wiring VE2, so the arithmetic circuit CC of Fig. 10B can have a smaller circuit area than the arithmetic circuit CC of Fig. 10A. This can lead to a reduction in the circuit area of ​​the arithmetic device CDV.

[0396] 10B does not include the wiring VE2, so there is no need to generate the fixed potential or variable potential provided by the wiring VE2, and therefore power consumption for generating the fixed potential or variable potential can be reduced. This can lead to a reduction in power consumption of the arithmetic device CDV when the arithmetic device CC of FIG. 10B is provided in the arithmetic device CDV.

[0397] In the calculation circuit CC of FIG. 10A, the holding time of the first data w written to the calculation cell IM and the holding time of the second data x written to the driving cell IMda are １ and the second data x written to the driving cell IMdb. ２ When it is desired to lengthen the holding time of and it is preferable to change the circuit configuration of the arithmetic circuit CC shown in FIG. 10A to that of the arithmetic circuit CC shown in FIG. 11A.

[0398] The calculation circuit CC shown in Figure 11A has a circuit configuration similar to that of the calculation circuit CC in Figure 10A, except that the calculation cell IM further includes a transistor M4 and a capacitance element CQ, the driving cell IMda includes a transistor M4a and a capacitance element CQa, and the driving cell IMdb includes a transistor M4b and a capacitance element CQb.

[0399] Specifically, in the computation cell IM, the first terminal of the transistor M4 is connected to the second terminal of the transistor M1_2 and the first terminal of the capacitance element CQ, and the gate of the transistor M4 is connected to the wiring WSL. The second terminal of the transistor M4 and the second terminal of the transistor M3_1 are each connected to the wiring WCL_1. The second terminal of the capacitance element CQ is connected to the wiring VE3.

[0400] In the driving cell IMda, the first terminal of the transistor M4a is connected to the second terminal of the transistor M1a and the first terminal of the capacitance element CQa, and the gate of the transistor M4a is connected to the wiring WSL. The second terminal of the transistor M4a, the second terminal of the transistor M3a, and the second terminal of the capacitance element CQa are each connected to the wiring XCL_1.

[0401] In the driving cell IMdb, the first terminal of the transistor M4b is connected to the second terminal of the transistor M1b and the first terminal of the capacitance element CQb, and the gate of the transistor M4b is connected to the wiring WSL. The second terminal of the transistor M4b, the second terminal of the transistor M3b, and the second terminal of the capacitance element CQb are each connected to the wiring XCL_2.

[0402] 11A, a connection point between the first terminal of the transistor M1_1, the gate of the transistor M2_1, and the first terminal of the capacitor CP_1 is indicated as a node N_1, a connection point between the first terminal of the transistor M1_1, the first terminal of the transistor M1_2, the gate of the transistor M2_2, and the first terminal of the capacitor CP_2 is indicated as a node N_2, a connection point between the second terminal of the transistor M1_2, the first terminal of the transistor M4, and the first terminal of the capacitor CQ is indicated as a node NQ, a connection point between the first terminal of the transistor M1a, the gate of the transistor M2a, and the first terminal of the capacitor CPa is indicated as a node Na_1, and a connection point between the second terminal of the transistor M1a, the first terminal of the transistor M4a, and the first terminal of the capacitor CQa is indicated as a node Na_2. In addition, the connection point between the first terminal of transistor M1b, the gate of transistor M2b, and the first terminal of capacitance element CPb is indicated as node Nb_1, and the connection point between the second terminal of transistor M1b, the first terminal of transistor M4b, and the first terminal of capacitance element CQb is indicated as node Nb_2.

[0403] 7 , by applying a high-level potential to the wiring WSL, the transistors M1_1, M1_2, and M4 of the arithmetic cell IM can be turned on. Also, in a period T03 of the timing chart of FIG. 7 , a current corresponding to the first data w flows from the wiring WCL_1 to the arithmetic cell IM, thereby writing potentials corresponding to the first data w to the nodes N_1, N_2, and NQ. Also, in a period T04 of the timing chart of FIG. 7 , by applying a low-level potential to the wiring WSL, the transistors M1_1, M1_2, and M4 of the arithmetic cell IM can be turned off, and the potentials corresponding to the first data w can be held at the nodes N_1, N_2, and NQ.

[0404] In addition, during a period T05 in the timing chart of FIG. 7, the circuit XCDa_1 supplies a potential V ＮBy applying the potential V Ｎ is applied, the potential of the node Na_1 changes due to capacitive coupling by the capacitor CPa, and no current flows between the source and drain of the transistor M2a. The potential of the node Na_2 also changes due to capacitive coupling by the capacitor CQa. In addition, the circuit XCDa_2 applies a potential V Ｎ , the second terminal of the capacitance element CPb and the second terminal of the capacitance element CQb in the driving cell IMdb are supplied with the potential V Ｎ , the potential of the node Nb_1 changes due to the capacitive coupling of the capacitor CPb, and no current flows between the source and drain of the transistor M2b. The potential of the node Nb_2 also changes due to the capacitive coupling of the capacitor CQb.

[0405] The driver circuit XCD supplies a potential V Ｎ is applied to the second terminal of the capacitance element CP_1 in the calculation cell IM. Ｎ is applied to the second terminal of the capacitor CP_2, the potential of the node N_1 changes due to capacitive coupling by the capacitor CP_1, and no current flows between the source and drain of the transistor M2_1. Ｎ is applied, the potential of the node N_2 changes due to capacitive coupling by the capacitor CP_2, and no current flows between the source and drain of the transistor M2_2. Note that since the transistors M1_2 and M4 are both off, the node NQ is in a floating state. Therefore, the potential V Ｎ is applied, the potential V Ｗ Ideally, does not change.

[0406] In addition, during a period T08 in the timing chart of FIG. 7, the circuit XCDa_1 transmits the second data x １ As a result of a current flowing according to the voltage V ... ｇｍ (r) + p(ΔV ｇｍ (x １ ) -ΔV ｇｍ Further, the circuit XCDa_2 transmits the second data x ２ As a result, in the driving cell IMdb, the potentials of the nodes Nb_1 and Nb_2 are increased to V due to the capacitive coupling between the capacitive elements CPb and CQb. ｇｍ (r) + p(ΔV ｇｍ (x ２ ) -ΔV ｇｍ In the operation cell IM, the node NQ is in a floating state. Therefore, the second data x １ , x ２ Even if a current corresponding to Ｗ Ideally, does not change.

[0407] Unlike the above, in reality, the node NQ is temporarily supplied with a potential V Ｗ After writing the data, in and after the period T04, the potential of the node NQ may also fluctuate due to capacitive coupling between the source and drain of the transistor M4 depending on the potential of the wiring WCL_1. At this time, if the potential of the node NQ is held by the wiring VE3 that applies a fixed potential and the capacitor CQ, fluctuations in the potential of the node NQ due to capacitive coupling between the source and drain of the transistor M4, which occur when a potential is applied from the wiring WCL_1, can be suppressed. As a result, changes in the potential of the node N_2 due to capacitive coupling between the source and drain of the transistor M1_2 caused by changes in the potential of the node NQ can also be suppressed.

[0408] As described above, by using the arithmetic circuit CC of Figure 11A, in the timing chart of Figure 7, nodes Na_1 and Na_2 can each maintain an equal potential while maintaining a floating state, and similarly, nodes Nb_1 and Nb_2 can each maintain an equal potential while maintaining a floating state.

[0409] As shown in FIG. 11A , in the driver cell IMda, by connecting the first terminal of the transistor M4a to the second terminal of the transistor M1a, the channel length of the transistor M1a can be effectively increased. This reduces the off-state current of each of the transistors M1a and M4a. Because the capacitor CQa is provided between the second terminal of the transistor M1a and the first terminal of the transistor M4a, as described above, the first terminal of the capacitor CPa and the first terminal of the capacitor CQa can be maintained at approximately the same potential. This prevents charge distribution via the transistor M1a even if the off-state current of the transistor M1a increases, allowing the potential of the node Na_1 to be maintained for a long period of time. The same applies to the driver cell IMdb.

[0410] 11A can be changed to, for example, the configuration of the arithmetic circuit CC shown in Fig. 11B. The arithmetic circuit CC shown in Fig. 11B differs from the configuration of the arithmetic circuit CC shown in Fig. 11A in that the second terminal of the capacitance element CQa is connected to the wiring VE3 instead of the wiring XCL_1, and the second terminal of the capacitance element CQb is connected to the wiring VE3 instead of the wiring XCL_2.

[0411] Because the second terminal of the capacitor CQa is not connected to the wiring XCL_1, the potential of the node Na_2 does not change due to capacitive coupling caused by a potential change in the wiring XCL_1, for example, in the operation of the timing chart of Figure 7. Similarly, because the second terminal of the capacitor CQb is not connected to the wiring XCL_2, the potential of the node Nb_2 does not change due to capacitive coupling caused by a potential change in the wiring XCL_2, for example, in the operation of the timing chart of Figure 7. Furthermore, by applying a fixed potential from the wiring VE3, the potential of the node Na_2 in the floating state is held by the capacitor CQa, and similarly, the potential of the node Nb_2 in the floating state is held by the capacitor CQb.

[0412] Unlike the above, in reality, in the driving cell IMda, the potential V ｒ After writing the potential (based on the reference data), the potential of the node Na_2 may also fluctuate due to capacitive coupling between the source and drain of the transistor M4a depending on the potential of the wiring XCL_1 from period T04 onward. At this time, if the potential of the node Na_2 is held by the wiring VE3 that applies a fixed potential and the capacitor CQa, fluctuations in the potential of the node Na_2 due to capacitive coupling between the source and drain of the transistor M4a, which occur when a potential is applied from the wiring XCL_1, can be suppressed. This suppresses changes in the potential of the node Na_1 due to capacitive coupling between the source and drain of the transistor M1a_1 caused by changes in the potential of the node Na_2. The same applies to the driving cell IMdb.

[0413] Furthermore, in the arithmetic circuit CC of FIG. 11A or 11B, if transistors M2_1, M2_2, M2a, and M2b are not affected by DIBL, the arithmetic circuit CC of FIG. 11A or 11B can be modified to a configuration in which transistors M3_1, M3_2, M3a, and M3b are not provided.

[0414] For example, the arithmetic circuit CC in Fig. 11A can be changed to the configuration of the arithmetic circuit CC shown in Fig. 12A. Also, the arithmetic circuit CC in Fig. 11B can be changed to the configuration of the arithmetic circuit CC shown in Fig. 12B.

[0415] Specifically, the second terminal of the transistor M4 and the first terminal of the transistor M2_1 are connected to the wiring WCL_1, the first terminal of the transistor M2_2 is connected to the wiring WCL_2, the second terminal of the transistor M4a and the first terminal of the transistor M2a are connected to the wiring XCL_1, and the second terminal of the transistor M4b and the first terminal of the transistor M2b are connected to the wiring XCL_2.

[0416] The arithmetic circuit CC shown in FIG. 12A can reduce the circuit area compared to the arithmetic circuit CC of FIG. 11A. Specifically, the arithmetic circuit CC of FIG. 12A does not include transistors M3_1, M3_2, M3a, and M3b, and does not include wiring VE2. Therefore, the arithmetic circuit CC of FIG. 12A can reduce the circuit area compared to the arithmetic circuit CC of FIG. 11A. This can lead to a reduction in the circuit area of ​​the arithmetic device CDV. The same can be said for the arithmetic circuit CC shown in FIG. 12B.

[0417] 12A or 12B does not include the wiring VE2, and therefore there is no need to generate the fixed potential or variable potential provided by the wiring VE2, and therefore power consumption for generating the fixed potential or variable potential can be reduced. As a result, when the calculation device CDV includes the calculation circuit CC of FIG. 12A or 12B, the power consumption of the calculation device CDV can be reduced.

[0418] <Layout Example of Arithmetic Circuit> Next, an example of a schematic plan view of each of the arithmetic cell IM and the driving cell IMd shown in FIG. 1 will be described.

[0419] FIG. 13 is a schematic plan view showing an example of the processing cell IM shown in FIG. 1, and FIG. 14 is a schematic plan view showing an example of the driving cell IMd shown in FIG.

[0420] 13, the calculation cell IM includes, as an example, a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Similarly, the driving cell IMd includes, as an example, a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Note that, to clearly show the schematic plan views, the insulating layers included in the calculation cell IM and the driving cell IMd are not shown in FIGS. 13 and 14.

[0421] As an example, the semiconductor layer SMC is located below the conductive layers SDM and GEM. Also, as an example, the conductive layer PLG is located above the conductive layers SDM and GEM. Also, as an example, the conductive layer WIR is located above the conductive layer PLG. The order of formation can be as follows: first, the semiconductor layer SMC, second, one of the conductive layers SDM and GEM, third, the other of the conductive layers SDM and GEM, fourth, the conductive layer PLG, and fifth, the conductive layer WIR.

[0422] In the processing cell IM and the driving cell IMd, a part of the conductive layer GEM functions as, for example, the gates of the transistors M1_1, M1_2, M2_1, M2_2, M3_1, M3_2, M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2. Also, a part of the conductive layer GEM functions as, for example, one of a pair of electrodes of each of the capacitors CP_1, CP_2, CPd_1, and CPd_2.

[0423] 13 and 14, the wiring XCL_1, the wiring XCL_2, the wiring WSL, and the wiring VE2 extending in the horizontal direction of the drawing around the processing cell IM or the driving cell IMd can be formed as part of the conductive layer GEM.

[0424] In the calculation cell IM and the driving cell IMd, a portion of the conductive layer SDM functions as the source or drain of each of the transistors M1_1, M1_2, M2_1, M2_2, M3_1, M3_2, M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2, for example.

[0425] For example, a part of the conductive layer WIR functions as the other of the pair of electrodes of each of the capacitors CP_1, CP_2, CPd_1, and CPd_2.

[0426] Furthermore, a portion of the conductive layer WIR can be a wiring extending around the periphery of the processing cell IM or the driver cell IMd. For example, in FIG. 13, the wiring VE1, wiring WCL_1, and wiring WCL_2 extending in the vertical direction of the drawing around the processing cell IM can be formed as a portion of the conductive layer WIR. For example, in FIG. 14, the wiring VE1 extending in the vertical direction of the drawing around the driver cell IMd can be formed as a portion of the conductive layer WIR.

[0427] Furthermore, in Figures 13 and 14, the wiring VE1, wiring WCL_1, and wiring WCL_2 extend in the vertical direction of the drawing, and the wiring XCL_1, wiring XCL_2, wiring WSL, and wiring VE2 extend in the horizontal direction of the drawing, so it is preferable that the conductive layer WIR and the conductive layer GEM are arranged so as to intersect with each other.

[0428] The conductive layer GEM, the conductive layer SDM, the conductive layer WIR, and the semiconductor layer SMC can each be formed using, for example, a lithography method. Specifically, for example, when forming the conductive layer GEM, a conductive material to be the conductive layer GEM can be formed using one or more methods selected from a sputtering method, a CVD (Chemical Vapor Deposition) method, a PLD (Pulsed Laser Deposition) method, and an ALD (Atomic Layer Deposition) method, and then a desired pattern can be formed using a lithography method. In addition, the conductive layer SDM, the conductive layer WIR, the semiconductor layer SMC, and the conductive layer PLG can also be formed using the same method as above.

[0429] In this specification, the lithography method includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0430] Furthermore, insulating layers may be provided between the semiconductor layer SMC and the conductive layer GEM, between the conductive layer GEM and the conductive layer SDM, and between the conductive layer WIR and the conductive layer GEM. In particular, the insulating layer provided between the semiconductor layer SMC and the conductive layer GEM may function as a gate insulating film (sometimes referred to as a front gate insulating film, etc.). Furthermore, in the region where the capacitance elements CP_1, CP_2, CPd_1, and CPd_2 are provided, it is preferable that an insulating layer functioning as a dielectric of each of the capacitance elements CP_1, CP_2, CPd_1, and CPd_2 be provided between the conductive layer WIR and the conductive layer GEM.

[0431] As shown in FIG. 13, the capacitance element CP_1 is preferably provided in a part of the region where the conductive layer GEM extends as the wiring XCL_1. Similarly, as shown in FIG. 13, the capacitance element CP_2 is preferably provided in a part of the region where the conductive layer GEM extends as the wiring XCL_2. In this way, by using a part of the extending wiring as one of a pair of electrodes of the capacitance element and providing the other of the pair of electrodes of the capacitance element above it, it is possible to easily ensure an area for providing the capacitance element and reduce the circuit area of ​​the processing cell IM. The same applies to the capacitance elements CPd_1 and CPd_2 of the driving cell IMd, and this also reduces the circuit area of ​​the driving cell IMd.

[0432] Furthermore, in order to increase the capacitance of the region of the wiring XCL_1 where the capacitor CP_1 is provided, the width of the region may be made longer than the width of the region of the wiring XCL_1 where the capacitor CP_1 is not provided. Increasing the capacitance of the capacitor CP_1 in this manner can increase the retention time of the potential of the node N_1 shown in FIG. 1 . Similarly, for the capacitor CP_2, the width of the region of the wiring XCL_2 where the capacitor CP_2 is provided can be made longer than the width of the region of the wiring XCL_2 where the capacitor CP_2 is not provided, thereby increasing the capacitance of the capacitor CP_2. Increasing the capacitance of the capacitor CP_2 in this manner can increase the retention time of the potential of the node N_2 shown in FIG. 1 . The same applies to the capacitors CPd_1 and CPd_2 of the driving cell IMd, thereby increasing the capacitance of one or both of the capacitors CPd_1 and CPd_2.

[0433] 13 , the width d1 of the conductive layer WIR, which functions as the other of the pair of electrodes of the capacitance element CP_1, is shorter than the width d2 of the conductive layer GEM, which functions as one of the pair of electrodes of the capacitance element CP_1. When an insulating layer functioning as a dielectric is formed on the conductive layer GEM, the insulating layer may be poorly formed at the edge of the conductive layer GEM or in its surrounding area. Specifically, the insulating layer formed at the edge of the conductive layer GEM or in its surrounding area may have poor coverage. In this case, if the width d1 of the conductive layer WIR is longer than the width d2 of the conductive layer GEM, the edge of the conductive layer GEM or its surrounding area may come into contact with the area of ​​the conductive layer WIR that overlaps it, causing a short circuit. Furthermore, even if the width d1 of the conductive layer WIR is longer than the width d2 of the conductive layer GEM and the edge of the conductive layer GEM or the region around it does not come into contact with the region of the conductive layer WIR that overlaps it, the electric field from the conductive layer WIR will be concentrated locally at the end of the conductive layer GEM, causing dielectric breakdown in the insulating layer and possibly degrading the retention characteristics at the node N_1. For this reason, it is preferable that the width d1 of the conductive layer WIR be shorter than the width d2 of the conductive layer GEM.

[0434] Conversely, if a material that is resistant to dielectric breakdown can be used for the insulating layer and the insulating layer formed on the edge of the conductive layer GEM or its surrounding area can be highly coated, it is preferable to make the width d1 longer than the width d2. Specifically, since the capacitance value of a capacitive element is proportional to the area of ​​the region where one of the pair of electrodes, the dielectric, and the other of the pair of electrodes overlap, it is preferable to increase the area of ​​that region if a high capacitance value is desired. Therefore, by making the width d1 longer than the width d2, the width of that region can be increased from d1 to d2. As a result, the conductive layer WIR is formed above the edge of the conductive layer GEM, which increases the area of ​​the other of the pair of electrodes of the capacitive element CP_1, thereby increasing the capacitance value of the capacitive element CP_1 and improving the retention characteristics at the node N_1.

[0435] The same can be said for the capacitive element CP_2, and the same can be said for the capacitive elements CPd_1 and CPd_2 of the driving cell IMd in FIG.

[0436] Furthermore, an opening is provided in the region where a portion of the conductive layer SDM overlaps a portion of the conductive layer WIR, and a conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer SDM and a portion of the conductive layer WIR via the conductive layer PLG. Similarly, an opening is provided in the region where a portion of the conductive layer GEM overlaps a portion of the conductive layer WIR, and another conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer GEM and a portion of the conductive layer WIR via the conductive layer PLG.

[0437] 1, because the transistors M1 and M1_2 are connected in series, the transistors M1_1 and M1_2 can be formed to share the island-shaped semiconductor layer SMC, as shown in the schematic plan view of the processing cell IM in FIG. 13. Similarly, because the transistors M2_1 and M2_2 are connected in series, the transistors M2_1 and M2_2 can be formed to share the island-shaped semiconductor layer SMC, as shown in the schematic plan view of the processing cell IM in FIG. 13. Similarly, because the transistors M3_1 and M3_2 are connected in series, the transistors M3_1 and M3_2 can be formed to share the island-shaped semiconductor layer SMC, as shown in the schematic plan view of the processing cell IM in FIG. 13. This reduces the area in which the transistors of the processing cell IM are formed, thereby increasing the cell density of the processing cell IM and reducing the circuit area of ​​the processing device CDV. 13, the circuit area of ​​the processing cell IM can be reduced by arranging three island-shaped semiconductor layers SMC side by side. The same applies to the plan view of the driving cell IMd in FIG.

[0438] 13 , by arranging three island-shaped semiconductor layers SMC side by side, it becomes easy to provide wirings (back-gate wirings) functioning as back gate electrodes for the transistors M1_1, M1_2, M2_1, M2_2, M3_1, and M3_2 included in the processing cell IM. For example, as shown in FIG. 15 , a conductive layer BGM functioning as the wiring BGL1, which is a back-gate wiring, can be extended below the semiconductor layer SMC including the channel formation regions of the transistors M1_1, M2_1, and M2_2. Similarly, a conductive layer BGM functioning as the wiring BGL2, which is a back-gate wiring, can be extended below the semiconductor layer SMC including the channel formation regions of the transistors M1_2, M3_1, and M3_2. This facilitates routing of the wirings BGL1 and BGL2 and shortens the wiring distance, thereby reducing parasitic resistance and power consumption.

[0439] Note that the schematic plan views of the arithmetic circuit of one embodiment of the present invention are not limited to those shown in FIGS. 13 and 14 . The schematic plan views of the arithmetic circuit of one embodiment of the present invention may be appropriately modified as shown in FIGS. 13 and 14 . For example, in FIG. 13 , the transistors M1_1 and M1_2 are formed to share an island-shaped semiconductor layer SMC, but each of them can have a separate island-shaped semiconductor layer SMC. Furthermore, for example, in the schematic plan view shown in FIG. 13 , when focusing on the transistors M1_1, M1_2, M2_1, and M3_1, these transistors are connected in series, and therefore these transistors can be formed to share an island-shaped semiconductor layer SMC.

[0440] 13 and 14, the transistors M1_1, M1_2, M2_1, M2_2, M3_1, and M3_2 are illustrated as having approximately the same size (including channel length and channel width), and the transistors M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2 are illustrated as having approximately the same size. However, the transistors M1_1, M1_2, M2_1, M2_2, M3_1, and M3_2 may be different in size, and similarly, the transistors M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2 may be different in size.

[0441] 13, the channel width d3 of each of the transistors M1_1 and M1_2 is preferably shorter than the channel width d5 ​​of each of the transistors M2_1 and M2_2 and the channel width d7 of each of the transistors M3_1 and M3_2. In other words, the channel width of the switching transistor is preferably shorter than the channel width of the amplification transistor. By making d3 shorter than one or both of d5 and d7, the off-state current of each of the transistors M1_1 and M1_2 can be made smaller than that of each of the transistors M2_1, M2_2, M3_1, and M3_2, and therefore the potentials of the nodes N_1 and N_2 of the processing cell IM can be held for a long period of time.

[0442] Specifically, for example, d3 is preferably 0.5 times or more and less than 1 time of d5 or d7, more preferably 0.1 times or more and less than 0.5 times, and even more preferably 0.01 times or more and less than 0.1 times.

[0443] Furthermore, the channel length d4 of each of the transistors M1_1 and M1_2 is preferably longer than the channel length d6 of each of the transistors M2_1 and M2_2 and the channel length d8 of each of the transistors M3_1 and M3_2. In other words, the channel length of the switching transistor is preferably longer than the channel length of the amplification transistor. By making d4 longer than one or both of d6 and d8, the off-state current of each of the transistors M1_1 and M1_2 can be made smaller than that of the transistors M2_1, M2_2, M3_1, and M3_2, and therefore the potentials of the nodes N_1 and N_2 of the processing cell IM can be held for a long period of time.

[0444] Furthermore, the channel length d6 of each of the transistors M2_1 and M2_2 is preferably shorter than the channel length d4 of each of the transistors M1_1 and M1_2. By making d6 shorter than d4, the on-state current of the transistors M2_1 and M2_2 can be made larger than that of the transistors M1_1 and M1_1. Furthermore, the channel length d8 of each of the transistors M3_1 and M3_2 is preferably shorter than the channel length d4 of each of the transistors M1_1 and M1_2. By making d8 shorter than d4, the on-state current of the transistors M3_1 and M3_2 can be made larger than that of the transistors M1_1 and M1_1. In other words, the channel lengths of the amplification transistors (the transistors M2_1, M2_2, M3_1, and M3_2 in the above) are preferably shorter than the channel lengths of the switching transistors (the transistors M1_1 and M1_2 in the above).

[0445] Specifically, for example, d4 is preferably greater than 1 time and less than 2 times the value of d6 or d8, more preferably greater than 2 times and less than 10 times the value, and even more preferably greater than 10 times and less than 100 times the value of d6 or d8.

[0446] Since the transistors M3_1 and M3_2 function as clamp transistors, the channel length d8 of each of the transistors M3_1 and M3_2 is preferably longer than the channel length d6 of each of the transistors M2_1 and M2_2. By making d8 longer than d6, DIBL in the transistors M2_1 and M2_2 can be prevented. DIBL in the transistors M2_1 and M2_2 can be prevented even if d8 is equal to or shorter than d6. To prevent a decrease in the amount of current flowing between the source and drain of the transistors M3_1 and M3_2, the channel width d7 of each of the transistors M3_1 and M3_2 is preferably longer than the channel width d5 ​​of the transistors M2_1 and M2_2. Even if d7 is equal to or shorter than d5, a decrease in the amount of current flowing between the source and drain of the transistors M2_1 and M2_2 can be prevented.

[0447] Specifically, for example, d8 is preferably greater than 1 time but not greater than 2 times d6, more preferably greater than 2 times but not greater than 10 times, and even more preferably greater than 10 times but not greater than 100 times. Also, for example, d7 is preferably greater than 1 time but not greater than 2 times d5, more preferably greater than 2 times but not greater than 10 times, and even more preferably greater than 10 times but not greater than 100 times.

[0448] Each of the channel widths d3, d5, and d7 is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0449] Furthermore, each of the channel lengths d4, d6, and d8 is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0450] The same applies to the transistors M1d_1, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2 of the driving cell IMd.

[0451] Furthermore, two or more selected from the transistor M1_1, the transistor M1_2, the transistor M1d_1, and the transistor M1d_2 preferably have approximately the same channel length and / or channel width. Specifically, the ratio of the number of transistors selected from the transistors M1_1, M1_2, M1d_1, and M1d_2 to the number of transistors selected from the remaining transistors is preferably 0.85 to 1.15. For example, when the channel width of the transistor M1_1 is d, the channel width of one or more selected from the transistors M1_2, M1d_1, and M1d_2 is preferably 0.85d to 1.15d. Similarly, when the channel length of the transistor M1_2 is d, the channel length of one or more selected from the transistors M1_1, M1d_1, and M1d_2 is preferably 0.85d to 1.15d.

[0452] Similarly, two or more selected from transistors M2_1, M2_2, M2d_1, and M2d_2 preferably have approximately the same channel length and / or channel width. Specifically, the ratio of the number of transistors selected from transistors M2_1, M2_2, M2d_1, and M2d_2 to the number of remaining transistors is preferably 0.85 to 1.15. Similarly, two or more selected from transistors M3_1, M3_2, M3d_1, and M3d_2 preferably have approximately the same channel length and / or channel width. Specifically, the ratio of the number of transistors selected from transistors M3_1, M3_2, M3d_1, and M3d_2 to the number of remaining transistors is preferably 0.85 to 1.15.

[0453] In addition, in the plan view schematic diagrams of Figures 13 and 14, each of the capacitance elements CP_1, CP_2, CPd_1, and CPd_2 is a flat-plate type capacitance element, but they can be changed to capacitance elements in which a pair of electrodes and a dielectric are embedded in an opening in an insulating layer, as shown in the cross-sectional view schematic diagrams of Figures 21 and 24A described later.

[0454] 13 and 14, the wirings XCL_1, XCL_2, WSL, and VE2 are respectively provided below the wirings WCL_1, WCL_2, and VE1, but the vertical relationship of the wirings is not particularly limited. For example, one or more selected from the wirings XCL_1, XCL_2, WSL, and VE2 can be provided above the wirings WCL_1, WCL_2, and VE1, respectively. Furthermore, the selected one or more of the above-described wirings can be provided in a direction perpendicular or approximately perpendicular to the drawing, rather than in the planar direction of the drawing. For example, in FIG. 13 or 14, the above-described wirings can be formed using a conductive layer that can be formed in a vertical or approximately vertical direction, such as a plug.

[0455] 1 includes one arithmetic circuit CC, but the number of arithmetic circuits CC may be two or more. Also, the arithmetic circuit CC includes one arithmetic cell IM, but the number of arithmetic cells IM may be two or more.

[0456] The arithmetic device CDVA shown in Figure 16 is a modified example of the arithmetic device CDV of Figure 1, and differs from the arithmetic device CDV of Figure 1 in that it has a cell array CA in which multiple arithmetic circuits CC, each including multiple arithmetic cells IM, are arranged in the column direction.

[0457] 16, the cell array CA has arithmetic circuits CC[1] to CC[m] (where m is an integer equal to or greater than 1). Each of the arithmetic circuits CC[1] to CC[m] has one driving cell IMd and n (where n is an integer equal to or greater than 1) processing cells IM. As described above, in the cell array CA, m driving cells IMd are arranged in the column direction, and the processing cells IM are arranged in an m x n matrix.

[0458] 16, when only the calculation cells IM of the cell array CA are focused on, [i, j] is added to the symbol of the calculation cell IM located at the address of row i and column j (where i is an integer between 1 and m, and j is an integer between 1 and n). Furthermore, calculation cells IM[1,1] to IM[m,n] have the same circuit configuration as the calculation cell IM shown in FIG. 1, and the description of the calculation cell IM in FIG. 1 can be referred to for the circuit configuration of each of calculation cells IM[1,1] to IM[m,n].

[0459] 16, when only the driver cells IMd of the cell array CA are focused on, the driver cell IMd located at the address of the i-th row is designated by an [i]. Driver cells IMd[1] to IMd[m] have the same circuit configuration as the driver cell IMd shown in FIG. 1, and the description of the driver cell IMd in FIG. 1 can be referred to for the circuit configuration of each of driver cells IMd[1] to IMd[m].

[0460] 16 includes circuits WCDa[1] to WCDa[n] corresponding to the circuit WCDa in FIG. 1 and switches SA[1] to SA[n] corresponding to the switch SA in FIG. 1.

[0461] 1. The driver circuit XCD in the arithmetic device CDVA in FIG. 16 includes circuits XCDa[1] to XCDa[m] corresponding to the circuit XCDa in FIG.

[0462] 16 corresponds to the drive circuit WSD in Fig. 1. Therefore, the drive circuit WSD can transmit a selection signal to each of the processing cells IM and the drive cells IMd arranged in one row selected from the first to m-th rows of the cell array CA, and transmit a non-selection signal to each of the processing cells IM and the drive cells IMd arranged in the remaining rows.

[0463] 16 includes circuits ITSa_1[1] to ITSa_1[n] corresponding to the circuit ITSa_1 in FIG. 1, circuits ITSa_2[1] to ITSa_2[n] corresponding to the circuit ITSa_2 in FIG. 1, switches SB_1[1] to SB_1[n] corresponding to the switch SB_1 in FIG. 1, and switches SB_2[1] to SB_2[n] corresponding to the switch SB_2 in FIG. 1.

[0464] 16 correspond to the wiring WCL_1 in FIG. 1 and extend in the column direction of the cell array CA. Also, the wirings WCL_2[1] to WCL_2[n] in FIG. 16 correspond to the wiring WCL_2 in FIG. 1 and extend in the column direction of the cell array CA. Also, the wirings IWL[1] to IWL[n] in FIG. 16 correspond to the wiring IWL in FIG. 1. Also, the wirings OL_1[1] to OL_1[n] in FIG. 16 correspond to the wiring OL_1 in FIG. 1. Also, the wirings OL_2[1] to OL_2[n] in FIG. 16 correspond to the wiring OL_2 in FIG. 1.

[0465] The wiring IWL[j] is connected to the input terminal of the circuit WCDa[j], the output terminal of the circuit WCDa[j] is connected to the first terminal of the switch SA[j], and the second terminal of the switch SA[j] is connected to the wiring WCL_1[j]. The wiring WCL_1[j] is connected to each of the calculation cells IM[1,j] to IM[m,j] arranged in the jth column of the cell array CA and the first terminal of the switch SB_1[j]. The second terminal of the switch SB_1[j] is connected to the input terminal of the circuit ITSa_1[j], and the output terminal of the circuit ITSa_1[j] is connected to the wiring OL_1[j]. The wiring WCL_2[j] is connected to each of the calculation cells IM[1,j] to IM[m,j] arranged in the jth column of the cell array CA and the first terminal of the switch SB_2[j]. The second terminal of the switch SB_2[j] is connected to the input terminal of the circuit ITSa_2[j], the output terminal of the circuit ITSa_2[j] is connected to the wiring OL_2[j], the control terminal of the switch SA[j] is connected to the wiring SWLA, and the control terminals of the switch SB_1[j] and the switch SB_2[j] are connected to the wiring SWLB.

[0466] 16 correspond to the wiring XCL_1 in FIG. 1 and extend in the row direction of the cell array CA. Also, the wirings XCL_2[1] to XCL_2[m] in FIG. 16 correspond to the wiring XCL_2 in FIG. 1 and extend in the row direction of the cell array CA. Also, the wirings IXL_1[1] to IXL_1[m] in FIG. 16 correspond to the wiring IXL_1 in FIG. 1. Also, the wirings IXL_2[1] to IXL_2[m] in FIG. 16 correspond to the wiring IXL_2 in FIG. 1. Also, the wirings WSL[1] to WSL[m] in FIG. 16 correspond to the wiring WSL in FIG. 1 and extend in the row direction of the cell array CA.

[0467] The wiring IXL_1[i] is connected to the input terminal of the circuit XCDa_1[i], and the output terminal of the circuit XCDa_1[i] is connected to the wiring XCL_1[i]. The wiring XCL_1[i] is connected to the driver cell IMd[i] arranged in the i-th row of the cell array CA and each of the calculation cells IM[i,1] to IM[i,n]. The wiring IXL_2[i] is connected to the input terminal of the circuit XCDa_2[i], and the output terminal of the circuit XCDa_2[i] is connected to the wiring XCL_2[i]. The wiring XCL_2[i] is connected to the driver cell IMd[i] arranged in the i-th row of the cell array CA and each of the calculation cells IM[i,1] to IM[i,n].

[0468] For the connection configuration between the driving cell IMd[i] and the surrounding wiring, refer to the description of FIG. 1. For example, in the driving cell IMd[i], the gates of the transistors M1d_1 and M1d_2 are connected to the wiring WSL[i]. The second terminals of the capacitors CPd_1, M1d_2, and M3d_1 are connected to the wiring XCL_1[i]. The second terminals of the capacitors CPd_2 and M3d_2 are connected to the wiring XCL_2[i].

[0469] For the connection configuration between the arithmetic cell IM[i,j] and the surrounding wiring, refer to the description of FIG. 1 . For example, in the arithmetic cell IM[i,j], the gates of the transistors M1_1 and M1_2 are connected to the wiring WSL[i]. The second terminal of the capacitor CP_1 is connected to the wiring XCL_1[i]. The second terminal of the capacitor CP_2 is connected to the wiring XCL_2[i]. The second terminal of the transistor M1_2 and the second terminal of the transistor M3_1 are connected to the wiring WCL_1[j]. The second terminal of the transistor M3_2 is connected to the wiring WCL_2[j].

[0470] Next, the writing of the first data to the arithmetic unit CDVA in FIG. 16 and the multiplication of the first data and the second data will be described.

[0471] 16 , when first data is written to each of the computation cells IM[i,1] to IM[i,n], a current corresponding to the reference data r[i] flows from each of the circuit XCDa_1[i] and the circuit XCDa_2[i] to the driving cell IMd[i]. Note that the above description focuses on the i-th row of the cell array CA, and, for example, currents corresponding to the reference data r[1] to r[m] can be simultaneously and separately passed from the circuits XCDa_1[1] to XCDa_1[m] and the circuits XCDa_2[1] to XCDa_2[m] to the driving cells IMd[1] to IMd[m], respectively.

[0472] During this time, w[1,1] to w[m,n] are written separately as first data into the arithmetic cells IM[1,1] to IM[m,n], respectively. Specifically, for example, currents corresponding to w[1,j] to w[m,j] generated by the circuit WCDa[j] flow sequentially into the arithmetic cells IM[1,j] to IM[m,j] arranged in the jth column, respectively. Note that the description of the arithmetic device CDV in FIG. 1 can be referred to for the write operation.

[0473] After w[1,1] to w[m,n] are written as first data to the calculation cells IM[1,1] to IM[m,n], respectively, the circuits XCDa_1[1] to XCDa_1[m] write second data x １ [1] to x １ [m] to the driver cells IMd and the calculation cells IM of each row, and the circuits XCDa_2[1] to XCDa_2[m] transmit the second data x ２ [1] to x ２ By transmitting the first data w and the second data x to the driving cells IMd and the calculation cells IM[m,n] of each row, the first data w and the second data x to be transmitted are transmitted to the calculation cells IM[1,1] to IM[m,n]. １ and multiplying the first data w and the second data x to be transmitted. ２ For example, in the calculation cell IM[i,j], w[i,j] and x １Multiplication of [i] and w[i,j] and x ２ [i] are multiplied, respectively.

[0474] In the j-th column of the cell array CA, the wiring WCL_1[j] is connected to the w×x １ Specifically, the current flowing through the wiring WCL_1[j] is expressed as I Ｓ１ When [j] is set, I Ｓ１ Similarly, in the j-th column of the cell array CA, the wiring WCL_2[j] is connected to the calculation cells IM[1,j] to IM[m,j], respectively, with w×x ２ Specifically, the current flowing through the wiring WCL_2[j] is I Ｓ２ When [j] is set, I Ｓ２ [j] can be expressed as in equation (1.16) below.

[0475]

[0476] Therefore, the amount of current flowing through the wiring WCL_1[j] is I Ｓ１ [j] flows into the circuit ITSa_1[j], and the circuit ITSa_1[j] Ｓ１ The value z of the function according to [j] １ Calculate [j] and get z １ [j] is output to the wiring OL_1[j]. Similarly, the amount of current I Ｓ２ [j] flows into the circuit ITSa_2[j], and the circuit ITSa_2[j] Ｓ２ The value z of the function according to [j] ２ Calculate [j] and get z ２ [j] is output to wiring OL_2[j].

[0477] This means that z １ [j] can be expressed as the following equation (1.17) using the above equation (1.15). ２ [j] can be expressed as the following equation (1.18) using the above equation (1.16).

[0478]

[0479] In this way, by arranging the processing cells IM in an m×n matrix, the first data w[1,j] to w[m,j] and the second data x １ [1] to x １ 16 is arranged in n columns, it is possible to simultaneously perform n product-sum operations and calculate functions by substituting the results of those operations as variables.

[0480] Also, z １ [j] is output to the outside via wiring OL_1[j]. ２ [j] is output to the outside via wiring OL_2[j].

[0481] In particular, the arithmetic unit CDVA is suitable for performing calculations on a neural network in a fully connected layer. For example, by storing a weight coefficient as first data in each arithmetic cell IM of the cell array CA of the arithmetic unit CDVA and inputting the value of an input signal of a neuron as second data to the wiring XCL_1, a multiplication and accumulation operation can be performed on the weight coefficient w and the input signal of the neuron. Furthermore, by using the circuit ITSa_1[j] and the circuit ITSa_2[j] as calculation circuits for an activation function applied to the neural network in the fully connected layer, the value of the activation function can be output using the result of the multiplication and accumulation operation as an input value. This value can then be input to the next hidden layer, output layer, etc.

[0482] The arithmetic unit CDVA can also suitably perform calculations of a convolutional neural network. In particular, since the arithmetic cell IM of the cell array CA of the arithmetic unit CDVA can hold the first data for a long period of time, it is preferable to use the first data as a filter value used in the convolution process. In the convolution process of the convolutional neural network, the same filter value is multiplied by multiple image data, so it can be said that the arithmetic cell IM of the arithmetic unit CDVA is suitable as a multiplication cell that can hold a filter value for a long period of time.

[0483] Furthermore, the calculation unit CDVA stores w[1,1] to w[m,n] as filter values ​​in the calculation cells IM[1,1] to IM[m,n], respectively, and calculates x １ [1] to x １ [m] and x ２ [1] to x ２ By inputting [m] and [m] to the cell array CA, it is possible to simultaneously perform convolution processing of two pieces of data for one filter. In this way, the arithmetic unit CDVA can multiply the same filter value by multiple pieces of image data, so it can be said that the arithmetic unit CDVA is suitable as a device for performing convolution processing of a convolutional neural network.

[0484] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0485] Embodiment Mode 2 In this embodiment mode, a configuration example of the arithmetic device described in the above embodiment mode will be described.

[0486] Fig. 17 is a perspective view schematically illustrating the calculation device CDV described in the above embodiment. The calculation device CDVS shown in Fig. 17 has, as an example, a circuit layer PHRL and an arithmetic layer OMAL. The circuit layer PHRL is located below the arithmetic layer OMAL.

[0487] FIG. 18 is a block diagram showing an example of the configuration of the circuit layer PHRL and the arithmetic layer OMAL shown in FIG.

[0488] 18, the circuit layer PHRL includes, for example, the drive circuits WCD, XCD, ITS, and WSD described in the above embodiments, and the operation layer OMAL includes, for example, the cell array CA described in the above embodiments.

[0489] Note that one or more selected from the driving circuits WCD, XCD, ITS, and WSD described in the above embodiments may be included in the arithmetic layer OMAL.

[0490] The circuit layer PHRL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of usable substrates include an SOI (silicon-on-insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, lamination films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper. If the manufacturing process of the computing device CDV includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0491] In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate having silicon.

[0492] By using a semiconductor substrate made of silicon as the substrate included in the circuit layer PHRL, the transistors included in each of the drive circuits WCD, XCD, ITS, and WSD can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Si transistors have high field-effect mobility and can therefore pass large on-state currents. This makes it possible to increase the drive speed of each of the drive circuits listed above and widen the signal range.

[0493] The stacked structure of the circuit layer PHRL and the arithmetic layer OMAL can be fabricated by forming the arithmetic layer OMAL directly on top of the circuit layer PHRL, or by mounting the arithmetic layer OMAL on top of the circuit layer PHRL as a structure in which circuit elements such as transistors and capacitive elements are provided on a substrate.

[0494] When the arithmetic layer OMAL is formed directly on the circuit layer PHRL, the arithmetic layer OMAL preferably includes an OS transistor. Since OS transistors can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, or even on a conductive film, an insulating film, or a semiconductor film, they can be easily provided on a semiconductor substrate (on the circuit layer PHRL) on which Si transistors are formed.

[0495] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the arithmetic layer OMAL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer PHRL side, a second bonding layer may be provided on the substrate of the arithmetic layer OMAL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the arithmetic layer OMAL on the circuit layer PHRL. In particular, bonding in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and the copper is bonded to each other is called Cu-Cu (copper-copper) direct bonding.

[0496] <Cross-sectional configuration example 1 of arithmetic device> Next, a specific configuration example of the arithmetic device CDVS shown in Fig. 17 and Fig. 18 will be described. Fig. 19 is a schematic cross-sectional view of one example of the arithmetic device CDVS shown in Fig. 17 and Fig. 18.

[0497] Fig. 19 shows a schematic cross-sectional view of the circuit layer PHRL and the arithmetic layer OMAL. Note that the arithmetic device CDV in Fig. 19 shows a configuration in which the arithmetic layer OMAL is formed directly on the circuit layer PHRL.

[0498] 19 illustrates a transistor 100 included in the circuit layer PHRL. The transistor 100 is provided over a substrate 101 and includes a conductive layer 131 functioning as a gate, an insulating layer 161 and an insulating layer 111 functioning as gate insulating films, a semiconductor region 171 including part of the substrate 101, and low-resistance regions 172a and 172b functioning as source and drain regions including part of the substrate. The transistor 100 can be a p-channel transistor or an n-channel transistor. The substrate 101 can be, for example, a single crystal silicon substrate.

[0499] 19 is formed by providing an element isolation layer 102 in a substrate 101. The element isolation layer 102 can also be said to be provided to isolate a plurality of transistors formed on the substrate 101. The element isolation layer can be formed by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0500] Here, in the transistor 100 shown in FIG. 19 , a semiconductor region 171 (a part of the substrate 101) where a channel is formed has a convex shape. A conductive layer 131 is provided to cover the side and top surfaces of the semiconductor region 171 with an insulating layer 161 interposed therebetween. Note that the conductive layer 131 may be made of a material that adjusts the work function. Such a transistor 100 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0501] Note that the transistor 100 illustrated in FIG. 19 is just an example, and the structure is not limited to this example. It is preferable to use an appropriate transistor depending on the circuit configuration or driving method.

[0502] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0503] For example, an insulating layer 112, an insulating layer 181, and an insulating layer 113 are stacked in this order as an interlayer film over the transistor 100. A conductive layer 132 and the like are embedded in the insulating layer 112. A conductive layer 133 and the like are embedded in the insulating layer 181 and the insulating layer 113. The conductive layer 132 and the conductive layer 133 function as contact plugs or wirings.

[0504] The insulating layer serving as an interlayer film may also serve as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 112 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0505] Wiring layers may be provided over the insulating layer 113 and the conductive layer 133. For example, in FIG. 19 , an insulating layer 182, an insulating layer 114, an insulating layer 115, and an insulating layer 116 are stacked in this order over the insulating layer 113 and the conductive layer 133. A conductive layer 134 is formed in the insulating layer 182, the insulating layer 114, and the insulating layer 115. The conductive layer 134 functions as a contact plug or a wiring.

[0506] An insulating layer 116 is provided on the insulating layer 115 and the conductive layer 134. It is preferable that contact plugs or wiring are embedded in the insulating layer 116 to connect to an upper circuit (for example, a circuit included in the circuit included in the arithmetic layer OMAL).

[0507] 19 also illustrates some of the operation cells included in the operation layer OMAL. Specifically, FIG. 19 illustrates the transistors M1_1, M1_2, M2_1, M2_2, capacitors CP_1, and CP_2 included in the operation cell IM of the operation circuit CC shown in FIG.

[0508] 19 , the transistors M2_1 and M2_2 are formed on an insulating layer 183. The transistors M1_1 and M1_2 are formed on an insulating layer 184. The capacitors CP_1 and CP_2 are formed on an insulating layer 185. The insulating layer 184 is located above the insulating layer 183, and the insulating layer 185 is located above the insulating layer 184. Therefore, the capacitors CP_1 and CP_2 are located above the transistors M1_1 and M1_2, and the transistors M1_1 and M1_2 are located above the transistors M2_1 and M2_2.

[0509] Note that each of the insulating layers 183 to 185 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layers 183 to 185 can prevent the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be applied to each of the insulating layers 183 to 185, the description of the insulating layers in the section on constituent materials of transistors can be referred to.

[0510] A conductive layer functioning as a wiring VE2 is connected to one of the source electrode or drain electrode of the transistor M2_1 through a conductive layer 234_1 functioning as a plug. Similarly, a conductive layer functioning as a wiring VE2 is connected to one of the source electrode or drain electrode of the transistor M2_2 through a conductive layer 234_2 functioning as a plug. Although not shown, the other of the source electrode or drain electrode of the transistor M2_1 may be connected to the source electrode or drain electrode of the transistor M3_1. Similarly, the other of the source electrode or drain electrode of the transistor M2_2 may be connected to the source electrode or drain electrode of the transistor M3_2.

[0511] The conductive layers 234_1 and 234_2 can be the conductive layers 234a and 234b described later. For this reason, the conductive layers 234_1 and 234_2 can be formed using materials that can be used for the conductive layers 234a and 234b, respectively.

[0512] For example, the wiring VE2 extends in the channel width direction of the transistor M2_1 or the transistor M2_2.

[0513] A conductive layer functioning as one of a pair of electrodes of a capacitor CP_1 is connected to the gate electrode of the transistor M2_1 through a conductive layer 235_1 functioning as a plug. A conductive layer functioning as one of a pair of electrodes of a capacitor CP_2 is connected to the gate electrode of the transistor M2_2 through a conductive layer 235_2 functioning as a plug.

[0514] One of the source electrode or drain electrode of the transistor M1_1 is connected to a conductive layer that functions as one of a pair of electrodes of a capacitor CP_1 through a conductive layer 235_3 that functions as a plug. The other of the source electrode or drain electrode of the transistor M1_1 is connected to a conductive layer that functions as one of a pair of electrodes of a capacitor CP_2 through a conductive layer 235_4 that functions as a plug. The other of the source electrode or drain electrode of the transistor M1_2 is connected to a conductive layer that functions as one of a pair of electrodes of a capacitor CP_2 through a conductive layer 235_4 that functions as a plug. The other of the source electrode or drain electrode of the transistor M1_2 is connected to a conductive layer that functions as a wiring WCL_1 through a conductive layer 235_6 that functions as a plug.

[0515] Similarly to the conductive layers 234_1 and 234_2, the conductive layers 235_1 and 235_6 can be formed using a material that can be applied to the conductive layers 234a and 234b.

[0516] A conductive layer functioning as a wiring WSL is connected to the gate electrodes of the transistors M1_1 and M1_2. The conductive layers serving as the gate electrodes of the transistors M1_1 and M1_2 extend in the channel width direction.

[0517] An insulating layer functioning as an interlayer film is formed between the transistors M2_1 and M2_2 and the transistors M1_1 and M1_2. The insulating layer has openings in regions overlapping with the gate electrodes of the transistors M2_1 and M2_2, and conductive layers serving as plugs are embedded in the openings. Similarly, openings are also formed in regions overlapping with the source or drain electrodes of the transistors M2_1 and M2_2, and conductive layers serving as plugs are embedded in the openings.

[0518] An insulating layer functioning as an interlayer film is formed between the transistors M1_1 and M1_2 and the capacitors CP_1 and CP_2. The insulating layer has openings in regions overlapping with the gate electrodes of the transistors M1_1 and M1_2, and conductive layers serving as plugs are embedded in the openings. Similarly, openings are also formed in regions overlapping with the source or drain electrodes of the transistors M1_1 and M1_2, and conductive layers serving as plugs are embedded in the openings.

[0519] A conductive layer functioning as one of a pair of electrodes of the capacitor CP_1 is formed to be embedded in the insulating layer 117 over the insulating layer 185. Similarly, a conductive layer functioning as one of a pair of electrodes of the capacitor CP_2 is also formed to be embedded in the insulating layer 117.

[0520] A conductive layer functioning as the other electrode of the capacitor CP_1 is provided above one of the pair of electrodes of the capacitor CP_1 and part of the insulating layer 117, with an insulating layer 441_1 functioning as a dielectric therebetween. The conductive layer also functions as the wiring XCL_1.

[0521] Similarly, a conductive layer functioning as the other electrode of the capacitor CP_2 is provided above one of the pair of electrodes of the capacitor CP_2 and another part of the insulating layer 117, with an insulating layer 441_2 functioning as a dielectric therebetween. Note that the conductive layer also functions as the wiring XCL_2.

[0522] Note that for the insulating layer 441_1 and the insulating layer 441_2, the later description of the insulating layer 441 can be referred to. Therefore, a material that can be used for the insulating layer 441 can be used for the insulating layer 441_1 and the insulating layer 441_2.

[0523] By embedding the conductive layer that functions as one of the pair of electrodes of the capacitor CP_1 in the insulating layer 117, the conductive layer that functions as one of the pair of electrodes of the capacitor CP_1 and the insulating layer 117 can be planarized to be flush with each other. This allows the insulating layer 441_1 and the conductive layer that functions as the other of the pair of electrodes of the capacitor CP_1 to be formed with good flatness on the top surfaces of the conductive layer that functions as one of the pair of electrodes of the capacitor CP_1 and the insulating layer 117, which have good flatness. By improving the flatness of both the pair of electrodes of the capacitor CP_1 and the insulating layer 441_1, localized concentration of an electric field can be suppressed, and as a result, leakage current between the pair of electrodes of the capacitor CP_1 can be prevented. Furthermore, one of the pair of electrodes of the capacitor CP_1 (here, the lower electrode) has a smaller area than the other of the pair of electrodes of the capacitor CP_1 (here, the upper electrode). This configuration makes it possible to suppress local electric field concentration that may occur in the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitor CP_1, thereby realizing a highly reliable semiconductor device. Note that the same applies to the capacitor CP_2.

[0524] For example, in the computation cell IM in FIG. 1 , by configuring the capacitor CP_1 as described above, leakage current between the pair of electrodes of the capacitor CP_1, which occurs between the node N_1 and the wiring XCL_2, can be prevented. Therefore, in the computation cell IM, fluctuations in the potential of the node N_1 due to the leakage current can be prevented, and the potential of the node N_1 can be held for a long period of time. Similarly, by configuring the capacitor CP_2 as described above, leakage current between the pair of electrodes of the capacitor CP_2, which occurs between the node N_2 and the wiring XCL_2, can be prevented. Therefore, fluctuations in the potential of the node N_2 due to the leakage current can be prevented in the computation cell IM, and the potential of the node N_2 can be held for a long period of time. Furthermore, local electric field concentration can be suppressed in the insulating layer 441_1, which is the dielectric of the capacitor CP_1, and the insulating layer 441_2, which is the dielectric of the capacitor CP_2, respectively, and therefore the reliability of the computation cell IM can be improved.

[0525] Furthermore, for example, in the driver cell IMd of FIG. 1 , by configuring the capacitor CPd_1 as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitor CPd_1 that occurs between the node Nd_1 and the wiring XCL_1. Therefore, in the driver cell IMd, fluctuations in the potential of the node Nd_1 due to the leakage current can be prevented, and the potential of the node Nd_1 can be maintained for a long period of time. Similarly, by configuring the capacitor CPd_2 as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitor CPd_2 that occurs between the node Nd_2 and the wiring XCL_2. Therefore, in the driver cell IMd, fluctuations in the potential of the node Nd_2 due to the leakage current can be prevented, and the potential of the node Nd_2 can be maintained for a long period of time. Furthermore, local electric field concentration can be suppressed in the dielectrics of the capacitors CPd_1 and CPd_2, thereby improving the reliability of the driver cell IMd. As a result, it is possible to improve the reliability of the calculation circuit CC.

[0526] In addition, in the configuration example of FIG. 19, the conductive layer functioning as the wiring XCL_1 and the conductive layer functioning as the wiring XCL_2 are each extended in the channel width direction of the transistor M1_1, the transistor M1_2, the transistor M2_1, and the transistor M2_2.

[0527] 19, a conductive layer functioning as a back gate may be provided under the island-shaped semiconductor layer of each of the transistors M1_1, M1_2, M2_1, and M2_2. By providing a back gate for each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0528] For example, by providing a back gate to each of the transistors M1_1, M1_2, M2_1, and M2_2, the influence of an external electric field can be reduced and the transistors can be stably maintained in an off state. Therefore, data written to the capacitors CP_1 and CP_2 can be stably held. In this way, providing a back gate stabilizes the operation of the calculation cell IM and can improve the reliability of the calculation layer OMAL including the calculation cell IM.

[0529] As the semiconductor layers in which the channels of the transistors M1_1, M1_2, M2_1, and M2_2 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used as described in Embodiment 1. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0530] Note that the transistors M1_1, M1_2, M2_1, and M2_2 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the arithmetic cell can be reduced. Therefore, the power consumption of the arithmetic device CDVS including the arithmetic cell IM can be reduced.

[0531] 19 can store the first data, and therefore also functions as a memory device. Therefore, the calculation cell or the calculation device CDVS in FIG. 19 can be called an "OS memory."

[0532] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0533] Note that when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid formation of parasitic capacitance with the back gate.

[0534] 19 has been described, the same can be said for the transistors M3_1 and M3_2 included in the calculation cell IM in Fig. 1. The same can be said for the transistors M1d_2, M1d_2, M2d_1, M2d_2, M3d_1, and M3d_2 included in the driving cell IMd in Fig. 1.

[0535] <<Transistor Configuration Example 1>> Next, a specific configuration example of a transistor having a gate last (GL) structure that can be applied to the transistors M1_1, M1_2, M2_1, and M2_2 illustrated in Fig. 19 and the transistors M3_1 and M3_2 not illustrated in Fig. 19 will be described. A transistor 200 illustrated in Fig. 20A and Fig. 20B is an example of a transistor having a GL structure that can be applied to the transistors M1_1, M1_2, M2_1, and M2_2 illustrated in Fig. 19.

[0536] In particular, FIG. 20A shows a schematic cross-sectional view of the transistor 200 in the channel length direction, and FIG. 20B shows a schematic cross-sectional view of the transistor 200 in the channel width direction.

[0537] 20A and 20B , for example, the transistor 200 includes a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, an insulating layer 213, a conductive layer 233, an insulating layer 281, an insulating layer 212, an insulating layer 261, an insulating layer 262, an insulating layer 263, an insulating layer 264, an insulating layer 282, an insulating layer 283, an insulating layer 213, and an insulating layer 214. Note that the transistor 200 does not necessarily include all of the above components. For example, the conductive layer 231 functions as a backgate electrode of the transistor 200, but the transistor 200 may not include the conductive layer 231.

[0538] Materials that can be used for the conductive layer, insulating layer, and semiconductor layer will be described later.

[0539] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are disposed above a substrate (not shown in FIG. 20). In particular, the conductive layer 231 is preferably provided so as to be embedded in the insulating layer 212. Specifically, the conductive layer 231a is preferably provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 212. The conductive layer 231b is preferably provided so as to be embedded in a recess formed in the conductive layer 231a. Note that in the transistor 200 shown in FIGS. 20A and 20B , the height of the top surface of the conductive layer 231b is approximately the same as the height of the top surface of the conductive layer 231a and the height of the top surface of the insulating layer 212.

[0540] The insulating layer 212 functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112. Furthermore, by using a material with a low dielectric constant for the insulating layer 212, the parasitic capacitance between wirings can be reduced.

[0541] For this reason, the insulating layer 212 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 212 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. Alternatively, the insulating layer 212 can be made of, for example, a resin. The material used for the insulating layer 212 may be an appropriate combination of the above-mentioned insulating materials.

[0542] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0543] The semiconductor layer 251 and the conductive layer 233 are disposed in a region overlapping the conductive layer 231. The semiconductor layer 251b is disposed on the semiconductor layer 251a. The conductive layers 232a and 232b are disposed on the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is disposed on the conductive layers 232a and 232b. In particular, an opening is formed in the insulating layer 213 in a region between the conductive layers 232a and 232b. The conductive layer 233 is disposed in the opening. The insulating layer 264 is disposed between the semiconductor layer 251b, the conductive layers 232a and 232b, and the insulating layer 213 and the conductive layer 233. Here, as shown in FIGS. 20A and 20B , it is preferable that the top surface of the conductive layer 233 substantially coincides with the top surfaces of the insulating layer 264 and the insulating layer 213. Note that hereinafter, the conductive layers 231a and 231b may be collectively referred to as conductive layers 231. The semiconductor layers 251a and 251b may be collectively referred to as semiconductor layers 251. The conductive layers 232a and 232b may be collectively referred to as conductive layers 232.

[0544] 20A , a region 171a may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232a and in its vicinity. Similarly, a region 171b may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232b and in its vicinity. In this case, the region 171a functions as one of a source region and a drain region, and the region 171b functions as the other of the source region and the drain region. Therefore, the region 171a can be one of a source electrode and a drain electrode, and the region 171b can be the other of the source electrode and the drain electrode. A channel formation region is formed in a region sandwiched between the region 171a and the region 171b.

[0545] By providing the conductive layer 232a (conductive layer 232b) so as to be in contact with the semiconductor layer 251, the oxygen concentration in the region 171a (region 171b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductive layer 232a (conductive layer 232b) and a component of the semiconductor layer 251 may be formed in the region 171a (region 171b). Furthermore, the region 171a (region 171b) may have a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In such cases, the carrier concentration in the region 171a (region 171b) increases, and the region 171a (region 171b) becomes a low-resistance region. That is, the source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.

[0546] On the other hand, the channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0547] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm−３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0548] Note that when the carrier concentration of the semiconductor layer 251 is reduced, the impurity concentration in the semiconductor layer 251 is reduced to reduce the density of defect states. In this specification, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic. Note that an oxide semiconductor (or a metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or a metal oxide).

[0549] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration of the channel formation region in the semiconductor layer 251. In addition, in order to reduce the impurity concentration of the semiconductor layer 251, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 251 refer to, for example, elements other than the main components constituting the semiconductor layer 251. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0550] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 251. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0551] In a transistor using an oxide semiconductor for the semiconductor layer 251, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0552] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, and the conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0553] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. ＯIt is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being excessively reduced. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 233, the conductive layer 232a, the conductive layer 232b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 233, the conductive layer 232a, the conductive layer 232b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0554] 20A and 20B , the side surfaces of the conductive layers 232a and 232b facing the conductive layer 233 have a substantially perpendicular shape. Note that the transistor 200 shown in FIGS. 20A and 20B is not limited thereto, and the angle formed between the side surface and the bottom surface of the conductive layers 232a and 232b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductive layers 232a and 232b may have a plurality of surfaces.

[0555] Note that the transistor 200 has a structure in which two layers, the semiconductor layer 251a and the semiconductor layer 251b, are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof; however, the present invention is not limited to this. For example, the semiconductor layer 251b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 251a and the semiconductor layer 251b may have a stacked structure of two or more layers.

[0556] The conductive layer 233 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and as described above, the conductive layer 232a and the conductive layer 232b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 233 is formed so as to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layer 232a and the conductive layer 232b. Here, the conductive layer 233, the conductive layer 232a, and the conductive layer 232b are formed in a self-aligned manner with respect to the opening of the insulating layer 213. That is, in the transistor 200, the first gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 233 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor 200. This allows the density of arithmetic cells in the arithmetic device to be increased.

[0557] 20A and 20B , the conductive layer 233 is shown as having a two-layer structure. Here, the conductive layer 233 preferably includes a conductive layer 233a and a conductive layer 233b disposed on the conductive layer 233a. For example, the conductive layer 233a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 233a.

[0558] The conductive layer 233a is preferably made of a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen.

[0559] Furthermore, since the conductive layer 233a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 233b caused by oxygen contained in the insulating layer 213, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0560] The conductive layer 233b is preferably a conductive layer with high conductivity. For example, the conductive layer 233b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 233b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0561] For the conductive layers 232a and 232b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 232a and 232b. When a conductive material containing metal and nitrogen is used for the conductive layers 232a and 232b, the conductive layers 232a and 232b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 233a and 233b described above.

[0562] For example, the conductive layers 234a and 234b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0563] For example, the conductive layer 234 a and the conductive layer 234 b can have a stacked structure including a plurality of layers. In particular, it is preferable to stack a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and a material with high conductivity.

[0564] The conductive layer 231 may function as a second gate electrode (also referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 231 may be changed independently of the potential applied to the conductive layer 233, thereby reducing the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 231, the V ｔｈTherefore, when a negative potential is applied to the conductive layer 231, the drain current when the potential applied to the conductive layer 233 is 0 V can be made smaller than when no negative potential is applied.

[0565] The conductive layer 231 is preferably provided to be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Fig. 20B, the conductive layer 231 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 251. That is, outside the side surface of the semiconductor layer 251 in the channel width direction, the conductive layer 231 and the conductive layer 233 preferably overlap with each other with an insulating layer interposed therebetween.

[0566] 20A , the conductive layer 233 preferably includes a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although the conductive layer 233 is shown as having a two-layer stacked structure in FIGS. 20A and 20B , the present invention is not limited to this. For example, the conductive layer 233 may have a single-layer structure or a stacked structure of three or more layers.

[0567] 20A and 20B , the transistor 200 preferably includes an insulating layer 211 disposed on a substrate (not shown in FIG. 20 ), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. A semiconductor layer 251 a is preferably disposed on the insulating layer 263.

[0568] 20A and 20B, an insulating layer 282 is preferably disposed between the insulating layer 262, the insulating layer 263, the semiconductor layer 251a, the semiconductor layer 251b, the conductive layer 232a, the conductive layer 232b, and the insulating layer 213. Here, the insulating layer 282 is preferably in contact with the side surface of the insulating layer 264, the top and side surfaces of the conductive layer 232a, the top and side surfaces of the conductive layer 232b, the side surfaces and top surfaces of the semiconductor layer 251a, the semiconductor layer 251b, and the insulating layer 263, and the top surface of the insulating layer 262, as shown in FIG.

[0569] An insulating layer 283 and an insulating layer 214 which function as interlayer films are preferably provided over the transistor 200. Here, the insulating layer 283 is preferably provided in contact with top surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, the top surface of the insulating layer 213 is preferably planarized.

[0570] It is preferable to provide a conductive layer 234 (conductive layer 234a and conductive layer 234b) that is connected to the transistor 200 and functions as a plug. For this reason, the conductive layer 234 is provided in contact with the inner walls of the openings of the insulating layer 282, the insulating layer 213, the insulating layer 283, and the insulating layer 214. In particular, a first conductive layer of the conductive layer 234 may be provided in contact with the inner walls, and a second conductive layer of the conductive layer 234 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 234 can be made approximately the same as the height of the top surface of the insulating layer 214.

[0571] Specifically, for example, a first conductive layer of the conductive layer 234a is provided in contact with one of the inner walls of two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 234a is formed in contact with the side surface thereof. Note that the conductive layer 232a is located in part of the bottom of the opening, and the conductive layer 234a is in contact with the conductive layer 232a. Similarly, for example, a first conductive layer of the conductive layer 234b is provided in contact with the other inner wall of the two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 234b is formed in contact with the side surface thereof. Note that the conductive layer 232b is located in part of the bottom of the opening, and the conductive layer 234b is in contact with the conductive layer 232b.

[0572] Note that although the transistor 200 shows a structure in which the first conductive layer of the conductive layer 234 and the second conductive layer of the conductive layer 234 are stacked, one embodiment of the present invention is not limited to this. For example, the conductive layer 234 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0573] 20B , in a region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is arranged to be covered with the conductive layer 233. This makes it easier for the electric field of the conductive layer 233, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. This increases the on-state current of the transistor 200 and improves its frequency characteristics.

[0574] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 213 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0575] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0576] The upper surfaces of the insulating layers 213 may be planarized, so that the insulating layers 213 also function as planarizing films.

[0577] As described above, the insulating layer 213 can be formed using a material similar to that of the insulating layer 212 .

[0578] <<Constituent Materials of Transistor>> Next, the materials that constitute the transistor 200 will be described.

[0579] [Metal Oxide (Oxide Semiconductor)] The transistor 200 preferably includes a metal oxide that functions as an oxide semiconductor, including a channel formation region. For example, the band gap is preferably larger than the band gap of silicon (typically 1.1 eV). For example, the band gap of the metal oxide that forms the channel formation region is preferably 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more. Specifically, for example, in the case of the transistor 200 in FIGS. 20A and 20B , the semiconductor layer 251 preferably includes a metal oxide that functions as an oxide semiconductor.

[0580] Note that metal oxide structures are divided into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures can be used. However, use of a crystalline metal oxide, such as a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0581] The metal oxide can be an oxide semiconductor having an axial growth CAAC (AG CAAC) structure. The AG CAAC refers to an oxide semiconductor having a CAAC structure, which is produced by solid-phase growth of a metal oxide contained in an oxide semiconductor layer including a first layer and a second layer having higher crystallinity than the first layer, using the second layer as a nucleus or seed.

[0582] For example, the first layer is preferably formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Examples of CVD include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The first layer may also be formed by a wet process. Furthermore, molecular beam epitaxy (MBE), which is a film formation method for growing a thin film having a crystalline structure that reflects the crystalline system of the substrate, may also be used. These film formation methods can reduce damage to the surface to be formed compared to sputtering.

[0583] Next, the second layer is preferably formed by sputtering or pulsed laser deposition (PLD). By forming the second layer after the first layer, in particular, it is possible to prevent a mixed layer from being formed at the interface between the first and second layers. Furthermore, it is possible to prevent impurities contained in the surface on which the second layer is formed from being mixed into the second layer. These factors further enhance the crystallinity of the second layer.

[0584] Examples of methods for solid-phase growth of the metal oxide contained in the first layer using the second layer as a nucleus or seed include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0585] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0586] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering can be used, respectively. In particular, forming the first oxide semiconductor layer by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated ...

Claims

A first cell and a second cell, the first cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitance element, and a second capacitance element; the second cell includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third capacitive element, and a fourth capacitive element; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor and the first terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the second transistor, the gate of the fifth transistor, and a first terminal of the second capacitive element; one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; the other of the source or the drain of the second transistor and the other of the source or the drain of the fourth transistor are electrically connected to a first wiring; the other of the source and the drain of the sixth transistor is electrically connected to a second wiring; one of the source and the drain of the seventh transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitive element; the other of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the eighth transistor, the gate of the eleventh transistor, and a first terminal of the fourth capacitive element; one of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor; one of the source and the drain of the eleventh transistor is electrically connected to one of the source and the drain of the twelfth transistor; the other of the source or the drain of the eighth transistor, the other of the source or the drain of the tenth transistor, a second terminal of the first capacitance element, and a second terminal of the third capacitance element are each electrically connected to a third wiring; the other of the source and the drain of the twelfth transistor, the second terminal of the second capacitance element, and the second terminal of the fourth capacitance element are electrically connected to a fourth wiring; a gate of the first transistor, a gate of the second transistor, a gate of the seventh transistor, and a gate of the eighth transistor are electrically connected to a fifth wiring; Semiconductor device. 　 In claim 1, a channel length of one selected from the first transistor, the second transistor, the seventh transistor, and the eighth transistor is longer than a channel length of each of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor; a channel width of one selected from the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is longer than a channel width of each of the first transistor, the second transistor, the seventh transistor, and the eighth transistor; Semiconductor device. 　 A first cell and a second cell, the first cell includes a first transistor, a second transistor, a third transistor, a fifth transistor, a first capacitance element, and a second capacitance element; the second cell includes a seventh transistor, an eighth transistor, a ninth transistor, an eleventh transistor, a third capacitance element, and a fourth capacitance element; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor and the first terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the second transistor, the gate of the fifth transistor, and a first terminal of the second capacitive element; the other of the source or the drain of the second transistor and the one of the source or the drain of the third transistor are electrically connected to a first wiring; one of the source and the drain of the fifth transistor is electrically connected to a second wiring; one of the source and the drain of the seventh transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitive element; the other of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the eighth transistor, the gate of the eleventh transistor, and a first terminal of the fourth capacitive element; the other of the source or the drain of the eighth transistor, the one of the source or the drain of the ninth transistor, the second terminal of the first capacitance element, and the second terminal of the third capacitance element are each electrically connected to a third wiring; one of the source and the drain of the eleventh transistor, the second terminal of the second capacitance element, and the second terminal of the fourth capacitance element are electrically connected to a fourth wiring; a gate of the first transistor, a gate of the second transistor, a gate of the seventh transistor, and a gate of the eighth transistor are electrically connected to a fifth wiring; Semiconductor device. 　 In claim 3, a channel length of one selected from the first transistor, the second transistor, the seventh transistor, and the eighth transistor is longer than a channel length of each of the third transistor, the fifth transistor, the ninth transistor, and the eleventh transistor; a channel width of one selected from the third transistor, the fifth transistor, the ninth transistor, and the eleventh transistor is longer than a channel width of each of the first transistor, the second transistor, the seventh transistor, and the eighth transistor; Semiconductor device. In any one of claims 1 to 4, each of the transistors included in the first cell and the second cell has an oxide semiconductor in a channel formation region; the oxide semiconductor contains indium; Semiconductor device. 　 In claim 5, a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit; the first driving circuit has a function of supplying a first current corresponding to first data w to the first cell via the first wiring; The second drive circuit is The second data x is transmitted to the second cell via the third wiring. １ a function of supplying a second current according to the second current or a reference current according to the reference data r; The third data x is transmitted to the second cell via the fourth wiring. ２ and a function of flowing a third current corresponding to the reference current or the third current corresponding to the reference current; the third driving circuit has a function of transmitting a selection signal to the fifth wiring in order to write the first data w to the first cell and write the reference data r to the second cell; The fourth driving circuit is W×x flows between the source or drain of the third transistor and the first wiring. １ a function of acquiring a fourth current according to / r and outputting a result of calculation of a first function into which the amount of the fourth current is substituted as a variable; W×x flows between one of the source or drain of the fifth transistor and the second wiring. ２ and a function of acquiring a fifth current according to / r and outputting a result of calculation of a second function into which the amount of the fifth current is substituted as a variable, the first current, the second current, the third current, the fourth current, the fifth current, and the reference current each have a current amount within a range in which the third transistor, the fifth transistor, the ninth transistor, and the eleventh transistor operate in a subthreshold region; Semiconductor device. 　 In any one of claims 1 to 4, each of the transistors included in the first cell and the second cell has an oxide semiconductor in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Semiconductor device. 　 In claim 7, a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit; the first driving circuit has a function of supplying a first current corresponding to first data w to the first cell via the first wiring; The second drive circuit is The second data x is transmitted to the second cell via the third wiring. １ a function of supplying a second current according to the second current or a reference current according to the reference data r; The third data x is transmitted to the second cell via the fourth wiring. ２ and a function of flowing a third current corresponding to the reference current or the third current corresponding to the reference current; the third driving circuit has a function of transmitting a selection signal to the fifth wiring in order to write the first data w to the first cell and write the reference data r to the second cell; The fourth driving circuit is W×x flows between the source or drain of the third transistor and the first wiring. １ a function of acquiring a fourth current according to / r and outputting a result of calculation of a first function into which the amount of the fourth current is substituted as a variable; W×x flows between one of the source or drain of the fifth transistor and the second wiring. ２ and a function of acquiring a fifth current according to / r and outputting a result of calculation of a second function into which the amount of the fifth current is substituted as a variable, the first current, the second current, the third current, the fourth current, the fifth current, and the reference current each have a current amount within a range in which the third transistor, the fifth transistor, the ninth transistor, and the eleventh transistor operate in a subthreshold region; Semiconductor device.

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