Power conversion device

Abstract

A power conversion device (100) comprises: one or more single-phase inverters (INV(n)) that are connected in series and supply power to a load (10); and a control unit (20) that controls the semiconductor switches (Q1(n)-Q4(n)) of the single-phase inverters (INV(n)). The control unit (20) controls the semiconductor switches (Q1(n)-Q4(n)) to; a first control state in which the semiconductor switches (Q1(n)) and the semiconductor switches (Q3(n)) are brought into the ON state and the semiconductor switches (Q2(n)) and the semiconductor switches (Q4(n)) are brought into the OFF state; and a second control state in which the semiconductor switches (Q2(n)) and the semiconductor switches (Q4(n)) are brought into the ON state and the semiconductor switches (Q1(n)) and the semiconductor switches (Q3(n)) are brought into the OFF state. The control unit (20) selects the first control state or the second control state when outputting the zero voltage to the single-phase inverters (INV(n)).

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] If losses are concentrated in a specific semiconductor switching element in an inverter or multiple inverter series circuits, a larger heat sink is required to dissipate the heat, which leads to larger equipment and higher costs. For this reason, it is necessary to distribute the losses generated in the semiconductor switching elements.

[0003] A drive control device is disclosed that dissipates heat generated in semiconductor switching elements in an inverter that converts DC power into AC power and supplies it to a load by changing the path through which current flows during the inverter's reflux period.

[0004] JP 2014-121129 A

[0005] However, in the drive control device of Patent Document 1, because the reflux period is divided equally within one control cycle, uniform heat dispersion cannot be achieved depending on the load and waveform. Also, because the voltage application time is divided into two within one control cycle, there are problems such as increased switching loss due to an increase in the number of switching operations and waveform distortion due to dead time.

[0006] The present disclosure discloses a technology for solving the above-mentioned problems, and aims to provide a power conversion device that can disperse heat generated by semiconductor switching elements by devising inverter control in a single-phase inverter circuit or a multi-series inverter circuit.

[0007] In the power conversion device of the present disclosure, in a single-phase inverter INV(n), where n is an integer of 1 or more, one end of a semiconductor switch Q1(n) and one end of a semiconductor switch Q3(n) are connected to a high-potential terminal of a DC power supply V(n), one end of a semiconductor switch Q2(n) and one end of a semiconductor switch Q4(n) are connected to a low-voltage terminal of the DC power supply V(n), the other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) are connected in series at a first midpoint P1(n), and the other end of the semiconductor switch Q3(n) and the other end of the semiconductor switch Q4(n) are connected in series at a first midpoint P1(n). The inverter includes a single-phase inverter INV(n) configured such that the other end of the semiconductor switch Q4(n) is connected in series at a second midpoint P2(n); a load connected to a first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(n) of the single-phase inverter INV(n) and supplied with DC power or AC power; and a control unit that controls the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n), wherein the control unit and the semiconductor switch Q3(n) is in an on state and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) is in an off state, and a second control state is in an on state and the semiconductor switch Q1(n) and the semiconductor switch Q3(n) is in an off state, and the control unit controls the semiconductor switch Q1(n) and the semiconductor switch Q4(n) to an on state and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) is in an off state. The inverters are controlled to a first conduction state in which the semiconductor switch Q3(n) is turned off, and a second conduction state in which the semiconductor switch Q2(n) and the semiconductor switch Q3(n) are turned on and the semiconductor switch Q1(n) and the semiconductor switch Q4(n) are turned off, and when zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n) in at least one of the single-phase inverters INV(n), either the first control state or the second control state is selected.

[0008] According to the power conversion device of the present disclosure, by devising inverter control in a single-phase inverter circuit or a multi-series inverter circuit, a power conversion device can be obtained that can achieve dispersion of heat generated in semiconductor switching elements.

[0009] FIG. 2A is an overall configuration diagram of a power conversion device according to embodiment 1. FIG. 2A is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 1. FIG. 2B is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 1. FIG. 2C is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 1. FIG. 2D is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 1. FIG. 2D is an explanatory diagram of an operating state transition of a single-phase inverter according to embodiment 1. FIG. 5A is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 5B is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 5C is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 6A is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 6B is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 6C is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 6D is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 7A is a diagram of a semiconductor switch layout of a single-phase inverter according to embodiment 2. FIG. 7B is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 7C is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 7D is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 7E is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8A is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8B is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8C is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8D is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8E is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8F is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 9A is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 3. FIG. 9B is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 3. FIG. 10A is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 3.FIG. 10B is an explanatory diagram of an operating state of a plurality of single-phase inverters according to embodiment 3. FIG. 11A is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 11B is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 12A is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 12B is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 13A is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 13B is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 14A is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 14B is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 15A is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 15B is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 16A is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 16B is a diagram illustrating a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 1 is a hardware configuration example of a control unit. FIG. 2 is an explanatory diagram of transition timing of a single-phase inverter according to embodiment 1. FIG. 3 is an explanatory diagram of transition timing of a single-phase inverter according to embodiment 1. FIG. 4 is an explanatory diagram of transition timing of a single-phase inverter according to embodiment 1. FIG. 5 is an explanatory diagram of transition timing of a single-phase inverter according to embodiment 1. FIG. 6 is an explanatory diagram of transition timing of a single-phase inverter according to embodiment 1. FIG. 7 is an explanatory diagram of transition timing of a single-phase inverter according to embodiment 1.

[0010] Embodiment 1 In embodiment 1, in a power conversion device including one or more single-phase inverters connected in series to supply power to a load and a control unit that controls semiconductor switches of the single-phase inverters, the control unit controls the semiconductor switches to a first control state and a second control state, and selects the first control state or the second control state when zero voltage is to be output to the single-phase inverter.

[0011] The configuration and operation of the power conversion device according to embodiment 1 will be described below with reference to FIG. 1, which is an overall configuration diagram of the power conversion device, FIGS. 2A and 2B, which are explanatory diagrams of the operating states of the single-phase inverter, FIGS. 3 and 4, which are operating state transition diagrams of the single-phase inverter, and FIGS. 18 to 24, which are explanatory diagrams of the transition timing of the single-phase inverter.

[0012] The overall configuration of the power conversion device and the configuration of the single-phase inverter of the first embodiment will be described with reference to Fig. 1. The power conversion device 100 includes an inverter unit 1 and a control unit 20, and supplies AC power or DC power to a load 10.

[0013] First, we will explain the configuration and operation of the inverter unit 1 of the power conversion device 100. The inverter unit 1 is composed of single-phase inverters INV(1), INV(2), INV(3), ..., INV(n) (n is an integer equal to or greater than 1). In the figure, for example, INV(n) is written as INVn.

[0014] Next, the configuration of each single-phase inverter will be described, taking the single-phase inverter INV(n) as a representative. The single-phase inverter INV(n) is composed of a full-bridge circuit consisting of self-arc-suppressing semiconductor switching elements Q1(n), Q2(n), Q3(n), and Q4(n), such as insulated gate bipolar transistors (IGBTs), each with a plurality of diodes connected in antiparallel, and a DC power supply V(n). For simplicity, in FIG. 1 , the diodes of the semiconductor switching elements are omitted and are represented as switches. In the figure, for example, Q1(n) is referred to as Q1n, Q2(n) as Q2n, Q3(n) as Q3n, Q4(n) as Q4n, and V(n) as Vn. The semiconductor switching elements are also referred to as semiconductor switches. The semiconductor switching elements may be transistors, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc. Although the examples shown are each composed of a single component, each semiconductor switching element may be composed of a plurality of semiconductor switching elements connected in series, parallel, or series-parallel in order to ensure sufficient withstand voltage and current.

[0015] One end of semiconductor switch Q1(n) and one end of semiconductor switch Q3(n) are connected to the high-potential terminal of DC power supply V(n), and one end of semiconductor switch Q2(n) and one end of semiconductor switch Q4(n) are connected to the low-voltage terminal of DC power supply V(n). The other end of semiconductor switch Q1(n) and the other end of semiconductor switch Q2(n) are connected in series at a first midpoint P1(n), and the other end of semiconductor switch Q3(n) and the other end of semiconductor switch Q4(n) are connected in series at a second midpoint P2(n). In the figure, for example, P1(n) is written as P1n.

[0016] Next, the internal configuration of the inverter unit 1 and the relationship between the inverter unit 1, the load 10, and the control unit 20 will be described. The outputs of each single-phase inverter INV(n) are connected in series. Specifically, for example, the second midpoint P2(1) of the single-phase inverter INV(1) is connected to the first midpoint P1(2) of the single-phase inverter INV(2). The second midpoint P2(2) of the single-phase inverter INV(2) is connected to the first midpoint P1(3) of the single-phase inverter INV(3). The load 10 is connected to the first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(n) of the single-phase inverter INV(n). The control unit 20 controls the semiconductor switches Q1(n), Q2(n), Q3(n), and Q4(n) of each single-phase inverter INV(n). The load 10 may be a resistive load, an inductive load, or a capacitive load. It should be noted that FIG. 1 shows a typical example of the circuit, and modifications can be made as needed, such as adding a drive circuit for the semiconductor switch, adding a snubber circuit, adding an input capacitor, or adding an output filter.

[0017] Next, the operating states of the single-phase inverter INV(n) will be described based on the operating state diagrams of the single-phase inverters shown in FIGS. 2A to 2D. Each single-phase inverter INV(n) has the following four operating states (first control state, second control state, first conduction state, and second conduction state). In the first control state (see FIG. 2A), the control unit 20 turns on the semiconductor switches Q1(n) and Q3(n) and turns off the semiconductor switches Q2(n) and Q4(n). The first control state is a state in which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n). In the second control state (see FIG. 2B), the control unit 20 turns on the semiconductor switches Q2(n) and Q4(n) and turns off the semiconductor switches Q1(n) and Q3(n). The second control state is a state in which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n). In the first conduction state (see FIG. 2C), the control unit 20 turns on the semiconductor switches Q1(n) and Q4(n) and turns off the semiconductor switches Q2(n) and Q3(n). In the first conduction state, a voltage of Vn is output between the first midpoint P1(n) and the second midpoint P2(n). In the second conduction state (see FIG. 2D), the control unit 20 turns on the semiconductor switches Q2(n) and Q3(n) and turns off the semiconductor switches Q1(n) and Q4(n). In the second conduction state, a voltage of -Vn is output between the first midpoint P1(n) and the second midpoint P2(n). In each figure, the thick solid lines indicate the paths along which current flows.

[0018] Next, transitions in the operating states of the single-phase inverter INV(n), particularly transitions between the first and second control states, which are characteristic of the power conversion device 100 of the first embodiment, will be described with reference to the operating state transition diagrams of the single-phase inverter shown in FIGS. 3 and 4 . First, basic transitions in the operating states (switching of selections) that are typically performed will be described with reference to FIG. 3 . The control unit 20 can arbitrarily select between the first and second control states. By arbitrarily selecting between the first and second control states, conduction losses, which are losses generated in the semiconductor switches, can be dispersed. As shown in FIG. 3 , transitions between the first and second control states are basically performed via the first conduction state or the second conduction state. That is, the control state transitions are performed after transitions (switching of selections) to the first conduction state or the second conduction state at least once. By not directly transitioning from the first control state to the second control state (or from the second control state to the first control state), increases in switching losses due to an increase in the number of switching operations of the semiconductor switches can be suppressed, and waveform distortion due to the dead time required during the transitions can also be suppressed. It should be noted that the transition of the control state from the first control state to the second control state (or from the second control state to the first control state) does not necessarily have to be performed every control cycle. The timing of the transition (switching) of the control state will be described later.

[0019] Next, a case where a direct transition between the first control state and the second control state is performed will be described with reference to Fig. 4. As shown in Fig. 4, the transition between the first control state and the second control state is performed without passing through the first conduction state or the second conduction state. When the period of the first control state or the period of the second control state is long (i.e., when no transition to the first conduction state or the second conduction state occurs), it is effective to perform this direct transition between the first control state and the second control state (i.e., switching of selection) at least once, thereby enabling effective heat dissipation.

[0020] Next, we will explain the timing and effect of the transition (switching of selection) from the first control state to the second control state (from the second control state to the first control state). The transition timing will be explained using the examples shown in Figures 18 to 24. Figures 18 to 24 show an example of the operation of INV(m), which outputs a voltage of magnitude V. For simplicity, in Figures 18 to 24, the output states (INV states) of the four INV(m) are labeled A to D, i.e., A for the first control state, B for the second control state, C for the first conduction state, and D for the second conduction state. Method (1): Method (1) switches the selection between the first control state and the second control state every control period of the control unit 20 or every integer multiple of the control period. In the example shown in Figure 18, the INV state when outputting zero voltage is switched between the first control state (A) and the second control state (B) every control period. Method (1) is a method that enables heat dissipation with a simple configuration. Method (2): Method (2) switches between the first and second control states at the cycle of the AC power waveform output to the load 10 or an integer multiple thereof. In the example shown in FIG. 19 , the INV state at zero voltage output is set to the first control state (A) during the first output power cycle, and then the INV state at zero voltage output is switched to the second control state (B) during the next output power cycle. Like method (1), method (2) enables heat dissipation with a simple configuration. Furthermore, as shown in FIG. 19 , this method enables equal heat dissipation even under conditions where the off time changes periodically. Method (3): Method (3) switches between the first and second control states after a certain time has elapsed. In the example shown in FIG. 20 , time is measured, and when a certain time has elapsed (when a threshold value has been reached), the INV state at zero voltage output is switched from the first control state (A) to the second control state (B) for operation. Like method (1), method (3) enables heat dissipation with a simple configuration. This method also allows for equal heat distribution even under conditions where the off time varies. Note that Figure 20 shows an example of a method that does not directly switch between the first control state (A) and the second control state (B). Therefore, the first control state (A) and the second control state (B) are switched after passing through the first conduction state (C).In FIG. 20 , time measurement begins when the measurement time reaches a threshold and the control state switches to the first conduction state (C). However, the timing of measurement is not limited to this. For example, measurement may begin immediately upon reaching the threshold, or upon switching to the second control state (B). Method (4): Method (4) measures the time during the first or second control state, and switches between the first and second control states when the total time reaches a certain value. In the example shown in FIG. 21 , the time during zero voltage output is measured, and once a certain time (threshold value) is reached, the INV state during zero voltage output is switched from the first control state (A) to the second control state (B). Compared to method (3), method (4) distributes the off time more evenly between the first and second control states, enabling more precise heat dissipation. Note that FIG. 21 illustrates an example of a method that does not directly switch between the first control state (A) and the second control state (B). Method (5): Method (5) switches between the first and second control states when the output voltage and current waveforms output to the load 10 reach zero current or zero voltage. In the example shown in FIG. 22 , the INV state during zero voltage output is switched from the first control state (A) to the second control state (B) when the output current reaches zero. Method (5) reduces losses in the semiconductor switch through zero-current switching or zero-voltage switching. Methods (1) to (5) can be freely combined. For example, method (3) may be used under certain output conditions, and method (2) may be used when the output conditions change. For example, method (1) may be normally used, and when a timing permitting switching to method (5) occurs, switching to method (5) may be performed.

[0021] Methods (1) to (5) can be applied both to cases where the transition between the first and second control states is performed directly and cases where it is not. Method (4) will be used as an example. Figure 23 illustrates a case where the transition between the first and second control states is not performed directly. The transition is performed after a predetermined time has elapsed and then after switching to another state. Figure 24 illustrates a case where the transition between the first and second control states is performed directly. The transition is performed immediately after a predetermined time has elapsed. When the zero voltage output time shown in Figures 23 and 24 is long, not performing direct switching would result in a longer time in the first or second control state, potentially resulting in concentrated heat generation. Therefore, direct switching is desirable when the zero voltage output time is long. Conversely, performing direct switching in the example of Figure 21 would increase the number of switching cycles and increase heat generation due to switching losses, so it is preferable not to perform switching. The decision on whether to perform direct switching should be made after considering the effects of increased switching cycles and the heat generation concentration caused by maintaining the same control state.

[0022] The above-described switching of the control unit 20 is targeted for the operation during a period excluding the dead time period. Specifically, assuming that the semiconductor switch is a MOSFET, the switching operation of the control unit 20 is defined for the period during which the semiconductor switch is on and the gate voltage is applied between the gate and source of the MOSFET to turn the MOSFET on.

[0023] Although not specifically described in this embodiment, when transitioning from one control state or conduction state to another, a dead time period is inserted in which the upper and lower MOSFETs are simultaneously turned off to prevent short-circuiting of the semiconductor switches arranged above and below. The current path during this dead time period is determined by the direction of the current. It may form a current path different from the first and second control states and the first and second conduction states, or it may be the same path as the first and second control states or the first and second conduction states. For example, when a direct state transition is made from the first control state to the second control state, a period during the dead time period may occur in which the current path is the same as the first conduction state or the second conduction state.

[0024] In this embodiment, the switching operation of the control unit 20 covers a period excluding the dead time period. In the example of switching from the first control state to the second control state described above, even if the first conduction state or the second conduction state is entered during the dead time, it is treated as switching from the first control state to the second control state. The reason for excluding the dead time period is that the dead time period is generally sufficiently short compared to the on-time and off-time, and can be considered not to contribute to the heat dissipation that is the subject of this discussion. Note that if the proportion of the dead time period is large and operation during the dead time period affects heat dissipation, the switching operation of the control unit may be performed including the dead time state.

[0025] As described above, the power conversion device of the first embodiment includes one or more single-phase inverters connected in series to supply power to a load, and a control unit that controls the semiconductor switches of the single-phase inverters. The control unit controls the semiconductor switches between a first control state and a second control state, and selects the first control state or the second control state when zero voltage is output to the single-phase inverters. Therefore, the power conversion device of the first embodiment can achieve heat dissipation in the semiconductor switches in a single-phase inverter circuit or a multi-series inverter circuit by devising inverter control. Distributing the heat dissipation allows for a smaller heat sink, thereby enabling a more compact device. It also enables a smaller mounting area for the single-phase inverter. A smaller mounting area reduces wiring inductance due to wiring length, thereby reducing surge voltages generated by the switching operation of the semiconductor switches. This allows for further heat dissipation reduction when low-voltage semiconductor switches with good characteristics can be used.

[0026] Second Embodiment A power conversion device according to a second embodiment aims to dissipate heat from semiconductor switches by appropriately arranging the semiconductor switches.

[0027] The power conversion device of embodiment 2 will be described, focusing on the differences from embodiment 1, based on Figures 5A to 5C which are semiconductor switch layout diagrams (basic layout) of a single-phase inverter, Figures 6A to 6D which are semiconductor switch layout diagrams (single-row layout) of a single-phase inverter, Figures 7A to 7C which are semiconductor switch layout diagrams (L-shaped layout) of a single-phase inverter, Figures 7D and 7E which are semiconductor switch layout diagrams (two-row layout) of a single-phase inverter, and Figures 8A to 8F which are semiconductor switch layout diagrams (modified example) of a single-phase inverter. In the configuration diagram of embodiment 2, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals.

[0028] In the power conversion device of the second embodiment, an appropriate arrangement method for heat dissipation when arranging semiconductor switches in a single-phase inverter INV(n) will be described. This disclosure is characterized by arranging semiconductor switches Q1(n) and Q3(n), through which current flows in the first control state of the single-phase inverter INV(n), and semiconductor switches Q2(n) and Q4(n), through which current flows in the second control state, at a distance from each other to achieve heat dissipation. The basic arrangement of semiconductor switches in this disclosure is shown in Figures 5A to 5C. Figure 5A illustrates an arrangement method for arranging semiconductor switches in a single row. By sandwiching semiconductor switches Q2(n) or Q4(n), through which current flows in the second control state, between semiconductor switches Q1(n) and Q3(n), through which current flows in the first control state, the distance between semiconductor switches that generate heat in the same control state can be increased. Figure 5B illustrates an arrangement method for arranging semiconductor switches in two rows. The semiconductor switches Q1(n) and Q3(n), or the semiconductor switches Q2(n) and Q4(n), are arranged diagonally across a rectangle with the semiconductor switches at the vertices. This allows for greater distance between semiconductor switches that generate heat under the same control state. FIG. 5C shows an L-shaped arrangement. The semiconductor switches Q2(n) and Q4(n) are arranged at the corners of the L-shape, and the semiconductor switches Q1(n) and Q3(n) are arranged at the remaining points of the L-shape. This allows for greater distance between semiconductor switches that generate heat under the same control state. In the second embodiment, by selecting and combining the above three arrangement methods, the distance between semiconductor switches that generate heat under the same control state is increased, thereby achieving heat dispersion. Note that, due to the possibility of dielectric breakdown and short circuits, semiconductor switches are generally arranged with a space between them, rather than arranged so that one side of each semiconductor switch touches another, as shown in FIGS. 6A to 6D (described later). For simplicity, the description in this disclosure ignores the space between the switches. The shape of the semiconductor switch does not have to be square as shown in the drawing, and can be modified according to the package shape of the semiconductor switch.

[0029] Below, we will explain examples of combinations and variations of the above three arrangement methods. Figures 6A to 6D show arrangement examples when four semiconductor switches are arranged in a row. In all of Figures 6A to 6D, semiconductor switch Q2(n) or Q4(n) is arranged between semiconductor switch Q1(n) and semiconductor switch Q3(n), and semiconductor switch Q1(n) and semiconductor switch Q3(n) are arranged between semiconductor switch Q2(n) and semiconductor switch Q4(n). This makes it possible to increase the distance between semiconductor switches that generate heat under the same control state.

[0030] 7A to 7C are examples of arrangements in which four semiconductor switches are arranged in an L-shape. FIG. 7A is an example of a combination of a linear arrangement and an L-shape arrangement, in which semiconductor switch Q2(n) is arranged at the corner of the L-shape, thereby spacing semiconductor switch Q1(n) and semiconductor switch Q3(n). Furthermore, semiconductor switch Q3(n) is sandwiched between semiconductor switch Q2(n) and semiconductor switch Q4(n), spacing semiconductor switch Q2(n) and semiconductor switch Q4(n). FIG. 7B is also an example of a combination of a linear arrangement and an L-shape arrangement. This differs from FIG. 7A in that semiconductor switch Q3(n) is arranged at the corner of the L-shape, but like FIG. 7A, the distance between semiconductor switches that generate heat under the same control state can be increased. FIG. 7C is an example of a combination of an L-shape arrangement and an L-shape arrangement. By combining an L-shape arrangement in which semiconductor switch Q2(n) is arranged at the corner with an L-shape arrangement in which semiconductor switch Q3(n) is arranged at the corner, the distance between semiconductor switches that generate heat under the same control state can be increased.

[0031] 7D and 7E show examples of arrangements when four semiconductor switches are arranged in two rows. In both Figures 7D and 7E, semiconductor switch Q1(n) and semiconductor switch Q3(n) or semiconductor switch Q2(n) and semiconductor switch Q4(n) are arranged diagonally in a rectangle with the semiconductor switches as vertices. This allows the distance between semiconductor switches that generate heat under the same control state to be increased.

[0032] Figures 8A to 8F are diagrams showing modified examples of Figures 6A to 6D and Figures 7A to 7E. Even if the semiconductor switches are offset vertically or horizontally, or even if the spacing between the semiconductor switches is not constant, they can be considered to be arranged in a single row, a double row, or an L-shape. Although Figure 5A is described as a single row arrangement, it can also be considered as a linear arrangement. Furthermore, although Figure 5B is described as a double row arrangement, it can also be considered as a square, rectangle, or parallelogram.

[0033] As described above, the power conversion device of the second embodiment aims to disperse heat from the semiconductor switches by appropriately arranging the semiconductor switches. Therefore, the power conversion device of the second embodiment can realize dispersal of heat generated by the semiconductor switches in a single-phase inverter circuit or a multi-series inverter circuit by devising inverter control. Furthermore, heat can be disperse by appropriately arranging the semiconductor switches of the inverter.

[0034] Third Embodiment A power conversion device according to a third embodiment relates to selection of a first control state and a second control state between a plurality of single-phase inverters.

[0035] The power conversion device of embodiment 3 will be described, focusing on the differences from embodiment 1, based on Figures 9A and 9B, which are explanatory diagrams of the operating states of multiple single-phase inverters (current path coincidence), and Figures 10A and 10B, which are explanatory diagrams of the operating states of multiple single-phase inverters (current path reversal). In the configuration diagram of embodiment 3, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals.

[0036] In the power conversion device of the third embodiment, two single-phase inverters INV(i) and INV(k) will be described. Note that i and k are integers equal to or greater than 1, and i≠k holds true. In a power conversion device configured with two or more single-phase inverters INV(n), the zero voltage output state (first control state and second control state) of one single-phase inverter INV(i) is linked to the zero voltage output state of another single-phase inverter INV(k). In this case, the single-phase inverters INV(i) and INV(k) may select the same zero voltage output state (current path coincidence) or may select opposite zero voltage output states (current path reversal).

[0037] First, the case where the single-phase inverters INV(i) and INV(k) select the same zero-voltage output state (current path coincidence) will be described with reference to Figures 9A and 9B. Specifically, when the single-phase inverter INV(i) selects the first control state, the single-phase inverter INV(k) also selects the first control state, and when the single-phase inverter INV(i) selects the second control state, the single-phase inverter INV(k) also selects the second control state. In Figure 9A, both the single-phase inverters INV(i) and INV(k) select the first control state. In Figure 9B, both the single-phase inverters INV(i) and INV(k) select the second control state.

[0038] A case where the single-phase inverters INV(i) and INV(k) select opposite zero-voltage output states (current path reversal) will be described with reference to FIGS. 10A and 10B . Specifically, when the single-phase inverter INV(i) selects the first control state, the single-phase inverter INV(k) selects the second control state, and when the single-phase inverter INV(i) selects the second control state, the single-phase inverter INV(k) selects the first control state. In FIG. 10A , the single-phase inverter INV(i) selects the first control state, and the single-phase inverter INV(k) selects the second control state. In FIG. 10B , the single-phase inverter INV(i) selects the second control state, and the single-phase inverter INV(k) selects the first control state.

[0039] By selecting the first control state and the second control state as described above for a plurality of single-phase inverters, the process of selecting the first control state and the second control state by the control unit 20 is simplified, and the load on the control unit 20 can be reduced.

[0040] As described above, the power conversion device of the third embodiment selects the first control state and the second control state in a plurality of single-phase inverters so that the current paths coincide or the current paths are reversed. Therefore, the power conversion device of the third embodiment can achieve dispersion of heat generated in semiconductor switching elements in a single-phase inverter circuit or a multi-series inverter circuit by devising inverter control. In addition, the load on the control unit can be reduced.

[0041] Fourth Embodiment A power conversion device according to a fourth embodiment aims to dissipate heat by appropriately arranging semiconductor switches in a plurality of single-phase inverters.

[0042] The power conversion device of embodiment 4 will be described, focusing on the differences from embodiment 1, based on Figures 11A, 11B, 12A, 12B, 13A, and 13B, which are semiconductor switch layout diagrams (current path coincidence) of a plurality of single-phase inverters, and Figures 14A, 14B, 15A, 15B, 16A, and 16B, which are semiconductor switch layout diagrams (current path reversal) of a plurality of single-phase inverters. In the configuration diagrams of embodiment 4, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals.

[0043] In the power conversion device of the fourth embodiment, two single-phase inverters INV(i) and INV(k) are described. Note that i and k are integers equal to or greater than 1, and i ≠ k. In a power conversion device configured with two or more single-phase inverters INV(n), the zero-voltage output state (first control state and second control state) of one single-phase inverter INV(i) is linked to the zero-voltage output state (first control state and second control state) of another single-phase inverter INV(k). In this case, the single-phase inverter INV(i) and the single-phase inverter INV(k) may select the same zero-voltage output state (current path coincidence) or may select opposite zero-voltage output states (current path reversal). In either case, the semiconductor switches in the single-phase inverter INV(i) and the single-phase inverter INV(k) that generate heat simultaneously are spaced apart to prevent heat generation from concentrating. Methods for spaced arrangement include the single-row arrangement, double-row arrangement, and L-shaped arrangement described in the second embodiment. The fourth embodiment is characterized in that the above-mentioned single-row arrangement, double-row arrangement, and L-shaped arrangement, or a combination thereof, is extended and applied to two INV(i) and INV(k).

[0044] First, we will explain the arrangement of semiconductor switches when single-phase inverters INV(i) and INV(k) select the same zero-voltage output state (current path coincidence). For example, assume that both single-phase inverters INV(i) and INV(k) select the first control state. In this case, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) also generate heat. For this reason, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) so that they are not adjacent to each other. For example, assume that both single-phase inverters INV(i) and INV(k) select the second control state. In this case, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) also generate heat. For this reason, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) are arranged at a distance from each other.

[0045] As a specific example of a case where single-phase inverters INV(i) and INV(k) select the same zero-voltage output state (current path coincidence), an example of the arrangement of the semiconductor switches of single-phase inverter INV(i) and the semiconductor switches of single-phase inverter INV(k) is described with reference to FIGS. 11A, 11B, 12A, 12B, 13A, and 13B. In FIG. 11A, the semiconductor switches of single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are also arranged in a row. Semiconductor switches Q4(i) and Q2(k), which generate heat at the same time, can be separated by sandwiching semiconductor switch Q1(k) between them. Similarly, semiconductor switches Q3(i) and Q1(k), which generate heat at the same time, can be separated by sandwiching semiconductor switch Q4(i) between them. 11B shows the semiconductor switches of the single-phase inverters INV(i) and INV(k) arranged in a single row, with the single-phase inverters INV(i) and INV(k) arranged in two rows. The semiconductor switches Q1(i) and Q3(k) and the semiconductor switches Q2(i) and Q4(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q3(k) and the semiconductor switches Q2(i) and Q2(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q1(k) and the semiconductor switches Q4(i) and Q2(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart.

[0046] In FIG. 12A , the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are arranged at right angles (L-shape). By placing semiconductor switch Q1(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q2(k), which generate heat at the same time, can be increased. In FIG. 12B , the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are arranged in two rows, but with a staggered arrangement. By placing semiconductor switch Q3(i) at the corner of the L-shape, the distance between semiconductor switch Q2(i) and semiconductor switch Q4(k), which generate heat at the same time, can be increased. Furthermore, by placing semiconductor switch Q3(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q2(k), which generate heat at the same time, can be increased. Furthermore, semiconductor switches Q3(i) and Q3(k) and semiconductor switches Q4(i) and Q4(k), which generate heat at the same time, can be placed at diagonal corners of a rectangle with the semiconductor switches as vertices, thereby allowing them to be placed at a distance from each other.

[0047] In Figure 13A, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in two rows, and the single-phase inverters INV(i) and INV(k) are arranged in a single row. The semiconductor switches Q2(i) and Q4(k), and the semiconductor switches Q3(i) and Q1(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing for spacing between them. In Figure 13B, the semiconductor switches of the single-phase inverter INV(i) are arranged in a single row, and the semiconductor switches of INV(k) are arranged in two rows, and the single-phase inverters INV(i) and INV(k) are arranged in a single row. By arranging the semiconductor switch Q1(k) at the corner of an L, the distance between the semiconductor switches Q4(i) and Q2(k), which generate heat simultaneously, can be increased.

[0048] 11A, 11B, 12A, 12B, 13A, and 13B are merely examples, and the single-phase inverters may be arranged in a single row, a double row, or an L-shape. Furthermore, the single-phase inverters may be arranged in a single row, a double row, an L-shape, or offset. Although not shown, the spacing does not have to be constant. Regarding the arrangement of semiconductor switches within the same single-phase inverter, semiconductor switches that generate heat are arranged far apart, as described in the second embodiment.

[0049] Next, the arrangement of the semiconductor switches when the single-phase inverters INV(i) and INV(k) select the opposite zero-voltage output state (current path reversal) will be described. For example, assume that the single-phase inverter INV(i) selects the first control state and INV(k) selects the second control state. In this case, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) also generate heat. Therefore, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) so that they are not adjacent to each other. For example, assume that the single-phase inverter INV(i) selects the second control state and INV(k) selects the first control state. In this case, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) also generate heat. For this reason, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k).

[0050] As a specific example of a case where the single-phase inverters INV(i) and INV(k) select different zero-voltage output states (current path reversal), examples of the arrangement of the semiconductor switches of the single-phase inverter INV(i) and the semiconductor switches of the single-phase inverter INV(k) are shown in Figures 14A, 14B, 15A, 15B, 16A, and 16B. In Figure 14A, the single-phase inverters INV(i) and INV(k) are arranged in a line, with the semiconductor switches arranged in different orders in a straight line. The semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(k) between them. Similarly, the semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(i) between them. In Figure 14B, single-phase inverters INV(i) and INV(k) are arranged in a line, with semiconductor switches arranged in a different order in a straight line. However, the order of the semiconductor switches in single-phase inverter INV(k) is changed from that in Figure 14A. The semiconductor switches Q4(i) and Q1(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q2(k) between them. Similarly, the semiconductor switches Q3(i) and Q2(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(i) between them.

[0051] 15A shows single-phase inverters INV(i) and INV(k) with semiconductor switches arranged in different orders in one row, arranged in two rows. The semiconductor switches Q1(i) and Q4(k), and the semiconductor switches Q2(i) and Q1(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q2(i) and Q3(k), and the semiconductor switches Q3(i) and Q4(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q2(k), and the semiconductor switches Q4(i) and Q3(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. In Figure 15B, single-phase inverters INV(i) and INV(k) are arranged in two rows, with the semiconductor switches arranged in a different order in one row. However, the order of the semiconductor switches in single-phase inverter INV(k) is changed from that in Figure 15A. By arranging the semiconductor switches Q1(i) and Q2(k), and the semiconductor switches Q2(i) and Q1(k), which generate heat simultaneously, at diagonal corners of a rectangle with the semiconductor switches as vertices, they can be spaced apart. Similarly, by arranging the semiconductor switches Q2(i) and Q3(k), and the semiconductor switches Q3(i) and Q2(k), which generate heat simultaneously, at diagonal corners of a rectangle with the semiconductor switches as vertices, they can be spaced apart. Similarly, by arranging the semiconductor switches Q3(i) and Q4(k), and the semiconductor switches Q4(i) and Q3(k), which generate heat simultaneously, at diagonal corners of a rectangle with the semiconductor switches as vertices, they can be spaced apart.

[0052] In FIG. 16A, single-phase inverters INV(i) and INV(k), each having semiconductor switches arranged in a row with different arrangement orders, are arranged at a right angle (L-shape). By arranging semiconductor switch Q4(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q1(k), which generate heat at the same time, can be increased. In FIG. 16B, single-phase inverters INV(i) and INV(k), each having semiconductor switches arranged in a row with different arrangement orders, are arranged at a right angle (L-shape). However, the arrangement order of the semiconductor switches of single-phase inverter INV(k) is changed from that of FIG. 16A. By arranging semiconductor switch Q2(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q3(k), which generate heat at the same time, can be increased.

[0053] As described above, the power conversion device of the fourth embodiment achieves heat dispersion by appropriately arranging the semiconductor switches in a plurality of single-phase inverters. Therefore, the power conversion device of the fourth embodiment can achieve dispersion of heat generated in the semiconductor switching elements in a single-phase inverter circuit or a multi-series inverter circuit by devising inverter control. Furthermore, in a plurality of single-phase inverters, appropriate arrangement of the semiconductor switches can further achieve heat dispersion.

[0054] The control unit 20 is configured with a processor 1000 and a storage device 1001, as shown in FIG. 17 , which illustrates an example of hardware. The storage device 1001 includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory, both not shown. Alternatively, a hard disk auxiliary storage device may be provided instead of the flash memory. The processor 1000 executes a program input from the storage device 1001. In this case, the program is input to the processor 1000 from the auxiliary storage device via the volatile storage device. The processor 1000 may output data such as calculation results to the volatile storage device of the storage device 1001, or may store the data in the auxiliary storage device via the volatile storage device.

[0055] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0056] 1 inverter unit, 10 load, 20 control unit, 100 power conversion device, 1000 processor, 1001 storage device, INV(1), INV(2), INV(3), INV(i), INV(k), INV(n) single-phase inverter, Q1(1), Q2(1), Q3(1), Q4(1), Q1(2), Q2(2), Q3(2), Q4(2), Q1(3), Q2(3), Q3(3), Q4(3), Q1(4), Q2(4), Q3(4), Q4(4), Q1(i), Q2(i), Q3(i), Q4(i), Q1(k), Q2(k), Q3(k), Q4(k), Q1(n), Q2(n), Q3(n), Q4(n) Semiconductor switch, V(1), V(2), V(3), V(n) DC power supply, P1(1), P1(2), P1(3), P1(n) first midpoint, P2(1), P2(2), P2(3), P2(n) second midpoint.

Claims

1. A single-phase inverter INV(n), where n is an integer of 1 or greater, having one end of a semiconductor switch Q1(n) and one end of a semiconductor switch Q3(n) connected to a high-potential terminal of a DC power supply V(n), one end of a semiconductor switch Q2(n) and one end of a semiconductor switch Q4(n) connected to a low-voltage terminal of the DC power supply V(n), the other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) connected in series at a first midpoint P1(n), and the other end of the semiconductor switch Q3(n) and the other end of the semiconductor switch Q4(n) connected in series at a second midpoint P2(n); a load connected between the first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(n) of the single-phase inverter INV(n) and supplied with DC power or AC power; a control unit that controls the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n), wherein the control unit controls a first control state in which the semiconductor switch Q1(n) and the semiconductor switch Q3(n) are in an on state and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are in an off state, and a second control state in which the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are in an on state and the semiconductor switch Q1(n) and the semiconductor switch Q3(n) are in an off state, and the control unit controls a first conduction state in which the semiconductor switch Q1(n) and the semiconductor switch Q4(n) are in an on state and the semiconductor switch Q2(n) and the semiconductor switch Q3(n) are in an off state, and a second conduction state in which the semiconductor switch Q2(n) and the semiconductor switch Q3(n) are turned on and the semiconductor switch Q1(n) and the semiconductor switch Q4(n) are turned off; and in at least one of the single-phase inverters INV(n), when zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n), the power conversion device selects either the first control state or the second control state.

2. The power conversion device according to claim 1, wherein, in a state in which either the first control state or the second control state is selected for at least one of the single-phase inverters INV(n), the control unit switches the semiconductor switches Q1(n) to Q4(n) to the first conduction state or the second conduction state at least once, and then selects the first control state or the second control state.

3. The power conversion device according to claim 1 or 2, wherein the control unit, for at least one of the single-phase inverters INV(n), switches the semiconductor switches Q1(n) to Q4(n) from a state in which either the first control state or the second control state is selected to the first conduction state or the second conduction state, and then selects the other of the first control state or the second control state.

4. The power conversion device according to claim 1, wherein the control unit switches between the first control state and the second control state at least once for at least one of the single-phase inverters INV(n) during at least one period during which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n) of the single-phase inverter INV(n).

5. The power conversion device according to any one of claims 1 to 4, wherein for at least one of the single-phase inverters INV(n), at least three of the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) are arranged in a row, and either the semiconductor switch Q2(n) or the semiconductor switch Q4(n) is arranged between the semiconductor switch Q1(n) and the semiconductor switch Q3(n), or either the semiconductor switch Q1(n) or the semiconductor switch Q3(n) is arranged between the semiconductor switch Q2(n) and the semiconductor switch Q4(n).

6. The power conversion device according to any one of claims 1 to 4, wherein for at least one of the single-phase inverters INV(n), the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) are arranged in two rows, and the semiconductor switch Q1(n) and the semiconductor switch Q3(n), and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are arranged at diagonal corners of a rectangle with each of the semiconductor switches as its vertices.

7. The power conversion device according to any one of claims 1 to 4, wherein for at least one of the single-phase inverters INV(n), at least three of the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) are arranged in an L-shape, with the semiconductor switch Q1(n) or the semiconductor switch Q3(n) being arranged at a corner of the L-shape and the semiconductor switch Q2(n) or the semiconductor switch Q4(n) being arranged on two different sides of the L-shape; or the semiconductor switch Q2(n) or the semiconductor switch Q4(n) being arranged at a corner of the L-shape and the semiconductor switch Q1(n) or the semiconductor switch Q3(n) being arranged on two different sides of the L-shape.

8. A power conversion device according to any one of claims 1 to 7, wherein n is an integer of 2 or more, i and k are integers of 1 or more, and i≠k holds true, and wherein the control unit, when at least two single-phase inverters INV(n) simultaneously output zero voltage, selects the first control state for one single-phase inverter INV(i), and also selects the first control state for the remaining single-phase inverters INV(k), and selects the second control state for one single-phase inverter INV(i).

9. The power conversion device according to any one of claims 1 to 7, wherein n is an integer of 2 or more, i and k are integers of 1 or more and have a relationship of i≠k, and wherein the control unit, when at least two single-phase inverters INV(n) simultaneously output zero voltage, if one single-phase inverter INV(i) selects the first control state, at least one single-phase inverter INV(k) of the remaining single-phase inverters INV(n) selects the second control state, and if one single-phase inverter INV(i) selects the second control state, at least one single-phase inverter INV(k) of the remaining single-phase inverters INV(n) selects the first control state.

10. where i and k are integers of 1 or more and there is a relationship of i≠k, and for at least two of the one or more single-phase inverters INV(n), when at least some of the semiconductor switches Q1(n) to Q4(n) included in each of the single-phase inverters INV(n) are arranged in a single row, a double row, or an L-shaped arrangement, and when each of the single-phase inverters INV(n) simultaneously outputs zero voltage, when one single-phase inverter INV(i) selects the first control state, the other single-phase inverter INV(k) also selects the first control state, and when one single-phase inverter INV(i) selects the second control state, the other single-phase inverter INV(k) also selects the second control state, and when the first control state is selected, the semiconductor switches Q1(n) and Q3(n) of the single-phase inverter INV(n) generate heat, 8. The power conversion device according to claim 5, wherein when the second control state is selected, the semiconductor switches Q2(n) and Q4(n) of the single-phase inverter INV(n) generate heat, and at least some of the semiconductor switches of one of the single-phase inverters INV(n) and the semiconductor switches of the other single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shaped arrangement, and the semiconductor switches that generate heat in the first control state or the second control state that are simultaneously selected are arranged so that the semiconductor switches that generate heat in the other of the first control state or the second control state are sandwiched between them in an arrangement between the different single-phase inverters INV(n).

11. where i and k are integers of 1 or more and there is a relationship of i≠k, and for at least two of the one or more single-phase inverters INV(n), when at least some of the semiconductor switches Q1(n) to Q4(n) included in each of the single-phase inverters INV(n) are arranged in a single row, a double row, or an L-shaped arrangement, and when each of the single-phase inverters INV(n) simultaneously outputs zero voltage, when one single-phase inverter INV(i) selects the first control state, the other single-phase inverter INV(k) selects the second control state, and when one single-phase inverter INV(i) selects the second control state, the other single-phase inverter INV(k) selects the first control state, when the first control state is selected, the semiconductor switches Q1(n) and Q3(n) of the single-phase inverter INV(n) generate heat, 8. The power conversion device according to claim 5, wherein when the second control state is selected, the semiconductor switches Q2(n) and Q4(n) of the single-phase inverter INV(n) generate heat, and at least some of the semiconductor switches of one of the single-phase inverters INV(n) and the semiconductor switches of the other single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shaped arrangement, and the semiconductor switches that generate heat in the first control state or the second control state that are simultaneously selected are arranged so that the semiconductor switches that generate heat in the other of the first control state or the second control state are sandwiched between them in an arrangement between the different single-phase inverters INV(n).

12. The power conversion device according to any one of claims 1 to 11, wherein the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters every control period of the control unit or every integral multiple of the control period.

13. The power conversion device according to any one of claims 1 to 11, wherein in a single-phase inverter in which AC power is supplied to the load, the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters at intervals of an integer multiple of a period of the waveform of the AC power output from one or more of the single-phase inverters to the load.

14. The power conversion device according to any one of claims 1 to 11, wherein the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters after a certain period of time has elapsed.

15. The power conversion device according to claim 14, wherein the control unit switches the selection of the first control state or the second control state when the total time during which the first control state or the second control state is selected for at least one of the single-phase inverters matches the certain time.

16. The power conversion device according to any one of claims 1 to 11, wherein in a single-phase inverter in which AC power is supplied to the load, the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters when the waveform supplied to the load is zero current or zero voltage.

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