Distributed amplifier

Abstract

A distributed amplifier according to the present invention comprises: a plurality of transistors (11)-(14) at which respective source nodes are grounded; a gate line (2) that electrically connects an input terminal (100) and the gate node of the last transistor (14) located on an output terminal (200) side, and that has a plurality of gate connection points (21)-(24) to which the gate nodes of the plurality of transistors (11)-(14) are electrically connected, and a plurality of inter-gate lines (201)-(204) respectively connected between the gate connection points that are adjacent to each other; a drain line (3) that electrically connects the output terminal (200) and the drain node of the first transistor (11) located on the input terminal (100) side, and that has a plurality of drain connection points (31)-(34) to which respective drain nodes of the plurality of transistors (11)-(14) are electrically connected, and a plurality of inter-drain lines (301)-(304) respectively connected between the drain connection points that are adjacent to each other and constitute a series circuit between capacitors (30b1)-{30b4) and drain-side transmission lines (30a1)-(30a4); and a plurality of drain voltage supply circuits (61-(64) that are respectively connected between a drain voltage supply node and corresponding drain connection points (31)-(34) of the drain line (3).

Description

Distributed Amplifier

[0001] The present disclosure relates to a distributed amplifier, which is a type of high-frequency amplifier.

[0002] Distributed amplifiers are implemented as high-frequency amplifiers that amplify high-frequency signals in wireless communication devices, radar devices, and the like. This type of distributed amplifier is shown in Non-Patent Document 1. The distributed amplifier shown in Non-Patent Document 1 has a plurality of source-grounded transistors arranged in parallel, with the drain electrodes of adjacent transistors of the plurality of transistors electrically connected by a drain-side transmission line and the gate electrodes of adjacent transistors of the plurality of transistors electrically connected by a gate-side transmission line.

[0003] C. Campbell, “A Wideband Power Amplifier MMIC Utilizing GaN on SiC HEMT Technology,” IEEE JOURNAL. Solid-State Circuits, vol.44, no.10, Oct.2009. pp. 2640-2647

[0004] The distributed amplifier shown in Non-Patent Document 1 has a configuration in which the drain supply voltage for all transistors is given from a common bias circuit, that is, the drain supply voltage is equal for all transistors. Therefore, the drain efficiency of the transistors on the input side becomes lower in turn relative to the drain efficiency of the transistors on the output side, which causes a problem in that the efficiency of the distributed amplifier as a whole becomes lower.

[0005] The present disclosure is intended to solve the above-mentioned problems, and has an object to provide a distributed amplifier in which the drain efficiency of a transistor is improved and the efficiency of the distributed amplifier as a whole is improved.

[0006] The distributed amplifier according to the present disclosure comprises: a plurality of transistors, each having a grounded source node; a gate line electrically connecting between an input terminal and a gate node of a last transistor located on the output terminal side, the gate nodes of the plurality of transistors being electrically connected to each other, a plurality of gate connection points to which the gate nodes of the plurality of transistors are electrically connected, and a plurality of inter-gate lines each connected between adjacent gate connection points; a drain line electrically connecting between a drain node of a first transistor located on the input terminal side and the output terminal, the drain nodes of the plurality of transistors being electrically connected to each other, and a plurality of inter-drain lines each connected between adjacent drain connection points, the drain line being a series circuit of a drain-side transmission line and a capacitor; and a plurality of drain voltage supply circuits each connected between a drain voltage supply node and a corresponding drain connection point of the drain line.

[0007] According to the present disclosure, it is possible to accommodate a wideband input signal, the drain efficiency of the transistor is improved, and the efficiency of the distributed amplifier as a whole is improved.

[0008] FIG. 1 is a configuration diagram showing an equivalent circuit of a distributed amplifier according to a first embodiment. FIG. 2 is a diagram showing an example of static characteristics and load lines of adjacent transistors in the distributed amplifier according to the first embodiment when the drain voltages and gate bias voltages are the same. FIG. 3 is a diagram showing an example of load lines of the first to fourth transistors in the distributed amplifier according to the first embodiment when the drain voltages and gate bias voltages are the same. FIG. 4 is a diagram showing an example of drain efficiencies of the first to fourth transistors in the distributed amplifier according to the first embodiment when the drain voltages and gate bias voltages are the same. FIG. 5 is a diagram showing an example of static characteristics and load lines of adjacent transistors in the distributed amplifier according to the first embodiment when the drain voltage of the transistor on the input terminal side is set lower than the drain voltage of the transistor on the output terminal side. FIG. 6 is a diagram showing drain voltages and gate bias voltages in the distributed amplifier according to the first embodiment. 1 is a diagram showing an example of load lines of the first to fourth transistors in the distributed amplifier according to the first embodiment, when the drain voltage supplied from the drain voltage supply node located on the output terminal side to the drain voltage supply node located on the input terminal side is sequentially decreased, and the gate bias voltage applied from the gate voltage application node located on the output terminal side to the gate voltage application node located on the input terminal side is sequentially increased. 2 is a diagram showing an example of drain efficiencies of the first to fourth transistors in the distributed amplifier according to the first embodiment, when the drain voltage supplied from the drain voltage supply node located on the output terminal side to the drain voltage supply node located on the input terminal side is sequentially decreased, and the gate bias voltage applied from the gate voltage application node located on the output terminal side to the gate voltage application node located on the input terminal side is sequentially increased. 3 is a diagram showing an example of drain efficiency as a distributed amplifier relative to the frequency of an input signal in the distributed amplifier according to the first embodiment. 4 is a diagram showing an example of output power as a distributed amplifier relative to the frequency of an input signal in the distributed amplifier according to the first embodiment. 5 is a diagram showing a configuration diagram of an equivalent circuit of a distributed amplifier according to a second embodiment. 6 is a diagram showing a configuration diagram of an equivalent circuit of a distributed amplifier according to a third embodiment.FIG. 10 is a configuration diagram showing an equivalent circuit of a distributed amplifier according to a fourth embodiment.

[0009] First Embodiment A distributed amplifier according to a first embodiment will be described with reference to Figures 1 to 10. The distributed amplifier according to the first embodiment is a high-frequency amplifier that amplifies high-frequency signals used in wireless communication devices, radar devices, etc. The distributed amplifier according to the first embodiment is implemented in a GaN (Gallium Nitride) MMIC (Monolithic Microwave Integrated Circuit).

[0010] The distributed amplifier according to the first embodiment includes a plurality of transistors 1 １ ~1 ４ and a plurality of inter-gate lines 20 １ ~20 ５ and a plurality of drain-to-drain lines 30. １ ~30 ４ and a plurality of gate input circuits 4. １ ~4 ４ and a plurality of gate bias voltage application circuits 5 １ ~5 ４ and a plurality of drain voltage supply circuits 6 １ ~6 ４ and a termination resistor 7.

[0011] A plurality of transistors 1 １ ~1 ４ In the figure, the subscripts attached to the symbols indicate the first, second, third, and fourth transistors in order from the input terminal 100 side. １ is the first transistor located on the input terminal 100 side, and the fourth transistor 1 ４ is the last transistor located on the output terminal 200 side.

[0012] A plurality of inter-gate lines 20 １ ~20 ５ and a plurality of inter-drain lines 30 １ ~30 ４ and a plurality of gate bias voltage application circuits 5 １ ~5 ４ and a plurality of drain voltage supply circuits 6 １ ~6 ４In the above, the subscripts attached to the symbols indicate the number of transistors 1. １ ~1 ４ Each transistor corresponds to a １ ~1 ４ Similarly, the first, second, third, and fourth terminals are designated in this order from the input terminal 100 side.

[0013] For the sake of explanation, transistor 1 １ ~1 ４ Although the case where there are four is described, any number may be used. When referring to any one of a plurality of numbers (N: a natural number of 2 or more), the subscript n (1 to N) is added. When describing common numbers, the subscripts and the numbers 1 to 4 are omitted to avoid complication.

[0014] An input signal, which is a high frequency signal, is input to an input terminal 100. The input signal input to the input terminal 100 is transmitted through a plurality of transistors 100. １ ~1 ４ The amplified signal is output from the output terminal 200 as an output signal.

[0015] First transistor 1 １ to the fourth transistor 1 ４ Each of these is an element in which an input signal from input terminal 100 is input to a gate node to which the gate electrode is connected, a drain voltage is supplied to a drain node to which the drain electrode is connected, and a source node to which the source electrode is connected is connected to a ground potential node and is grounded, and which amplifies the input signal input from input terminal 100.

[0016] First transistor 1 １ to the fourth transistor 1 ４ The gate width of the first transistor 1 is the same, and is set to 1 mm as an example. １ to the fourth transistor 1 ４ The gate width of each of the gates does not have to be 1 mm, and each gate width may be different.

[0017] First transistor 1 １ to the fourth transistor 1 ４Each of the first and second transistors is a GaN field effect transistor (FET). １ to the fourth transistor 1 ４ In the first embodiment, the operation class will be described as Class B, but Class A or Class C operation may also be used. １ to the fourth transistor 1 ４ Since the gate bias voltages applied to the respective gate potentials can be individually adjusted to different voltage values, the first transistor 1 １ to the fourth transistor 1 ４ Each operating class may be different.

[0018] The gate lines 2 are electrically connected between the input terminal 100 and one end of the terminating resistor 7. The gate lines 2 are each connected to the first transistor 1. １ to the fourth transistor 1 ４ A plurality of gate connection points 2 electrically connected to the gate nodes of １ ~2 ４ The gate lines 2 are made up of a plurality of inter-gate lines 20 connected between adjacent gate connection points. １ ~20 ５ It has.

[0019] First inter-gate line 20 １ is the input terminal 100 and the first gate connection point 2 １ The second inter-gate line 20 is connected between the first and second gates. ２ is the first gate connection point 2 １ and second gate connection point 2 ２ The third inter-gate line 20 is connected between the ３ is the second gate connection point 2 ２ and the third gate connection point 2 ３ is connected between

[0020] Fourth inter-gate line 20 ４ is the third gate connection point 2 ３ and the fourth gate connection point 2 ４ The fifth inter-gate line 20 ５ is the fourth gate connection point 2４ and one end of the termination resistor 7.

[0021] First inter-gate line 20 １ to the fifth inter-gate line 20 ５ Each of them is a gate side transmission line 20a １ ~20a ５ and capacitor 20b １ ~20b ５ The capacitor 20b is a series circuit of １ ~20b ５ Each cuts off DC current between the adjacent gate nodes to which it is electrically connected.

[0022] Gate side transmission line 20a １ ~20a ５ Each of them is a microstrip line mounted on a GaN MMIC. １ ~20a ５ Each of the capacitors 20b is formed in a meander line shape on the GaN MMIC and functions as an inductor. １ ~20b ５ Each is a MIM (Metal Insulator Metal) capacitor mounted on a GaN MMIC.

[0023] The drain line 3 is connected to the first transistor 1 １ The drain lines 3 are electrically connected between the drain nodes of the first transistors 1 and 2 and the output terminal 200. １ to the fourth transistor 1 ４ a plurality of drain nodes 3 electrically connected to the drain nodes of the １ ~3 ４ The drain line 3 has a plurality of inter-drain lines 30 connected between adjacent drain connection points. １ ~30 ４ It has.

[0024] First inter-drain line 30 １ is the first drain connection point 3 １ and the second drain connection point 3 ２ The second inter-drain line 30 is connected between the drains. ２is the second drain connection point 3 ２ and the third drain connection point 3 ３ The third inter-drain line 30 is connected between the drains. ３ is the third drain connection point 3 ３ and the fourth drain connection point 3 ４ The fourth inter-drain line 30 ４ is the fourth drain connection point 3 ４ and the output terminal 200.

[0025] First inter-drain line 30 １ to the fourth drain-to-drain line 30 ４ Each of them is a drain side transmission line 30a １ ~30a ４ and capacitor 30b １ ~30b ４ A capacitor 30b is a series circuit of １ ~30b ４ Each cuts off DC current between the adjacent drain nodes to which it is electrically connected.

[0026] Drain side transmission line 30a １ ~30a ４ Each of them is a microstrip line mounted on a GaN MMIC. １ ~30a ４ Each of them is formed in a meander line shape on the GaN MMIC and functions as an inductor. １ ~30b ４ Each is a MIM capacitor mounted on a GaN MMIC.

[0027] First gate input circuit 4 １ to the fourth gate input circuit 4 ４ Each of them is a first transistor 1 １ to the fourth transistor 1 ４ The first gate input circuit 4 is provided corresponding to each of the first gate input circuits. １ to the fourth gate input circuit 4 ４ Each of the first transistors 1 １ to the fourth transistor 1 ４Each gate node and the corresponding gate connection point 2 of the gate line 2 １ ~2 ４ and are connected between.

[0028] First gate input circuit 4 １ to the fourth gate input circuit 4 ４ Each is resistor 4a １ ~4a ４ and capacitor 4b １ ~4b ４ Resistor 4a is a parallel circuit. １ ~4a ４ Each of these is a resistor mounted on the GaN MMIC. １ ~4b ４ Each is a MIM capacitor mounted on a GaN MMIC.

[0029] The first gate input circuit 4 １ to the fourth gate input circuit 4 ４ In each case, a capacitor 4b is used to increase the cutoff frequency. １ ~4b ４ Although each of them is provided, they may not be provided. １ to the fourth gate input circuit 4 ４ Each is resistor 4a １ ~4a ４ Only this is acceptable.

[0030] First gate bias voltage application circuit 5 １ to the fourth gate bias voltage application circuit 5 ４ Each of them is a first transistor 1 １ to the fourth transistor 1 ４ The first gate bias voltage application circuit 5 is provided corresponding to each of the first and second gate bias voltage application circuits. １ to the fourth gate bias voltage application circuit 5 ４ Each of them corresponds to a gate voltage application node 8 １ ~8 ４ and the corresponding gate connection point 2 of the gate line 2 １ ~2 ４ is connected between

[0031] First gate bias voltage application circuit 5 １ is the first gate voltage application node 8 １ and the first gate connection point 2 １ A first gate voltage application inductor 5a is connected between the １ and the first gate voltage application node 8 １ and a ground potential node. １ The second gate bias voltage application circuit 5 ２ is the second gate voltage application node 8 ２ and second gate connection point 2 ２ A second gate voltage application inductor 5a is connected between the ２ and the second gate voltage application node 8 ２ and a second capacitor 5b connected between the ２ It has.

[0032] Third gate bias voltage application circuit 5 ３ is the third gate voltage application node 8 ３ and the third gate connection point 2 ３ A third gate voltage application inductor 5a is connected between the ３ and the third gate voltage application node 8 ３ and a ground potential node. ３ The fourth gate bias voltage application circuit 5 ４ is the fourth gate voltage application node 8 ４ and the fourth gate connection point 2 ４ A fourth gate voltage application inductor 5a is connected between the ４ and the fourth gate voltage application node 8 ４ and a fourth capacitor 5b connected between the ground potential node. ４ It has.

[0033] First gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The corresponding gate bias voltage Vg １ ~Vg ４ is applied to the gate line 20 between the gates. １ ~20５ Each capacitor 20b １ ~20b ５ As a result, the input terminal 100 and the gate connection point 2 １ During this time, the gate connection point 2 on the gate line 2 １ ~2 ４ and the gate connection point 2 on the gate line 2 ４ and one end of the termination resistor 7 is cut off.

[0034] As a result, the first transistor 1 １ to the fourth transistor 1 ４ A gate voltage application inductor 5a is connected to each gate node. １ ~5a ４ and gate input circuit 4 １ ~4 ４ through the corresponding gate voltage application node 8 １ ~8 ４ Gate bias voltage Vg １ ~Vg ４ are applied individually.

[0035] Gate bias voltage Vg １ ~Vg ４ can be adjusted individually, so that the first transistor 1 １ to the fourth transistor 1 ４ The operating points of each can be adjusted individually, and the output and efficiency can be improved as a distributed amplifier. １ ~Vg ４ can be adjusted individually, so that the first transistor 1 １ to the fourth transistor 1 ４ Each operating class can be changed from Class B operation to Class A operation and Class C operation individually.

[0036] The gate bias voltage Vg １ ~Vg ４ The relationship between V and V is expressed by the following equation (1): １ ≧Vg ２ ≧Vg ３≧Vg4 (1) That is, in the adjacent transistors 1, the gate bias voltage Vg for the transistor 1 located on the input terminal 100 side is set to be equal to or higher than the gate bias voltage Vg for the transistor 1 located on the output terminal 200 side.

[0037] In particular, as shown in the following equation (2), the fourth gate bias voltage Vg ４ to the first gate bias voltage Vg １ It is more preferable to increase the voltage value in order from Vg １ >Vg ２ >Vg ３ >Vg4 (2)

[0038] Gate voltage application inductor 5a １ ~5a ４ Each of them is formed in a spiral shape on the GaN MMIC and functions as an inductor. １ ~5b ４ Each is a MIM capacitor mounted on a GaN MMIC.

[0039] First drain voltage supply circuit 6 １ to the fourth drain voltage supply circuit 6 ４ Each of them is a first transistor 1 １ to the fourth transistor 1 ４ The first drain voltage supply circuit 6 is provided corresponding to each of the first and second drain voltage supply circuits. １ to the fourth drain voltage supply circuit 6 ４ Each of them has a corresponding drain voltage supply node 9 １ ~9 ４ and the corresponding drain connection point 3 of the drain line 3 １ ~3 ４ is connected between

[0040] First drain voltage supply circuit 6 １ is the first drain voltage supply node 9 １ and the first drain connection point 3 １ A first drain voltage supply inductor 6a connected between １ and the first drain voltage supply node 9 １and a ground potential node. １ The second drain voltage supply circuit 6 ２ is the second drain voltage supply node 9 ２ and the second drain connection point 3 ２ A second drain voltage supply inductor 6a is connected between ２ and the second drain voltage supply node 9 ２ and a second capacitor 6b connected between the ground potential node. ２ It has.

[0041] Third drain voltage supply circuit 6 ３ is the third drain voltage supply node 9 ３ and the third drain connection point 3 ３ A third drain voltage supply inductor 6a connected between ３ and the third drain voltage supply node 9 ３ and a third capacitor 6b connected between the ground potential node ３ The fourth drain voltage supply circuit 6 ４ is the fourth drain voltage supply node 9 ４ and the fourth drain connection point 3 ４ A fourth drain voltage supply inductor 6a connected between ４ and the fourth drain voltage supply node 9 ４ and a fourth capacitor 6b connected between the ground potential node ４ It has.

[0042] First drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ Each of them has a corresponding drain supply voltage Vd １ ~Vd ４ is supplied. １ ~30 ５ Each capacitor 30b １ ~30b ５ As a result, the drain connection point 3 １ ~3 ４ and the drain connection point 3 in the drain line 3 ４and the output terminal 200 is cut off.

[0043] As a result, the first transistor 1 １ to the fourth transistor 1 ４ A corresponding drain voltage supply inductor 6a is connected to each drain node. １ ~6a ４ through the corresponding drain voltage supply node 9 １ ~9 ４ Each of them supplies a drain supply voltage Vd １ ~Vd ４ are applied individually.

[0044] Drain supply voltage Vd １ ~Vd ４ can be adjusted individually, so that the first transistor 1 １ to the fourth transistor 1 ４ The operating points of the respective amplifiers can be adjusted individually, and the output and efficiency can be improved as a distributed amplifier. １ ~Vd ４ can be adjusted individually, so that the first transistor 1 １ to the fourth transistor 1 ４ The on-resistance of each can be adjusted. In particular, the fourth drain supply voltage Vd ４ to the first drain supply voltage Vd １ By gradually decreasing the voltage value toward ４ to the first transistor 1 １ Since the on-resistance of the first transistor 1 decreases in the order of １ to the fourth transistor 1 ４ The drain efficiency of the transistor 1 is improved, and the difference in drain efficiency between adjacent transistors 1 is reduced.

[0045] Drain supply voltage Vd １ ~Vd ４ The relationship between Vd and Vd is expressed by the following equation (3): １ ≦Vd ２ ≦Vd ３≦Vd4 (3) That is, in the adjacent transistors 1, the drain supply voltage Vd for the transistor 1 located on the input terminal 100 side is set to be equal to or lower than the drain supply voltage Vd for the transistor 1 located on the output terminal 200 side.

[0046] In particular, as shown in the following equation (4), the fourth drain supply voltage Vd ４ to the first drain supply voltage Vd １ It is more preferable to gradually decrease the voltage value toward Vd. １ <Vd ２ <Vd ３ <Vd4 (4)

[0047] Drain voltage supply inductor 6a １ ~6 ４ Each of them is formed in a spiral shape on the GaN MMIC and functions as an inductor. １ ~6b ４ Each of them is an MIM capacitor mounted on a GaN MMIC. The other end of the termination resistor 7 is connected to the ground node.

[0048] Next, the operation of the distributed amplifier according to the first embodiment will be described. When an input signal consisting of a high frequency signal is input to the input terminal 100, the input signal is transmitted through the gate line 2 to the first inter-gate line 20. １ and propagates to the first gate node 2 １ First gate node 2 １ The input signal that reaches the first gate input circuit 4 １ and the second inter-gate line 20 ２ will be distributed to

[0049] First gate input circuit 4 １ The input signal distributed to the first gate bias voltage application circuit 5 １ The first gate bias voltage Vg is supplied from １ The first transistor 1 is biased to １ The first transistor 1 １ is the first gate bias voltage Vg １The input signal biased to the first drain voltage supply circuit 6 is amplified and output as an output signal. １ to the first drain supply voltage Vd １ The first drain connection point 3 in the drain line 3 is supplied with １ The first drain connection point 3 １ The output signal output to the drain line 3 is transmitted to the first inter-drain line 30 １ and the second drain node 3 ２ to reach.

[0050] Second inter-gate line 20 ２ The input signal distributed to the second inter-gate line 20 ２ and propagates to the second gate node 2 ２ The second gate node 2 ２ The input signal that reaches the second gate input circuit 4 ２ and the third inter-gate line 20 ３ will be distributed to

[0051] Second gate input circuit 4 ２ The input signal distributed to the second gate bias voltage application circuit 5 ２ A second gate bias voltage Vg is supplied from ２ The second transistor 1 is biased to ２ The second transistor 1 ２ is the second gate bias voltage Vg ２ The input signal biased to the drain voltage supply circuit 6 is amplified and output as an output signal. ２ to the second drain supply voltage Vd ２ The second drain connection point 3 in the drain line 3 is supplied with ２ Output to.

[0052] Second drain node 3 ２ The output signal output to the second drain connection point 3 of the drain line 3 is ２ In the first inter-drain line 30 １ The first transistor 1 １ The output signal from the first transistor 1 is combined with the output signal from the first transistor 1. １The output signal from the second transistor 1 ２ The combined signal obtained by combining the output signals of the first and second drain-to-drain lines 30 is output from the drain line 3. ２ and the third drain node 3 ３ to reach.

[0053] Third inter-gate line 20 ３ The input signal distributed to the third inter-gate line 20 ３ and propagates to the third gate node 2 ３ The third gate node 2 ３ The input signal that reaches the third gate input circuit 4 ３ and the fourth inter-gate line 20 ４ will be distributed to

[0054] Third gate input circuit 4 ３ The input signal distributed to the third gate bias voltage application circuit 5 ３ A third gate bias voltage Vg is supplied from ３ The third transistor 1 is biased to ３ The third transistor 1 ３ is the third gate bias voltage Vg ３ The third drain voltage supply circuit 6 amplifies the input signal biased to ３ to the third drain supply voltage Vd ３ The third drain connection point 3 in the drain line 3 is supplied with ３ Output to.

[0055] Third drain node 3 ３ The output signal output to the third drain connection point 3 of the drain line 3 is ３ In the second inter-drain line 30 ２ The first transistor 1 １ The output signal from the second transistor 1 ２ The output signal of the first transistor 1 is combined with the combined signal. １ to the third transistor 1 ３ The combined signal of the output signals is output to the drain line 3 via the third drain-to-drain line 30.３ and the fourth drain node 3 ４ to reach.

[0056] Fourth inter-gate line 20 ４ The input signal distributed to the fourth inter-gate line 20 ４ and propagates to the fourth gate node 2 ４ The fourth gate node 2 ４ The input signal that reaches the fourth gate input circuit 4 ４ and the fifth inter-gate line 20 ５ will be distributed to

[0057] Fourth gate input circuit 4 ４ The input signal distributed to the fourth gate bias voltage application circuit 5 ４ A fourth gate bias voltage Vg is supplied from ４ The fourth transistor 1 is biased to ４ The fourth transistor 1 ４ is the fourth gate bias voltage Vg ４ The input signal biased to the drain voltage supply circuit 6 is amplified and output as an output signal. ４ to the fourth drain supply voltage Vd ４ The fourth drain connection point 3 in the drain line 3 is supplied with ４ Output to.

[0058] Fourth drain node 3 ４ The output signal output to the fourth drain connection point 3 of the drain line 3 is ４ In the third inter-drain line 30 ３ The first transistor 1 １ to the third transistor 1 ３ The respective output signals are combined into a combined signal. １ to the fourth transistor 1 ４ The combined signal of the output signals is output to the drain line 3 via the fourth inter-drain line 30. ４ is propagated through the fifth inter-gate line 20 and output from the output terminal 200. ５ The input signal distributed to the fifth inter-gate line 20５ is propagated and terminated by the termination resistor 7.

[0059] In this way, the first transistor 1 １ to the fourth transistor 1 ４ Each corresponds to a gate bias voltage Vg １ ~Vg ４ The input signals, each gate biased individually by the corresponding drain supply voltage Vd １ ~Vd ４ Each operates by its own amplifier, and the first transistor 1 １ to the fourth transistor 1 ４ The amplified output signals are combined and output to an output terminal 200 .

[0060] Next, we will explain the operating characteristics of the distributed amplifier according to embodiment 1. First, we will explain the static characteristics and load line (VI characteristics) for two adjacent transistors 1 when the gate bias voltage Vg applied to the gate voltage application node 8 is the same gate bias voltage Vg and the drain supply voltage Vd supplied to the drain voltage supply node 9 is the same drain supply voltage Vdd.

[0061] The two adjacent transistors 1 are the same size, i.e., have the same gate width of 1 mm, and are transistors operating in class B operation. Furthermore, the drain current Ids flowing through each of the two adjacent transistors 1 is the same as the instantaneous maximum drain current Imax. As an example, the drain supply voltage Vdd is 30 V, and the gate bias voltage Vg is -2.7 V. An input signal consisting of a high-frequency signal with a frequency of 12 GHz is input to the input terminal 100.

[0062] Under these conditions, the distributed amplifier was operated, and the static characteristics and load lines of the two adjacent transistors were investigated, resulting in the results shown in Figure 2. In Figure 2, the horizontal axis represents the drain voltage Vds, the vertical axis represents the drain current Ids, the dashed line represents the static characteristics, and the solid line A represents the load line. ０１ is the load line (VI characteristics) of transistor 1 on the input terminal side, and the waveform B is shown by the solid line ０１is the voltage amplitude Vds of the drain node relative to the source node (ground potential) of the transistor 1 on the input terminal side ０１ , dashed line A ０２ is the load line (VI characteristics) of transistor 1 on the output terminal side, and waveform B is shown by the dashed line. ０２ is the voltage amplitude Vds of the drain node relative to the source node (ground potential) of the transistor 1 on the output terminal side ０２ Shows.

[0063] As can be seen from FIG. 2, the voltage amplitude is Vds ０１ <Vds ０２ , the instantaneous drain voltage when the drain current is maximum is Vmin ０１ >Vmin ０２ , on-resistance is Ron ０１ >Ron ０２ , the load corresponding to the inverse of the slope of the load line is RL ０１ <RL ０２ Here, the subscript 01 indicates the transistor 1 on the input terminal side, and the subscript 02 indicates the transistor 1 on the output terminal side.

[0064] The above relationship is due to the fact that the output signal amplified by the transistor 1 on the input terminal side and the output signal amplified by the transistor 1 on the output terminal side are combined at the drain connection point of the drain line 3 to which the drain node of the transistor 1 on the output terminal side is connected. ０２ is the voltage amplitude Vds of transistor 1 on the input terminal side ０１ This can be understood from the fact that it becomes larger.

[0065] The output power Pout and drain efficiency DE of the transistor can be expressed by the following equations (5) and (6), respectively.

[0066] In the above equations (5) and (6), Vdd is the drain supply voltage supplied to the transistor 1, Ron is the on-resistance value of the transistor 1, and RL is the resistance value of the load. As can be seen from the above equation (6), the drain efficiency DE decreases as the load resistance value RL decreases and the on-resistance value Ron increases.

[0067] The first transistor 1 shown in FIG. １ to the fourth transistor 1 ４ In the distributed amplifier according to the first embodiment, the first drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ and the first gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The gate bias voltage Vg applied to each １ ~Vg ４ When the gate bias voltage Vg is the same and an input signal consisting of a high frequency signal with a frequency of 12 GHz is input to the input terminal 100, １ to the fourth transistor 1 ４ The load lines (VI characteristics) for each were investigated, and the results shown in FIG. 3 were obtained.

[0068] First transistor 1 １ to the fourth transistor 1 ４ The transistors are of the same size, i.e., the same gate width of 1 mm, and operate in class B. As an example, the drain supply voltage Vdd is 30 V and the gate bias voltage Vg is −2.7 V.

[0069] In FIG. 3, the horizontal axis represents the drain voltage, the vertical axis represents the drain current, and the solid curve E ０１ is the first transistor 1 １ Load line (VI characteristics), dashed curve E ０２ is the second transistor 1 ２ Load line (VI characteristics), curve E shown by the dashed line ０３ is the third transistor 1 ３ The load line (VI characteristics) and the curve E shown by the two-dot chain line ０４ is the fourth transistor 1 ４ The load line (VI characteristics) of

[0070] Also, the first gate voltage application node 8 １to the fourth gate voltage application node 8 ４ The gate bias voltage Vg applied to each １ ~Vg ４ and the first drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ When the drain supply voltage Vdd is the same and the frequency of the input signal input to the input terminal 100 is changed from 2.5 GHz to 13 GHz, １ to the fourth transistor 1 ４ The drain efficiency in each case was investigated, and the results shown in FIG. 4 were obtained.

[0071] First transistor 1 １ to the fourth transistor 1 ４ The transistors are of the same size, i.e., the same gate width of 1 mm, and operate in class B. As an example, the gate bias voltage Vg is set to -2.7 V and the drain supply voltage Vdd is set to 30 V.

[0072] In FIG. 4, the horizontal axis represents the frequency of the input signal, the vertical axis represents the drain efficiency, and the solid line represents the ０１ is the first transistor 1 １ The drain efficiency of ０２ is the second transistor 1 ２ The drain efficiency of ０３ is the third transistor 1 ３ and the drain efficiency of the curve F shown by the dashed double-dashed line. ０４ is the fourth transistor 1 ４ The drain efficiency is shown.

[0073] The results of the investigation of the drain efficiency Ea of the entire distributed amplifier are shown as a dashed line in Fig. 9. As is clear from Fig. 9, in the input signal frequency band of 2.5 GHz to 13 GHz, the minimum value of the drain efficiency Ea of the entire distributed amplifier was 34.5%.

[0074] Next, in the distributed amplifier according to the first embodiment, the drain-to-drain line 30 in the drain line 3 １ ~30 ４ Capacitor 30b １ ~30b ４ The DC cut function of the first transistor 1 １ to the fourth transistor 1 ４ The drain node of １ ~Vd ４ and the inter-gate line 20 in the gate line 2. １ ~20 ５ Capacitor 20b １ ~20b ５ The DC cut function of the first transistor 1 １ to the fourth transistor 1 ４ The gate node is applied with a gate bias voltage Vg １ ~Vg ４ The first transistor 1 can be applied by individually adjusting the characteristics. １ to the fourth transistor 1 ４ The static characteristics, load line (VI characteristics) and drain efficiency of the transistor will be explained.

[0075] First, the static characteristics and load lines (VI characteristics) of the input-side transistor 1 and the output-side transistor 1 investigated under the following conditions will be described for two adjacent transistors 1. The drain supply voltage supplied to the drain voltage supply node 9 for the output-side transistor 1 is the drain supply voltage Vd ０２ and the drain supply voltage supplied to the drain voltage supply node 9 of the input-side transistor 1 is Vd ０２ The drain supply voltage Vd is a smaller voltage value. ０１ Let's say.

[0076] The gate bias voltage applied to the gate voltage application node 8 for the output side transistor 1 is the gate bias voltage Vg ０２ The gate bias voltage applied to the gate voltage application node 8 of the input side transistor 1 is Vg ０２ The gate bias voltage Vg is a larger voltage value.０１ The two adjacent transistors 1 are of the same size, that is, have the same gate width of 1 mm, and are transistors that operate in class B mode.

[0077] In addition, the instantaneous maximum drain current Imax is the same for the drain current Ids flowing through each of two adjacent transistors 1. As an example, ０２ 30V (Vdd), drain supply voltage Vd ０１ 28V, gate bias voltage Vg ０２ -2.7V (Vg), gate bias voltage Vg ０１ was set to −2.5 V. An input signal consisting of a high frequency signal with a frequency of 12 GHz was input to the input terminal 100.

[0078] Under these conditions, the distributed amplifier was operated, and the static characteristics and load line (VI characteristics) of two adjacent transistors were investigated, resulting in the results shown in Figure 5. In Figure 5, the horizontal axis represents the drain voltage Vds, the vertical axis represents the drain current Ids, the dashed line represents the static characteristics, and the straight line A shown by the dashed line represents the ２ is the load line (VI characteristics) of transistor 1 on the output terminal side, and line A shown by the two-dot chain line １ is the load line (VI characteristics) of transistor 1 on the input terminal side.

[0079] In addition, the straight line A shown by the solid line ０１ is the same drain supply voltage Vd as the transistor 1 on the output terminal side ０２ (Vdd), the same gate bias voltage Vg ０２ (Vg) is the load line (VI characteristics) of the input side transistor 1, and is shown by the solid line A in FIG. ０１ The load line (VI characteristics) of the transistor 1 on the input terminal side is the same as that of the transistor 1 shown by the dashed line. ２ is the straight line A shown by the dashed line in FIG. ０２ This is the same as the load line (VI characteristics) of the transistor 1 on the output terminal side indicated by

[0080] As can be seen from FIG. 5, the load line (VI characteristics) A of the transistor 1 on the input side １ is the drain supply voltage Vd ０２The load line (VI characteristics) of the input side transistor 1 is (Vdd) ０１ with respect to the drain supply voltage Vd ０２ and the drain supply voltage Vd ０１ The difference between the two is shown as the load line shifted toward the origin.

[0081] The instantaneous drain voltage Vmin when the drain current of the input-side transistor 1 is at its maximum １ The instantaneous drain voltage Vmin when the drain current in the transistor 1 on the output terminal side is maximum ２ (Vmin ０２ ) can be approximated to the on-resistance Ron of the transistor 1 on the input side. １ is the drain supply voltage Vd ０２ (Vdd) The on-resistance Ron of the input side transistor 1 ０１ The on-resistance of the transistor 1 on the output terminal side is Ron ２ (Ron ０２ ) will be closer to

[0082] As a result, the on-resistance Ron of the input-side transistor 1 １ is the on-resistance Ron ０１ As can be seen from the above formula (6), by making the drain efficiency of the transistor 1 on the input side smaller, the drain efficiency of the transistor 1 on the input side is improved. By improving the drain efficiency of the transistor 1 on the input side, the difference between the drain efficiency of the transistor 1 on the input side and the drain efficiency of the transistor 1 on the output terminal side can be reduced, and the drain efficiency of the transistor 1 on the input side can be made closer to the drain efficiency of the transistor 1 on the output terminal side.

[0083] In short, the relationship between two adjacent transistors can be as follows: That is, the voltage amplitude can be Vds １ ≒ Vds ２ , the instantaneous drain voltage when the drain current is maximum is Vmin １ ≒ Vmin ２ , on-resistance is Ron １ ≒Ron ２ , the load corresponding to the inverse of the slope of the load line is R １ ≒RL ２Here, the subscript 1 indicates the transistor 1 on the input terminal side, and the subscript 2 indicates the transistor 1 on the output terminal side. As a result, the drain efficiency of the transistor 1 on the input side can be made to approach the drain efficiency of the transistor 1 on the output terminal side, and a decrease in drain efficiency due to the transistor 1 on the input side can be prevented.

[0084] The first transistor 1 shown in FIG. １ to the fourth transistor 1 ４ In the distributed amplifier according to the first embodiment, the first drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ The fourth drain voltage supply node 9 located on the output terminal 200 side ４ The first drain voltage supply node 9 located on the input terminal 100 side from １ The drain voltage supplied to the １ <Vd ２ <Vd ３ <Vd ４ ) and the first gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The gate bias voltage Vg applied to each １ ~Vg ４ to the fourth gate voltage application node 8 located on the output terminal 200 side. ４ The first gate voltage application node 8 located on the input terminal 100 side from １ (Vg １ >Vg ２ >Vg ３ >Vg ４ ) and when an input signal consisting of a high frequency signal with a frequency of 12 GHz is input to the input terminal 100, １ to the fourth transistor 1 ４ When the load lines (VI characteristics) for each were investigated, the results shown in FIG. 7 were obtained.

[0085] First transistor 1 １ to the fourth transistor 1 ４The transistors are of the same size, i.e., the gate width is 1 mm, and they operate in class B mode. As an example, as shown in FIG. 6, the drain supply voltage, Vd ４ to 30V, Vd ３ 28V, Vd ２ to 25V, Vd １ is set to 20V, and the gate bias voltage, Vg ４ to -2.7V, V g ３ to -2.5V, Vg ２ to -2.2V, Vg １ was set to −1.7V.

[0086] In FIG. 7, the horizontal axis represents the drain voltage, the vertical axis represents the drain current, and the solid curve E １ is the first transistor 1 １ Load line (VI characteristics), dashed curve E ２ is the second transistor 1 ２ Load line (VI characteristics), curve E shown by the dashed line ３ is the third transistor 1 ３ The load line (VI characteristics) and the curve E shown by the two-dot chain line ４ is the fourth transistor 1 ４ The load line (VI characteristics) of

[0087] As can be seen from FIG. １ to the third transistor 1 ３ The load line (VI characteristics) of the fourth transistor 1 ４ The load line (VI characteristic) of the first transistor 1 approaches the axis of the drain current. １ to the third transistor 1 ３ In this case, the instantaneous drain voltage Vmin when the drain current is maximum １ ~Vmin ３ is the fourth transistor 1 ４ The instantaneous drain voltage Vmin when the drain current is maximum ４ approaching.

[0088] In other words, the first transistor 1 １ to the fourth transistor 1 ４The instantaneous drain voltage when the drain current is maximum is Vmin １ ≒ Vmin ２ ≒ Vmin ３ ≒ Vmin ４ The first transistor 1 １ to the third transistor 1 ３ The decrease in drain efficiency of the fourth transistor 1 can be suppressed. ４ As a result, the drain efficiency of the entire distributed amplifier is improved.

[0089] Also, the first drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ Vd １ <Vd ２ <Vd ３ <Vd ４ and the first gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The gate bias voltage Vg applied to each １ ~Vg ４ Vg １ >Vg ２ >Vg ３ >Vg ４ When the frequency of the input signal input to the input terminal 100 is changed from 2.5 GHz to 13 GHz, １ to the fourth transistor 1 ４ The drain efficiency in each case was investigated, and the results shown in FIG. 8 were obtained.

[0090] First transistor 1 １ to the fourth transistor 1 ４ The transistors are of the same size, i.e., the gate width is 1 mm, and they operate in class B mode. As an example, as shown in FIG. 6, the drain supply voltage, Vd ４ to 30V, Vd ３ 28V, Vd ２ to 25V, Vd １ is set to 20V, and the gate bias voltage, Vg ４to -2.7V, V g ３ to -2.5V, Vg ２ to -2.2V, Vg １ was set to −1.7V.

[0091] In FIG. 8, the horizontal axis represents the frequency of the input signal, the vertical axis represents the drain efficiency, and the solid line represents the １ is the first transistor 1 １ The drain efficiency of ２ is the second transistor 1 ２ The drain efficiency of ３ is the third transistor 1 ３ and the drain efficiency of the curve F shown by the dashed double-dashed line. ４ is the fourth transistor 1 ４ The drain efficiency is shown.

[0092] As can be seen from FIG. 8, the first transistor 1 １ to the third transistor 1 ３ The decrease in drain efficiency of the first transistor 1 can be suppressed. １ to the third transistor 1 ３ The drain efficiency of the fourth transistor is ４ The drain efficiency approaches that of

[0093] As a result, the fourth drain voltage supply node 9 located on the output terminal 200 side is low over a wide frequency range of the input signal from 2.5 GHz to 13 GHz. ４ The first drain voltage supply node 9 located on the input terminal 100 side from １ The drain supply voltage Vd １ ~Vd ４ Decrease Vd １ <Vd ２ <Vd ３ <Vd ４ ) leads to an improvement in the drain efficiency of the entire distributed amplifier.

[0094] That is, the result of the investigation of the drain efficiency Eb of the entire distributed amplifier is shown as a solid line in Fig. 9, and in the input signal frequency band of 2.5 GHz to 13 GHz, the minimum value of the drain efficiency Eb of the entire distributed amplifier is 41.5%. As can be seen from the investigation result shown in Fig. 9, １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ Vd １ <Vd ２ <Vd ３ <Vd ４ When the above relationship is satisfied, the drain efficiency Eb of the entire distributed amplifier is improved.

[0095] Furthermore, in the distributed amplifier according to the first embodiment, an input signal having a frequency of 2.5 GHz to 13 GHz was input to the input terminal 100, and the output power output from the output terminal 200 was investigated. The results of the investigation are shown in Fig. 10. In Fig. 10, the horizontal axis represents the frequency of the input signal input to the input terminal 100, and the vertical axis represents the output power output from the output terminal 200.

[0096] In FIG. 10, the dashed curve Oa indicates the first gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The gate bias voltage Vg applied to each １ ~Vg ４ and the first drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ 1 indicates the output power output at the output terminal 200 when the drain supply voltage is the same.

[0097] In FIG. 10, the solid curve Ob indicates the voltage at the first drain voltage supply node 9 １ to the fourth drain voltage supply node 9 ４ The drain supply voltage Vd supplied to each １ ~Vd ４ Vd１ <Vd ２ <Vd ３ <Vd ４ and the first gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The gate bias voltage Vg applied to each １ ~Vg ４ Vg １ >Vg ２ >Vg ３ >Vg ４ 2 shows the output power output to the output terminal 200 when

[0098] 10, in the input signal frequency band of 2.5 GHz to 13 GHz, the minimum value of the output power Oa was 41.8 dBm, and the minimum value of the output power Ob was 42.0 dBm. As can be seen from the investigation results, the fourth gate voltage application node 8 located on the output terminal 200 side has a low frequency response across the wide input signal frequency band of 2.5 GHz to 13 GHz. ４ The first gate voltage application node 8 located on the input terminal 100 side from １ A gate bias voltage Vg is applied to １ ~Vg ４ Increasing Vg １ >Vg ２ >Vg ３ >Vg ４ ) leads to an improvement in the output power outputted to the output terminal 200 of the distributed amplifier.

[0099] The distributed amplifier according to the first embodiment includes a plurality of transistors 1, each of whose source nodes is grounded. １ ~1 ４ a plurality of transistors 1 １ ~1 ４ a drain line 3 connected in parallel to a plurality of transistors 1, １ ~1 ４ A plurality of drain connection points 3 to which the drain nodes of １ ~3 ４ , and drain-side transmission lines 30a each connected between adjacent drain connection points. １ ~30a４ and capacitor 30b １ ~30b ４ A plurality of inter-drain lines 30 which are a series circuit of １ ~30 ４ , each of which is connected to a drain voltage supply node 9 １ ~9 ４ and the corresponding drain connection point 3 of the drain line 3 １ ~3 ４ A plurality of drain voltage supply circuits 6 connected between １ ~6 ４ Therefore, the drain efficiency of the entire distributed amplifier is improved.

[0100] In particular, the fourth drain voltage supply node 9 located on the output terminal 200 side ４ The first drain voltage supply node 9 located on the input terminal 100 side from １ The drain supply voltage Vd １ ~Vd ４ Decrease Vd １ <Vd ２ <Vd ３ <Vd ４ ) leads to an improvement in the drain efficiency of the entire distributed amplifier, specifically, an improvement in the drain efficiency of the entire distributed amplifier over a wide input signal frequency band from 2.5 GHz to 13 GHz.

[0101] The distributed amplifier according to the first embodiment also includes a plurality of transistors 1 １ ~1 ４ A plurality of gate connection points 2 electrically connected to the gate nodes of １ ~2 ４ The gate lines 2 having the gate side transmission lines 20a are connected between adjacent gate connection points. １ ~20a ４ and capacitor 20b １ ~20b ４ A plurality of inter-gate lines 20 which are a series circuit of １ ~20 ４ , each of which is a gate voltage application node 8 １ ~8 ４ and the corresponding gate connection point 2 of the gate line 2 １ ~2４ A plurality of gate bias voltage application circuits 5 connected between １ ~5 ４ Therefore, the fourth gate voltage application node 8 located on the output terminal 200 side ４ The first gate voltage application node 8 located on the input terminal 100 side from １ A gate bias voltage Vg is applied to １ ~Vg ４ Increasing Vg １ >Vg ２ >Vg ３ >Vg ４ ) leads to an improvement in the output power output from the output terminal 200 of the distributed amplifier over a wide frequency band of the input signal from 2.5 GHz to 13 GHz.

[0102] Furthermore, in the distributed amplifier according to the first embodiment, the respective corresponding transistors 1 １ ~1 ４ The gate node of the gate line 2 and the corresponding gate connection point 2 １ ~2 ４ and a resistor 4a １ ~4a ４ and capacitor 4b １ ~4b ４ A plurality of gate input circuits 4 consisting of parallel circuits １ ~4 ４ Therefore, transistor 1 １ ~1 ４ This makes it possible to increase the cutoff frequency of the input signal input to the gate node of the transistor.

[0103] Although the distributed amplifier according to the first embodiment has been described taking as an example a distributed amplifier mounted on a GaN MMIC, it may also be mounted on a GaAs MMIC, or may be configured with individual components discretely.

[0104] Second Embodiment A distributed amplifier according to a second embodiment will be described with reference to FIG. 11. The distributed amplifier according to the first embodiment is １ to the fourth transistor 1 ４ Each gate node and the corresponding first gate connection point 2 of the gate line 2１ to the fourth gate connection point 2 ４ The first gate input circuit 4 is connected between １ to the fourth gate input circuit 4 ４ is connected.

[0105] In contrast, in the distributed amplifier according to the second embodiment, the first transistor 1 １ to the fourth transistor 1 ４ Each gate node and the corresponding first gate connection point 2 of the gate line 2 １ to the fourth gate connection point 2 ４ 11. The distributed amplifier according to the second embodiment differs from the distributed amplifier according to the first embodiment in that a direct wiring path is used to connect the first and second inputs to the second inputs. In Fig. 11, the same reference numerals as in Fig. 1 indicate the same or corresponding parts. The distributed amplifier according to the second embodiment has the same effects as the distributed amplifier according to the first embodiment.

[0106] Third Embodiment A distributed amplifier according to a third embodiment will be described with reference to Fig. 12. The distributed amplifier according to the third embodiment differs from the distributed amplifier according to the first embodiment in that it has a gate line 2 and a gate input circuit 4. １ ~4 ４ and gate bias voltage application circuit 5 １ ~5 ４ Therefore, the gate line 2 and the first DC blocking capacitor 20b are the same. ２ to the fourth DC blocking capacitor 20b ５ and gate bias voltage application circuit 5 １ ~5 ４ 12, the same reference numerals as in FIG. 1 denote the same or corresponding parts.

[0107] The gate lines 2 are electrically connected between the input terminal 100 and one end of the terminating resistor 7. The gate lines 2 are each connected to the first transistor 1. １ to the fourth transistor 1 ４ A plurality of gate connection points 2 electrically connected to the gate nodes of １ ~2 ４The gate lines 2 are made up of a plurality of inter-gate lines 20 connected between adjacent gate connection points. １ ~20 ５ It has.

[0108] First inter-gate line 20 １ is the input terminal 100 and the first gate connection point 2 １ and the gate side transmission line 20a １ and a capacitor 20b. ２ is the first gate connection point 2 １ and second gate connection point 2 ２ and the gate side transmission line 20a ２ The third inter-gate line 20 ３ is the second gate connection point 2 ２ and the third gate connection point 2 ３ and the gate side transmission line 20a ３ is.

[0109] Fourth inter-gate line 20 ４ is the third gate connection point 2 ３ and the fourth gate connection point 2 ４ and the gate side transmission line 20a ４ The fifth inter-gate line 20 ５ is the fourth gate connection point 2 ４ and one end of the termination resistor 7, and the gate side transmission line 20a ５ is.

[0110] Gate side transmission line 20a １ ~20a ５ Each of them is a microstrip line mounted on a GaN MMIC. １ ~20a ５ Each of them is formed in a meander line shape on the GaN MMIC and functions as an inductor.

[0111] First DC blocking capacitor 20b ２ to the fourth DC blocking capacitor 20b ５ Each of them is a first transistor 1 １ to the fourth transistor 1 ４A first DC blocking capacitor 20b is provided corresponding to each of the first and second DC blocking capacitors. ２ to the fourth DC blocking capacitor 20b ５ Each of them corresponds to the first transistor 1 １ to the fourth transistor 1 ４ Each gate node and the corresponding gate connection point 2 of the gate line 2 １ ~2 ４ and are connected between.

[0112] First DC blocking capacitor 20b ２ to the fourth DC blocking capacitor 20b ５ Each of them is connected to the corresponding first transistor 1 １ to the fourth transistor 1 ４ The gate input circuit 4 in the first embodiment has a function of cutting off the direct current between each gate node and the gate line 2. １ ~4 ４ Capacitor 4b in each １ ~4b ４ The first DC blocking capacitor 20b also functions as a ２ to the fourth DC blocking capacitor 20b ５ Each is a MIM capacitor mounted on a GaN MMIC.

[0113] First gate bias voltage application circuit 5 １ to the fourth gate bias voltage application circuit 5 ４ Each of them is a first transistor 1 １ to the fourth transistor 1 ４ The first gate bias voltage application circuit 5 is provided corresponding to each of the first and second gate bias voltage application circuits. １ to the fourth gate bias voltage application circuit 5 ４ Each of them is connected to a corresponding gate voltage application node 8 １ ~8 ４ and the corresponding transistor 1 １ ~1 ４ It is connected between each of the gate nodes.

[0114] First gate bias voltage application circuit 5 １is the first gate voltage application node 8 １ and the first transistor 1 １ a first gate voltage application inductor 5a connected between the gate nodes of １ and the first gate voltage application node 8 １ and a ground potential node. １ The second gate bias voltage application circuit 5 ２ is the second gate voltage application node 8 ２ and the second transistor 1 ２ a second gate voltage application inductor 5a connected between the gate nodes of ２ and the second gate voltage application node 8 ２ and a second capacitor 5b connected between the ２ It has.

[0115] Third gate bias voltage application circuit 5 ３ is the third gate voltage application node 8 ３ and the third transistor 1 ３ a third gate voltage application inductor 5a connected between the gate nodes of ３ and the third gate voltage application node 8 ３ and a ground potential node. ３ The fourth gate bias voltage application circuit 5 ４ is the fourth gate voltage application node 8 ４ and the fourth transistor 1 ４ a fourth gate voltage application inductor 5a connected between the gate nodes of ４ and the fourth gate voltage application node 8 ４ and a fourth capacitor 5b connected between the ground potential node. ４ It has.

[0116] First gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The corresponding gate bias voltage Vg １ ~Vg ４ is applied to the first DC blocking capacitor 20b. ２to the fourth DC blocking capacitor 20b ５ Each of them activates the corresponding first transistor 1 １ to the fourth transistor 1 ４ A first gate bias voltage application circuit 5 connected to each gate node １ to the fourth gate bias voltage application circuit 5 ４ is cut off from the gate line 2 in terms of DC current.

[0117] As a result, the first transistor 1 １ to the fourth transistor 1 ４ A gate voltage application inductor 5a is connected to each gate node. １ ~5a ４ through the corresponding gate voltage application node 8 １ ~8 ４ Gate bias voltage Vg １ ~Vg ４ are applied individually.

[0118] Gate bias voltage Vg １ ~Vg ４ can be adjusted individually, so that the first transistor 1 １ to the fourth transistor 1 ４ The operating points of each can be adjusted individually, and the output and efficiency can be improved as a distributed amplifier. １ ~Vg ４ can be adjusted individually, so that the first transistor 1 １ to the fourth transistor 1 ４ Each operating class can be changed from Class B operation to Class A operation and Class C operation individually.

[0119] The gate bias voltage Vg １ ~Vg ４ The relationship between Vg １ ≧Vg ２ ≧Vg ３ ≧Vg ４ More preferably, Vg １ >Vg ２ >Vg ３ >Vg ４The gate voltage application inductor 5a １ ~5 ４ Each of them is formed in a spiral shape on the GaN MMIC and functions as an inductor. １ ~5b ４ Each is a MIM capacitor mounted on a GaN MMIC.

[0120] The distributed amplifier according to the third embodiment has a drain voltage supply node 9 １ ~9 ４ and the corresponding drain connection point 3 of the drain line 3 １ ~3 ４ A plurality of drain voltage supply circuits 6 connected between １ ~6 ４ Therefore, the drain efficiency of the entire distributed amplifier is improved.

[0121] In particular, the distributed amplifier according to the third embodiment has a fourth drain voltage supply node 9 located on the output terminal 200 side, similar to the distributed amplifier according to the first embodiment. ４ The first drain voltage supply node 9 located on the input terminal 100 side from １ The drain supply voltage Vd １ ~Vd ４ Decrease Vd １ <Vd ２ <Vd ３ <Vd ４ ) leads to an improvement in the drain efficiency of the entire distributed amplifier, specifically, an improvement in the drain efficiency of the entire distributed amplifier over a wide input signal frequency band from 2.5 GHz to 13 GHz.

[0122] In addition, the distributed amplifier according to the second embodiment has a plurality of inter-gate lines 20 in the gate line 2. ２ ~20 ５ Each of them is a gate side transmission line 20a ２ ~20a ５ and each corresponds to a transistor 1 １ ~1 ４ The gate node of the gate line 2 and the corresponding gate connection point 2 １ ~2４ A plurality of DC blocking capacitors 20b connected between ２ ~20b ５ and the corresponding gate voltage application nodes 8 １ ~8 ４ and the corresponding transistor 1 １ ~1 ４ and a plurality of gate bias voltage application circuits 5 connected between the gate nodes of the １ ~5 ４ Therefore, the fourth gate voltage application node 8 located on the output terminal 200 side ４ The first gate voltage application node 8 located on the input terminal 100 side from １ A gate bias voltage Vg is applied to １ ~Vg ４ Increasing Vg １ >Vg ２ >Vg ３ >Vg ４ ) leads to an improvement in the output power output from the output terminal 200 of the distributed amplifier over a wide frequency band of the input signal from 2.5 GHz to 13 GHz.

[0123] Fourth Embodiment A distributed amplifier according to a fourth embodiment will be described with reference to FIG. 13. The distributed amplifier according to the first embodiment has a first transistor 1 １ to the fourth transistor 1 ４ A gate bias voltage Vg is applied to each gate node. １ ~Vg ４ , which are connected to the first gate voltage application node 8 １ to the fourth gate voltage application node 8 ４ The first gate bias voltage application circuit 5 connected to １ to the fourth gate bias voltage application circuit 5 ４ The voltage was applied via

[0124] In contrast, in the distributed amplifier according to the fourth embodiment, the first transistor 1 １ to the fourth transistor 1 ４ A gate bias voltage Vg is applied to each gate node. １ ~Vg ４is applied via a common gate bias voltage application circuit 5 and a voltage distribution circuit 50, the present embodiment is different from the distributed amplifier according to the first embodiment, and the other points are the same. １ to the fourth transistor 1 ４ A gate bias voltage Vg is applied to each gate node. １ ~Vg ４ The following description will be focused on the gate bias voltage application circuit 5 and the voltage distribution circuit 50. In Fig. 13, the same reference numerals as in Fig. 1 indicate the same or corresponding parts.

[0125] The common gate bias voltage application circuit 5 is connected to the gate voltage application node 8 and the last gate connection point located on the output terminal 200 side of the gate line 2, which is the fourth gate connection point 2 in this fourth embodiment. ４ A gate bias voltage Vgg is applied to the gate voltage application node 8 in the distributed amplifier according to the first embodiment. ４ The gate bias voltage Vg applied to ４ Specifically, it is −2.7V.

[0126] The voltage distribution circuit 50 receives the gate bias voltage Vgg applied to the gate voltage application node 8 via the gate bias voltage application circuit 5, and distributes the voltage to the transistor located on the output terminal 200 side, the fourth transistor 1 in this fourth embodiment. ４ In this fourth embodiment, the first transistor 1 is １ The gate bias voltage is increased in order (Vg １ >Vg ２ >Vg ３ >Vg ４ ) and apply.

[0127] The voltage distribution circuit 50 includes a fourth transistor 1 ４ and a ground node. １ to the fourth transistor 1 ４ The first voltage dividing resistors 50 corresponding to each １to the fourth voltage dividing resistor 50 ４ The first voltage dividing resistor 50 is a resistor series circuit in which the first voltage dividing resistor 50 is connected in series. １ has one end connected to the ground node and the other end connected to the first transistor 1 １ is connected to the gate node of

[0128] Second voltage dividing resistor 50 ２ One end of the resistor 50 is connected to the first voltage dividing resistor 50 １ The other end of the second transistor 1 ２ The third voltage dividing resistor 50 is connected to the gate node of the ３ One end of the resistor 50 is connected to the second voltage dividing resistor 50 ２ The other end of the third transistor 1 ３ is connected to the gate node of

[0129] Fourth voltage dividing resistor 50 ４ One end of the resistor 50 is connected to the third voltage dividing resistor 50. ３ The other end of the fourth transistor 1 ４ The first voltage dividing resistor 50 is connected to the gate node of the first voltage dividing resistor 50. １ to the fourth voltage dividing resistor 50 ４ Each is a resistor mounted on a GaN MMIC.

[0130] Inter-gate line 20 in gate line 2 １ ~20 ５ Each capacitor 20b １ ~20b ５ As a result, the input terminal 100 and the gate connection point 2 １ During this time, the gate connection point 2 on the gate line 2 １ ~2 ４ and the gate connection point 2 on the gate line 2 ４ and one end of the termination resistor 7 is cut off.

[0131] Therefore, the first voltage dividing resistor 50 １ to the fourth voltage dividing resistor 50 ４ Each resistance value is Rg １ ~Rg ４ Then, the second voltage dividing resistor 50 ２ to the fourth voltage dividing resistor 50４ The voltage drop across each of these transistors causes the first transistor 1 １ to the third transistor 1 ３ The gate bias voltage Vg applied to each １ to Vg ３ is expressed by the following equations (7) to (9).

[0132] Vg ３ = Vg ４ -Rg ４ ×Ig (7) Vg ２ = Vg ３ -Rg ３ ×Ig=Vg ４ -Rg ４ ×Ig-Rg ３ ×Ig =Vg ４ -(Rg ４ +Rg ３ ) × Ig (8) Vg １ = Vg ２ -Rg ２ ×Ig=Vg ４ -Rg ４ ×Ig-Rg ３ ×Ig-Rg ２ ×Ig =Vg ４ -(Rg ４ +Rg ３ +Rg ２ ) × Ig (9)

[0133] In the above equations (7) to (9), Ig is the first voltage dividing resistor 50 １ to the fourth voltage dividing resistor 50 ４ The fourth gate bias voltage Vg ４ is set to -2.7 V, so as can be understood from the above equations (7) to (9) with the ground potential of the ground potential node as the reference, Vg １ >Vg ２ >Vg ３ >Vg ４ The following relationship holds.

[0134] In addition, the first voltage dividing resistor 50 １ to the fourth voltage dividing resistor 50 ４ Each resistance value Rg １~Rg ４ By setting Vg ４ to -2.7V, V g ３ to -2.5V, Vg ２ to -2.2V, Vg １ can be set to −1.7 V. The distributed amplifier according to the fourth embodiment has the same effects as the distributed amplifier according to the first embodiment.

[0135] It should be noted that the embodiments may be freely combined, or any of the components in each embodiment may be modified, or any of the components in each embodiment may be omitted.

[0136] The distributed amplifier according to the present disclosure is suitable for use as a high-frequency amplifier that amplifies high-frequency signals transmitted and received by wireless communication devices, radar devices, and the like.

[0137] 100 Input terminal, 200 Output terminal, 1 １ ~1 ４ Transistor, 2 Gate line, 20 １ ~20 ５ Inter-gate line, 20a １ ~20a ５ Gate side transmission line, 20b １ ~20b ５ Capacitor, 3 Drain line, 30 １ ~30 ４ Drain-to-drain line, 4 １ ~4 ４ Gate input circuit, 5 １ ~5 ４ Gate bias voltage application circuit, 5a １ ~Ta5a ４ Inductor for applying gate voltage, 6 １ ~6 ４ Drain voltage supply circuit, 6a １ ~6a ４ Drain voltage supply inductor, 7 Termination resistor, 8 １ ~8 ４ Gate voltage application node, 9 １ ~9 ４ Drain voltage supply node, 50 １ ~50 ４ Voltage division resistor.

Claims

1. A distributed amplifier comprising: a plurality of transistors, each having a grounded source node; a gate line electrically connecting between an input terminal and a gate node of a last transistor located on the output terminal side, the gate nodes of the plurality of transistors being electrically connected to one another, and the gate line having a plurality of gate connection points to which the gate nodes of the plurality of transistors are electrically connected, and a plurality of inter-gate lines each connected between adjacent gate connection points; a drain line electrically connecting between a drain node of a first transistor located on the input terminal side and the output terminal, the drain nodes of the plurality of transistors being electrically connected to one another, and the inter-drain lines each being a series circuit of a drain-side transmission line and a capacitor, the inter-drain lines each connected between adjacent drain connection points; and a plurality of drain voltage supply circuits each connected between a drain voltage supply node and a corresponding drain connection point of the drain line.

2. A distributed amplifier according to claim 1, wherein, at each of the drain voltage supply nodes to which the plurality of drain voltage supply circuits are connected, the drain supply voltage supplied to the drain voltage supply node located on the input terminal side of adjacent drain voltage supply nodes is equal to or lower than the drain supply voltage supplied to the drain voltage supply node located on the output terminal side.

3. A distributed amplifier according to claim 1, wherein at each of the drain voltage supply nodes to which the plurality of drain voltage supply circuits are connected, the drain supply voltages supplied from the drain voltage supply node located on the output terminal side to the drain voltage supply node located on the input terminal side are sequentially decreased.

4. A distributed amplifier according to any one of claims 1 to 3, wherein each of the plurality of inter-gate lines in the gate line is a series circuit of a gate-side transmission line and a capacitor.

5. A distributed amplifier according to any one of claims 1 to 4, comprising a plurality of gate input circuits, each connected between the gate node of a corresponding transistor and a corresponding gate connection point of said gate line.

6. A distributed amplifier according to claim 5, wherein each of said plurality of gate input circuits is a parallel circuit of a resistor and a capacitor.

7. A distributed amplifier according to claim 5, comprising a plurality of gate bias voltage application circuits, each connected between a gate voltage application node and a corresponding gate connection point of said gate line.

8. A distributed amplifier according to claim 7, wherein, at each of the gate voltage application nodes to which the plurality of gate bias voltage application circuits are connected, the gate bias voltage applied to the gate voltage application node located on the input terminal side of adjacent gate voltage application nodes is equal to or higher than the gate bias voltage applied to the gate voltage application node located on the output terminal side.

9. A distributed amplifier as claimed in claim 7, wherein at each of the gate voltage application nodes to which the plurality of gate bias voltage application circuits are connected, the gate bias voltages applied from the gate voltage application node located on the output terminal side to the gate voltage application node located on the input terminal side are increased in order.

10. A distributed amplifier according to any one of claims 1 to 3, wherein each of the plurality of inter-gate lines in the gate line is a gate-side transmission line, and further comprising: a plurality of DC blocking capacitors each connected between the gate node of a corresponding transistor and a corresponding gate connection point of the gate line; and a plurality of gate bias voltage application circuits each connected between a corresponding gate voltage application node and the gate node of a corresponding transistor.

11. A distributed amplifier according to claim 10, wherein, at each of the gate voltage application nodes to which the plurality of gate bias voltage application circuits are connected, the gate bias voltage applied to the gate voltage application node located on the input terminal side of adjacent gate voltage application nodes is equal to or higher than the gate bias voltage applied to the gate voltage application node located on the output terminal side.

12. A distributed amplifier according to claim 10, wherein at each of the gate voltage application nodes to which the plurality of gate bias voltage application circuits are connected, the gate bias voltages applied are increased in order from the gate voltage application node located on the output terminal side to the gate voltage application node located on the input terminal side.

13. A distributed amplifier according to any one of claims 1 to 3, comprising: each of the plurality of inter-gate lines in the gate line is a series circuit of a gate-side transmission line and a capacitor; a gate bias voltage application circuit connected to a gate voltage application node and a final gate connection point located on the output terminal side of the gate line; and a voltage distribution circuit that receives the gate bias voltage applied to the gate voltage application node via the gate bias voltage application circuit and applies gate bias voltages in increasing order from the gate node of the transistor located on the output terminal side to the gate node of the transistor located on the input terminal side.

14. A distributed amplifier according to claim 13, wherein the voltage division circuit is a resistor series circuit in which voltage division resistors corresponding to each of the plurality of transistors are connected in series between the gate node of a transistor located on the output terminal side and a ground node.

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