Semiconductor device and method for manufacturing same

Abstract

A wiring layer (20) includes a connection wire (413) and a resistance (R) comprising a resistance wire (422b) thinner than the connection wire (413). An electrode (85) connected to the connection wire (413) is disposed in a connection wire contact hole (75) that exposes the connection wire (413). Electrodes (83, 84) connected to the resistance (R) are disposed in resistance contact holes (73, 74) that expose the resistance (R). The resistance (R) comprises: stopper wires (422a, 423a) composed of conductive material and disposed in portions where the resistance contact holes (72, 73) are formed; and the resistance wire (422b), which is disposed on the stopper wires (422a, 423a). A stopper layer (52) composed of a material different from that of insulating films (32-34) is disposed on portions of the resistor (R) in which the resistance contact holes (72, 73) are formed.

Description

Semiconductor device and manufacturing method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-071961, filed on April 25, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] For example, Patent Document 1 proposes a semiconductor device having a wiring layer disposed on a substrate. Specifically, the wiring layer in this semiconductor device is configured to have portions where insulating films and wiring portions are alternately stacked. The wiring portion has connection wiring and a resistor formed of resistive wiring that is disposed on an insulating film different from the insulating film on which the connection wiring is disposed and that is thinner than the connection wiring.

[0004] The wiring layer is formed with contact holes exposing the connection wiring and contact holes exposing the resistance wiring, and electrodes connected to the connection wiring and resistance wiring are embedded in each contact hole. Note that the contact holes exposing the connection wiring and the contact holes exposing the resistance wiring have different depths because the insulating film on which the connection wiring is disposed is different from the insulating film on which the resistance wiring is disposed.

[0005] Japanese Patent Application Laid-Open No. 2019-186407

[0006] In the semiconductor device described above, the present inventors have considered simultaneously forming contact holes of different depths, one exposing a connection wiring and the other exposing a resistance wiring. However, if contact holes of different depths are simultaneously formed, the contact holes may penetrate the thin resistance wiring that constitutes the resistor, which may result in poor connection between the electrode disposed in the contact hole and the resistance wiring.

[0007] The present disclosure aims to provide a semiconductor device and a manufacturing method thereof that can suppress the occurrence of poor connections between electrodes placed in contact holes and resistors when contact holes of different depths are formed simultaneously.

[0008] According to one aspect of the present disclosure, a semiconductor device comprises a substrate having one surface, and a wiring layer disposed on the one surface and having a portion in which a plurality of insulating films and a plurality of wiring portions are alternately stacked, the wiring layer having connection wiring and a resistor including a resistive wiring that is thinner than the connection wiring and disposed on an insulating film different from the insulating film on which the connection wiring is disposed, connection wiring contact holes exposing the connection wiring are formed, and electrodes connected to the connection wiring are disposed in the connection wiring contact holes, resistor contact holes exposing the resistor and having a depth different from the connection wiring contact holes are formed, and electrodes connected to the resistor are disposed in the resistor contact holes, the resistor is made of a conductive material and is composed of a stopper wiring disposed in a portion where the resistor contact hole is formed, and a resistance wiring disposed on the stopper wiring, and a stopper layer made of a material different from the insulating film is disposed on the portion of the resistor where the resistor contact hole is formed.

[0009] According to this, the portion of the resistor that connects to the electrode disposed in the resistor contact hole is configured by stacking stopper wiring and resistor wiring. A stopper layer is disposed on the resistor wiring. Therefore, even if the resistor contact hole and the connection wiring contact hole with different depths are formed simultaneously, the resistor contact hole can be prevented from penetrating the resistor. Therefore, poor connection between the resistor and the electrode disposed in the resistor contact hole can be prevented.

[0010] According to another aspect of the present disclosure, the method for manufacturing the semiconductor device described above includes preparing a substrate having one surface, repeatedly forming an insulating film and forming a wiring portion, and simultaneously forming a resistor contact hole and a connection wiring contact hole to form a wiring layer, and forming the wiring layer includes forming the connection wiring, arranging a stopper wiring and a resistor wiring on an insulating film different from the insulating film on which the connection wiring is arranged, and arranging a stopper layer on the resistor wiring, and when forming the resistor contact hole and the connection wiring contact hole, the stopper layer is used as an etching stopper layer, and first dry etching is performed to form the resistor contact hole reaching the stopper layer and the connection wiring contact hole reaching the connection wiring, second dry etching is performed to dig down the resistor contact hole so that the resistor contact hole penetrates the stopper layer and reaches the resistor wiring, and reverse sputtering is performed on the resistor wiring exposed from the resistor contact hole and the connection wiring exposed from the connection wiring contact hole.

[0011] According to this, the portion of the resistor that connects to the electrode disposed in the resistor contact hole is configured by stacking a stopper wiring and a resistor wiring. A stopper layer is disposed on the resistor wiring. Therefore, by using the stopper layer as an etching stopper when performing the first dry etching and using the stopper wiring as a stopper when performing the second dry etching and reverse sputtering, resistor contact holes and connection wiring contact holes of different depths can be formed simultaneously. This prevents poor connection between the resistor and the electrode disposed in the resistor contact hole.

[0012] 4B. A cross-sectional view of a semiconductor device according to a first embodiment. FIG. 4C. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4D. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4E. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4G. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4H. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4I. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4J. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4K. A cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4L ...

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0014] (First Embodiment) A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitable for use, for example, in a vehicle and for driving various electronic components mounted on the vehicle. First, the configuration of the semiconductor device of this embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view taken along line II in FIG. 2.

[0015] The semiconductor device includes a substrate 10 made of a silicon substrate or the like. Semiconductor elements such as diodes and transistors are formed on the substrate 10, although not shown. A wiring layer 20 having a portion where first to fourth interlayer insulating films 31 to 34 and first to third wiring portions 41 to 43 are alternately stacked, and having a resistor R and a capacitor C therein, is disposed on one surface 10a of the substrate 10. Hereinafter, the region where the capacitor C is formed will be referred to as a capacitor region RC, the region where the resistor R is formed will be referred to as a resistor region RR, and the region different from the capacitor region RC and the resistor region RR will be referred to as a wiring region RW. Note that the wiring region RW is a region different from the capacitor region RC and the resistor region RR, and does not mean that connection wiring 413, etc., described below, is formed only in the wiring region RW.

[0016] Specifically, a first interlayer insulating film 31 is formed on one surface 10a of the substrate 10. The first interlayer insulating film 31 is a silicon oxide film (SiO ２ ), a carbon-doped silicon dioxide film (SiOC), a fluorine-doped silicon dioxide film (SiOF), a tetraethoxysilane film (TEOS), etc. Second to fourth interlayer insulating films 32 to 34, which will be described later, are made of the same material as the first interlayer insulating film 31. However, the materials that make up the first to fourth interlayer insulating films 31 to 34 can be changed as appropriate, and they may be made of different materials.

[0017] A first wiring portion 41 is formed on the first interlayer insulating film 31. In this embodiment, the first wiring portion 41 is formed to include a lower electrode 411, a dummy wiring 412, and a connection wiring 413 of the capacitor C. More specifically, the lower electrode 411 is formed in the capacitor region RC, the dummy wiring 412 is formed in the resistor region RR, and the connection wiring 413 is formed in the wiring region RW.

[0018] In this embodiment, the connection wiring 413 is formed from the wiring region RW to the resistor region RR, and a portion of the connection wiring 413 faces a resistor R (described later) in the resistor region RR. In this embodiment, two dummy wirings 412 are formed, each facing a resistor R (described later). The first wiring portion 41 is made of a common electrode material, and in this embodiment, it is made of a laminate of titanium nitride (TiN), aluminum (Al), and titanium nitride. The third wiring portion 43 (described later) is made of the same material as the first wiring portion 41. However, the materials constituting the first wiring portion 41 and the third wiring portion 43 can be changed as appropriate, and may be made of a single layer of aluminum, for example. The first wiring portion 41 and the third wiring portion 43 may also be made of different materials.

[0019] A second interlayer insulating film 32 is formed on the first interlayer insulating film 31 so as to cover the first wiring portion 41. A hole 32a is formed in the second interlayer insulating film 32 to expose the lower electrode 411 of the first wiring portion 41. In this embodiment, the hole 32a is tapered so that its width narrows from the opening side toward the lower electrode 411 side.

[0020] A first oxidation prevention film 51 is disposed on the second interlayer insulating film 32. Specifically, the first oxidation prevention film 51 is formed on the second interlayer insulating film 32 around the hole 32a in the capacitor region RC and in the resistor region RR. The first oxidation prevention film 51 is made of, for example, a silicon nitride film (SiN) or a nitrogen-doped silicon carbide film (SiCN) that has low moisture permeability.

[0021] Furthermore, on the second interlayer insulating film 32, a capacitance film 60 is formed in the capacitor region RC and the resistor region RR. Specifically, the capacitance film 60 in the capacitor region RC is formed on the wall surface of the hole 32a and on the lower electrode 411 exposed from the hole 32a, and is also arranged on the first oxidation prevention film 51 arranged around the hole 32a. In this embodiment, the capacitance film 60 formed in the resistor region RR is arranged between a first stopper wiring 422a (to be described later) and the first oxidation prevention film 51, and between a second stopper wiring 423a (to be described later) and the first oxidation prevention film 51, and is arranged in two separate locations. The capacitance film 60 may be formed of a silicon oxide film, a silicon nitride film, a tantalum oxide (Ta ２ O ５ ) etc.

[0022] Then, a second wiring portion 42 is formed in the capacitor region RC and the resistor region RR on the second interlayer insulating film 32. The second wiring portion 42 of this embodiment is configured by stacking a lower-layer second wiring portion 42 a and an upper-layer second wiring portion 42 b.

[0023] The lower-layer second wiring portion 42a is formed in the capacitor region RC to include a first upper electrode 421a that is disposed opposite the lower electrode 411 and constitutes the capacitor C. The first upper electrode 421a is disposed on the capacitance film 60 and also around the hole 32a. The lower-layer second wiring portion 42a is formed in the resistor region RR to include a first stopper wiring 422a and a second stopper wiring 423a that are disposed on the capacitance film 60. More specifically, the first stopper wiring 422a and the second stopper wiring 423a are formed separately, with the first stopper wiring 422a disposed on one side of the separated capacitance film 60 and the second stopper wiring 423a disposed on the other side of the separated capacitance film 60. In this embodiment, the lower-layer second wiring portion 42a is made of titanium nitride. That is, the first stopper wiring 422a and the second stopper wiring 423a are made of a conductive material.

[0024] The upper-layer second wiring portion 42b has a second upper electrode 421b disposed on the first upper electrode 421a in the capacitor region RC. Therefore, the upper electrode 421 in the capacitor C of this embodiment is configured to include the first upper electrode 421a and the second upper electrode 421b. In this embodiment, the capacitor C has a so-called metal-insulator-metal (i.e., MIM) structure, including the lower electrode 411, the upper electrode 421, and the capacitance film 60 located between the lower electrode 411 and the upper electrode 421.

[0025] The upper-layer second wiring portion 42b is disposed on the first stopper wiring 422a and the second stopper wiring 423a in the resistance region RR, and is formed to include the resistance wiring 422b disposed between the first stopper wiring 422a and the second stopper wiring 423a. The upper-layer second wiring portion 42b is made of tantalum nitride (TaN) and is thinner than the lower-layer second wiring portion 42a, the first wiring portion 41, and the third wiring portion 43.

[0026] In the resistance region RR, the first stopper wiring 422a, the second stopper wiring 423a, and the resistance wiring 422b are each made of a conductive material, and therefore, as shown in Figure 3, the resistance R is made up of the first stopper wiring 422a, the second stopper wiring 423a, and the resistance wiring 422b.

[0027] Here, the properties of the resistor R in this embodiment will be described. As described above, the resistor R in this embodiment is configured to include the first stopper wiring 422a, the second stopper wiring 423a, and the resistive wiring 422b, each of which has a resistance temperature coefficient. For example, if the first stopper wiring 422a and the second stopper wiring 423a are configured from titanium nitride, the resistance temperature coefficient is 460 ppm / °C. If the resistive wiring 422b is configured from tantalum nitride, the resistance temperature coefficient is −60 ppm / °C. In other words, the signs of the resistance temperature coefficients of the first stopper wiring 422a and the second stopper wiring 423a and the resistive wiring 422b in this embodiment are opposite. Therefore, by configuring the first stopper wiring 422a and the second stopper wiring 423a from titanium nitride and configuring the resistive wiring 422b from tantalum nitride, as in this embodiment, the resistance temperature coefficient of the entire resistor R can be made to approach zero more easily.

[0028] Furthermore, when the first stopper wiring 422a and the second stopper wiring 423a are made of titanium nitride and the resistive wiring 422b is made of tantalum nitride, the absolute value of the temperature coefficients of resistance of the first stopper wiring 422a and the second stopper wiring 423a is greater than that of the resistive wiring 422b. Therefore, in this embodiment, the resistive wiring 422b is arranged so that its area is greater than that of the first stopper wiring 422a and the second stopper wiring 423a, so that the overall temperature coefficient of resistance of the resistor R approaches 0 ppm / °C. In this embodiment, the first stopper wiring 422a and the second stopper wiring 423a are arranged separately, as described above. The resistive wiring 422b is arranged on the first stopper wiring 422a, on the second stopper wiring 423a, and between the first stopper wiring 422a and the second stopper wiring 423a, so that the area of ​​the resistive wiring 422b is larger than that of the first stopper wiring 422a and the second stopper wiring 423a.

[0029] In this embodiment, the outer edge of the first upper electrode 421a, the first stopper wiring 422a, and the second stopper wiring 423a are respectively disposed on the first antioxidant film 51 and the capacitance film 60 on the second interlayer insulating film 32. Therefore, the outer edge of the first upper electrode 421a, the first stopper wiring 422a, and the second stopper wiring 423a are located on the same plane. Similarly, the outer edge of the second upper electrode 421b and the resistance wiring 422b are located on the same plane. In this embodiment, by arranging parts made of the same material on the same plane and allowing them to be processed in the same process, the manufacturing process can be simplified.

[0030] Furthermore, the outer edge portions of the first upper electrode 421a and the second upper electrode 421b are aligned in the stacking direction (hereinafter simply referred to as the stacking direction) of the first to fourth interlayer insulating films 31 to 34 and the first to third wiring portions 41 to 43. In other words, the first upper electrode 421a and the second upper electrode 421b are formed so that the end faces of the outer edge portions are located on the same plane along the stacking direction. This reduces the parasitic capacitance formed between the first upper electrode 421a and the lower electrode 411, for example, compared to when the first upper electrode 421a protrudes from the second upper electrode 421b. Note that the stacking direction can also be referred to as the normal direction relative to the surface 10a of the substrate 10.

[0031] On the upper-layer second wiring portion 42b, in the capacitor region RC and the resistor region RR, a second oxidation prevention film 52 and an internal insulating film 53 are disposed in this order from the upper-layer second wiring portion 42b side. Like the first oxidation prevention film 51, the second oxidation prevention film 52 is composed of a silicon nitride film, a nitrogen-doped silicon carbide film, or the like, which has low moisture permeability. The second oxidation prevention film 52 also functions as an etching stopper, is composed of a different material from the second to fourth interlayer insulating films 32 to 34, and corresponds to a stopper layer. The internal insulating film 53, which will be described in detail later, is used as a mask when the first oxidation prevention film 51, the capacitance film 60, the second wiring portion 42, and the second oxidation prevention film 52 are collectively patterned, and may not be provided.

[0032] A third interlayer insulating film 33 is disposed on the second interlayer insulating film 32 so as to cover the second wiring portion 42 and the like, and a fourth interlayer insulating film 34 is disposed on the third interlayer insulating film 33. The fourth interlayer insulating film 34 functions as a cap insulating film, and seals off any foreign matter that is exposed from the surface of the third interlayer insulating film 33 opposite to the substrate 10 side.

[0033] In the capacitor region RC, an upper electrode contact hole 71 is formed, which penetrates the fourth interlayer insulating film 34, the third interlayer insulating film 33, the internal insulating film 53, and the second antioxidant film 52 to reach the upper electrode 421. In addition, in the capacitor region RC, a lower electrode contact hole 72 is formed, which penetrates the fourth interlayer insulating film 34, the third interlayer insulating film 33, and the second interlayer insulating film 32 to expose the lower electrode 411.

[0034] In the resistor region RR, a first resistor contact hole 73 is formed, penetrating the fourth interlayer insulating film 34, the third interlayer insulating film 33, the internal insulating film 53, and the second oxidation resistant film 52 to reach a portion of the resistor wiring 422b located above the first stopper wiring 422a. In the resistor region RR, a second resistor contact hole 74 is formed, penetrating the fourth interlayer insulating film 34, the third interlayer insulating film 33, the internal insulating film 53, and the second oxidation resistant film 52 to reach a portion of the resistor wiring 422b located above the second stopper wiring 423a. More specifically, in this embodiment, the first resistor contact hole 73 is formed to penetrate the resistor wiring 422b to reach the first stopper wiring 422a. The second resistor contact hole 74 is formed to penetrate the resistor wiring 422b to reach the second stopper wiring 423a.

[0035] In the wiring region RW, a contact hole 75 for connection wiring is formed, which penetrates the fourth interlayer insulating film 34 , the third interlayer insulating film 33 and the second interlayer insulating film 32 and reaches the connection wiring 413 .

[0036] In this embodiment, the lower electrode contact hole 72 and the connection wiring contact hole 75 have the same depth. Furthermore, the first resistor contact hole 73 and the second resistor contact hole 74 have the same depth. However, the lower electrode contact hole 72 and the connection wiring contact hole 75, the first resistor contact hole 73 and the second resistor contact hole 74, and the upper electrode contact hole 71 have different depths. Furthermore, in this embodiment, the first resistor contact hole 73 and the second resistor contact hole 74 are shallower than the other contact holes 71, 72, and 75.

[0037] A first electrode 81 is disposed in the upper electrode contact hole 71, and a second electrode 82 is disposed in the lower electrode contact hole 72. A third electrode 83 is disposed in the first resistor contact hole 73, and a fourth electrode 84 is disposed in the second resistor contact hole 74. A fifth electrode 85 is disposed in the connection wiring contact hole 75. In this embodiment, the first to fifth electrodes 81 to 85 are configured by first to fifth buried electrodes 81b to 85b disposed via first to fifth barrier metal films 81a to 85a. The first to fifth barrier metal films 81a to 85a are configured, for example, by stacked films of titanium and titanium nitride, and the first to fifth buried electrodes 81b to 85b are configured by tungsten plugs. In this way, by configuring the first to fifth electrodes 81 to 85 to include tungsten plugs, the size of the opening of each contact hole 71 to 75 can be made smaller than when the first to fifth electrodes 81 are configured by embedding the third wiring portion 43 described below, thereby improving the degree of freedom in design.

[0038] A third wiring portion 43 is formed on the fourth interlayer insulating film 34. Specifically, the third wiring portion 43 is formed to include an upper electrode wiring portion 431 and a lower electrode wiring portion 432 arranged in the capacitor region RC, a first resistor wiring portion 433, a second resistor wiring portion 434, and a dummy wiring portion 435 arranged in the resistor region RR, and a connection wiring portion 436 arranged in the wiring region RW.

[0039] The upper electrode wiring portion 431 formed in the capacitor region RC is connected to the upper electrode 421 via the first electrode 81, and the lower electrode wiring portion 432 is connected to the lower electrode 411 via the second electrode 82. The first resistor wiring portion 433 formed in the resistor region RR is connected to a portion of the resistor R on the first stopper wiring 422a side via the third electrode 83. The second resistor wiring portion 434 formed in the resistor region RR is connected to a portion of the resistor R on the second stopper wiring 423a side via the fourth electrode 84. In this embodiment, the dummy wiring portion 435 is disposed between the first resistor wiring portion 433 and the second resistor wiring portion 434, and is disposed so as to face a portion of the resistor wiring 422b located between the first stopper wiring 422a and the second stopper wiring 423a. The dummy wiring portion 435 is intended to prevent moisture from above the fourth interlayer insulating film 34 from penetrating into the wiring layer 20. The connection wiring wiring portion 436 formed in the wiring region RW is connected to the connection wiring 413 via the fifth electrode 85 .

[0040] The above is the configuration of the semiconductor device in this embodiment. The first to third wiring portions 41 to 43 are only a part of the configuration of the semiconductor device, and are also formed as appropriate in a cross section different from that shown in Figure 1. The first to third wiring portions 41 to 43 formed in a cross section different from that shown in Figure 1 are electrically connected through connection vias formed in the first to fourth interlayer insulating films 31 to 34 as appropriate.

[0041] Next, a method for manufacturing the semiconductor device will be described with reference to FIGS. 4A to 4M.

[0042] First, as shown in FIG. 4A , a substrate 10 on which semiconductor elements are formed is prepared. A first interlayer insulating film 31 is then formed on the substrate 10 by, for example, CVD (Chemical Vapor Deposition) or the like. Then, a metal layer including titanium nitride, aluminum, and titanium nitride stacked together is formed on the first interlayer insulating film 31 by, for example, sputtering or the like. A photoresist mask (not shown) is then placed on the metal layer, and dry etching is performed to form a first wiring portion 41 including a lower electrode 411, dummy wiring 412, and connection wiring 413. Then, a second interlayer insulating film 32 is formed on the first interlayer insulating film 31 by, for example, CVD so as to cover the first wiring portion 41. Next, the surface of the second interlayer insulating film 32 opposite the substrate 10 side is planarized by, for example, CMP (Chemical Mechanical Polishing) or the like. Then, a first oxidation prevention film 51 is then formed on the second interlayer insulating film 32 by, for example, CVD or the like.

[0043] 4B, photoresist 100 is placed on the first oxidation prevention film 51 and patterned, and dry etching is performed using the photoresist 100 as a mask to form a hole 32a that exposes the lower electrode 411. Thereafter, the photoresist 100 is removed by ashing or the like.

[0044] 4C, the capacitance film 60 and the lower-layer second wiring portion 42a are sequentially disposed. The capacitance film 60 is disposed by, for example, a CVD method, and the lower-layer second wiring portion 42a is disposed by a sputtering method or the like.

[0045] 4D, photoresist 110 is disposed on the lower-layer second wiring portion 42a and patterned. Then, dry etching is performed using the photoresist 110 as a mask to simultaneously pattern the lower-layer second wiring portion 42a and the capacitance film 60, thereby forming a first upper electrode 421a, a first stopper wiring 422a, and a second stopper wiring 423a.

[0046] In this process, the lower-layer second wiring portion 42a is patterned to form the first upper electrode 421a, the first stopper wiring 422a, and the second stopper wiring 423a, but the outer edge is patterned slightly larger than the final shape. Specifically, in this process, the outer edge of the first upper electrode 421a is made slightly larger in the surface direction. The first stopper wiring 422a is made slightly larger in the surface direction on the side opposite the second stopper wiring 423a. The second stopper wiring 423a is made slightly larger in the surface direction on the side opposite the first stopper wiring 422a.

[0047] 4E, the upper-layer second wiring portion 42b, the second oxidation prevention film 52, and the internal insulating film 53 are sequentially arranged. The upper-layer second wiring portion 42b is arranged by a sputtering method or the like, and the second oxidation prevention film 52 and the internal insulating film 53 are arranged by a CVD method or the like.

[0048] 4F , photoresist 120 is disposed on the internal insulating film 53 and patterned, and dry etching is performed using the photoresist 120 as a mask to pattern the internal insulating film 53. Specifically, the internal insulating film 53 is patterned so that the internal insulating film 53 remains only on the portion that will ultimately form the resistor R and the portion that will ultimately form the upper electrode 421.

[0049] In this embodiment, the connection wiring 413 extends to the resistance region RR and has a portion facing the portion that becomes the resistance R. In this case, when exposure is performed to pattern the photoresist 120, reflection differs between the portion where the connection wiring 413 is arranged and the portion where the connection wiring 413 is not arranged, which may reduce the accuracy of patterning. For this reason, in this embodiment, a dummy wiring 412 is arranged in the resistance region RR to suppress the difference in reflection between the portion where the connection wiring 413 is arranged and the portion where the connection wiring 413 is not arranged in the region below the portion that becomes the resistance R.

[0050] 4G , after the photoresist 120 is removed by ashing or the like, dry etching is performed using the internal insulating film 53 as a mask (i.e., a hard mask) to simultaneously pattern the second oxidation prevention film 52, the second wiring portion 42, the capacitance film 60, and the first oxidation prevention film 51. As a result, a capacitor C having the lower electrode 411, the upper electrode 421, and the capacitance film 60 is formed, and a resistor R having the first stopper wiring 422 a, the second stopper wiring 423 a, and the resistance wiring 422 b is formed.

[0051] 4H , a third interlayer insulating film 33 is disposed by CVD or the like, and the surface of the third interlayer insulating film 33 opposite the substrate 10 side is planarized by CMP or the like. During this process, metallic foreign matter or the like generated in each process may be exposed from the surface of the third interlayer insulating film 33 opposite the substrate 10 side, which may cause a short circuit or the like. For this reason, in this embodiment, a fourth interlayer insulating film 34 serving as a cap insulating film is further disposed on the third interlayer insulating film 33 by CVD or the like.

[0052] 4I and 4J, contact holes 71 for the upper electrode, contact holes 72 for the lower electrode, contact holes 73 for the first resistor, contact holes 74 for the second resistor, and contact holes 75 for the connecting wiring are formed simultaneously. In other words, contact holes of different depths are formed simultaneously.

[0053] In this embodiment, first, as shown in FIG. 4I , photoresist 130 is disposed on the fourth interlayer insulating film 34 and patterned. Then, a first dry etching process is performed using the photoresist 130 as a mask to form an upper electrode contact hole 71, a lower electrode contact hole 72, a first resistor contact hole 73, a second resistor contact hole 74, and a connection wiring contact hole 75. Specifically, the first dry etching process is performed by adjusting the selectivity so that the second oxidation prevention film 52 serves as an etching stopper. As a result, the upper electrode contact hole 71, the first resistor contact hole 73, and the second resistor contact hole 74 are formed to reach the second oxidation prevention film 52. The lower electrode contact hole 72 and the connection wiring contact hole 75 are each formed to reach the first wiring portion 41.

[0054] 4J, the photoresist 130 is removed by ashing or the like. Then, a second dry etching is performed by adjusting the selectivity to penetrate the second oxidation prevention film 52, so that the upper electrode contact hole 71, the first resistor contact hole 73, and the second resistor contact hole 74 reach the upper layer second wiring portion 42b. At this time, the lower electrode contact hole 72 and the connection wiring contact hole 75 are also slightly removed, but because the lower electrode 411 and the connection wiring 413 are made of thick metal, the slight removal by the second dry etching does not pose any particular problem.

[0055] When removing the photoresist 130 or between steps, the second upper electrode 421b exposed from the upper electrode contact hole 71 and the lower electrode 411 exposed from the lower electrode contact hole 72 may be oxidized to form a natural oxide film. Also, the resistor wiring 422b exposed from the first resistor contact hole 73 and the second resistor contact hole 74 and the connection wiring 413 exposed from the connection wiring contact hole 75 may be oxidized to form a natural oxide film. For this reason, in this embodiment, a reverse sputtering method is performed to remove the natural oxide film.

[0056] Note that, when performing the second dry etching or reverse sputtering, the first resistor contact hole 73 and the second resistor contact hole 74 may penetrate the resistor wiring 422b because the resistor wiring 422b is thin. For this reason, in this embodiment, the first stopper wiring 422a and the second stopper wiring 423a are arranged below the resistor wiring 422b so that the first stopper wiring 422a and the second stopper wiring 423a serve as stoppers even if the first resistor contact hole 73 and the second resistor contact hole 74 penetrate the resistor wiring 422b. For this reason, when the third electrode 83 and the fourth electrode 84 are arranged as described below, connection between the resistor R and the third electrode 83 and the fourth electrode 84 can be prevented from being made only through the side surfaces of the first resistor contact hole 73 and the second resistor contact hole 74, thereby preventing connection defects from occurring.

[0057] In this embodiment, the upper electrode contact hole 71, the lower electrode contact hole 72, the first resistor contact hole 73, the second resistor contact hole 74, and the connection wiring contact hole 75 are formed simultaneously in this manner.

[0058] Next, as shown in FIG. 4K , in a vacuum state during reverse sputtering, titanium and titanium nitride are deposited in sequence by sputtering or the like to form first to fifth barrier metal films 81 a to 85 a. Thereafter, as shown in FIG. 4L , the vacuum state is released, and tungsten is deposited by CVD or the like to form first to fifth buried electrodes 81 b to 85 b that fill the upper electrode contact hole 71, the lower electrode contact hole 72, the first resistor contact hole 73, the second resistor contact hole 74, and the connection wiring contact hole 75, thereby forming the first to fifth electrodes 81 b to 85 b. Subsequently, as shown in FIG. 4M , the material constituting the first to fifth barrier metal films 81 a to 85 a and the material constituting the first to fifth buried electrodes 81 b to 85 b that are disposed on the fourth interlayer insulating film 34 is removed by CMP or the like to expose the fourth interlayer insulating film 34.

[0059] Thereafter, although not particularly shown, the third wiring portion 43 is disposed on the fourth interlayer insulating film 34 by a sputtering method or the like. Then, the third wiring portion 43 is patterned to form an upper electrode wiring portion 431, a lower electrode wiring portion 432, a first resistor wiring portion 433, a second resistor wiring portion 434, a dummy wiring portion 435, and a connection wiring portion 436, thereby manufacturing the semiconductor device shown in FIG.

[0060] According to the embodiment described above, the portion of the resistor R connected to the third electrode 83 arranged in the first resistor contact hole 73 is configured by stacking the first stopper wiring 422a and the resistor wiring 422b. The portion of the resistor R connected to the fourth electrode 84 arranged in the second resistor contact hole 74 is configured by stacking the second stopper wiring 423a and the resistor wiring 422b. The second oxidation prevention film 52 is disposed on the resistor wiring 422b. Therefore, even if the first resistor contact hole 73 and the second resistor contact hole 74 are formed simultaneously with the upper electrode contact hole 71, the lower electrode contact hole 72, and the connection wiring contact hole 75, which have different depths, the first resistor contact hole 73 and the second resistor contact hole 74 can be prevented from penetrating the resistor R. This can prevent poor connection between the resistor R and the third electrode 83 arranged in the first resistor contact hole 73 and the fourth electrode 84 arranged in the second resistor contact hole 74.

[0061] (1) In this embodiment, the resistor R is configured by stacking the first stopper wiring 422a and the second stopper wiring 423a, which have temperature coefficients of resistance with opposite signs, and the resistive wiring 422b. Therefore, for example, compared to when the resistor R is configured only by the resistive wiring 422b, the temperature coefficient of resistance of the resistor R can be made closer to 0.

[0062] (2) In this embodiment, the absolute values ​​of the resistance temperature coefficients of the first stopper wiring 422 a and the second stopper wiring 423 a are set to be larger than the resistance temperature coefficient of the resistive wiring 422 b. Therefore, in this embodiment, the resistive wiring 422 b is arranged so that its area is larger than the areas of the first stopper wiring 422 a and the second stopper wiring 423 a. This makes it easier to bring the resistance temperature coefficient of the resistor R closer to 0.

[0063] (3) In this embodiment, the wiring layer 20 is configured to include a capacitor C. The upper electrode 421 of the capacitor C is configured by stacking a first upper electrode 421a made of the same material as the first stopper wiring 422a and the second stopper wiring 423a, and a second upper electrode 421b made of the same material as the resistance wiring 422b. Therefore, the material of the resistor R can be the same as the material of the upper electrode 421 of the capacitor C.

[0064] (4) In this embodiment, the outer edge of the first upper electrode 421a, the first stopper wiring 422a, and the second stopper wiring 423a are located on the same plane. Similarly, the outer edge of the second upper electrode 421b and the resistance wiring 422b are located on the same plane. Therefore, the resistor R and the upper electrode 421 can be processed in the same process, which simplifies the manufacturing process.

[0065] (5) In this embodiment, the outer edges of the first upper electrode 421 a and the second upper electrode 421 b are aligned in the stacking direction, which reduces the parasitic capacitance between the first upper electrode 421 a and the lower electrode 411 compared to when the first upper electrode 421 a protrudes from the second upper electrode 421 b.

[0066] (6) In this embodiment, the first resistor contact hole 73 and the second resistor contact hole 74 are shallower than the upper electrode contact hole 71, the lower electrode contact hole 72, and the connecting wiring contact hole 75. This makes it easier to form the capacitor C by forming the hole 32a as in this embodiment and arranging the upper electrode 421 in this hole 32a.

[0067] Second Embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the resistor R is changed. As the other features are the same as those of the first embodiment, a description thereof will be omitted here.

[0068] 5, in this embodiment, the first stopper wiring 422a and the second stopper wiring 423a are combined into one stopper wiring 424a. The resistive wiring 422b is disposed over the entire stopper wiring 424a. The resistive wiring 422b is disposed over the entire stopper wiring 424a, and has the same area as the resistive wiring 422b.

[0069] 6, in this semiconductor device, the resistor R is configured by connecting the stopper wiring 424a and the resistance wiring 422b in parallel. Compared to the first embodiment, the stopper wiring 424a is not separated from the resistor R, so that the resistance value of the resistor R can be easily reduced.

[0070] Such a semiconductor device is manufactured by forming one stopper wiring 424a when patterning the second wiring portion 42 in the step of FIG. 4D.

[0071] (1) In this embodiment, the resistive wiring 422b is disposed over the entire stopper wiring 424a and has the same area as the stopper wiring 424a. This makes it easier to reduce the resistance value of the resistor R.

[0072] According to the present embodiment described above, the portion of the resistor R that is connected to the third electrode 83 arranged in the first resistor contact hole 73 is configured by laminating a first stopper wiring 422a and a resistor wiring 422b. The portion of the resistor R that is connected to the fourth electrode 84 arranged in the second resistor contact hole 74 is configured by laminating a second stopper wiring 423a and a resistor wiring 422b. The second oxidation prevention film 52 is disposed on the resistor wiring 422b. Therefore, the same effects as those of the first embodiment can be obtained.

[0073] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0074] For example, in each of the above embodiments, the capacitor C may not be provided in the wiring layer 20. Furthermore, in each of the above embodiments, when the capacitor C is provided in the wiring layer 20, the upper electrode 421 of the capacitor C and the resistor R may not be made of the same material. Furthermore, when the capacitor C is provided in the wiring layer 20, the outer edge of the upper electrode 421 of the capacitor C and the resistor R may not be formed on the same plane. Furthermore, when the capacitor C is provided in the wiring layer 20, the outer edge surfaces of the first upper electrode 421a and the second upper electrode 421b of the capacitor C along the stacking direction may not be aligned.

[0075] Furthermore, in each of the above embodiments, the first resistor contact hole 73 and the second resistor contact hole 74 may be deeper than the upper electrode contact hole 71, the lower electrode contact hole 72, and the connecting wiring contact hole 75.

[0076] In each of the above embodiments, the dummy wiring 412 and the dummy wiring portion 435 arranged in the resistor region RR may be configured as connection wiring that is connected to other components or the like, depending on how the wiring portion is routed.

[0077] Furthermore, in each of the above-described embodiments, the materials constituting the lower-layer second wiring portion 42 a and the upper-layer second wiring portion 42 b can be changed as appropriate. For example, the lower-layer second wiring portion 42 a may be made of chromium silicon (CrSi) or the like.

[0078] In the above embodiments, the semiconductor device has been described with one resistor R and one capacitor C as an example, but the number of resistors R and capacitors C can be changed as appropriate. For example, when a plurality of resistors R are provided, paired resistors may be configured. When configuring paired resistors, the accuracy of the paired resistors can be improved by making the configuration of the portion located closer to the substrate 10 than each resistor R the same and the configuration of the portion located opposite the substrate 10 than each resistor R the same.

[0079] [Disclosure of the Present Invention] The above-described disclosure can be understood from the following perspectives, for example. [First Aspect] A semiconductor device comprising: a substrate (10) having one surface (10a); and a wiring layer (20) disposed on the one surface and having a portion in which a plurality of insulating films (31-34) and a plurality of wiring portions (41-43) are alternately stacked, the wiring layer having connection wiring (413) and a resistor (R) including resistive wiring (422b) that is thinner than the connection wiring and disposed on an insulating film different from the insulating film on which the connection wiring is disposed, a connection wiring contact hole (75) exposing the connection wiring is formed, and an electrode (85) connected to the connection wiring is disposed in the connection wiring contact hole, resistor contact holes (73, 74) exposing the resistor and having a depth different from that of the connection wiring contact hole are formed, and electrodes (83, 84) connected to the resistor are disposed in the resistor contact holes, a stopper layer (52) made of a material different from that of the insulating film is disposed on the portion of the resistor where the resistor contact hole is formed. [Second Aspect] The semiconductor device according to the first aspect, wherein the resistive wiring and the stopper wiring are made of materials having opposite signs of the temperature coefficient of resistance. [Third Aspect] The semiconductor device according to the second aspect, wherein the resistor is arranged on an oxidation prevention film (51), the resistive wiring and the stopper wiring are made of a material whose absolute value of the temperature coefficient of resistance of the resistive wiring is smaller than that of the stopper wiring, the stopper wiring has a first stopper wiring (422a) and a second stopper wiring (423a) arranged separately, the resistive wiring is arranged on the first stopper wiring and the second stopper wiring, and is arranged on the oxidation prevention film between the first stopper wiring and the second stopper wiring, and has an area larger than that of the stopper wiring. [Fourth Aspect]The semiconductor device according to the second aspect, wherein the stopper wiring is formed to be continuous, and the resistance wiring is formed over the entire stopper wiring. [Fifth Aspect] The semiconductor device according to any one of the first to fourth aspects, wherein the wiring layer has, in two of the plurality of wiring portions opposing each other in a stacking direction of the insulating film and the wiring portions, a lower electrode (411) on the substrate side and an upper electrode (421) on the opposite side to the substrate side, and a capacitor (C) having a capacitance film (60) between the upper electrode and the lower electrode, and the upper electrode is configured by stacking a first upper electrode (421a) made of the same material as the stopper wiring and a second upper electrode (421b) made of the same material as the resistance wiring. [Sixth Aspect] The semiconductor device according to the fifth aspect, wherein the stopper wiring and an outer edge of the first upper electrode are located on the same plane, the resistance wiring and an outer edge of the second upper electrode are located on the same plane, and the stopper layer is disposed on the upper electrode. [Seventh Aspect] A semiconductor device according to the fifth or sixth aspect, in which the first upper electrode and the second upper electrode have outer edge portions aligned in the stacking direction. [Eighth Aspect] A semiconductor device according to any one of the fifth to seventh aspects, in which the lower electrode is disposed on an insulating film different from the insulating film on which the resistor is disposed. [Ninth Aspect] A semiconductor device according to any one of the first to eighth aspects, in which the resistor contact hole is shallower in depth than the connection wiring contact hole. [Tenth Aspect] A semiconductor device comprising: a substrate (10) having one surface (10a); and a wiring layer (20) disposed on the one surface, the wiring layer (20) having a portion in which a plurality of insulating films (31-34) and a plurality of wiring portions (41-43) are alternately stacked,the wiring layer has a connection wiring (413) and a resistor (R) comprising a resistance wiring (422b) thinner than the connection wiring and arranged on an insulating film different from the insulating film on which the connection wiring is arranged, a connection wiring contact hole (75) exposing the connection wiring is formed, and an electrode (85) connected to the connection wiring is arranged in the connection wiring contact hole, a resistor contact hole (73, 74) exposing the resistor and having a depth different from that of the connection wiring contact hole is formed, and an electrode (83, 84) connected to the resistor is arranged in the resistor contact hole, the resistor is made of a conductive material and comprises stopper wiring (422a, 423a, 424a) arranged in a portion where the resistor contact hole is formed, and the resistor wiring arranged on the stopper wiring, and a stopper layer (52) made of a material different from the insulating film is arranged on a portion of the resistor where the resistor contact hole is formed. A method for manufacturing a semiconductor device comprising: preparing the substrate having the one surface; forming the wiring layer by repeatedly forming the insulating film and the wiring portion and simultaneously forming the resistor contact hole and the connection wiring contact hole, and forming the wiring layer by forming the connection wiring, and arranging the stopper wiring and the resistor wiring on the insulating film different from the insulating film on which the connection wiring is arranged, and arranging the stopper layer on the resistor wiring,A method for manufacturing a semiconductor device, comprising the steps of: performing a first dry etching process using the stopper layer as an etching stopper layer when forming the resistor contact holes and the connection wiring contact holes, forming the resistor contact holes that reach the stopper layer and the connection wiring contact holes that reach the connection wiring; performing a second dry etching process to dig down the resistor contact holes so that the resistor contact holes reach the resistor wiring by penetrating the stopper layer; and performing a reverse sputtering process on the resistor wiring exposed from the resistor contact holes and the connection wiring exposed from the connection wiring contact holes.

Claims

1. A semiconductor device comprising: a substrate (10) having one surface (10a); and a wiring layer (20) disposed on the surface and having a portion in which a plurality of insulating films (31-34) and a plurality of wiring portions (41-43) are alternately laminated; the wiring layer has connection wiring (413) and a resistor (R) comprising a resistive wiring (422b) that is thinner than the connection wiring and disposed on an insulating film different from the insulating film on which the connection wiring is disposed; connection wiring contact holes (75) exposing the connection wiring are formed, and electrodes (85) connected to the connection wiring are disposed in the connection wiring contact holes; resistor contact holes (73, 74) exposing the resistor and having a depth different from that of the connection wiring contact holes are formed, and electrodes (83, 84) connected to the resistor are disposed in the resistor contact holes; The resistor is made of a conductive material and includes stopper wiring (422a, 423a, 424a) arranged in a portion where the resistor contact hole is formed, and the resistor wiring arranged on the stopper wiring, and a stopper layer (52) made of a material different from the insulating film is arranged on the portion of the resistor where the resistor contact hole is formed.

2. The semiconductor device according to claim 1, wherein the resistive wiring and the stopper wiring are made of materials having temperature coefficients of resistance with opposite signs.

3. The semiconductor device according to claim 2, wherein the resistor is arranged on an oxidation prevention film (51), the resistive wiring and the stopper wiring are made of a material whose absolute value of the temperature coefficient of resistance of the resistive wiring is smaller than the absolute value of the temperature coefficient of resistance of the stopper wiring, the stopper wiring has a first stopper wiring (422a) and a second stopper wiring (423a) arranged separately, and the resistive wiring is arranged on the first stopper wiring and the second stopper wiring, and is arranged on the oxidation prevention film between the first stopper wiring and the second stopper wiring, and has an area larger than that of the stopper wiring.

4. The semiconductor device according to claim 2, wherein the stopper wiring is formed to be continuous, and the resistance wiring is formed over the entire stopper wiring.

5. The semiconductor device according to claim 1, wherein the wiring layer has a capacitor (C) having a capacitance film (60) between the upper electrode (421) and the wiring portion on the substrate side as a lower electrode (411) and the wiring portion on the opposite side to the substrate side as an upper electrode (421), in two of the plurality of wiring portions that are opposed in the stacking direction of the insulating film and the wiring portions, and the upper electrode is formed by stacking a first upper electrode (421a) made of the same material as the stopper wiring and a second upper electrode (421b) made of the same material as the resistance wiring.

6. The semiconductor device according to claim 5, wherein the stopper wiring and the outer edge of the first upper electrode are located on the same plane, the resistive wiring and the outer edge of the second upper electrode are located on the same plane, and the stopper layer is disposed on the upper electrode.

7. The semiconductor device according to claim 5 or 6, wherein the outer edge portions of the first upper electrode and the second upper electrode are aligned in the stacking direction.

8. The semiconductor device according to claim 5 or 6, wherein the lower electrode is disposed on an insulating film different from the insulating film on which the resistor is disposed.

9. The semiconductor device according to claim 1, wherein the resistor contact hole is shallower in depth than the connection wiring contact hole.

10. A substrate (10) having one surface (10a), and a wiring layer (20) disposed on the surface and having a portion in which a plurality of insulating films (31-34) and a plurality of wiring portions (41-43) are alternately laminated, wherein the wiring layer has connection wiring (413) and a resistor (R) comprising a resistive wiring (422b) thinner than the connection wiring and disposed on an insulating film different from the insulating film on which the connection wiring is disposed, a connection wiring contact hole (75) exposing the connection wiring is formed, and an electrode (85) connected to the connection wiring is disposed in the connection wiring contact hole, and resistor contact holes (73, 74) exposing the resistor and having a depth different from that of the connection wiring contact hole are formed, and electrodes (83, 84) connected to the resistor are disposed in the resistor contact hole, the resistor is made of a conductive material and includes stopper wiring (422a, 423a, 424a) arranged in a portion where the resistor contact hole is to be formed, and the resistor wiring arranged on the stopper wiring, and a stopper layer (52) made of a material different from that of the insulating film is arranged on the portion of the resistor where the resistor contact hole is to be formed. A method for manufacturing a semiconductor device, comprising: preparing the substrate having the one surface; repeatedly forming the insulating film and the wiring portion; and simultaneously forming the resistor contact hole and the connection wiring contact hole, thereby forming the wiring layer; forming the wiring layer includes forming the connection wiring; and arranging the stopper wiring and the resistor wiring on the insulating film different from the insulating film on which the connection wiring is to be arranged; and arranging the stopper layer on the resistor wiring;A method for manufacturing a semiconductor device, comprising the steps of: performing a first dry etching process using the stopper layer as an etching stopper layer when forming the resistor contact holes and the connection wiring contact holes, forming the resistor contact holes that reach the stopper layer and the connection wiring contact holes that reach the connection wiring; performing a second dry etching process to dig down the resistor contact holes so that the resistor contact holes reach the resistor wiring by penetrating the stopper layer; and performing a reverse sputtering process on the resistor wiring exposed from the resistor contact holes and the connection wiring exposed from the connection wiring contact holes.

Images