Encapsulated superconducting quantum flip chip and fabrication method

Abstract

The present invention relates to an encapsulated superconducting quantum flip chip and a fabrication method. The encapsulated superconducting quantum flip chip comprises, arranged to be stacked, a first substrate, a first superconducting thin film, metal fences, a second superconducting thin film and a second substrate. The first superconducting thin film comprises a first circuit layer; the second superconducting thin film comprises a second circuit layer and a Josephson junction; the metal fences surround the peripheries of the first circuit layer, the second circuit layer and the Josephson junction. The structural design of the metal fences helps to first make the metal fences and then fabricate a circuit structure and the Josephson junction. Further provided is a fabrication method for the encapsulated superconducting quantum flip chip, which helps to improve the performance of quantum bit devices.

Description

A wrap-around superconducting quantum flip chip and a preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum devices, and in particular to a wrap-around superconducting quantum flip chip and a preparation method thereof. BACKGROUND

[0002] With the deepening of quantum computing research, superconducting quantum computing schemes have made significant breakthroughs in multiple key indicators. For example, in the operation of single-bit and double-bit quantum gates, the fidelity has reached and exceeded the important thresholds of 99.9% and 99%, respectively. The number of qubits, an important indicator of quantum computing performance, has successfully broken through 100. This makes the superconducting quantum computing scheme have great potential in realizing practical applications, and thus has attracted widespread attention from all walks of life. However, as the number of bits continues to increase, the traditional single-plane integration method has been unable to meet the growing demand for bit integration, which has become a major challenge for superconducting quantum computing. In order to overcome this challenge, researchers have begun to explore new solutions to achieve larger-scale integration of quantum bits.

[0003] In order to solve the problem of large-scale integration of quantum bits on a single plane, advanced packaging technologies are introduced into the preparation of superconducting quantum chips. These technologies, such as flip-chip bonding and TSV technology, can split the circuit structure onto multiple planes and achieve efficient connection between these planes through precise alignment and compression bonding processes. The introduction of this method not only solves the limitations of single-plane integration, but also provides the possibility for superconducting quantum chips to develop towards higher bit numbers. Through the application of these advanced packaging technologies, the preparation efficiency and reliability of superconducting quantum chips have been significantly improved.

[0004] However, the preparation of the flip-chip bonding chip of the current commonly used superconducting quantum chip is generally to first prepare the corresponding circuit structure on two independent chip planes, then make a large number of dispersedly arranged indium columns on the two chip circuit planes respectively, and finally use a flip-chip bonding device to align the two chips, align the upper and lower indium columns one by one, and compress bond to the preset height to realize the electrical interconnection of the upper and lower chips. This process will reduce the performance of the existing bits. SUMMARY

[0005] To solve the above technical problems, the present application provides a wrap-around superconducting quantum flip chip and a preparation method thereof.

[0006] To achieve the above purpose, the present application provides a wrap-around superconducting quantum flip chip, comprising a first substrate, a first superconducting thin film, a metal fence, a second superconducting thin film and a second substrate which are stacked,

[0007] The first superconducting thin film comprises a first circuit layer; and the second superconducting thin film comprises a second circuit layer and a Josephson junction.

[0008] The metal fence surrounds the periphery of the first circuit layer, the second circuit layer and the Josephson junction.

[0009] Based on the above scheme, the metal fence surrounds the periphery of the first circuit layer, the second circuit layer and the Josephson junction, which facilitates the preparation of the metal fence before the preparation of the circuit structure or the Josephson junction in the process of preparing the wrap-around superconducting quantum flip chip, so as to improve the performance of the quantum bit device.

[0010] As a further improvement of the present application, a first recess is arranged on the surface of the first substrate adjacent to the second substrate and / or a second recess is arranged on the surface of the second substrate adjacent to the first substrate, the first circuit layer is located in the first recess, and the second circuit layer and the Josephson junction are located in the second recess. In the process of pressure welding, the height and area of the metal fence are not easy to control, and this kind of structure design is beneficial to reduce the requirement for the height of the metal fence and realize high-precision control.

[0011] As a further improvement of the present application, a third recess is arranged on the surface of the first substrate adjacent to the second substrate and a fourth recess is arranged on the surface of the second substrate adjacent to the first substrate, and the two ends of the metal fence are respectively embedded into the third recess and the fourth recess. This kind of structure design is beneficial to realize the sunken design of the metal fence, and in the process of pressure welding of the upper top sheet and the lower bottom sheet, the substrate at the edge of the recess realizes the limiting action, so that the metal fence is limited in the recess, which is beneficial to accurately control the sheet spacing and uniformity between the upper top sheet and the lower bottom sheet, and improve the performance of the quantum bit device.

[0012] As a further improvement of the present application, the first substrate, the second substrate and the metal fence form a closed cavity, and the first circuit layer, the second circuit layer and the Josephson junction are all located in the closed cavity. This kind of structure design is beneficial to completely wrap the circuit structure and the Josephson junction in the metal fence, realizes the complete self-isolation of the chip circuit structure from the external environment, and reduces the influence of the chip performance caused by the pollution of the external environment noise.

[0013] As a further improvement of the present application, a third superconducting thin film is further arranged on the surface of the first substrate away from the first superconducting thin film, the third superconducting thin film comprises a third circuit layer, a TSV through hole for filling superconducting material is arranged on the first substrate, the metal fence surrounds the periphery of the TSV through hole, and the first circuit layer is electrically interconnected with the third circuit layer through the superconducting material in the TSV through hole.

[0014] Based on the above scheme, since the TSV through hole is arranged on the first substrate, and the TSV through hole is filled with superconducting material, it is beneficial to arrange the third circuit layer on the surface of the first substrate away from the first superconducting film, and the area of the chip is greatly reduced.

[0015] As a further improvement of the present application, the materials of the first substrate and the second substrate are selected from one or more of the following: sapphire, intrinsic silicon;

[0016] The materials of the first superconducting film, the second superconducting film and the third superconducting film are selected from one or more of the following: niobium-based superconducting material, tantalum-based superconducting material, TiN-based superconducting material, NbN-based superconducting material, NbTiN-based superconducting material, Al-based superconducting material;

[0017] The metal fence is an indium column.

[0018] As a further improvement of the present application, the superconducting material is any one or several of aluminum, indium, TiN, NbN, NbTiN.

[0019] As a further improvement of the present application, the first circuit layer can include a resonant cavity, a read line and a control line, etc., the second circuit layer can be a cross bit capacitor, etc., and the third circuit layer can be a PAD circuit structure, etc.

[0020] To achieve the above object, the present application also provides a preparation method of a wrapped superconducting quantum flip chip, comprising the following steps:

[0021] Preparation of the lower bottom sheet:

[0022] A1, take a first substrate, the first substrate includes opposite first and second surfaces, clean the first surface of the first substrate, and then deposit a first superconducting film on the first surface of the first substrate;

[0023] A2, prepare a first metal fence and a first circuit layer on the first superconducting film, the first metal fence is arranged to surround the edge of the first surface of the first substrate;

[0024] Preparation of the upper top sheet:

[0025] B1, take a second substrate, the second substrate includes opposite first and second surfaces, clean the first surface of the second substrate, and then deposit a second superconducting film on the first surface of the second substrate;

[0026] B2, first, a second metal wall is prepared on the second superconducting thin film, the second metal wall is arranged to surround the edge of the surface of the second substrate; second, a second circuit layer and a Josephson junction are prepared on the second superconducting thin film in sequence, the second metal wall is arranged outside the second circuit layer and the Josephson junction;

[0027] Preparation of the device:

[0028] In a vacuum environment, the lower substrate and the upper substrate are respectively installed on a flip-chip device, the lower substrate and the upper substrate are parallel, and the first metal wall and the second metal wall are arranged one by one, the flip-chip device is used to apply pressure to the lower substrate and the upper substrate, the first metal wall and the second metal wall are welded and connected, and a preset height is formed, so as to realize the bonding connection of the lower substrate and the upper substrate, and the preset height can be 20 μm, 15 μm, 10 μm, 5 μm, 2 μm, etc.

[0029] Based on the above scheme, the upper substrate of the quantum bit device is prepared in the process of manufacturing, the metal column is prepared first, and the preparation process of the circuit structure and the Josephson junction is prepared, which avoids the influence of the preparation of the metal column on the quantum bit assembly, and improves the bit performance of the quantum bit device.

[0030] As a further improvement of the present application, in step A1: before depositing the first superconducting thin film on the first surface of the first substrate, further comprising: preparing a first groove on the first surface of the first substrate, the first metal wall is arranged outside the first groove; and / or;

[0031] In step B1, before depositing the second superconducting thin film on the first surface of the second substrate, further comprising: preparing a second groove on the first surface of the second substrate, the second metal wall is arranged outside the second groove.

[0032] Based on the above scheme, the first groove and / or the second groove are arranged, which is conducive to accommodating the circuit structure, and can also reduce the height requirement of the metal wall.

[0033] As a further improvement of the present application, in step A1: before depositing the first superconducting thin film on the first surface of the first substrate, further comprising: preparing a third groove on the first surface of the first substrate, the first metal wall is arranged in the third groove;

[0034] In step B1, before depositing the second superconducting thin film on the first surface of the second substrate, further comprising: preparing a fourth groove on the first surface of the second substrate, the second metal wall is arranged in the fourth groove.

[0035] Based on the above scheme, in the process of flip welding and pressure welding, the metal column can be limited in the third groove and the fourth groove due to the influence of the third groove and the fourth groove, so as to realize accurate control of the compression height and the occupying area of the metal wall.

[0036] As a further improvement of the present application, in step A1, before depositing the first superconducting thin film on the first surface of the first substrate, further comprising: preparing a TSV through hole on the first substrate, the first metal wall is arranged outside the TSV through hole, and the TSV through hole is filled with superconducting material.

[0037] As a further improvement of the present application, in the preparation of the lower negative, further comprising step A3: after cleaning the second surface of the first substrate, depositing a third superconducting thin film on the second surface of the first substrate, and preparing a third circuit layer on the third superconducting thin film.

[0038] As a further improvement of the present application, the method for cleaning the surface of the substrate can be as follows: soaking the first substrate and the second substrate in a solvent, ultrasonic cleaning, and blowing the first substrate and the second substrate with nitrogen gas after the ultrasonic cleaning is completed; preferably, the solvent is acetone or isopropyl alcohol; preferably, the power of the ultrasonic is 50-1000W, more preferably 90W; preferably, the time of the ultrasonic is 1-30 minutes, more preferably 10 minutes; or; soaking the first substrate and the second substrate in a buffer oxide etching solution (BOE), rinsing, drying, etc.

[0039] As a further improvement of the present application, the process of depositing the first superconducting thin film, the second superconducting thin film or the first superconducting thin film can be one or more of but not limited to magnetron sputtering, electron beam evaporation, etc.

[0040] As a further improvement of the present application, the process of preparing the first groove, the second groove, the third groove, the fourth groove and the TSV through hole can be one or more of but not limited to photolithography process, etching process, deep silicon etching process, etc.

[0041] As a further improvement of the present application, the process of preparing the first circuit layer, the second circuit layer, the third circuit layer and the Josephson junction can be one or more of but not limited to photolithography process, etching process, thin film deposition process, oxygen oxidation process, degumming process, cleaning process, etc.

[0042] As a further improvement of the present application, the process of filling the TSV through hole can be one or more of but not limited to metal melting filling, PVD, CVD, ALD, electroplating, etc.

[0043] As a further improvement of the application, the depth of the first groove, the second groove, the third groove and the fourth groove can be adjusted according to the specific circuit structure, for example, the depth of the first groove can be 2-12 μm, the depth of the second groove can be 2-12 μm, the depth of the third groove can be 0.5-5.5 μm, and the depth of the fourth groove can be 0.5-5.5 μm.

[0044] As a further improvement of the application, the thickness of the first superconducting film, the second superconducting film and the third superconducting film can also be adjusted according to the circuit structure, for example, the thickness of the first superconducting film can be 50-500 nm, the thickness of the second superconducting film can be 50-500 nm, and the thickness of the third superconducting film can be 50-500 nm, etc.

[0045] As a further improvement of the application, the shape and height of the metal fence can be adjusted according to the circuit structure, for example, the shape of the metal fence can be, but is not limited to, a circle, a square, a rectangle, etc., and the height of the metal fence can be 0.5-20 μm, etc.

[0046] As a further improvement of the application, the process for preparing the first metal fence and / or the second metal fence can be, but is not limited to, magnetron sputtering, electron beam evaporation, etc.

[0047] The application has the following advantages:

[0048] The application provides a wrapped superconducting quantum flip chip and a preparation method thereof. The wrapped superconducting quantum flip chip comprises a first substrate, a first superconducting film, a metal fence, a second superconducting film and a second substrate which are arranged in layers, the first superconducting film comprises a first circuit layer, the second superconducting film comprises a second circuit layer and a Josephson junction, and the metal fence surrounds the periphery of the first circuit layer, the second circuit layer and the Josephson junction. In the application, the metal fence arranged in a large number in the circuit area is adjusted to the periphery of the circuit, the metal fence is prepared first and then the circuit layer is prepared, and the influence of the preparation of the metal column on the bit performance is effectively avoided. BRIEF DESCRIPTION OF DRAWINGS

[0049] Fig. 1 is a process flow diagram of the preparation method of the wrapped superconducting quantum flip chip of Example 4;

[0050] Fig. 2 is a process flow diagram of the preparation method of the wrapped superconducting quantum flip chip of Example 8;

[0051] Fig. 3 is a top view structural schematic diagram of the wrapped superconducting quantum flip chip of Example 9. DETAILED DESCRIPTION

[0052] The technical solutions of the present application will be described clearly and completely below in conjunction with the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0053] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below in conjunction with specific embodiments.

[0054] Embodiment 1

[0055] Preparation of the lower bottom sheet:

[0056] A1, take a first substrate, the material of the first substrate is intrinsic silicon, the first substrate includes opposite first and second surfaces, the first surface of the first substrate and the second surface of the first substrate are both polished surfaces, clean the first surface of the first substrate by using BOE (Buffered Oxide Etch), then deposit a first superconducting thin film on the first surface of the first substrate, the material of the first superconducting thin film is tantalum (Ta) based superconducting material, and the thickness of the first superconducting thin film is 100 nm;

[0057] A2, first, prepare a first circuit layer on the first superconducting thin film by using a photolithography process and an etching process; second, define a first metal fence area by using a photolithography process, remove the oxide layer on the surface of the first superconducting thin film at the first metal fence area by using ion beam milling (Ion Beam Milling), and evaporate a first metal fence on the first metal fence area by using an electron beam evaporation process, the height of the first metal fence is 10 μm, the material of the first metal fence is In, the first metal fence is arranged to surround the edge of the first surface of the first substrate, and a first metal fence is obtained;

[0058] Preparation of the upper top sheet:

[0059] B1, take a second substrate, the material of the second substrate is intrinsic silicon, the second substrate includes opposite first and second surfaces, the first surface of the second substrate is a polished surface, and the second surface of the second substrate is a rough surface, clean the first surface of the second substrate by using BOE, then deposit a second superconducting thin film on the first surface of the second substrate, the material of the second superconducting thin film is tantalum based superconducting material, and the thickness of the second superconducting thin film is 100 nm;

[0060] B2, first, a second metal fence is prepared on the second superconducting thin film, the second metal fence is arranged to surround the edge of the surface of the second substrate, specifically as follows: a second metal fence area is defined by using a photolithography process, an oxidation layer on the surface of the second superconducting thin film at the second metal fence area is removed by using ion beam milling, the second metal fence is evaporated on the second metal fence area by using an electron beam evaporation process, the height of the second metal fence is 10 μm, and the material of the second metal fence is In; second, a second circuit layer is prepared on the second superconducting thin film by using a photolithography process and an etching process, a Josephson junction pattern is defined on the second superconducting thin film by using a photolithography process, an oxidation layer of the second superconducting thin film is removed by using an ion beam process, a layer of Al film with a thickness of about 30 nm is deposited, oxygen is introduced for oxidation, a layer of Al film with a thickness of about 60 nm is deposited, and finally, a Josephson junction is prepared by peeling off the adhesive and cleaning.

[0061] Preparation of the device:

[0062] In a vacuum environment, the lower base sheet and the upper top sheet are respectively installed on a flip chip bonding device, the lower base sheet and the upper top sheet are parallel, and the first metal fence and the second metal fence are arranged one by one, the flip chip bonding device is used to apply pressure to the lower base sheet and the upper top sheet, the first metal fence and the second metal fence are welded and connected, and a height of 10 μm is formed, so as to realize the bonding connection of the lower base sheet and the upper top sheet.

[0063] Embodiment 2

[0064] The difference between this embodiment and embodiment 1 is that in step A1, before depositing the first superconducting thin film on the first surface of the first substrate, a first groove with a depth of about 10 μm is prepared on the first surface of the first substrate by using a photolithography process and an etching process, and the first metal fence is arranged to surround the outside of the first groove. At this time, the height of the corresponding first metal fence is 2 μm, and the height of the corresponding second metal fence is 2 μm.

[0065] Embodiment 3

[0066] The difference between this embodiment and embodiment 2 is that in step A1, before preparing the first groove, a third groove with a depth of about 1 μm is prepared on the first surface of the first substrate by using a photolithography process and an etching process, and the first metal fence is located in the third groove; in step B1, before depositing the second superconducting thin film on the first surface of the second substrate, a fourth groove with a depth of about 1 μm is prepared on the first surface of the second substrate, and the second metal fence is located in the fourth groove.

[0067] Embodiment 4

[0068] The difference between this embodiment and embodiment 3 is that, in step A1, after the first recess is prepared, a TSV via hole is prepared to the second surface of the first substrate by using a photolithography process, a deep silicon etching process, the TSV via hole is filled with a molten superconducting material solution, and then the excess superconducting material is removed by using a CMP polishing technique, and the superconducting material is aluminum.

[0069] In step A2, after the first circuit layer is prepared and before the first metal enclosure is prepared, the first surface of the first substrate on which the first circuit layer is located is protected by uniform glue, the oxide layer on the silicon surface of the second surface of the first substrate and the oxide layer on the surface of the TSV via hole are removed by using an ion beam milling, a third superconducting thin film is deposited on the second surface of the first substrate, the material of the third superconducting thin film is a Ta-based superconducting material, the thickness of the third superconducting thin film is 100 nm, and a third circuit layer is prepared on the third superconducting thin film. The process flow chart of the preparation method of the wrapped superconducting quantum flip chip of this embodiment is shown in FIG. 1.

[0070] Embodiment 5

[0071] The difference between this embodiment and embodiment 1 is that, in step B1, before the second superconducting thin film is deposited on the first surface of the second substrate, a second recess with a depth of about 10 μm is prepared on the first surface of the second substrate, and the second metal enclosure is arranged outside the second recess. At this time, the height of the corresponding first metal enclosure is 2 μm, and the height of the corresponding second metal enclosure is 2 μm.

[0072] Embodiment 6

[0073] The difference between this embodiment and embodiment 1 is that, in step A1, before the first superconducting thin film is deposited on the first surface of the first substrate, a first recess with a depth of about 8 μm is prepared on the first surface of the first substrate by using a photolithography process and an etching process, and the first metal enclosure is arranged outside the first recess.

[0074] In step B1, before the second superconducting thin film is deposited on the first surface of the second substrate, a second recess with a depth of about 2 μm is prepared on the first surface of the second substrate, and the second metal enclosure is arranged outside the second recess.

[0075] At this time, the height of the corresponding first metal enclosure is 2 μm, and the height of the corresponding second metal enclosure is 2 μm.

[0076] Embodiment 7

[0077] The difference between this embodiment and embodiment 1 is that in step A1, before the first superconducting thin film is deposited on the first surface of the first substrate, a TSV via hole is prepared to the second surface of the first substrate by using a photolithography process and a deep silicon etching process on the first surface of the first substrate, the first metal fence is arranged outside the TSV via hole, and then the excess superconducting material is removed by using a CMP polishing technique, and the superconducting material is aluminum.

[0078] In step A2, after the first circuit layer is prepared and before the first metal fence is prepared, the first surface of the first substrate on which the first circuit layer is located is protected by uniform glue, the oxide layer on the silicon surface of the second surface of the first substrate and the oxide layer on the surface metal of the TSV via hole are removed by using an ion beam milling, a third superconducting thin film is deposited on the second surface of the first substrate, the material of the third superconducting thin film is a Ta-based superconducting material, the thickness of the third superconducting thin film is 100 nm, and a third circuit layer is prepared on the third superconducting thin film.

[0079] Embodiment 8

[0080] The difference between this embodiment and embodiment 6 is that in step A1, before the first recess is prepared, a third recess with a depth of about 1 μm is prepared on the first surface of the first substrate by using a photolithography process and an etching process, and the first metal fence is located in the third recess; after the first recess is prepared, a TSV via hole is prepared to the second surface of the first substrate in the first recess by using a photolithography process and a deep silicon etching process, the TSV via hole is filled with a molten superconducting material solution, and then the excess superconducting material is removed by using a CMP polishing technique, and the superconducting material is aluminum.

[0081] In step A2, after the first circuit layer is prepared and before the first metal fence is prepared, the first surface of the first substrate on which the first circuit layer is located is protected by uniform glue, the oxide layer on the silicon surface of the second surface of the first substrate and the oxide layer on the surface metal of the TSV via hole are removed by using an ion beam milling, a third superconducting thin film is deposited on the second surface of the first substrate, the material of the third superconducting thin film is a Ta-based superconducting material, the thickness of the third superconducting thin film is 100 nm, and a third circuit layer is prepared on the third superconducting thin film.

[0082] In step B1, before the second superconducting thin film is deposited on the first surface of the second substrate, a fourth recess with a depth of about 1 μm is prepared on the first surface of the second substrate, and the second metal fence is located in the fourth recess. The process flow chart of the preparation method of the wrapped superconducting quantum flip chip of this embodiment is shown in FIG. 2.

[0083] Embodiment 9

[0084] The difference between the embodiment and the embodiment 4 is that, in the prepared device: the first substrate, the second substrate and the closed cavity formed between the first metal fence and the second metal fence, the first circuit layer, the second circuit layer and the Josephson junction are all located in the closed cavity. The top view structure diagram of the wrap-around superconducting quantum flip chip of the embodiment is shown in FIG. 3, and the circuit area formed by the first circuit layer and the second circuit layer and the Josephson junction are located in the closed cavity.

[0085] Although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that those skilled in the art can understand.

[0086] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present application, and are not used to limit the protection scope of the present application, and any equivalent embodiments or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A wrap-around superconducting quantum inverse-d dome chip, characterized by, The first substrate, the first superconducting film, the metal fence, the second superconducting film and the second substrate are arranged in a stack, The first superconducting film comprises a first circuit layer; the second superconducting film comprises a second circuit layer and a Josephson junction; The metal fence surrounds the periphery of the first circuit layer, the second circuit layer and the Josephson junction.

2. The wrapped superconducting quantum inverted chip of claim 1, wherein, A first recess is arranged on the surface of the first substrate adjacent to the second substrate, and / or a second recess is arranged on the surface of the second substrate adjacent to the first substrate, the first circuit layer is located in the first recess, and the second circuit layer and the Josephson junction are located in the second recess.

3. The wrapped superconducting quantum inverted chip of claim 2, wherein, A third recess is arranged on the surface of the first substrate adjacent to the second substrate, and a fourth recess is arranged on the surface of the second substrate adjacent to the first substrate, and the two ends of the metal fence are respectively embedded into the third recess and the fourth recess.

4. The wrapped superconducting quantum inverse-dipole chip according to any one of claims 1 to 3, characterized in that The first substrate, the second substrate and the metal fence form a closed cavity, and the first circuit layer, the second circuit layer and the Josephson junction are all located in the closed cavity.

5. The wrapped superconducting quantum inverted chip of claim 4, wherein, A third superconducting film is further arranged on the surface of the first substrate away from the first superconducting film, the third superconducting film comprises a third circuit layer, a TSV through hole for filling superconducting material is arranged on the first substrate, the metal fence surrounds the periphery of the TSV through hole, and the first circuit layer is electrically interconnected with the third circuit layer through the superconducting material in the TSV through hole.

6. The wrapped superconducting quantum inverse-d dome chip of claim 5, wherein, The materials of the first substrate and the second substrate are selected from one or more of the following: sapphire, intrinsic silicon; The materials of the first superconducting film, the second superconducting film and the third superconducting film are selected from one or more of the following: niobium-based superconducting material, tantalum-based superconducting material, TiN-based superconducting material, NbN-based superconducting material, NbTiN-based superconducting material, Al-based superconducting material; The metal fence is an indium column.

7. The wrapped superconducting quantum inverse-dipole chip of claim 5, wherein, The superconducting material is any one or several of aluminum, indium, TiN, NbN and NbTiN.

8. A method of fabricating a wrap-around superconducting quantum inverse-d dome, characterized by, The method comprises the following steps: Preparation of the lower base plate: A1. Take a first substrate, the first substrate comprises opposite first and second surfaces, clean the first surface of the first substrate, and deposit a first superconducting film on the first surface of the first substrate; A2. Prepare a first metal fence and a first circuit layer on the first superconducting film, the first metal fence is arranged to surround the edge of the first surface of the first substrate once; Preparation of the upper top plate: B1. Take a second substrate, the second substrate comprises opposite first and second surfaces, clean the first surface of the second substrate, and deposit a second superconducting film on the first surface of the second substrate; B2. First, prepare a second metal fence on the second superconducting film, the second metal fence is arranged to surround the edge of the surface of the second substrate once; second, sequentially prepare a second circuit layer and a Josephson junction on the second superconducting film, and the second metal fence surrounds the outside of the second circuit layer and the Josephson junction; Preparation of the device: In a vacuum environment, the lower substrate and the upper substrate are respectively installed on a flip-chip device, so that the lower substrate and the upper substrate are parallel and the first metal wall and the second metal wall are one-to-one correspondingly arranged, the flip-chip device is used to apply pressure to the lower substrate and the upper substrate, so that the first metal wall and the second metal wall are welded and connected and a preset height is formed, so as to realize the bonding connection of the lower substrate and the upper substrate.

9. The method of claim 8, wherein the method further comprises: In step A1, before the first superconducting thin film is deposited on the first surface of the first substrate, the step further comprises: preparing a first groove on the first surface of the first substrate, and the first metal wall is arranged outside the first groove; and / or, In step B1, before the second superconducting thin film is deposited on the first surface of the second substrate, the step further comprises: preparing a second groove on the first surface of the second substrate, and the second metal wall is arranged outside the second groove.

10. The method of claim 9, wherein the method further comprises: In step A1, before the first superconducting thin film is deposited on the first surface of the first substrate, the step further comprises: preparing a third groove on the first surface of the first substrate, and the first metal wall is arranged in the third groove. In step B1, before the second superconducting thin film is deposited on the first surface of the second substrate, the step further comprises: preparing a fourth groove on the first surface of the second substrate, and the second metal wall is arranged in the fourth groove.

11. The method of claim 8 or 9, wherein In step A1, before the first superconducting thin film is deposited on the first surface of the first substrate, the step further comprises: preparing a TSV through hole on the first substrate, the first metal wall is arranged outside the TSV through hole, and the TSV through hole is filled with superconducting material.

12. The method of claim 11, wherein the method further comprises: In the preparation of the lower substrate, step A3 is further included: after cleaning the second surface of the first substrate, a third superconducting thin film is deposited on the second surface of the first substrate, and a third circuit layer is prepared on the third superconducting thin film.

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