Display panel, and pixel circuit and driving method therefor

Abstract

A display panel, and a pixel circuit (PC) and a driving method therefor, which relate to the technical field of display. The PC comprises: a driving transistor (T3); a compensation circuit (10), which is connected to a first electrode and a gate electrode of the driving transistor (T3) and is used for coupling the voltage of the first electrode of the driving transistor (T3) to the gate electrode in response to a signal of a coupling control terminal (G7); a first light emission control circuit (20), which is connected to the first electrode of the driving transistor (T3) and is used for transmitting a first power source signal to the first electrode of the driving transistor (T3) in response to a signal of a first light emission control terminal (G4), wherein a second electrode of the driving transistor (T3) is connected to a light-emitting device (LD); a first reset circuit (30), which is connected to the gate electrode of the driving transistor (T3) and is used for writing a first reset signal (Ref) to the gate electrode of the driving transistor (T3) in response to a signal of a first reset control terminal (G1); and a write circuit (40), which is connected to the gate electrode of the driving transistor (T3) and is used for writing a data signal (Data) to the gate electrode of the driving transistor (T3) in response to a signal of a write control terminal (G2), wherein at least one of the first reset signal (Ref) and the data signal (Data) is used for switching on the driving transistor (T3).

Description

Display panel, pixel circuit and driving method thereof TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel, a pixel circuit and a driving method of the pixel circuit. BACKGROUND

[0002] OLED (Organic Light Emitting Diode) display panel has the advantages of self-luminescence, wide color gamut, high contrast, high response, etc., and has wide application prospects. However, the uniformity of the luminous brightness of the current display panel still needs to be improved, and the picture abnormality such as trailing is easy to occur.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The present disclosure provides a display panel, a pixel circuit and a driving method of the pixel circuit.

[0006] According to one aspect of the present disclosure, a pixel circuit is provided, comprising:

[0007] a driving transistor;

[0008] a compensation circuit connected to the first electrode and the gate electrode of the driving transistor, for coupling the voltage of the first electrode of the driving transistor to the gate electrode in response to the signal of the coupling control end;

[0009] a first light emitting control circuit connected to the first electrode of the driving transistor, for transmitting a first power signal to the first electrode of the driving transistor in response to the signal of the first light emitting control end; the second electrode of the driving transistor is connected to a light emitting device;

[0010] a first reset circuit connected to the gate electrode of the driving transistor, for writing a first reset signal to the gate electrode of the driving transistor in response to the signal of the first reset control end;

[0011] a writing circuit connected to the gate electrode of the driving transistor, for writing a data signal to the gate electrode of the driving transistor in response to the signal of the writing control end; at least one of the first reset signal and the data signal is used to turn on the driving transistor.

[0012] In an exemplary embodiment of the present disclosure, the compensation circuit comprises a coupling capacitor and a coupling control circuit.

[0013] The first pole of the coupling capacitor is connected with the gate of the driving transistor, and the second pole is connected with the first pole of the driving transistor through the coupling control circuit; the coupling control circuit is used for turning on and turning off in response to the signal of the coupling control end.

[0014] In an exemplary embodiment of the present disclosure, the coupling control circuit comprises:

[0015] A coupling control transistor, the first pole of the coupling control transistor is connected with the first pole of the driving transistor, the second pole of the coupling control transistor is connected with the second pole of the coupling capacitor, and the gate of the coupling control transistor is connected with the coupling control end.

[0016] In an exemplary embodiment of the present disclosure, the first reset circuit comprises a first reset transistor, the first pole of the first reset transistor is used for receiving a first reset signal, the second pole is connected with the gate of the driving transistor, and the gate of the first reset transistor is connected with the first reset control end.

[0017] In an exemplary embodiment of the present disclosure, the first reset circuit further comprises a connection transistor, the first pole of the connection transistor is connected with the gate of the driving transistor, the second pole is connected with the second pole of the driving transistor, and the gate of the connection transistor is connected with a connection control end; the connection transistor is used for turning on and turning off in response to the signal of the connection control end.

[0018] In an exemplary embodiment of the present disclosure, the first light emitting control circuit comprises a first light emitting control transistor, and the write-in circuit comprises a write-in transistor;

[0019] The first pole of the first light emitting control transistor is used for receiving the first power supply signal, and the second pole is connected with the first pole of the driving transistor; the gate of the first light emitting control transistor is connected with the first light emitting control end;

[0020] The first pole of the write-in transistor is used for receiving the data signal, the second pole is connected with the gate of the driving transistor, and the gate of the write-in transistor is connected with the write-in control end.

[0021] In an exemplary embodiment of the present disclosure, the pixel circuit further comprises:

[0022] An energy storage circuit, connected with the second pole of the coupling capacitor and capable of receiving the first power supply signal.

[0023] In an exemplary embodiment of the present disclosure, the energy storage circuit comprises a storage capacitor, the first pole of the storage capacitor is connected with the second pole of the coupling capacitor, and the second pole of the storage capacitor is used for receiving the first power supply signal.

[0024] In an example embodiment of the present disclosure, the pixel circuit further comprises:

[0025] a second light emitting control circuit connected between the second electrode of the driving transistor and the light emitting device, for turning on and off in response to a signal of a second light emitting control terminal.

[0026] In an example embodiment of the present disclosure, the second light emitting control circuit comprises a second light emitting control transistor, a first electrode of the second light emitting control transistor being connected to the second electrode of the driving transistor, a second electrode of the second light emitting control transistor being connected to the light emitting device, and a gate of the second light emitting control transistor being connected to the second light emitting control terminal.

[0027] In an example embodiment of the present disclosure, the pixel circuit further comprises at least one of a second reset circuit and a third reset circuit.

[0028] The second reset circuit is connected to the first electrode of the driving transistor, for transmitting a second reset signal to the first electrode of the driving transistor in response to a signal of a second reset control terminal.

[0029] The third reset circuit is connected to the light emitting device, for transmitting a third reset signal to the light emitting device in response to a signal of a third reset control terminal.

[0030] In an example embodiment of the present disclosure, the second reset circuit comprises a second reset transistor, a first electrode of the second reset transistor being configured to receive the second reset signal, a second electrode of the second reset transistor being connected to the first electrode of the driving transistor, and a gate of the second reset transistor being connected to the second reset control terminal.

[0031] The third reset circuit comprises a third reset transistor, a first electrode of the third reset transistor being configured to receive the third reset signal, a second electrode of the third reset transistor being connected to the light emitting device, and a gate of the third reset transistor being connected to the third reset control terminal.

[0032] In an example embodiment of the present disclosure, the coupling control terminal is connected to the first light emitting control terminal.

[0033] In an example embodiment of the present disclosure, one of the write control terminal and the first reset control terminal is connected to the connection control terminal.

[0034] According to one aspect of the present disclosure, a driving method of a pixel circuit is provided, the pixel circuit comprising a driving transistor, a compensation circuit, a first light emitting control circuit, a first reset circuit and a write-in circuit; the compensation circuit is connected to a first electrode and a gate electrode of the driving transistor; the first light emitting control circuit is connected to the first electrode of the driving transistor and is configured to transmit a first power signal to the first electrode of the driving transistor; a second electrode of the driving transistor is connected to a light emitting device; the first reset circuit is connected to the gate electrode of the driving transistor; the write-in circuit is connected to the gate electrode of the driving transistor;

[0035] The driving method comprises:

[0036] In a first stage, a first reset signal is transmitted to the gate electrode of the driving transistor by the first reset circuit controlled by a first reset control terminal, so as to write the threshold voltage of the driving transistor into the first electrode of the driving transistor; the voltage of the first reset signal is less than the voltage of the first power signal;

[0037] In a second stage, a data signal is transmitted to the gate electrode of the driving transistor by the write-in circuit controlled by a write-in control terminal; the voltage of the data signal is less than the voltage of the first reset signal;

[0038] In a third stage, the first light emitting control circuit is turned on by the first light emitting control terminal, and the voltage of the first electrode of the driving transistor is coupled to the gate electrode by the compensation circuit, so as to couple the voltage of the first power signal and the threshold voltage of the driving transistor to the gate electrode of the driving transistor.

[0039] In an exemplary embodiment of the present disclosure, the pixel circuit further comprises a second light emitting control circuit, a second reset circuit and a third reset circuit, the second light emitting control circuit is connected to the second electrode of the driving transistor and the light emitting device; the second reset circuit is connected to the first electrode of the driving transistor; the third reset circuit is connected to the light emitting device;

[0040] The driving method further comprises:

[0041] In the third stage or a fourth stage after the third stage, the second light emitting control circuit is turned on by a second light emitting control terminal;

[0042] In a fifth stage before the first stage, a second reset signal is transmitted to the first electrode of the driving transistor by the second reset control circuit controlled by a second reset control terminal;

[0043] In the first stage, a third reset signal is transmitted to the light emitting device by the third reset control circuit controlled by a third reset control terminal.

[0044] According to one aspect of the present disclosure, a driving method of a pixel circuit is provided, the pixel circuit comprising a driving transistor, a compensation circuit, a first light emitting control circuit, a first reset circuit and a write-in circuit; the compensation circuit is connected to a first electrode and a gate electrode of the driving transistor; the first light emitting control circuit is connected to the first electrode of the driving transistor and is configured to transmit a first power signal to the first electrode of the driving transistor; a second electrode of the driving transistor is connected to a light emitting device; the first reset circuit is connected to the gate electrode of the driving transistor; the write-in circuit is connected to the gate electrode of the driving transistor;

[0045] The driving method comprises:

[0046] In a first stage, a data signal is transmitted to the gate electrode of the driving transistor by the write-in circuit under the control of a write-in control terminal, so as to write a threshold voltage of the driving transistor into the first electrode of the driving transistor; the voltage of the data signal is less than the voltage of the first power signal;

[0047] In a second stage, a first reset signal is transmitted to the gate electrode of the driving transistor by the first reset circuit under the control of a first reset control terminal; the voltage of the first reset signal is less than the voltage of the data signal;

[0048] In a third stage, the first light emitting control circuit is turned on under the control of a first light emitting control terminal, and the voltage of the first electrode of the driving transistor is coupled to the gate electrode by the compensation circuit, so as to couple the voltage of the first power signal and the threshold voltage of the driving transistor to the gate electrode of the driving transistor.

[0049] In an exemplary embodiment of the present disclosure, the pixel circuit further comprises a second light emitting control circuit, a second reset circuit and a third reset circuit, the second light emitting control circuit is connected to the second electrode of the driving transistor and the light emitting device; the second reset circuit is connected to the first electrode of the driving transistor; the third reset circuit is connected to the light emitting device;

[0050] The driving method further comprises:

[0051] In the third stage or a fourth stage after the third stage, the second light emitting control circuit is turned on under the control of a second light emitting control terminal;

[0052] In a fifth stage before the first stage, the second reset control circuit is controlled to transmit a second reset signal to the first electrode of the driving transistor under the control of a second reset control terminal;

[0053] In the first stage, the third reset control circuit is controlled to transmit a third reset signal to the light emitting device under the control of a third reset control terminal.

[0054] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is readily apparent to one skilled in the art that the following description is merely exemplary and explanatory of the present disclosure and that various embodiments of the present disclosure can be readily carried out according to these drawings without resorting to inventive faculty.

[0056] FIG. 1 is a top view of an embodiment of a display panel according to the present disclosure.

[0057] FIG. 2 is a cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0058] FIG. 3 is a cross-sectional view of another embodiment of a display panel according to the present disclosure.

[0059] FIG. 4 is a schematic diagram of a first type of pixel circuit according to the present disclosure.

[0060] FIG. 5 is a schematic diagram of a second type of pixel circuit according to the present disclosure.

[0061] FIG. 6 is a schematic diagram of a third type of pixel circuit according to the present disclosure.

[0062] FIG. 7 is a schematic diagram of a fourth type of pixel circuit according to the present disclosure.

[0063] FIG. 8 is a schematic diagram of a fifth type of pixel circuit according to the present disclosure.

[0064] FIG. 9 is a schematic diagram of a pixel circuit according to a first embodiment.

[0065] FIG. 10 is a timing diagram for the first embodiment.

[0066] FIGS. 11-13 are schematic diagrams of various stages of the timing diagram of FIG. 10.

[0067] FIG. 14 is a schematic diagram of a pixel circuit according to a second embodiment.

[0068] FIG. 15 is a timing diagram for the second embodiment.

[0069] FIG. 16 is a schematic diagram of a pixel circuit according to a third embodiment.

[0070] FIG. 17 is a timing diagram for the third embodiment.

[0071] FIG. 18 is a schematic diagram of a pixel circuit according to a fourth embodiment.

[0072] FIG. 19 is a timing diagram for the fourth embodiment.

[0073] FIG. 20 is a schematic view of a pixel circuit of a fifth embodiment.

[0074] FIG. 21 is a timing chart of the fifth embodiment.

[0075] FIG. 22 is a schematic view of a pixel circuit of a sixth embodiment.

[0076] FIG. 23 is a timing chart of the sixth embodiment.

[0077] FIG. 24 is a schematic view of a pixel circuit of a seventh embodiment.

[0078] FIG. 25 is a timing chart of the seventh embodiment.

[0079] FIGS. 26-28 are schematic views of the stages in FIG. 25.

[0080] FIG. 29 is a schematic view of a pixel circuit of an eighth embodiment.

[0081] FIG. 30 is a timing chart of the eighth embodiment.

[0082] FIG. 31 is a schematic view of a pixel circuit of a ninth embodiment.

[0083] FIG. 32 is a timing chart of the ninth embodiment.

[0084] FIG. 33 is a schematic view of a pixel circuit of a tenth embodiment.

[0085] FIG. 34 is a timing chart of the tenth embodiment. DETAILED DESCRIPTION

[0086] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and descriptions of the same or similar elements can be omitted. In addition, the drawings are to be used only as illustrative and not as defining the limits of the present disclosure.

[0087] The use of the terms "one," "a," "the" and "at least one" are used herein to mean that "one or more" unless explicitly indicated to the contrary. The use of the term "at least one" followed by a list of one or more items should be understood to mean at least one of each item in the list and that multiple items in the list can be used. The use of the term "one of' followed by a list of one or more items should be understood to mean at least one of each item in the list to the exclusion of the other items in the list. The use of the term "one" followed by a list of one or more items should be understood to mean at least one of each item in the list to the exclusion of the other items in the list. The use of the term "first," "second," and "third," etc. before an element in a claim are used merely as labels, and are not intended to impose numerical requirements on the element. Further, the use of "a," "an" and "the" to

[0088] The row direction and the column direction herein are two intersecting directions, which can be perpendicular to each other or not perpendicular to each other. In the drawings of the present disclosure, the row direction is the horizontal direction and the column direction is the vertical direction, but the present disclosure is not limited to this. It can be understood by those skilled in the art that if the display panel is rotated, the actual directions of the row direction and the column direction can change.

[0089] nTmC herein indicates that a circuit (for example, a pixel circuit, a gate drive circuit, etc.) includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C").

[0090] A transistor herein includes a gate, a first pole and a second pole, and the first pole and the second pole can be turned on and turned off by controlling the voltage of the gate; the first pole can be a source, and the second pole can be a drain; of course, the first pole can also be a drain, and the second pole can also be a source. Specifically, if a signal is input from the first pole, the first pole is the source and the second pole is the drain; if a signal is input from the second pole, the second pole is the source and the first pole is the drain; that is, the source and the drain can be interchanged according to the change of the input signal.

[0091] For a P-type transistor, when the gate receives a high level, the first pole and the second pole are turned off; when the gate receives a low level, the first pole and the second pole are turned on. For an N-type transistor, when the gate receives a high level, the first pole and the second pole are turned on; when the gate receives a low level, the first pole and the second pole are turned off.

[0092] As shown in FIG. 1, the display panel provided by the embodiment of the present disclosure can include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA can be a continuous annular area surrounding the display area AA, or can be a discontinuous area surrounding the display area AA.

[0093] As shown in FIGS. 2 and 3, the display panel can include a drive backplane BP and a plurality of light emitting devices LD arranged on one side of the drive backplane BP. The light emitting devices LD are distributed along the row direction and the column direction, and the light emitting devices LD can be driven to emit light by a drive circuit in the drive backplane BP to display an image.

[0094] The light emitting devices LD can be located in the display area AA, which can be an OLED (organic light emitting diode) using an organic light emitting material; can be an LED (light emitting diode) using an inorganic light emitting material, for example, a Micro LED (micron light emitting diode) and a Mini LED (sub-millimeter light emitting diode); or can be a QLED (quantum dot diode) and the like. The specific structure of the display panel is not specially limited herein, as long as it can display an image.

[0095] As shown in FIG. 2 and FIG. 3, taking OLED as an example, the light emitting device can include a first electrode ANO, a light emitting layer EL and a second electrode CAT stacked in sequence in a direction away from the driving back plate BP, and the light emitting layer EL can be excited to emit light by applying an electrical signal to the first electrode ANO and the second electrode CAT, and the specific principle will not be described here. Meanwhile, in order to define the range of the light emitting device LD, a pixel definition layer PDL can be provided on the driving back plate BP, the pixel definition layer PDL is located on the same surface of the driving back plate BP as the first electrode ANO, and the pixel definition layer PDL can have pixel openings exposing each first electrode ANO, so as to define the range of the light emitting device LD through each pixel opening.

[0096] As shown in FIG. 1, the driving circuit can include pixel circuits PC located in the display area AA and peripheral circuits WP located in the peripheral area WA, the pixel circuits PC can be distributed in the row direction and the column direction, one pixel circuit PC can be connected with the first electrode ANO of one light emitting device LD, and one row of pixel circuits PC can be connected with the first electrode ANO of each of one row of light emitting devices LD. Of course, the same pixel circuit PC can be connected with the first electrodes ANO of multiple light emitting devices LD. The pixel circuit PC can include multiple transistors, and can also include a capacitor, which can be a 2T1C, 3T1C, 7T1C, etc. structure.

[0097] The peripheral circuit WP can be connected with the light emitting device LD through the pixel circuit PC, on the other hand, the peripheral circuit WP can also be connected with the second electrode CAT of the light emitting device LD and apply a second power signal to the second electrode CAT, and the current through the light emitting device LD can be controlled through the pixel circuit PC, so as to control the brightness of the light emitting device LD.

[0098] The peripheral circuit WP can include a gate driving circuit and a light emitting control circuit, which are used to scan part of the transistors in the pixel circuit PC, that is, output a scanning signal to the gate of the transistor to control the conduction and turn-off of the transistor. The signals output by the above-mentioned gate driving circuit and light emitting driving circuit can realize the conduction and turn-off of the transistor in the pixel circuit PC, that is, realize the scanning of the pixel circuit PC, so as to control the light emitting of the light emitting device LD.

[0099] The gate driving circuit and the light emitting control circuit can each include multiple cascaded shift registers, that is, the output end of the nth shift register is connected with the gate of the transistor of at least one row of pixel circuits PC, and is also connected with the input end of the (n+1)th shift register, so that the output signal of the upper shift register is used as the input signal of the lower shift register. Any shift register can include multiple transistors and capacitors, which can be a 7T2C, 8T2C, etc. structure, which will not be specially limited here. In addition, the structures of the shift registers of the gate driving circuit and the light emitting control circuit can be different.

[0100] As shown in Fig. 1, the output signal of the output terminal of the shift register is the scanning signal described above, and the gate of a part of the transistors of a row of pixel circuits PC can be connected to the output terminal of the shift register. Of course, the shift register can be connected to multiple rows of pixel circuits PC, and simultaneously scan multiple rows of pixel circuits PC, but the output signal of the same shift register can have different effects in different rows of pixel circuits PC.

[0101] In addition, the peripheral area WA of the display panel can be provided with a source driving circuit DP for transmitting a data signal to the pixel circuit PC, which can be a chip or a circuit integrated on the display panel.

[0102] The pixel circuit of the present disclosure is described below by way of example:

[0103] As shown in Fig. 4, the pixel circuit can include a driving transistor T3, a compensation circuit 10, a first light-emitting control circuit 20, a first reset circuit 30, and a writing circuit 40, wherein:

[0104] The compensation circuit 10 is connected to the first electrode and the gate of the driving transistor T3, and is connected to the coupling control terminal G7. The compensation circuit 10 can be turned on and off in response to the signal of the coupling control terminal G7, and when turned on, can couple the voltage of the first electrode of the driving transistor T3 to the gate of the driving transistor T3. For example, the compensation circuit 10 and the gate of the driving transistor T3 can be connected to the first node N1, and the compensation circuit 10 and the first electrode of the driving transistor T3 can be connected to the second node N2.

[0105] The first light-emitting control circuit 20 is connected to the first electrode of the driving transistor T3, and is connected to the first light-emitting control terminal G4. The first light-emitting control circuit 20 can be turned on and off in response to the signal of the first light-emitting control terminal G4, and when turned on, can transmit a first source signal to the first electrode of the driving transistor T3, which is a constant voltage signal and has a voltage of VDD. At the same time, the second electrode of the driving transistor T3 is connected to the first electrode of the light-emitting device LD, and the second electrode of the light-emitting device LD can be used to receive a second source signal, which is a constant voltage signal and has a voltage of VSS. For example, the first light-emitting control circuit 20 is connected to the second node N2.

[0106] The first reset circuit 30 is connected to the gate of the driving transistor T3, and is connected to the first reset control terminal G1. The first reset circuit 30 can be turned on and off in response to the signal of the first reset control terminal G1, and when turned on, can write a first reset signal Ref to the gate of the driving transistor T3. For example, the first reset circuit 30 is connected to the first node N1.

[0107] The write circuit 40 is connected to the gate of the driving transistor T3 and the write control terminal G2, and the write circuit 40 can be turned on and turned off in response to the signal of the write control terminal G2, and when turned on, the write circuit 40 can write the data signal Data to the gate of the driving transistor T3. At least one of the first reset signal Ref and the data signal Data is used to turn on the driving transistor T3. For example, the write circuit 40 is connected to the first node N1.

[0108] The pixel circuit of the embodiment of the present disclosure can work in the linear region by controlling the voltage of the gate of the driving transistor T3, so that the current of the driving transistor T3 can be controlled by controlling the voltage of the gate, and the brightness of the light emitting device LD is controlled by the current. At the same time, the gate of the driving transistor T3 can be written with the first reset signal Ref or the data signal Data by the first reset circuit 30 or the write circuit 40, and the driving transistor T3 is turned on by the voltage difference between one of the first reset signal Ref and the data signal Data and the first electrode of the driving transistor T3 being greater than the threshold voltage of the driving transistor T3, and the driving transistor T3 is turned off as the voltage of the first electrode of the driving transistor T3 decreases, so that the threshold voltage is written to the first electrode of the driving transistor T3; and the voltage VDD of the first power signal and the threshold voltage of the driving transistor T3 are written to the gate of the driving transistor T3 by the coupling effect of the compensation circuit 10, and based on the current formula of the driving transistor T3, the voltage drop of the first power signal and the influence of the threshold voltage on the current can be eliminated at the same time. When the first reset signal Ref is a constant voltage signal, the size of the current can be controlled only by the data signal Data, and the brightness of the light emitting device LD is controlled. The problem of uneven brightness caused by the threshold voltage offset due to process, material, etc. can be avoided, and the problem of uneven brightness caused by the voltage drop of the first power signal can also be avoided, thereby improving the display abnormality of the ghosting.

[0109] It should be noted that the above-mentioned problem of uneven brightness refers to the problem that different pixel circuits are driven by the same signal but the current difference is large, resulting in a large difference in brightness of the connected light emitting device LD.

[0110] As shown in FIG. 4, in some embodiments of the present disclosure, the compensation circuit 10 can include a coupling capacitor Cc and a coupling control circuit 110, wherein:

[0111] The coupling capacitor Cc has opposite first and second electrodes, and the first electrode is connected to the gate of the driving transistor T3, and the second electrode is connected to the first electrode of the driving transistor T3 through the coupling control circuit 110. For example, the second electrode of the coupling capacitor Cc is connected to the fourth node N4 through the coupling control circuit 110.

[0112] The coupling control circuit 110 is connected with the coupling control terminal G7 and can be turned on and turned off in response to the signal of the coupling control terminal G7. When the coupling control circuit 110 is turned on, the voltage of the first electrode of the driving transistor T3 is coupled to the gate of the driving transistor T3 through the coupling capacitor Cc.

[0113] Further, in some embodiments, the coupling control circuit 110 is coupled with the coupling control transistor T7, the first electrode of the coupling control transistor T7 is connected with the first electrode of the driving transistor T3, the second electrode of the coupling control transistor T7 is connected with the second electrode of the coupling capacitor Cc, and the gate of the coupling control transistor T7 is connected with the coupling control terminal G7. That is, the coupling capacitor Cc and the coupling control transistor T7 can be connected in series between the first electrode and the gate of the driving transistor T3. For example, the second electrode of the coupling capacitor Cc and the second electrode of the coupling control transistor T7 are connected with the fourth node N4.

[0114] Of course, in other embodiments of the present disclosure, the coupling control circuit 110 can also use multiple transistors in parallel or in series, as long as the coupling control terminal G7 can be turned on and turned off in response to the signal of the control line to realize the coupling of the voltage between the first electrode and the gate of the driving transistor T3.

[0115] As shown in FIG. 4, in some embodiments of the present disclosure, the first light-emitting control circuit 20 includes the first light-emitting control transistor T4, and the write circuit 40 includes the write transistor T2.

[0116] The first electrode of the first light-emitting control transistor T4 can receive the first power signal, the second electrode is connected with the first electrode of the driving transistor T3, and the gate of the first light-emitting control transistor T4 is connected with the first light-emitting control terminal G4. The first light-emitting control transistor T4 can be turned on and turned off in response to the signal of the first light-emitting control terminal G4, so as to transmit the first power signal to the first electrode of the driving transistor T3. For example, the second electrode of the first light-emitting control transistor T4 is connected with the second node N2.

[0117] The first electrode of the write transistor T2 can receive the data signal Data, the second electrode is connected with the gate of the driving transistor T3, and the gate of the write transistor T2 is connected with the write control terminal G2. The write transistor T2 can be turned on and turned off in response to the signal of the write control terminal G2, so as to transmit the data signal Data to the gate of the driving transistor T3. For example, the second electrode of the write transistor T2 is connected with the first node N1.

[0118] As shown in FIG. 4, in some embodiments of the present disclosure, the first reset circuit 30 can include a first reset transistor T1, a first electrode of the first reset transistor T1 can be used to receive the first reset signal Ref, a second electrode of the first reset transistor T1 is connected with the gate electrode of the driving transistor T3, and a gate electrode of the first reset transistor T1 is connected with the first reset control terminal G1 and can be turned on and turned off under the control of the signal of the first reset control terminal G1, so that the first reset signal Ref can be transmitted to the gate electrode of the driving transistor T3 through the first reset transistor T1. For example, the second electrode of the first reset transistor T1 is connected with the first node N1.

[0119] Further, the first reset circuit 30 can further include a connection transistor T5, a first electrode of the connection transistor T5 is connected with the gate electrode of the driving transistor T3, a second electrode of the connection transistor T5 is connected with the second electrode of the driving transistor T3, and a gate electrode of the connection transistor T5 is connected with the connection control terminal G5. The connection transistor T5 can be turned on and turned off in response to the signal of the connection control terminal G5, so as to connect and disconnect the gate electrode and the second electrode of the driving transistor T3. For example, the first electrode of the connection transistor T5 is connected with the first node N1, and the second electrode of the connection transistor T5 is connected with the second electrode of the driving transistor T3 and the third node N3.

[0120] As shown in FIG. 5, in some embodiments of the present disclosure, the pixel circuit can further include an energy storage circuit 80, which can be connected with the second electrode of the coupling capacitor Cc and can receive the first power supply signal, for stabilizing the voltage of the second electrode of the coupling capacitor Cc, so as to maintain the voltage of the gate electrode of the driving transistor T3 within a certain time.

[0121] In some embodiments, the energy storage circuit 80 can include a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected with the second electrode of the coupling capacitor Cc, and a second electrode of the storage capacitor Cst is used to receive the first power supply signal. For example, the first electrode of the storage capacitor Cst is connected with the fourth node N4.

[0122] As shown in FIG. 5, in some embodiments of the present disclosure, the pixel circuit further includes a second light emitting control circuit 50, which can be connected with the second electrode of the driving transistor T3 and the first electrode of the light emitting device LD and can be turned on and turned off in response to the signal of the second light emitting control terminal G6, so as to control the time length of the light emitting of the light emitting device LD, and only when both the first light emitting control circuit 20 and the second light emitting control circuit 50 are turned on, the light emitting device LD will emit light. For example, the second light emitting control circuit 50 is connected with the third node N3.

[0123] In some embodiments, the second light-emitting control circuit 50 comprises a second light-emitting control transistor T6, a first electrode of the second light-emitting control transistor T6 is connected with the second electrode of the driving transistor T3, a second electrode of the second light-emitting control transistor T6 is connected with the light-emitting device LD, a gate electrode of the second light-emitting control transistor T6 is connected with the second light-emitting control terminal G6, and the second light-emitting control transistor T6 can be turned on and turned off in response to a signal of the second light-emitting control terminal G6. For example, the first electrode of the second light-emitting control transistor T6 is connected with the third node N3.

[0124] As shown in FIG. 6, in some embodiments of the present disclosure, the pixel circuit can further comprise a second reset circuit 60, which can be connected with the first electrode of the driving transistor T3 and can transmit a second reset signal Init1 to the first electrode of the driving transistor T3 in response to a signal of a second reset control terminal G8. The second reset signal Init1 has a constant voltage Vinit1, and the first electrode of the driving transistor T3 is reset by the second reset signal Init1, so as to eliminate the influence of voltage when displaying the previous frame of image, initialize the voltage of the first electrode of the driving transistor T3, and improve the uniformity of display. For example, the second reset circuit 60 is connected with the second node N2.

[0125] In some embodiments, the second reset circuit 60 can comprise a second reset transistor T8, a first electrode of the second reset transistor T8 can receive the second reset signal Init1, a second electrode of the second reset transistor T8 is connected with the first electrode of the driving transistor T3, and a gate electrode of the second reset transistor T8 is connected with the second reset control terminal G8, so as to be turned on and turned off under the control of the signal of the second reset control terminal G8, so as to transmit the second reset signal Init1 to the first electrode of the driving transistor T3. For example, the second electrode of the second reset transistor T8 is connected with the second node N2.

[0126] As shown in FIG. 7, in some embodiments of the present disclosure, the pixel circuit can further comprise a third reset circuit 70, which is connected with the first electrode of the light-emitting device LD and the second electrode of the driving transistor T3, and can transmit a third reset signal Init2 to the first electrode of the light-emitting device LD in response to a signal of a third reset control terminal G9. The third reset signal Init2 has a constant voltage Vinit2, and the voltage of the first electrode of the light-emitting device LD is reset by the third reset signal, so as to eliminate the influence of voltage when displaying the previous frame of image, initialize the voltage of the first electrode of the light-emitting device LD, and improve the uniformity of display. For example, the third reset circuit 70 is connected with the first electrode of the light-emitting device LD at the fifth node N5, and for the embodiment in which the second reset circuit 60 exists, the second reset circuit 60 connects the third node and the fifth node.

[0127] In some embodiments, the third reset circuit 70 comprises a third reset transistor T9, a first electrode of the third reset transistor T9 can receive the third reset signal, a second electrode of the third reset transistor T9 is connected with the first electrode of the light emitting device LD and the second electrode of the driving transistor T3, and a gate electrode of the third reset transistor T9 is connected with the third reset control terminal G9, and the third reset transistor T9 can be turned on and turned off under the control of the signal of the third reset control terminal G9, so as to transmit the third reset signal to the first electrode of the light emitting device LD. For example, the second electrode of the third reset transistor T9 is connected with the first electrode of the light emitting device LD at the fifth node N5, and for the embodiment in which the second reset transistor T8 exists, the first electrode of the second reset transistor T8 is connected with the third node N3, and the second electrode of the second reset transistor T8 is connected with the fifth node N5.

[0128] As shown in FIG. 8, in some embodiments of the present disclosure, the pixel circuit can simultaneously have the above-mentioned energy storage circuit 80, the second reset circuit 60 and the third reset circuit 70, and the specific structure is not described here again.

[0129] The driving method of the pixel circuit of the embodiment of the present disclosure is exemplarily described as follows:

[0130] As shown in FIG. 9 and FIG. 10, based on the pixel circuit in FIG. 5, in the first type of embodiment of the driving method, the driving method comprises:

[0131] As shown in FIG. 11, in the first stage t1, the first reset signal Ref is transmitted to the gate electrode of the driving transistor T3 by the signal of the first reset control terminal G1, and the gate electrode of the driving transistor T3 is reset; at the same time, the voltage Vref of the first reset signal Ref is less than the voltage VDD of the first power signal, so that the driving transistor T3 is turned on, and the voltage of the first electrode of the driving transistor T3 is increased from VDD-Vds in the last frame of light emission until Vref-Vth, and then the driving transistor T3 is turned off, so as to write the threshold voltage of the driving transistor T3 into the first electrode thereof. Wherein, Vds is the source-drain voltage difference of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0132] As shown in FIG. 12, in the second stage t2, the data signal Data is transmitted to the gate electrode of the driving transistor T3 by the write control terminal G2; the voltage Vdata of the data signal Data is less than the voltage Vref of the first reset signal Ref. At the same time, the compensation circuit 10 is turned off, so that when the gate electrode of the driving transistor T3 writes the data signal Data, the first electrode thereof can maintain the voltage written in the first stage t1 without being disturbed.

[0133] As shown in Fig. 13, at the third stage t3, the first light emitting control circuit 20 is controlled to be turned on by the first light emitting control terminal G4, and the first power signal is transmitted to the first electrode of the driving transistor T3, so that the voltage of the first electrode is VDD, the voltage of the first power signal; meanwhile, the voltage of the first electrode of the driving transistor T3 is coupled to the gate of the driving transistor T3 by the compensation circuit 10 when the voltage of the first electrode of the driving transistor T3 changes, so that the voltage of the gate of the driving transistor T3 is Vdata+VDD-(Vref-Vth), and Vdata is the voltage of the data signal Data. The gate-source voltage difference Vgs of the driving transistor T3 is Vdata-Vref+Vth, and the current I of the driving transistor T3 is (μWCox / 2L)×(Vdata-Vref) 2 =(μWCox / 2L)×(Vdata-Vref) 2 μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the length of the channel of the driving transistor T3.

[0134] It can be seen that, in the case that the voltage Vref of the first reset signal Ref is constant, the size of the current can be controlled only by adjusting the voltage Vdata of the data signal Data, so as to adjust the brightness, thereby avoiding the influence of the threshold voltage Vth and the voltage drop of the first power signal, and the constant voltage of the first reset signal Ref is not easy to fluctuate, which is beneficial to maintaining the stability of the voltage of the gate of the driving transistor T3 and ensuring the uniform brightness.

[0135] As shown in Figs. 24 and 25, based on the pixel circuit in Fig. 5, in the second type of embodiment of the driving method, the driving method comprises:

[0136] As shown in Fig. 26, at the first stage t1, the data signal Data is transmitted to the gate of the driving transistor T3 by the write circuit 40 controlled by the signal of the write control terminal G2, and meanwhile, the voltage Vdata of the data signal Data is less than the voltage VDD of the first power signal, so that the driving transistor T3 is turned on, the voltage of the first electrode of the driving transistor T3 is gradually reduced from VDD-Vds (the voltage at the time of the previous frame light emission) until Vdata-Vth is reached, the driving transistor T3 is turned off, and thus the threshold voltage Vth of the driving transistor T3 is written to the first electrode thereof.

[0137] As shown in Fig. 27, at the second stage t2, the first reset signal Ref is transmitted to the gate of the driving transistor T3 by the first reset circuit 30 controlled by the signal of the first reset control terminal G1. Meanwhile, the compensation circuit 10 is turned off, so that when the gate of the driving transistor T3 is written with the first reset signal Ref, the first electrode of the driving transistor T3 can maintain the voltage written at the first stage t1 without being disturbed.

[0138] As shown in FIG. 28, in the third stage t3, the first light emitting control circuit 20 is turned on by the signal of the first light emitting control terminal G4, and the first power signal is transmitted to the first electrode of the driving transistor T3, so that the voltage of the first electrode is the voltage VDD of the first power signal; at the same time, the voltage of the first electrode of the driving transistor T3 is coupled to the gate electrode of the driving transistor T3 by the compensation circuit 10 when the voltage of the first electrode of the driving transistor T3 changes, so that the voltage VDD of the first power signal and the threshold voltage of the driving transistor T3 are coupled to the gate electrode of the driving transistor T3, and the voltage of the gate electrode of the driving transistor T3 is Vref+VDD-(Vdata-Vth), wherein Vref is the voltage of the first reset signal Ref. The gate-source voltage Vgs of the driving transistor T3 is Vref+VDD-(Vdata-Vth)-VDD=Vref-Vdata+Vth, and the current I of the driving transistor T3 is (μWCox / 2L)×(Vgs-Vth) 2 =(μWCox / 2L)×(Vref-Vdata) 2 It can be seen that, in the case that the voltage of the first reset signal Ref is constant, the size of the current can be controlled by adjusting only the voltage Vdata of the data signal Data, so as to adjust the brightness, thereby avoiding the influence of the threshold voltage Vth and the voltage drop of the first power signal.

[0139] Based on the above two types of driving methods, as shown in FIG. 9 and FIG. 24, in some embodiments of the present disclosure, for the pixel circuit with the second light emitting control circuit 50, the second light emitting control circuit 50 and the first light emitting control circuit 20 can be turned on and turned off at the same time, so that the light emission of the light emitting device LD and the process of writing the threshold voltage Vth and the voltage VDD of the first power signal into the gate electrode of the driving transistor T3 are both performed in the third stage. Correspondingly, the driving method further comprises:

[0140] In the third stage t3, the second light emitting control circuit 50 is turned on by the second light emitting control terminal G6, so that the light emitting device LD emits light.

[0141] The first light emitting control terminal G4 and the second light emitting control terminal G6 can be connected, and the two can transmit the light emitting control signal EM at the same time. Of course, the first light emitting control terminal G4 and the second light emitting control terminal G6 can also be independently arranged, but receive the same light emitting control signal EM.

[0142] Based on the two types of driving methods described above, as shown in FIGS. 5-8, 14 and 15, in some embodiments of the present disclosure, for the pixel circuit with the second light-emitting control circuit 50, the second light-emitting control circuit 50 and the first light-emitting control circuit 20 are not turned on and off at the same time, so that the light emission of the light-emitting device LD is performed after the threshold voltage and the voltage VDD of the first power supply signal are written to the gate of the driving transistor T3, and correspondingly, the driving method further comprises:

[0143] In a fourth stage t4 after the third stage t3, the second light-emitting control circuit 50 is turned on by controlling the second light-emitting control terminal G6, so that the light-emitting device LD emits light. The light emission duration of the light-emitting device LD can be controlled by controlling the second light-emitting control circuit 50.

[0144] The first light-emitting control terminal G4 can transmit the first light-emitting control signal EM1, and the second light-emitting control terminal G6 can transmit the second light-emitting control signal EM2; in the third stage t3, the second light-emitting control circuit 50 is turned off, and the first light-emitting control circuit 20 is turned on, so that the voltage VDD of the first power supply signal is written to the first electrode of the driving transistor T3, and is coupled to the gate through the compensation circuit 10; in the fourth stage t4, the first light-emitting control circuit 20 and the second light-emitting control circuit 50 are turned on at the same time, so that the light-emitting device LD emits light.

[0145] Based on the two types of driving methods described above, as shown in FIGS. 6, 8, 18, 19, 22, 23, 31 and 32, in some embodiments of the present disclosure, for the pixel circuit with the second reset circuit 60, the first electrode of the driving transistor T3 can be reset before the threshold voltage is written to the first electrode; correspondingly, the driving method further comprises:

[0146] In a fifth stage t5 before the first stage t1, the second reset control circuit is controlled to transmit the second reset signal Init1 to the first electrode of the driving transistor T3 by controlling the second reset control terminal G8.

[0147] The second reset control terminal G8 can transmit the second reset control signal Rst2 to control the turning on and off of the second reset control circuit.

[0148] Based on the two types of driving methods described above, as shown in FIGS. 7, 8, 22-23, in some embodiments of the present disclosure, for the pixel circuit with the third reset circuit 70, the voltage of the first electrode of the light-emitting device LD can be reset before the light-emitting device LD emits light; for example, the driving method further comprises:

[0149] In the first stage t1, the third reset control circuit is controlled to transmit the third reset signal to the light-emitting device LD by controlling the third reset control terminal G9.

[0150] The third reset control terminal G9 can be connected with the first reset control terminal G1, so that they can be controlled by the same signal, or the third reset control terminal G9 can be independent of the first reset control terminal G1, but can transmit the same signal. Of course, in some embodiments, the third reset control terminal G9 and the first reset control terminal G1 can also transmit different signals, as long as the light emitting device LD can be reset before emitting light. For the pixel circuit with the second light emitting control circuit 50, the third reset control circuit is turned on before the second light emitting control circuit 50 is turned on.

[0151] Based on the above two types of driving methods, as shown in FIGS. 5-13, in some embodiments of the present disclosure, for the compensation circuit 10 which can include the coupling capacitor Cc and the coupling control circuit 110, the on and off of the coupling control circuit 110 can be controlled by the coupling control terminal G7, and in the second stage t2, the off of the coupling control circuit 110 can be controlled by the coupling control terminal G7 to prevent the writing of the data signal Data from affecting the voltage of the first electrode of the driving transistor T3; in the third stage t3, the coupling control circuit 110 is turned on to couple the voltage of the first electrode to the gate of the driving transistor T3; in the first stage t1, the coupling control circuit 110 can be turned on or off.

[0152] As shown in FIGS. 16 and 17, in some embodiments, the coupling control terminal G7 can be connected with the first light emitting control terminal G4, and the first light emitting control circuit 20 and the coupling control circuit 110 can be synchronously turned on and off by the light emitting control signal EM. Of course, the coupling control terminal G7 can also be independently set with the first light emitting control terminal G4, and the coupling control signal Ctl can be transmitted through the coupling control terminal G7 to control the on and off of the coupling control circuit 110.

[0153] Based on the above first type of driving method, as shown in FIGS. 9-13, in some embodiments of the present disclosure, for the first reset circuit 30 with the connection transistor T5, the connection control terminal G5 can be connected with the first reset control terminal G1, so that the connection transistor T5 and the first reset transistor T1 are synchronously turned on and off. In the first stage t1, the first reset signal Ref can be transmitted to the gate and the second electrode of the driving transistor T3.

[0154] Based on the above second type of driving method, as shown in FIGS. 24-28, in some embodiments of the present disclosure, for the first reset circuit 30 with the connection transistor T5, the connection control terminal G5 can be connected with the writing control terminal G2, so that the connection transistor T5 and the writing transistor T2 are synchronously turned on and off. In the first stage t1, the data signal Data can be transmitted to the gate and the second electrode of the driving transistor T3.

[0155] Based on the above description, the following will be exemplarily described in combination with various pixel circuits and their working principles:

[0156] First embodiment

[0157] As shown in FIG. 9, the pixel circuit includes the first reset transistor T1, the write transistor T2, the drive transistor T3, the first light-emitting control transistor T4, the connection transistor T5, the second light-emitting control transistor T6, the coupling control transistor T7, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor, and the specific connection relationship will not be described here.

[0158] The signals of the first reset control terminal G1 and the connection control terminal G5 are both the first reset control signal Rst1, and the first reset control terminal G1 and the connection control terminal G5 can be connected; the signal of the write control terminal G2 is the write control signal Gate; the signals of the first light-emitting control terminal G4 and the second light-emitting control terminal G6 are both the light-emitting control signal EM, and the first light-emitting control terminal G4 and the second light-emitting control terminal G6 can be connected; and the signal of the coupling control terminal G7 is the coupling control signal Ctl.

[0159] As shown in FIG. 10, in combination with the first type of driving method described above, the driving method of the pixel circuit includes:

[0160] As shown in FIG. 11, in the first stage t1, the first reset control signal Rst1 is at a low level, the first reset transistor T1 and the connection transistor T5 are turned on, and the first reset signal Ref is written to the first node N1 and the third node N3 to reset the first node N1 and the third node N3; at the same time, since the voltage of the second node N2 at the end of the last frame of light emission is VDD-Vds, and the voltage of the first reset signal Ref is less than the voltage VDD of the first power signal, the drive transistor T3 is turned on until the voltage of the second node N2 reaches Vref-Vth, and then the drive transistor T3 is turned off, so as to write the threshold voltage of the drive transistor T3 to its first electrode. At the same time, the coupling control signal Ctl is at a low level, and the coupling control transistor T7 is turned on. The write control signal Gate and the light-emitting control signal EM are at a high level, and the write transistor T2, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are turned off.

[0161] As shown in Fig. 12, at the second stage t2, the write control signal Gate is at low level, the write transistor T2 is turned on, and the data signal Data is written into the first node N1; the first reset control signal Rst1, the coupling control signal Ctl and the light-emitting control signal EM are all at high level, the first reset transistor T1, the connecting transistor T5, the coupling control transistor T7, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned off; the voltage of the first node is the voltage of the data signal Data, and the voltage of the second node N2 is maintained at Vref-Vth, which is not disturbed by the data signal Data.

[0162] As shown in Fig. 13, at the third stage t3, the light-emitting control signal EM and the coupling control signal Ctl are at low level, the coupling control transistor T7, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned on, the voltage VDD of the first power signal is written into the second node N2 (the voltage drop caused by the first light-emitting control transistor T4 can be ignored due to its small cross voltage), and the voltage of the first node N1 jumps with the change of the voltage of the second node N2 under the action of the coupling capacitor Cc, so that the voltage of the first node N1 becomes Vdata+VDD-(Vref-Vth), thereby writing the voltage VDD of the first power signal and the threshold voltage of the driving transistor T3 into the first node N1. At the same time, since the second light-emitting control transistor T6 is also turned on, the current I of the driving transistor T3 is I=(μWCox / 2L)×(Vgs-Vth) 2 =(μWCox / 2L)×(Vdata-Vref) 2 It can be seen that, in the case that the voltage of the first reset signal Ref is constant, the size of the current can be controlled by adjusting the voltage of the data signal Data only, thereby adjusting the brightness, so that the influence of the threshold voltage and the voltage drop of the first power signal is avoided. Since the coupling control transistor T7 is turned on, the voltage of the fourth node N4 can be maintained by the storage capacitor Cst.

[0163] In addition, the write control signal Gate and the first reset control signal Rst1 are both at high level, and the write transistor T2, the first reset transistor T1 and the connecting transistor T5 are all turned off.

[0164] Second embodiment

[0165] As shown in Fig. 14 and Fig. 15, the pixel circuit includes the first reset transistor T1, the write transistor T2, the driving transistor T3, the first light-emitting control transistor T4, the connecting transistor T5, the second light-emitting control transistor T6, the coupling control transistor T7, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor, and the specific connection relationship is not described here again.

[0166] The signal of the first reset control terminal G1 and the signal of the connection control terminal G5 are both the first reset control signal Rst1, and the first reset control terminal G1 and the connection control terminal G5 can be connected; the signal of the write control terminal G2 is the write control signal Gate; the signal of the first light-emitting control terminal G4 is the first light-emitting control signal EM1, and the signal of the second light-emitting control terminal G6 is the second light-emitting control signal EM2; and the signal of the coupling control terminal G7 is the coupling control signal Ctl.

[0167] As shown in FIG. 15, in combination with the above-mentioned first driving method, the driving method of the pixel circuit comprises:

[0168] In the first stage t1, the first reset control signal Rst1 is at a low level, the first reset transistor T1 and the connection transistor T5 are turned on, and the first reset signal Ref is written to the first node N1 and the third node N3; at the same time, the voltage Vref of the first reset signal Ref is less than the voltage VDD of the first power signal, and the threshold voltage Vth of the driving transistor T3 is written to the first electrode (Vref-Vth) thereof, and the specific principle can be referred to the above-mentioned driving method of the first pixel circuit, which will not be described here. At the same time, the coupling control signal Ctl is at a low level, and the coupling control transistor T7 is turned on. The write control signal Gate, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a high level, and the write transistor T2, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are turned off.

[0169] In the second stage t2, the write control signal Gate is at a low level, the write transistor T2 is turned on, and the data signal Data is written to the first node N1; the first reset control signal Rst1, the coupling control signal Ctl, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are all at a high level, and the first reset transistor T1, the connection transistor T5, the coupling control transistor T7, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned off; the voltage of the first node is the voltage of the data signal Data, and the voltage of the second node N2 is maintained at Vref-Vth and is not disturbed by the data signal Data.

[0170] In the third stage t3, the first light emitting control signal EM1 and the coupling control signal Ctl are low, the coupling control transistor T7 and the first light emitting control transistor T4 are turned on, the second node N2 writes the voltage VDD of the first power signal, and the voltage VDD of the first power signal and the threshold voltage Vth of the driving transistor T3 are written into the first node N1 under the action of the coupling capacitor Cc. The specific principle can be referred to the driving method of the first pixel circuit, and will not be described here.

[0171] In the fourth stage t4, the first light emitting control signal EM1, the second light emitting control signal EM2 and the coupling control signal Ctl are low, the first light emitting control transistor T4, the second light emitting control transistor T6 and the coupling control transistor T7 are turned on, and the light emitting device LD emits light. The specific principle can be referred to the driving method of the first pixel circuit, and will not be described here. At the same time, the first reset control signal Rst1, the write control signal Gate and the coupling first reset control signal Rst1 are high. The voltage of the fourth node N4 can be maintained by the storage capacitor Cst.

[0172] Third embodiment

[0173] As shown in FIG. 16 and FIG. 17, the pixel circuit includes the first reset transistor T1, the write transistor T2, the driving transistor T3, the first light emitting control transistor T4, the connection transistor T5, the second light emitting control transistor T6, the coupling control transistor T7, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor. The specific connection relationship will not be described here.

[0174] The signals of the first reset control end G1 and the connection control end G5 are the first reset control signal Rst1, and the first reset control end G1 and the connection control end G5 can be connected; the signal of the write control end G2 is the write control signal Gate; the signals of the coupling control end G7, the first light emitting control end G4 and the second light emitting control end G6 are the light emitting control signal EM, and the coupling control end G7, the first light emitting control end G4 and the second light emitting control end G6 can be connected.

[0175] The driving method of the third embodiment can refer to the driving method of the first embodiment, and the main difference is that the coupling control transistor T7 is turned on and turned off synchronously with the first light emitting control transistor T4, that is, in the first stage t1, the coupling control transistor T7 is turned off, and will not be described here in detail.

[0176] Fourth embodiment

[0177] As shown in FIG. 18, the pixel circuit includes the first reset transistor T1, the write transistor T2, the drive transistor T3, the first light-emitting control transistor T4, the connection transistor T5, the second light-emitting control transistor T6, the coupling control transistor T7, the second reset transistor T8, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor, and the specific connection relationship is not described here again.

[0178] The signals of the first reset control terminal G1 and the connection control terminal G5 are both the first reset control signal Rst1, and the first reset control terminal G1 and the connection control terminal G5 can be connected; the signal of the write control terminal G2 is the write control signal Gate; the signals of the first light-emitting control terminal G4 and the second light-emitting control terminal G6 are the light-emitting control signal EM, and the first light-emitting control terminal G4 and the second light-emitting control terminal G6 can be connected; the signal of the coupling control terminal G7 is the coupling control signal Ctl; and the signal of the second reset control terminal G8 is the second reset control signal Rst2.

[0179] As shown in FIG. 19, in combination with the first type of driving method described above, the driving method of the pixel circuit includes:

[0180] In the fifth stage t5, the second reset control signal Rst2 and the coupling control signal Ctl are low, the second reset transistor T8 and the coupling control transistor T7 are turned on, the second reset signal Init1 is written to the second node N2 and the fourth node N4, and the reset is realized. The first reset control signal Rst1, the write control signal Gate and the light-emitting control signal EM are all high, and the first reset transistor T1, the write transistor T2, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned off.

[0181] In the first stage t1, the first reset control signal Rst1 is low, the first reset transistor T1 and the connection transistor T5 are turned on, and the first reset signal Ref is written to the first node N1 and the third node N3; the first electrode of the light-emitting device LD is reset. At the same time, the voltage Vref of the first reset signal Ref is less than the voltage VDD of the first power signal, and the threshold voltage of the drive transistor T3 is written to its first electrode (Vref-Vth), and the specific principle can refer to the driving method of the first pixel circuit in the above, which is not described here again. At the same time, the coupling control signal Ctl is low, and the coupling control transistor T7 is turned on. The second reset control signal Rst2, the write control signal Gate and the light-emitting control signal EM are high, and the second reset transistor T8, the write transistor T2, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are turned off.

[0182] In the second stage t2, the write control signal Gate is low, the write transistor T2 is turned on, and the data signal Data is written into the first node N1; the first reset control signal Rst1, the second reset control signal Rst2, the coupling control signal Ctl and the light-emitting control signal EM are all high, the first reset transistor T1, the second reset transistor T8, the connection transistor T5, the coupling control transistor T7, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned off; the voltage of the first node N1 is the voltage Vdata of the data signal Data, and the voltage of the second node N2 is maintained as Vref-Vth, which is not disturbed by the data signal Data.

[0183] In the third stage t3, the light-emitting control signal EM and the coupling control signal Ctl are low, the coupling control transistor T7, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned on, the voltage VDD of the first power signal is written into the second node N2, and the voltage VDD of the first power signal and the threshold voltage of the driving transistor T3 are written into the first node N1 under the action of the coupling capacitor Cc. The specific principle can refer to the driving method of the first pixel circuit in the above, and will not be described here. At the same time, the write control signal Gate, the first reset control signal Rst1 and the second reset control signal Rst2 are all high, and the write transistor T2, the first reset transistor T1 and the connection transistor T5 are all turned off.

[0184] Fifth embodiment

[0185] As shown in FIG. 20, the pixel circuit includes the first reset transistor T1, the write transistor T2, the driving transistor T3, the first light-emitting control transistor T4, the connection transistor T5, the second light-emitting control transistor T6, the coupling control transistor T7, the third reset transistor T9, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor, and the specific connection relationship will not be described here.

[0186] The signals of the first reset control end G1 and the connection control end G5 are the first reset control signal Rst1, and the first reset control end G1 and the connection control end G5 can be connected; the signal of the write control end G2 is the write control signal Gate; the signals of the first light-emitting control end G4 and the second light-emitting control end G6 are the light-emitting control signal EM, and the first light-emitting control end G4 and the second light-emitting control end G6 can be connected; the signal of the coupling control end G7 is the coupling control signal Ctl; the signal of the third reset control end G9 is the third reset control signal Rst3, and the third reset control signal Rst3 and the first reset control signal Rst1 can be the same signal (pulse signals with the same frequency, pulse width and amplitude), or the third reset control end G9 can be connected with the first reset control end G1 and the connection control end G5 to adopt the same signal.

[0187] As shown in FIG. 21, in combination with the first driving method described above, the driving method of the pixel circuit comprises:

[0188] In the first stage t1, the first reset control signal Rst1 and the third reset control signal Rst3 are low, the first reset transistor T1, the connecting transistor T5 and the third reset transistor T9 are turned on, and the first reset signal Ref is written into the first node N1 and the third node N3; the third reset signal Init2 is written into the fifth node N5, and the first electrode of the light emitting device LD is reset. At the same time, the voltage Vref of the first reset signal Ref is less than the voltage VDD of the first power signal, and the threshold voltage Vth of the driving transistor T3 is written into the first electrode (Vref-Vth) thereof, and the specific principle can be referred to the driving method of the first pixel circuit in the above, which will not be described here. At the same time, the coupling control signal Ctl is low, and the coupling control transistor T7 is turned on. The write control signal Gate and the light emitting control signal EM are high, and the write transistor T2, the first light emitting control transistor T4 and the second light emitting control transistor T6 are turned off.

[0189] In the second stage t2, the write control signal Gate is low, the write transistor T2 is turned on, and the data signal Data is written into the first node N1; the first reset control signal Rst1, the third reset control signal Rst3, the coupling control signal Ctl and the light emitting control signal EM are all high, and the first reset transistor T1, the third reset transistor T9, the connecting transistor T5, the coupling control transistor T7, the first light emitting control transistor T4 and the second light emitting control transistor T6 are all turned off; the voltage of the first node is the voltage Vdata of the data signal Data, and the voltage of the second node N2 is maintained as Vref-Vth, which is not disturbed by the data signal Data.

[0190] In the third stage t3, the light emitting control signal EM and the coupling control signal Ctl are low, the coupling control transistor T7, the first light emitting control transistor T4 and the second light emitting control transistor T6 are all turned on, the second node N2 writes the voltage VDD of the first power signal, and under the action of the coupling capacitor Cc, the voltage VDD of the first power signal and the threshold voltage of the driving transistor T3 are written into the first node N1, and the specific principle can be referred to the driving method of the first pixel circuit in the above, which will not be described here. At the same time, the write control signal Gate, the first reset control signal Rst1 and the third reset control signal Rst3 are all high, and the write transistor T2, the first reset transistor T1 and the connecting transistor T5 are all turned off.

[0191] Sixth embodiment

[0192] As shown in FIG. 22 and FIG. 23, the pixel circuit includes the first reset transistor T1, the write transistor T2, the drive transistor T3, the first light-emitting control transistor T4, the connection transistor T5, the second light-emitting control transistor T6, the coupling control transistor T7, the second reset transistor T8, the third reset transistor T9, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor, and the specific connection relationship is not described here.

[0193] The signals of the first reset control terminal G1 and the connection control terminal G5 are both the first reset control signal Rst1, and the first reset control terminal G1 and the connection control terminal G5 can be connected; the signal of the write control terminal G2 is the write control signal Gate; the signals of the first light-emitting control terminal G4 and the second light-emitting control terminal G6 are the light-emitting control signal EM, and the first light-emitting control terminal G4 and the second light-emitting control terminal G6 can be connected; the signal of the coupling control terminal G7 is the coupling control signal Ctl; the signal of the second reset control terminal G8 is the second reset control signal Rst2, the signal of the third reset control terminal G9 is the third reset control signal Rst3, and the third reset control signal Rst3 and the first reset control signal Rst1 can be the same signal (pulse signals with the same frequency, pulse width and amplitude), or the third reset control terminal G9 can be connected with the first reset control terminal G1 and the connection control terminal G5 to adopt the same signal.

[0194] As shown in FIG. 23, in combination with the first driving method described above, the driving method of the pixel circuit includes:

[0195] In the fifth stage t5, the second reset control signal Rst2 and the coupling control signal Ctl are low, the second reset control transistor and the coupling control transistor T7 are turned on, the second reset signal Init1 is written into the second node N2 and the fourth node N4, and the reset is realized. The first reset control signal Rst1, the third reset control signal Rst3, the write control signal Gate and the light-emitting control signal EM are all high, and the first reset transistor T1, the third reset transistor T9, the write transistor T2, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned off.

[0196] In the first stage t1, the first reset control signal Rst1 and the third reset control signal Rst3 are low, the first reset transistor T1, the connection transistor T5 and the third reset transistor T9 are turned on, and the first reset signal Ref is written into the first node N1 and the third node N3; the third reset signal Init2 is written into the fifth node N5, and the first electrode of the light emitting device LD is reset. At the same time, the voltage Vref of the first reset signal Ref is less than the voltage VDD of the first power signal, and the threshold voltage of the driving transistor T3 is written into the first electrode (Vref-Vth), and the specific principle can refer to the driving method of the first pixel circuit in the foregoing, which will not be described here. At the same time, the coupling control signal Ctl is low, and the coupling control transistor T7 is turned on. The second reset control signal Rst2, the write control signal Gate and the light emitting control signal EM are high, and the second reset transistor T8, the write transistor T2, the first light emitting control transistor T4 and the second light emitting control transistor T6 are turned off.

[0197] In the second stage t2, the write control signal Gate is low, the write transistor T2 is turned on, and the data signal Data is written into the first node N1; the first reset control signal Rst1, the second reset control signal Rst2, the third reset control signal Rst3, the coupling control signal Ctl and the light emitting control signal EM are all high, and the first reset transistor T1, the second reset transistor T8, the third reset transistor T9, the connection transistor T5, the coupling control transistor T7, the first light emitting control transistor T4 and the second light emitting control transistor T6 are all turned off; the voltage of the first node N1 is the voltage Vata of the data signal Data, and the voltage of the second node N2 is maintained as Vref-Vth and is not disturbed by the data signal Data.

[0198] In the third stage t3, the light emitting control signal EM and the coupling control signal Ctl are low, the coupling control transistor T7, the first light emitting control transistor T4 and the second light emitting control transistor T6 are all turned on, the voltage VDD of the first power signal is written into the second node N2, and the voltage VDD of the first power signal and the threshold voltage of the driving transistor T3 are written into the first node N1 under the action of the coupling capacitor Cc. The specific principle can refer to the driving method of the first pixel circuit in the foregoing, which will not be described here. At the same time, the write control signal Gate, the first reset control signal Rst1, the second reset control signal Rst2 and the third reset control signal Rst3 are all high, and the write transistor T2, the first reset transistor T1 and the connection transistor T5 are all turned off.

[0199] Seventh implementation

[0200] As shown in FIG. 24, the pixel circuit includes the first reset transistor T1, the write transistor T2, the drive transistor T3, the first light-emitting control transistor T4, the connection transistor T5, the second light-emitting control transistor T6, the coupling control transistor T7, the coupling capacitor Cc and the storage capacitor Cst mentioned above, and each transistor is a P-type polysilicon transistor, and the specific connection relationship is not described here again.

[0201] The signals of the write control terminal G2 and the connection control terminal G5 are both write control signals Gate, and the write control terminal G2 and the connection control terminal G5 can be connected; the signal of the first reset control terminal G1 is a first reset control signal Rst1; the signal of the write control terminal G2 is a write control signal Gate; the signals of the first light-emitting control terminal G4 and the second light-emitting control terminal G6 are both light-emitting control signals EM, and the first light-emitting control terminal G4 and the second light-emitting control terminal G6 can be connected; and the signal of the coupling control terminal G7 is a coupling control signal Ctl.

[0202] As shown in FIG. 25, in combination with the second type of driving method described above, the driving method of the pixel circuit includes:

[0203] As shown in FIG. 26, in the first stage t1, the write control signal Gate is at a low level, the write transistor T2 and the connection transistor T5 are turned on, and the data signal Data is written into the first node N1 and the third node N3; at the same time, since the voltage of the second node N2 at the end of the light-emitting of the previous frame is VDD-Vds, and the voltage Vdata of the data signal Data is less than the voltage VDD of the first power signal, the drive transistor T3 is turned on until the voltage of the second node N2 reaches Vdata-Vth, the drive transistor T3 is turned off, thereby writing the threshold voltage Vth of the drive transistor T3 into the first electrode thereof. At the same time, the coupling control signal Ctl is at a low level, and the coupling control transistor T7 is turned on. The first reset control signal Rst1 and the light-emitting control signal EM are at a high level, and the first reset control transistor, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are turned off.

[0204] As shown in FIG. 27, in the second stage t2, the first reset control signal Rst1 is at a low level, the first reset transistor T1 is turned on, and the first reset signal Ref is written into the first node N1; the write control signal Gate, the coupling control signal Ctl and the light-emitting control signal EM are all at a high level, and the write transistor T2, the connection transistor T5, the coupling control transistor T7, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are all turned off; the voltage of the first node N1 is the voltage Vref of the first reset signal Ref, and the voltage of the second node N2 is maintained at Vdata-Vth and is not disturbed by the first reset signal Ref.

[0205] As shown in FIG. 28, at the third stage t3, the light emitting control signal EM and the coupling control signal Ctl are low, the coupling control transistor T7, the first light emitting control transistor T4 and the second light emitting control transistor T6 are all turned on, the second node N2 writes the voltage VDD of the first power signal (the voltage drop caused by the first light emitting control transistor T4 is small and can be ignored), and under the action of the coupling capacitor Cc, the voltage of the first node N1 jumps with the change of the voltage of the second node N2, and the voltage of the first node N1 becomes Vref+VDD-(Vdata-Vth), so as to write the voltage VDD of the first power signal and the threshold voltage Vth of the driving transistor T3 into the first node N1. At the same time, since the second light emitting control transistor T6 is also turned on, the current I of the driving transistor T3 is I=(μWCox / 2L)×(Vgs-Vth) 2 =(μWCox / 2L)×(Vref-Vdata) 2 It can be seen that, in the case that the voltage of the first reset signal Ref is constant, the size of the current can be controlled only by adjusting the voltage of the data signal Data, so as to adjust the brightness, thereby avoiding the influence of the threshold voltage and the voltage drop of the first power signal. Since the coupling control transistor T7 is turned on, the voltage of the fourth node N4 can be maintained by the storage capacitor Cst.

[0206] In addition, the write control signal Gate and the first reset control signal Rst1 are both high, and the write transistor T2, the first reset transistor T1 and the connection transistor T5 are all turned off.

[0207] Based on the driving method of the seventh embodiment, the data signal Data is written into the first node N1 at the first stage t1, and the first reset signal Ref is written into the first node N1 at the second stage t2. The embodiments of the present disclosure can also include other embodiments, for example:

[0208] In some embodiments, based on the seventh embodiment, the signals of the write control end G2 and the connection control end G5 are both the write control signal Gate, and the write control end G2 and the connection control end G5 can be connected; the signal of the first reset control end G1 is the first reset control signal Rst1; the signal of the first light emitting control end G4 is the first light emitting control signal EM1, the signal of the second light emitting control end G6 is the second light emitting control signal EM2; the signal of the coupling control end G7 is the coupling control signal Ctl; the specific principle can be referred to the second embodiment and the seventh embodiment in the foregoing, which will not be described in detail here.

[0209] In some embodiments, based on the seventh implementation, the signals of the write control end G2 and the connection control end G5 are both write control signals Gate, and the write control end G2 and the connection control end G5 can be connected; the signal of the first light emitting control end G4 and the second light emitting control end G6 is a light emitting control signal EM, and the first light emitting control end G4 and the second light emitting control end G6 can be connected; the signal of the coupling control end G7 is a coupling control signal Ctl; the signal of the first reset control end G1 is a first reset control signal Rst1; the signal of the second reset control end G8 is a second reset control signal Rst2, and the signal of the third reset control end G9 is a third reset control signal Rst3. The specific principles can refer to the third implementation and the seventh implementation in the foregoing, and will not be described in detail here.

[0210] In some embodiments, based on the seventh implementation, the signals of the write control end G2 and the connection control end G5 are both write control signals Gate, and the write control end G2 and the connection control end G5 can be connected; the signal of the first light emitting control end G4 and the second light emitting control end G6 is a light emitting control signal EM, and the first light emitting control end G4 and the second light emitting control end G6 can be connected; the signal of the coupling control end G7 is a coupling control signal Ctl; the signal of the first reset control end G1 is a first reset control signal Rst1; the signal of the second reset control end G8 is a second reset control signal Rst2, and the signal of the third reset control end G9 is a third reset control signal Rst3. The specific principles can refer to the third implementation and the seventh implementation in the foregoing, and will not be described in detail here.

[0211] In addition, in other implementations of the present disclosure, some of the transistors in the pixel circuit can be N-type metal oxide transistors, and the other transistors can be P-type polysilicon transistors, for example:

[0212] Eighth implementation

[0213] As shown in FIGS. 29 and 30, based on the first implementation, the first reset transistor T1, the write transistor T2 and the connection transistor T5 are N-type metal oxide transistors, and the other transistors are P-type polysilicon transistors. The specific connection relationship and driving timing will not be described here.

[0214] Ninth implementation

[0215] As shown in FIGS. 31 and 32, based on the fourth implementation, the pixel circuit has a second reset transistor T8, the first reset transistor T1, the write transistor T2, the second reset transistor T8 and the connection transistor T5 are N-type metal oxide transistors, and the other transistors are P-type polysilicon transistors. The specific connection relationship and driving timing will not be described here.

[0216] Tenth implementation

[0217] As shown in FIG. 33 and FIG. 34, based on the sixth embodiment, the pixel circuit has the second reset transistor T8, the first reset transistor T1, the write transistor T2, the second reset transistor T8 and the connection transistor T5 adopt N-type metal oxide transistors, and other transistors adopt P-type polysilicon transistors. The specific connection relationship and driving timing are not described here again.

[0218] By using the characteristics of smaller drain current of N-type metal oxide transistors, the drain current of the first node N1, the second node N2 and the fourth node N4 is reduced, and by using the characteristics of higher mobility of P-type polysilicon transistors, the current driving requirement is met, and the display effect is improved.

[0219] In addition, in the embodiment of using N-type transistors, the driving timing can refer to any of the above embodiments, and the difference is that the N-type transistor is turned on at high level and turned off at low level.

[0220] Based on the above embodiments and the concepts reflected therein, other embodiments including other pixel circuits and driving methods can be obtained by mutual combination, which are not listed one by one here.

[0221] It should be noted that although the steps of the driving method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc.

[0222] For the first type of display panel in the above, the driving backplane BP can include a substrate SU and a polysilicon semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, a first source-drain layer SD1, and a second source-drain layer SD2 arranged in sequence in a direction away from the substrate SU. The polysilicon semiconductor layer SE can be made of low-temperature polysilicon process, and can include the active part of each P-type polysilicon transistor of the pixel circuit.

[0223] In addition, the driving backplane BP can further include a first gate insulating layer GI1, a second gate insulating layer GI2, a first insulating layer IL1, a first planar layer PLN1 and a second planar layer PLN2 of insulating material, wherein:

[0224] The first gate insulating layer GIl covers the polysilicon semiconductor layer SE, and the first gate layer GA1 is arranged on a surface of the first gate insulating layer GIl away from the substrate SU. The second gate insulating layer GI2 covers the first gate layer GA1, and the second gate layer GA2 is arranged on a surface of the second gate insulating layer GI2 away from the substrate SU. The first insulating layer IL1 can cover the second gate layer GA2, and the first source-drain layer SD1 is arranged on a surface of the first insulating layer IL1 away from the substrate SU. The first planar layer PLN1 can cover the first source-drain layer SD1. The second source-drain layer SD2 can be arranged on a surface of the first planar layer PLN1 away from the substrate SU. The second planar layer PLN2 can cover the second source-drain layer SD2. The first electrode ANO and the pixel definition layer PDL of the light-emitting device LD can be arranged on a surface of the second planar layer PLN2 away from the substrate SU.

[0225] For the second type of display panel in the foregoing, the driving backplane BP can include a substrate SU and, in sequence along a direction away from the substrate SU, a polysilicon semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, an oxide semiconductor layer IG, a third gate layer GA3, a first source-drain layer SD1, and a second source-drain layer SD2. The polysilicon semiconductor layer SE can be made of low-temperature polysilicon and can include an active part of each P-type polysilicon transistor of a pixel circuit. The oxide semiconductor layer IG can be made of IGZO (Indium Gallium Zinc Oxide) or IZO (Indium Zinc Oxide) or other metal oxides, and can include an active part of each N-type metal oxide transistor of a pixel circuit.

[0226] In addition, the driving backplane BP can further include first and second gate insulating layers GIl and GI2, first and second insulating layers IL1 and IL2, and first and second planar layers PLN1 and PLN2 made of insulating materials, where:

[0227] A first gate insulating layer GI1 covers the polycrystal semiconductor layer SE, and a first gate layer GA1 is provided on a surface of the first gate insulating layer GI1 away from the substrate SU. A second gate insulating layer GI2 covers the first gate layer GA1, and a second gate layer GA2 is provided on a surface of the second gate insulating layer GI2 away from the substrate SU. A first insulating layer IL1 can cover the second gate layer GA2, and an oxide semiconductor layer IG is provided on a surface of the first insulating layer IL1 away from the substrate SU. A third gate insulating layer GI3 covers the oxide semiconductor layer IG, and a third gate layer GA3 is provided on a surface of the third gate insulating layer GI3 away from the substrate SU. A second insulating layer IL2 can cover the third gate layer GA3, and a first source-drain layer SD1 is provided on a surface of the second insulating layer IL2 away from the substrate SU. A first planar layer PLN1 can cover the first source-drain layer SD1. A second source-drain layer SD2 can be provided on a surface of the first planar layer PLN1 away from the substrate SU. A second planar layer PLN2 can cover the second source-drain layer SD2. A first electrode ANO and a pixel definition layer PDL of the light emitting device LD can be provided on a surface of the second planar layer PLN2 away from the substrate SU.

[0228] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. This application is intended to cover any variations, uses or adaptations of the disclosure including departures from the present disclosure that come within the scope of the general principles thereof following in the art. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the disclosure are indicated by the appended claims.

Claims

1. A pixel circuit, wherein, The pixel circuit comprises: a driving transistor; a compensation circuit connected to the first electrode and the gate electrode of the driving transistor, for coupling the voltage of the first electrode of the driving transistor to the gate electrode in response to a signal of a coupling control terminal; a first light emitting control circuit connected to the first electrode of the driving transistor, for transmitting a first power signal to the first electrode of the driving transistor in response to a signal of a first light emitting control terminal; the second electrode of the driving transistor is connected to a light emitting device; a first reset circuit connected to the gate electrode of the driving transistor, for writing a first reset signal to the gate electrode of the driving transistor in response to a signal of a first reset control terminal; a write circuit connected to the gate electrode of the driving transistor, for writing a data signal to the gate electrode of the driving transistor in response to a signal of a write control terminal; at least one of the first reset signal and the data signal is used to turn on the driving transistor.

2. The pixel circuit of claim 1, wherein, The compensation circuit comprises a coupling capacitor and a coupling control circuit; the first electrode of the coupling capacitor is connected to the gate electrode of the driving transistor, and the second electrode of the coupling capacitor is connected to the first electrode of the driving transistor through the coupling control circuit; the coupling control circuit is used to turn on and turn off in response to a signal of a coupling control terminal.

3. The pixel circuit of claim 2, wherein, The coupling control circuit comprises: a coupling control transistor, the first electrode of the coupling control transistor is connected to the first electrode of the driving transistor, the second electrode of the coupling control transistor is connected to the second electrode of the coupling capacitor, and the gate electrode of the coupling control transistor is connected to the coupling control terminal.

4. The pixel circuit of claim 1, wherein, The first reset circuit comprises a first reset transistor, the first electrode of the first reset transistor is used to receive the first reset signal, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, and the gate electrode of the first reset transistor is connected to the first reset control terminal.

5. The pixel circuit of claim 4, wherein, The first reset circuit further comprises a connection transistor, the first electrode of the connection transistor is connected to the gate electrode of the driving transistor, the second electrode of the connection transistor is connected to the second electrode of the driving transistor, and the gate electrode of the connection transistor is connected to a connection control terminal; the connection transistor is used to turn on and turn off in response to a signal of the connection control terminal.

6. The pixel circuit of claim 1, wherein, The first light emitting control circuit comprises a first light emitting control transistor, and the write circuit comprises a write transistor; the first electrode of the first light emitting control transistor is used to receive the first power signal, the second electrode of the first light emitting control transistor is connected to the first electrode of the driving transistor, and the gate electrode of the first light emitting control transistor is connected to the first light emitting control terminal; the first electrode of the write transistor is used to receive the data signal, the second electrode of the write transistor is connected to the gate electrode of the driving transistor, and the gate electrode of the write transistor is connected to the write control terminal.

7. The pixel circuit of claim 2, wherein, The pixel circuit further comprises: an energy storage circuit connected to the second electrode of the coupling capacitor and capable of receiving the first power signal.

8. The pixel circuit of claim 7, wherein, The energy storage circuit comprises a storage capacitor, the first electrode of the storage capacitor is connected to the second electrode of the coupling capacitor, and the second electrode of the storage capacitor is used to receive the first power signal.

9. The pixel circuit of claim 1, wherein, The pixel circuit further comprises: a second light emitting control circuit connected to the second electrode of the driving transistor and the light emitting device, for turning on and turning off in response to a signal of a second light emitting control terminal.

10. The pixel circuit of claim 9, wherein, The second light-emitting control circuit comprises a second light-emitting control transistor, a first electrode of the second light-emitting control transistor is connected with the second electrode of the driving transistor, a second electrode of the second light-emitting control transistor is connected with the light-emitting device, and a gate electrode of the second light-emitting control transistor is connected with the second light-emitting control terminal.

11. The pixel circuit of claim 1, wherein, The pixel circuit further comprises at least one of a second reset circuit and a third reset circuit. The second reset circuit is connected with the first electrode of the driving transistor, and is configured to transmit a second reset signal to the first electrode of the driving transistor in response to a signal of a second reset control terminal. The third reset circuit is connected with the light-emitting device, and is configured to transmit a third reset signal to the light-emitting device in response to a signal of a third reset control terminal.

12. The pixel circuit of claim 11, wherein, The second reset circuit comprises a second reset transistor, a first electrode of the second reset transistor is configured to receive the second reset signal, a second electrode of the second reset transistor is connected with the first electrode of the driving transistor, and a gate electrode of the second reset transistor is connected with the second reset control terminal. The third reset circuit comprises a third reset transistor, a first electrode of the third reset transistor is configured to receive the third reset signal, a second electrode of the third reset transistor is connected with the light-emitting device, and a gate electrode of the third reset transistor is connected with the third reset control terminal.

13. The pixel circuit of claim 5, wherein, The coupling control terminal is connected with the first light-emitting control terminal.

14. The pixel circuit of claim 5, wherein, One of the write control terminal and the first reset control terminal is connected with the connection control terminal.

15. A driving method of a pixel circuit, wherein The pixel circuit comprises a driving transistor, a compensation circuit, a first light-emitting control circuit, a first reset circuit and a write circuit. The compensation circuit is connected with the first electrode and the gate electrode of the driving transistor; the first light-emitting control circuit is connected with the first electrode of the driving transistor, and is configured to transmit a first power supply signal to the first electrode of the driving transistor; and a second electrode of the driving transistor is connected with a light-emitting device. The first reset circuit is connected with the gate electrode of the driving transistor. The write circuit is connected with the gate electrode of the driving transistor. The driving method comprises: In a first stage, the first reset circuit is controlled by the first reset control terminal to transmit a first reset signal to the gate electrode of the driving transistor, so as to write the threshold voltage of the driving transistor into the first electrode of the driving transistor; the voltage of the first reset signal is smaller than the voltage of the first power supply signal; In a second stage, the write circuit is controlled by the write control terminal to transmit a data signal to the gate electrode of the driving transistor; the voltage of the data signal is smaller than the voltage of the first reset signal; In a third stage, the first light-emitting control circuit is controlled by the first light-emitting control terminal to be turned on, and the voltage of the first electrode of the driving transistor is coupled to the gate electrode by the compensation circuit, so as to couple the voltage of the first power supply signal and the threshold voltage of the driving transistor to the gate electrode of the driving transistor.

16. The driving method according to claim 15, wherein The pixel circuit further comprises a second light-emitting control circuit, a second reset circuit and a third reset circuit, the second light-emitting control circuit is connected with the second electrode of the driving transistor and the light-emitting device; The second reset circuit is connected with the first electrode of the driving transistor; and the third reset circuit is connected with the light-emitting device. The driving method further comprises: in the third stage or a fourth stage after the third stage, controlling the second light emitting control circuit to be turned on through a second light emitting control terminal; in a fifth stage before the first stage, controlling the second reset control circuit to transmit a second reset signal to the first electrode of the driving transistor through a second reset control terminal; in the first stage, controlling the third reset control circuit to transmit a third reset signal to the light emitting device through a third reset control terminal.

17. A driving method of a pixel circuit, wherein The pixel circuit comprises a driving transistor, a compensation circuit, a first light emitting control circuit, a first reset circuit and a write-in circuit; the compensation circuit is connected to the first electrode and the gate electrode of the driving transistor; the first light emitting control circuit is connected to the first electrode of the driving transistor and is used for transmitting a first power supply signal to the first electrode of the driving transistor; the second electrode of the driving transistor is connected to the light emitting device; the first reset circuit is connected to the gate electrode of the driving transistor; the write-in circuit is connected to the gate electrode of the driving transistor; The driving method comprises: in a first stage, controlling the write-in circuit to transmit a data signal to the gate electrode of the driving transistor through a write-in control terminal, and writing the threshold voltage of the driving transistor into the first electrode of the driving transistor; the voltage of the data signal is less than the voltage of the first power supply signal; in a second stage, controlling the first reset control circuit to transmit a first reset signal to the gate electrode of the driving transistor through a first reset control terminal; the voltage of the first reset signal is less than the voltage of the data signal; in a third stage, controlling the first light emitting control circuit to be turned on through a first light emitting control terminal, and coupling the voltage of the first electrode of the driving transistor to the gate electrode through the compensation circuit, so that the voltage of the first power supply signal and the threshold voltage of the driving transistor are coupled to the gate electrode of the driving transistor.

18. The driving method according to claim 17, wherein The pixel circuit further comprises a second light emitting control circuit, a second reset circuit and a third reset circuit, and the second light emitting control circuit is connected to the second electrode of the driving transistor and the light emitting device; the second reset circuit is connected to the first electrode of the driving transistor; the third reset circuit is connected to the light emitting device; The driving method further comprises: in the third stage or a fourth stage after the third stage, controlling the second light emitting control circuit to be turned on through a second light emitting control terminal; in a fifth stage before the first stage, controlling the second reset control circuit to transmit a second reset signal to the first electrode of the driving transistor through a second reset control terminal; in the first stage, controlling the third reset control circuit to transmit a third reset signal to the light emitting device through a third reset control terminal.

19. A display panel, wherein, The pixel circuit comprises the pixel circuit according to any one of claims 1-14.

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