Driving circuit and display panel

Abstract

Provided in the present invention are a driving circuit and a display panel. A gate driving circuit of the driving circuit comprises stage transfer circuits, an output circuit and an output frequency division circuit, which are in electrical connection, wherein the output circuit is electrically connected to at least one clock signal line, two adjacent stages of gate driving circuits are connected to different clock signal lines, and in each clock signal line, the width between starting moments of two adjacent active levels is greater than or equal to the product of the width of an active level and eight.

Description

Driving circuit and display panel

[0001] This application claims priority to Chinese Patent Application No. 202410649368.4, filed on May 23, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a driving circuit and a display panel. BACKGROUND

[0003] Organic Light-Emitting Diode (OLED) display panels are widely used due to their flexibility and other characteristics.

[0004] In current OLED display panels, different refresh rates are usually used to drive different display areas to reduce the power consumption of the display panel; however, when different display areas of the display panel display at different display frequencies at the same time, the frequency switching area will have abnormal frequency division boundaries, which will cause display abnormalities of the display panel. SUMMARY

[0005] The present application provides a driving circuit and a display panel to solve the technical problem of display abnormalities of existing frequency division display panels.

[0006] The present application provides a driving circuit, comprising a frequency division signal line and a plurality of cascade gate driving circuits, the frequency division signal line being used to transmit a frequency division control signal to a plurality of gate driving circuits, the gate driving circuit comprising:

[0007] a stage transmission circuit, comprising a stage transmission receiving circuit and a stage transmission output circuit, the stage transmission receiving circuit being used to receive a stage transmission signal generated by a higher-level gate driving circuit, the stage transmission output circuit being electrically connected to the stage transmission receiving circuit through a first node and a second node, and being used to output the stage transmission signal of the current stage to a lower-level gate driving circuit according to the signals of the first node and the second node;

[0008] an output circuit, being electrically connected to the stage transmission output circuit through one of the first node and the second node and a third node, and being used to output a gate control signal according to the signals of one of the first node and the second node and the signal of the third node; and

[0009] A stage transmission frequency division circuit is electrically connected to the stage transmission receiving circuit through the first node or the second node, and is electrically connected to the stage transmission output circuit through a fourth node, for controlling the signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output circuit to output the stage transmission signal of the current stage.

[0010] An output frequency division circuit is connected between one of the first node, the second node and the third node, for controlling the signal of the third node according to the frequency division control signal, so as to control the output circuit to output the gate control signal of the current stage.

[0011] The application further provides a display panel comprising the above driving circuit. BRIEF DESCRIPTION OF DRAWINGS

[0012] Fig. 1 is a structural schematic diagram of a display panel of the application.

[0013] Fig. 2 is a structural diagram of a pixel driving circuit in the display panel of the application.

[0014] Fig. 3 is a timing diagram of the pixel driving circuit in Fig. 2.

[0015] Fig. 4 is a structural diagram of a gate driving group in the display panel of the application.

[0016] Fig. 5 is a first structural diagram of a third gate driving circuit in Fig. 4.

[0017] Fig. 6 is a second structural diagram of the third gate driving circuit in Fig. 4.

[0018] Fig. 7 is a first timing diagram of the third gate driving circuit in Fig. 5.

[0019] Fig. 8 is a structural diagram of a gate driving group in the prior art.

[0020] Fig. 9 is a timing diagram of a gate driving circuit in the gate driving group in Fig. 8.

[0021] Fig. 10 is a second timing diagram of the third gate driving circuit in Fig. 5.

[0022] Fig. 11 is a third structural diagram of the third gate driving circuit in Fig. 4. Embodiment of the application

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device.

[0024] Referring to FIG. 1, the display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and the display area AA is provided with a display part 200. Alternatively, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for playing a display function, and a plurality of sub-pixels Pi for realizing the display function are arranged in the display area AA. The non-display area NA can be a frame area of the display panel 100, and functional components for assisting the sub-pixels Pi in the display area AA to display can be arranged in the non-display area NA.

[0025] Referring to FIG. 1, a binding terminal 400 is arranged on the lower side of the display area AA, and the binding terminal 400 can be connected with an external circuit. The binding terminal 400 transmits signals input by the external circuit to data lines, so as to drive the display panel 100 to display a picture. For example, the binding terminal 400 can be connected with a chip or a chip on film, and is used to provide power supply and driving signals for the display panel 100.

[0026] In the embodiment, a plurality of light emitting devices LED and pixel driving circuits 302 for driving the light emitting devices LED can be arranged in an array in the display area AA. The pixel driving circuit 302 can be a 7T1C, 7T2C, 8T2C, or the like, and the pixel driving circuit 302 in FIG. 2 will be taken as an example for description.

[0027] In the structure of FIG. 1, a driving circuit 30 is arranged in the non-display area NA, and the driving circuit 30 includes a plurality of cascaded gate driving circuits 20. The gate control signals output by the gate driving circuits 20 are transmitted to the gates of a plurality of transistors in a plurality of pixel driving circuits 302 through corresponding scan lines, such as a first scan line EML1, a second scan line NDL1, a third scan line PSL, a fourth scan line NSL2, and a fifth scan line EML2.

[0028] Referring to FIG. 2, the pixel driving circuit 302 can include a data transistor M2, a source of the data transistor M2 being loaded with a data signal Vdata, a drain of the data transistor being electrically connected to a source of a driving transistor M1, and a gate of the data transistor M2 (e.g., a P-type transistor) being electrically connected to a third scan line PSL to be loaded with a PScan signal.

[0029] The pixel driving circuit 302 can further include a reset transistor M4 and a compensation transistor M3. A gate of the reset transistor M4 (e.g., an N-type transistor) can be electrically connected to a scan line NSL1 to be loaded with a NScan1 signal. The reset transistor M4 is configured to transmit a reset signal VI1 to a gate of the driving transistor M1 for resetting. A gate of the compensation transistor M3 (e.g., an N-type transistor) can be electrically connected to a fourth scan line NSL2 to be loaded with a NScan2 signal. A source and a drain of the compensation transistor M3 are electrically connected to a drain and a gate of the driving transistor M1, respectively.

[0030] The pixel driving circuit 302 can further include an initialization transistor M7. A gate of the initialization transistor M7 (e.g., a P-type transistor) can be electrically connected to a fifth scan line EML2 to be loaded with an EM2 signal. A drain of the initialization transistor M7 can be electrically connected to one end of the light emitting device 301 (the other end of the light emitting device 301 can be loaded with a low voltage signal VSS). The initialization transistor M7 is configured to transmit an initialization signal VI2 to the one end of the light emitting device 301 for initialization.

[0031] The pixel driving circuit 302 can further include a reset transistor M8. A gate of the reset transistor M8 (e.g., a P-type transistor) can be electrically connected to the fifth scan line EML2 to be loaded with the EM2 signal. A drain of the reset transistor M8 can be electrically connected to a source of the driving transistor M1. The reset transistor M8 is configured to transmit a reset signal VI3 to the source of the driving transistor M1 for resetting a voltage thereof.

[0032] The pixel driving circuit 302 can further include a first light emitting control transistor M5 and a second light emitting control transistor M6. A source of the first light emitting control transistor M5 can be loaded with a first high voltage VDD. A drain of the first light emitting control transistor M5 can be electrically connected to the source of the driving transistor M1. A source and a drain of the second light emitting control transistor M6 can be electrically connected to the drain of the driving transistor M1 and the one end of the light emitting device 301, respectively. Gates of the first light emitting control transistor M5 and the second light emitting control transistor M6 (e.g., both P-type transistors) can be electrically connected to a first scan line EML1 to be loaded with an EM1 signal. The first light emitting control transistor M5 and the second light emitting control transistor M6 are both configured to control a light emitting time of the light emitting device 301 according to the EM1 signal.

[0033] The pixel driving circuit 302 further comprises a storage capacitor Cst connected in series between the source of the first light emitting control transistor M5 and the gate of the driving transistor M1.

[0034] The pixel driving circuit 302 further comprises a boost capacitor Cboost connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.

[0035] In the structure of FIG. 1, the non-display area comprises a first sub-area NA1 and a second sub-area NA2 located on both sides of the display part, the first sub-area NA1 is provided with the Pscan driving circuit 110, the first Nscan driving circuit 121 and the EM signal source 130, the second sub-area NA2 is provided with the Pscan driving circuit 110, the second Nscan driving circuit 122 and the EM signal source 130, the Pscan driving circuit 110 is double-drive driving, the output end of the Pscan driving circuit 110 is connected with the third scan line PSL, the Nscan driving circuit is single-drive driving, the output end of the first Nscan driving circuit 121 can be connected with the fourth scan line NSL2, the output end of the second Nscan driving circuit 122 can be connected with the second scan line NSL1, and the EM signal source 130 can be connected with the first scan line EML1 and the fifth scan line EML2.

[0036] Please refer to FIG. 3, which is a timing diagram of the pixel driving circuit 302 in FIG. 2. In the gate driving circuit 20, due to the jump of the clock signal, it causes the scan signal output in the gate driving circuit 20 to appear ripple, for example, the fourth scan line NSL2 will appear ripple in the phase of the jump of the clock signal, and the fourth scan line NSL2 is electrically connected with the gate of the compensation transistor M3, in the structure of FIG. 3, the phase of the fourth scan line NSL2 appearing ripple coincides with the writing phase of the third scan line PSL, thereby causing the gate point potential of the driving transistor M1 to jump, when the signal output by the fourth scan line NSL2 is higher, the gate point potential of the driving transistor M1 is higher, and the brightness of the light emitting device LED is darker, when the signal output by the fourth scan line NSL2 is lower, the gate point potential of the driving transistor M1 is lower, and the brightness of the light emitting device LED is brighter, thereby causing the technical problem of display unevenness.

[0037] Please refer to FIG. 4, which is a structure diagram of the driving circuit 30 of the present application. The driving circuit 30 comprises a frequency division signal line FDL, a plurality of clock signal lines and a plurality of gate driving groups 500, each gate driving group 500 comprises a plurality of gate driving circuits 20 connected in cascade, the frequency division signal line FDL is used to transmit a frequency division control signal FD to the plurality of gate driving circuits 20, as shown in FIG. 5 and FIG. 6, the gate driving circuit 20 can comprise:

[0038] The stage transmission circuit 201 includes a stage transmission receiving circuit 2011 and a stage transmission output circuit 2012. The stage transmission receiving circuit 2011 is configured to receive a stage transmission signal generated by the upper-stage gate drive circuit 20. The stage transmission output circuit 2012 is electrically connected to the stage transmission receiving circuit 2011 through the first node P and the second node Q, and is configured to output a stage transmission signal of the current stage to the lower-stage gate drive circuit 20 according to a signal of the first node P and a signal of the second node Q.

[0039] The output circuit 202 is electrically connected to the first node P and the second node Q in the stage transmission circuit 201. The output circuit 202 is configured to output a gate control signal according to a frequency division control signal FD, a signal of the first node P and a signal of the second node Q. The output circuit 202 is electrically connected to a clock signal line. The clock signal lines connected by adjacent two-stage gate drive circuits 20 are different.

[0040] The output frequency division circuit 204 is connected to the third node S at one end and connected to one of the first node P or the second node Q at the other end in the stage transmission circuit 201. The output frequency division circuit 204 is configured to control the signal transmission between one of the first node P and the second node Q and the output circuit 202 according to a signal of one of the first node P or the second node Q and the frequency division control signal FD.

[0041] In the embodiment, in each clock signal line, the width of the effective level is H, and the width between the start times of the adjacent two effective levels is greater than or equal to 8H.

[0042] It should be noted that the gate drive circuit 20 in FIGS. 4-6 of the present application can be the Pscan drive circuit and the Nscan drive circuit in FIG. 1. In the following embodiments, the gate drive circuit 20 in FIGS. 4-6 is taken as the first Nscan drive circuit 121 or the second Nscan drive circuit 122 as an example, and a plurality of first Nscan drive circuits 121 or a plurality of second Nscan drive circuits 122 constitute a gate drive group 500.

[0043] The present application increases the width between the adjacent two effective levels in each clock signal line, increases the width between the ripples caused by the jump of the clock signal, avoids the non-overlapping of the data writing stage of the pixel drive circuit 302 in the display panel 100 and the ripple, eliminates the influence of the ripple on the sub-pixel Pi, avoids the abnormal phenomenon of the frequency division boundary in the frequency switching area, and improves the display effect of the display panel 100.

[0044] It should be noted that each stage transmission circuit 201 is connected to two different clock signal lines, and the four clock signal lines connected by the adjacent two stage transmission circuits 201 are all different. For example, the number of clock signal lines in the present application can be equal to the number of gate drive circuits 20 in the gate drive group 500; in the structure of FIG. 4, each gate drive group 500 includes a first gate drive circuit 21, a second gate drive circuit 22, a third gate drive circuit 23, and a fourth gate drive circuit 24, and a plurality of clock signal lines include at least a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, and a fourth clock signal line CKL4. Each gate drive circuit 20 can be connected to two clock signal lines, the first gate drive circuit 21 is connected to the first clock signal line CKL1 and the third clock signal line CKL3, the second gate drive circuit 22 is connected to the second clock signal line CKL2 and the fourth clock signal line CKL4, the third gate drive circuit 23 is connected to the first clock signal line CKL1 and the third clock signal line CKL3, and the fourth gate drive circuit 24 is connected to the second clock signal line CKL2 and the fourth clock signal line CKL4.

[0045] In the structure of FIG. 4, between the starting time of the active level of the first clock signal line CKL1 and the starting time of the active level of the second clock signal line CKL2, the width between the starting time of the active level of the first clock signal line CKL1 and the starting time of the active level of the second clock signal line CKL2, the width between the starting time of the active level of the second clock signal line CKL2 and the starting time of the active level of the third clock signal line CKL3, and the width between the starting time of the active level of the third clock signal line CKL3 and the starting time of the active level of the fourth clock signal line CKL4 are all the product of the width of the active level and 2.

[0046] For example, referring to FIG. 7, the width between the starting time of the active level of each clock signal line is 8H, the width between the starting time of the active level of the first clock signal line CKL1 and the starting time of the active level of the second clock signal line CKL2 is 2H, the width between the starting time of the active level of the second clock signal line CKL2 and the starting time of the active level of the third clock signal line CKL3 is 2H, the width between the starting time of the active level of the third clock signal line CKL3 and the starting time of the active level of the fourth clock signal line CKL4 is 2H, and the width between the starting time of the active level of the fourth clock signal line CKL4 and the starting time of the active level of the next first clock signal line CKL1 is 2H, where the width of the active level of the clock signal line is H.

[0047] It should be noted that each gate drive group 500 includes 6 gate drive circuits 20 connected in cascade, and the plurality of clock signal lines include 6 clock signal lines; or for example, each gate drive group 500 includes 8 gate drive circuits 20 connected in cascade, and the plurality of clock signal lines include 8 clock signal lines, and the more the number of clock signal lines, the greater the width of the adjacent two ripples on the fourth scan line NSL2; the following embodiment is described by taking the structure of FIG. 4 as an example.

[0048] In the structure of FIGS. 4-6, each gate drive circuit 20 includes a first transistor T6 and a second transistor T4 connected in series; the gate of the first transistor T6 of the first gate drive circuit 21 is electrically connected with the first clock signal line CKL1, and the drain of the second transistor T4 of the first gate drive circuit 21 is electrically connected with the third clock signal line CKL3; the gate of the first transistor T6 of the second gate drive circuit 22 is electrically connected with the second clock signal line CKL2, and the drain of the second transistor T4 of the second gate drive circuit 22 is electrically connected with the fourth clock signal line CKL4; the gate of the first transistor T6 of the third gate drive circuit 23 is electrically connected with the third clock signal line CKL3, and the drain of the second transistor T4 of the third gate drive circuit 23 is electrically connected with the first clock signal line CKL1; the gate of the first transistor T6 of the fourth gate drive circuit 24 is electrically connected with the fourth clock signal line CKL4, and the drain of the second transistor T4 of the fourth gate drive circuit 24 is electrically connected with the second clock signal line CKL2.

[0049] In the structure of FIGS. 4-6, the drive circuit 30 further includes a plurality of high potential lines arranged at intervals, and the number of high potential lines is the same as the number of gate drive circuits 20 in the gate drive group 500; the output circuit of one gate drive circuit 20 is connected with one high potential line, and in the gate drive group 500, the high potential lines connected by any two gate drive circuits 20 are different.

[0050] In the structure of FIGS. 4-6, the output circuit 202 includes a first coupling capacitor C4, one end of the first coupling capacitor C4 is connected to a high potential line, and the other end of the first coupling capacitor C4 is connected to the third node S; at the same time, in the gate drive group 500, the high potential lines connected by any first coupling capacitor C4 are different.

[0051] It should be noted that since the generation of the ripple is followed by the jump of the clock signal, the number of high potential lines needs to be increased while increasing the number of clock signal lines, so that the high potential lines connected by any gate drive circuit 20 in the gate drive group 500 are different.

[0052] For example, in the structure of FIG. 4, the output circuit 202 further includes a first output transistor T22, and the plurality of high potential lines include a first high potential line Vgh1, a second high potential line Vgh2, a third high potential line Vgh3, and a fourth high potential line Vgh4, which are arranged at intervals. The first coupling capacitor C4 of the first gate drive circuit 21 and the source of the first output transistor T22 are electrically connected to the first high potential line Vgh1. The first coupling capacitor C4 of the second gate drive circuit 22 and the source of the first output transistor T22 are electrically connected to the second high potential line Vgh2. The first coupling capacitor C4 of the third gate drive circuit 23 and the source of the first output transistor T22 are electrically connected to the third high potential line Vgh3. The first coupling capacitor C4 of the fourth gate drive circuit 24 and the source of the first output transistor T22 are electrically connected to the fourth high potential line Vgh4.

[0053] In the present embodiment, the voltages of the first high potential line Vgh1, the second high potential line Vgh2, the third high potential line Vgh3, and the fourth high potential line Vgh4 can be equal.

[0054] The following FIGS. 5 and 6 illustrate the structure of the gate drive circuit 20 of the present application by way of example of two circuit structures of the third gate drive circuit 23 of the present application.

[0055] Specifically, FIG. 4 illustrates a structure diagram of a gate drive group 500, i.e., the gate drive circuit 20 of the i-2th stage to the i+1th stage in cascade. FIGS. 5 and 6 illustrate the i-th gate drive circuit 20 by way of example. The i-th gate drive circuit 20 can generate and output the gate control signal Scan(i) of the present stage (i-th stage) based on the gate control signal Scan(i-1) of the (i-1)th stage.

[0056] In the structures of FIGS. 5 and 6, the gate drive circuit 20 can further include a stage transmission frequency division circuit 203, which is electrically connected to the stage transmission receiving circuit 2011 through the first node P or the second node Q, and is electrically connected to the stage transmission output circuit 2012 through the fourth node R. The stage transmission frequency division circuit 203 is configured to control the signal of one of the first node P and the second node Q based on the frequency division control signal FD, so as to control the stage transmission output circuit 2012 to output the stage transmission signal of the present stage.

[0057] It can be understood that, on the basis of the signal of one of the first node P and the second node Q electrically connected to the stage transmission output circuit 2012 being unchanged, on the one hand, the embodiment is provided with a stage transmission frequency division circuit 203 connected between the stage transmission receiving circuit 2011 and the stage transmission output circuit 2012, so as to control the signal of the other of the first node P and the second node Q (whether it can be acted on by the fourth node R) according to the frequency division control signal FD, so as to control the signal transmitted to the stage transmission output circuit 2012, and further determine the specific situation of the stage transmission signal output by the stage transmission output circuit 2012 of the current stage (whether it has a stage transmission effective pulse), so as to determine whether the next stage gate drive circuit 20 plays a driving role, if the stage transmission signal has a stage transmission effective pulse, it can be considered that the stage transmission receiving circuit 2011 in the next stage gate drive circuit 20 can work normally, and similarly, in combination with the stage transmission frequency division circuit 203 of the stage to determine the specific situation of the stage transmission signal output by the stage transmission output circuit 2012 of the stage.

[0058] On the other hand, the embodiment is also provided with an output frequency division circuit 204 connected between one of the first node P and the second node Q and the third node S, so as to control the signal of the third node S according to the frequency division control signal FD, so as to control the specific situation of the gate control signal output by the output circuit 202 of the current stage.

[0059] It should be understood that, for a plurality of gate drive circuits 20 cascaded in turn, if the plurality of gate control signals output by the first part of the plurality of gate drive circuits 20 are all output once in a frame in every n1 frames, the plurality of gate control signals output by the second part of the plurality of gate drive circuits 20 are all output once in a frame in every n2 frames, and the plurality of gate control signals output by the third part of the plurality of gate drive circuits 20 are all output once in a frame in every n3 frames, it can be considered that the three display areas respectively formed by the three parts of sub-pixels Pi corresponding to the three parts of gate drive circuits 20 respectively, the three refresh rates corresponding to the three display areas are m / n1, m / n2 and m / n3 respectively, and m is the least common multiple of n1, n2 and n3.

[0060] In summary, in the embodiment, the gate control signal for determining the refresh rate of any display area of the display panel 100 is directly determined by the corresponding output frequency dividing output circuit 204 and the frequency dividing control signal FD at this time. One input terminal of the output frequency dividing output circuit 204 is connected to one of the first node P and the second node Q, and the other input terminal is connected to the third node S, wherein the third node S is connected to the first node P or the second node Q through the stage transmission frequency dividing circuit 203. That is, the signal of the third node S is determined by the stage transmission frequency dividing circuit 203 and the frequency dividing control signal FD loaded to the stage transmission frequency dividing circuit 203. Therefore, the gate control signal is determined by the stage transmission frequency dividing circuit 203, the output frequency dividing output circuit 204, and the frequency dividing control signal FD loaded to the stage transmission frequency dividing circuit 203 and the output frequency dividing output circuit 204. The refresh rate of the corresponding display area can be determined by reasonably setting the three elements. Further, the above three elements in the different gate drive circuits 20 corresponding to different display areas of the display panel 100 can be reasonably set to achieve different refresh rates.

[0061] Referring to FIGS. 4 to 6, the frequency dividing control signal FD includes a first frequency dividing signal FD1 and a second frequency dividing signal FD2. The frequency dividing signal line FDL includes a first frequency dividing signal line FDL1 for transmitting the first frequency dividing signal FD1 and a second frequency dividing signal line FDL2 for transmitting the second frequency dividing signal FD2. The first frequency dividing signal line FDL is electrically connected to the output frequency dividing circuit 204 to control the signal of the third node S. The second frequency dividing signal line FDL is electrically connected to the stage transmission frequency dividing circuit 203 to control the signal of one of the first node P and the second node Q.

[0062] It can be understood that, in the embodiment, the frequency dividing signal line FDL is specifically set as the independent first frequency dividing signal line FDL and the first frequency dividing signal line FDL, which can respectively transmit the independent first frequency dividing signal FD1 and the second frequency dividing signal FD2 to independently control the working states of the output frequency dividing circuit 204 and the stage transmission frequency dividing circuit 203, thereby respectively controlling the specific conditions of the stage transmission signal and the gate signal generated by the gate drive circuit 20 at this stage.

[0063] Referring to FIGS. 4 to 6, the output frequency dividing circuit 204 includes a first frequency dividing transistor T18. The gate of the first frequency dividing transistor T18 is connected to the first frequency dividing signal line FDL. The source of the first frequency dividing transistor T18 is electrically connected to one of the first node P and the second node Q. The drain of the control transistor is electrically connected to the third node S. The first frequency dividing signal FD1 is used to control the electrical connection or disconnection between the third node S and the first node P or the second node Q. For example, the source of the first frequency dividing transistor T18 in FIG. 5 is electrically connected to the first node P, and the source of the first frequency dividing transistor T18 in FIG. 6 is electrically connected to the second node Q.

[0064] As discussed above, the first frequency division signal FD1 can act on the output frequency division circuit 204 to control whether the third node S is acted on by the first node P or the second node Q. In this embodiment, the first frequency division signal FD1 can act on the gate of the first frequency division transistor T18 in the output frequency division circuit 204 to control whether the third node S is electrically connected to the first node P or the second node Q.

[0065] Specifically, if electrically connected, it can be considered that the third node S can be acted on by the first node P or the second node Q, which means that the signal of the first node P or the signal of the second node Q can control whether the gate control signal generated and output by the output circuit 202 has a gate effective pulse; if disconnected, it can be considered that the third node S cannot be acted on by the first node P or the second node Q, and since the first node P or the second node Q for controlling the generation of the stage transmission signal cannot act on the output circuit 202, it can be considered that the gate control signal generated and output by the output circuit 202 does not have a gate effective pulse.

[0066] Referring to FIGS. 4-6, the output frequency division circuit 204 further includes a second frequency division transistor T20, the gate of the second frequency division transistor T20 is electrically connected to the fifth node Z of the stage transmission circuit 201, the source of the second frequency division transistor T20 is electrically connected to the first frequency division signal line FDL, and the drain of the second frequency division transistor T20 is electrically connected to the gate of the first frequency division transistor T18; wherein the first frequency division signal FD1 and the signal of the fifth node Z are used to control whether the third node S is electrically connected to the first node P or the second node Q; wherein the signal of the fifth node Z is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of the current stage.

[0067] It can be understood that in this embodiment, the second frequency division transistor T20 electrically connected to the gate of the first frequency division transistor T18 is further provided, and the opening of the second frequency division transistor T20 is determined by the signal of the fifth node Z, and the signal of the fifth node Z is also used to control the stage transmission signal and the gate control signal output by the current stage, that is, it can be considered that the state of the signal of the fifth node Z can feedback the state of both the stage transmission signal and the gate control signal of the current stage, so that the opening of the second frequency division transistor T20 is controlled only when the state of both the stage transmission signal and the gate control signal of the current stage is appropriate, and then the first frequency division signal FD1 is transmitted to the gate of the first frequency division transistor T18 of the current stage to control the opening of the first frequency division transistor T18, which can take into account the premise that the stage transmission signal and the gate control signal of each stage are output as correct waveforms, so as to realize the differentiated setting of the refresh rates of different display areas.

[0068] Referring to FIGS. 4-6, the stage transmission frequency division circuit 203 includes a third frequency division transistor T17, a gate of the third frequency division transistor T17 is electrically connected to the second frequency division signal line FDL, a source of a first frequency division transistor T18 is electrically connected to the fourth node R through the first node P or the second node Q; wherein the second frequency division signal FD2 is used to control the fourth node R to be electrically connected or disconnected with the first node P or the second node Q; for example, the drain of the third frequency division transistor T17 is electrically connected to the first node P in FIG. 5, and the drain of the third frequency division transistor T17 is electrically connected to the second node Q in FIG. 6.

[0069] Referring to FIGS. 4-6, the stage transmission output circuit 2012 includes a first stage transmission transistor T10, a gate of the first stage transmission transistor T10 is electrically connected to the first node P, a source of the first stage transmission transistor T10 is electrically connected to the high level source VGH, and a drain of the first stage transmission transistor T10 is electrically connected to the stage transmission output end OUT in the gate drive circuit 20 for outputting the stage transmission signal; a second stage transmission transistor T9, a gate of the second stage transmission transistor T9 is electrically connected to the second node Q, a source of the second stage transmission transistor T9 is electrically connected to the low level source VGL, and a drain of the second stage transmission transistor T9 is electrically connected to the stage transmission output end OUT.

[0070] Referring to FIGS. 4-6, the output circuit 202 includes a first output transistor T22 and a second output transistor T21, a gate of the first output transistor T22 is electrically connected to the third node S, a source of the first output transistor T22 is electrically connected to the third high potential line Vgh3, and a drain of the first output transistor T22 is electrically connected to the gate output end OUTA in the gate drive circuit 20 for outputting the gate control signal; a gate of the second output transistor T21 is electrically connected to the first node P or the second node Q, a source of the second output transistor T21 is electrically connected to the low level source VGL, and a drain of the second output transistor T21 is electrically connected to the gate output end OUTA.

[0071] It should be noted that if the structure of FIGS. 5 and 6 is the second gate drive circuit 22, the source of the first output transistor T22 is electrically connected to the second high potential line Vgh2, if the structure of FIGS. 5 and 6 is the first gate drive circuit 21, the source of the first output transistor T22 is electrically connected to the first high potential line Vgh1, and if the structure of FIGS. 5 and 6 is the fourth gate drive circuit 24, the source of the first output transistor T22 is electrically connected to the fourth high potential line Vgh4.

[0072] Similarly, the third node S can control the opening of the first output transistor T22 to control whether the high voltage can be transmitted to the gate output terminal OUTA, and the first node P or the second node Q can control the opening of the second output transistor T21 to control whether the low voltage can be transmitted to the gate output terminal OUTA. As discussed above, the first frequency division transistor T18 connected between the third node S and the first node P or the second node Q is arranged in the application to control whether the third node S can receive the signal of the first node P or the second node Q, to control the opening of the first output transistor T22 or the opening of the second output transistor T21, thereby controlling the specific conditions of the gate control signal generated and output by the gate output terminal OUTA.

[0073] Please refer to FIG. 4 to FIG. 6, the stage transfer receiving circuit 2011 includes an input circuit 2011c, a first control circuit 2011a and a second control circuit 2011b.

[0074] In the embodiment, the input circuit 2011c includes an input transistor T3, the gate of the input transistor T3 is loaded with the first type clock signal, the source of the input transistor T3 is configured as the input end of the input circuit 2011c, and the drain of the input transistor T3 is configured as the output end of the input circuit 2011c.

[0075] In the embodiment, the first control circuit 2011a includes a first transistor T4, a seventh transistor T5, a second transistor T6 and a third transistor T7 connected in series, the gate of the seventh transistor T5 is electrically connected to the drain of the input transistor T3, the source of the seventh transistor T5 is loaded with the first type clock signal, the gate of the first transistor T4 is loaded with the first type clock signal, the source of the first transistor T4 is loaded with a low level source VGL, the drain of the first transistor T4 is electrically connected to the gate of the second transistor T6 and the drain of the seventh transistor T5, the drain of the second transistor T6 is electrically connected to the source of the third transistor T7, the source of the second transistor T6 and the gate of the third transistor T7 are both loaded with the second type clock signal, and the drain of the third transistor T7 is electrically connected to the fourth node R.

[0076] In this embodiment, the second control circuit 2011b comprises a fourth transistor T13, a first capacitor C1, a fifth transistor T1 and a sixth transistor T2 connected in series, a gate of the fourth transistor T13 is loaded with a control signal, a source of the fourth transistor T13 is loaded with a high level source VGH, a drain of the fourth transistor T13 is electrically connected to a second node Q, a gate of the fifth transistor T1 is electrically connected to a drain of the first transistor T4, a source of the fifth transistor T1 is loaded with the high level source VGH, a drain of the fifth transistor T1 is electrically connected to a source of the sixth transistor T2, a drain of the sixth transistor T2 is loaded with the second clock signal, a gate of the sixth transistor T2 is also loaded with the stage transmission signal generated by the upper gate drive circuit 20, and the first capacitor C1 is electrically connected between the gate and the drain of the sixth transistor T2.

[0077] In the gate drive circuit 20, the transistors are all P-type transistors, and the working of some signals in some states is described as follows: at the time of starting, the control signal transmitted by the CL can control the fourth transistor T13 to be turned on to transmit the high level source VGH to the second node Q; in the later period, when the low voltage in the first clock signal and the low voltage in the (i-1) stage gate control signal NScano(i-1) are low, the gate control signal NScano(i-1) controls the seventh transistor T5 and the second output transistor T21 to be turned on, the low level source VGL is transmitted to the stage transmission output end OUT through the second output transistor T21, and the first clock signal controls the first transistor T4 to be turned on, and the low level source VGL is transmitted to the gate of the second transistor T6 to control it to be turned on, at this time, the high voltage in the second clock signal controls the third transistor T7 to be turned off; in the later period, when the high voltage in the first clock signal is high, the input transistor T3, the second transistor T6 and the first transistor T4 are turned off, at this time, it can be considered that the second output transistor T21 is maintained to be turned on, the low voltage in the second clock signal controls the third transistor T7 to be turned on, the fourth node R is still not loaded with a voltage, and the stage transmission output end OUT still outputs a low level.

[0078] It should be noted that the type of each transistor in the gate drive circuit 20 is not limited in the present application, for example, all of the transistors can be P-type transistors, or part of the transistors are N-type transistors and the other part are P-type transistors, and the corresponding signals can be matched and set according to the type of the transistors, and the specific can be referred to the principle description of the “all P-type transistors in the gate drive circuit 20” in the whole text.

[0079] Referring to FIGS. 4-6, the first control circuit 2011a can further include an eighth transistor T11 and a second capacitor C2, the second control circuit 2011b can further include a ninth transistor T12, and the stage transfer output circuit 2012 can further include a third capacitor C3 electrically connected between the gate and the source of the first stage transfer transistor T10, the gate of the eighth transistor T11 and the gate of the ninth transistor T12 can be loaded with a low voltage source VGL to maintain being turned on, the source and the drain of the eighth transistor T11 can be electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6 respectively, the second capacitor C2 can be electrically connected between the gate and the drain of the second transistor T6, and the source and the drain of the ninth transistor T12 can be electrically connected to the drain of the input transistor T3 and the second node Q respectively.

[0080] In the embodiment, the first capacitor C1, the second capacitor C2 and the third capacitor C3 can be used to maintain the voltage of the corresponding node and play a coupling role, and the eighth transistor T11 and the ninth transistor T12 can be respectively ensured to be turned on only when the voltage at the source of both is low enough, so as to maintain the lower voltage at the drain of both, which is beneficial to the turn-on of the first output transistor T22 and the second output transistor T21 respectively.

[0081] Referring to FIGS. 4-6, the second control circuit 2011b further includes a tenth transistor T14 and an eleventh transistor T16.

[0082] In the embodiment, the source of the tenth transistor T14 is loaded with a stage transfer signal generated by the upper stage gate drive circuit 20, the gate of the tenth transistor T14 is loaded with a first type of clock signal, and the drain of the tenth transistor T14 is electrically connected to the gate of the sixth transistor T2.

[0083] In the embodiment, the gate and the source of the eleventh transistor T16 are electrically connected to the gate of the sixth transistor T2, and the drain of the eleventh transistor T16 is electrically connected to the second node Q.

[0084] Referring to FIGS. 4-6, the second control circuit 2011b can further include a twelfth transistor T15 for maintaining a lower voltage at the gate of the sixth transistor T2, the gate of the twelfth transistor T15 can be loaded with a low voltage source VGL, and the source and the drain of the twelfth transistor T15 can be electrically connected to the drain of the tenth transistor T14 and the gate of the sixth transistor T2 respectively.

[0085] It can be understood that the second control circuit 2011b in this embodiment is also provided with the tenth transistor T14 and the eleventh transistor T16, the tenth transistor T14 can be used to control the voltage of the gate of the sixth transistor T2, and the eleventh transistor T16 is further arranged between the second node Q and the gate of the sixth transistor T2, so that the second node Q is not directly connected to the first capacitor C1, so as to avoid the coupling effect of the first capacitor C1, and the second node Q can maintain a lower voltage.

[0086] Please refer to FIG. 5 and FIG. 6, the gate drive circuit 20 further comprises a first coupling capacitor C4 and a second coupling capacitor C5, one end of the first coupling capacitor C4 is connected to the third high potential line Vgh3, the other end of the first coupling capacitor C4 is connected to the gate of the first output transistor T22, one end of the second coupling capacitor C5 is connected to the third high potential line Vgh3, the other end of the second coupling capacitor C5 is connected to the gate of the first frequency division transistor T18.

[0087] It should be noted that the difference between FIG. 5 and FIG. 6 is that the second frequency division transistor T20 in FIG. 5 is a P-type transistor, and the second frequency division transistor T20 in FIG. 6 is an N-type transistor.

[0088] It should be noted that since the gate drive circuit 20 in FIG. 5 and FIG. 6 is exemplified by the third gate drive circuit 23 in FIG. 4, the first type of clock signal is from the first clock signal line CKL1, and the second type of clock signal is from the third clock signal line CKL3.

[0089] Please refer to FIG. 8 and FIG. 9, FIG. 8 is a structural diagram of the prior art gate drive circuit 20, and FIG. 9 is a timing diagram of the gate drive circuit 20 in FIG. 8.

[0090] The driving circuit 30 in FIG. 8 is provided with two cascaded gate driving circuits 20, each of which is connected with two clock signal lines and periodically outputs an active level through the two clock signal lines to realize frequency division display of the display panel. FIG. 9 lists the timing diagram of the existing third scan line PSL and fourth scan line NSL2. According to the timing diagram in FIG. 9, the starting time of the ripple appearing in the fourth scan line NSL2 is the same as the starting time of the active level of the clock signal line. When the fourth scan line NSL2 outputs the active level, the interval between two adjacent ripples is 4H. In the active level stage of the fourth scan line NSL2, it can have 4 ripples. For example, the active level output by Nscano(i) in FIG. 9 has 4 ripples. Pscan(n+1) and Pscan(n+2) corresponding to Nscano(i) all fall into the ripple in Nscano(i), where i can be 1 and n can be 0. Pscan(n+3) and Pscan(n+4) corresponding to Nscano(i+1) all fall into the ripple in Nscano(i+1). Pscan(n+5) and Pscan(n+6) corresponding to Nscano(i+2) all fall into the ripple in Nscano(i+2).

[0091] In the structure of FIG. 4, the driving circuit 30 is provided with four cascaded gate driving circuits 20, each of which is connected with two clock signal lines. The four clock signal lines are arranged such that the first transistor T6 and the second transistor T4 in each gate driving circuit 20 are connected with different clock signal lines, and the interval between the starting times of two adjacent active levels in each clock signal line is 8H. Referring to FIG. 7, since the starting time of the ripple appearing in the fourth scan line NSL2 is the same as the starting time of the active level of the clock signal line, when the fourth scan line NSL2 outputs the active level, the interval between two adjacent ripples is 8H. Meanwhile, each gate driving group 500 in the present application is provided with four high potential lines arranged at intervals. The output end of each gate driving circuit 20 in the gate driving group 500 is connected with a different high potential line. The arrangement of the multiple high potential lines reduces the load of the high potential line and avoids the generation of ripples. For example, in the active level stage of the fourth scan line NSL2 in FIG. 7, it can have 2 ripples. The active level output by Nscano(i) has 2 ripples. Pscan(n+1) and Pscan(n+2) corresponding to Nscano(i) all do not fall into the ripple in Nscano(i), where i can be 1 and n can be 0. Pscan(n+3) and Pscan(n+4) corresponding to Nscano(i+1) all do not fall into the ripple in Nscano(i+1). Pscan(n+4) and Pscan(n+6) corresponding to Nscano(i+2) all do not fall into the ripple in Nscano(i+1).

[0092] It should be noted that in FIG. 7 and FIG. 9, when the first frequency division signal line jumps from low level to high level, due to the change of frequency, the load of the high potential line will decrease, and thus the amplitude of the ripple generated in the fourth scan line NSL2 will decrease.

[0093] It should be noted that the application can also control the timing of the active level in the third scan line PSL, for example, advance or delay the output time of the active level by H or 2H to avoid the ripple in the fourth scan line NSL2.

[0094] In the structure of FIG. 5 and FIG. 6, since one end of the second coupling capacitor C5 is connected to the third high potential line Vgh3 and the other end of the second coupling capacitor C5 is connected to the gate of the first frequency division transistor T18, when the first frequency division signal line jumps, due to the coupling effect of the second coupling capacitor C5, the output waveform of the third high potential line Vgh3 will have a jump ripple, for example, the active level of Nscano(i) in FIG. 10, which will cause the display panel to have a bright line.

[0095] Referring to FIG. 11, in the gate drive group 500, the high potential line connected by any first coupling capacitor C4 is the same. For example, based on FIG. 5 and FIG. 6, the drive circuit 30 further includes a fifth high potential line Vgh5, which is arranged apart from the first high potential line Vgh1, the second high potential line Vgh2, the third high potential line Vgh3 and the fourth high potential line Vgh4.

[0096] In the embodiment, the source of the first output transistor T22 of the first gate drive circuit 21 is electrically connected to the first high potential line Vgh1, the source of the first output transistor T22 of the second gate drive circuit 22 is electrically connected to the second high potential line Vgh2, the source of the first output transistor T22 of the third gate drive circuit 23 is electrically connected to the third high potential line Vgh3, the source of the first output transistor T22 of the fourth gate drive circuit 24 is electrically connected to the fourth high potential line Vgh4, and the first coupling capacitor C4 of the first gate drive circuit 21, the second gate drive circuit 22, the third gate drive circuit 23 and the fourth gate drive circuit 24 are electrically connected to the fifth high potential line Vgh5.

[0097] Taking the third gate drive circuit 23 as an example, in the structure of FIG. 11, one end of the first coupling capacitor C4 is connected to the fifth high potential line Vgh5, the other end of the first coupling capacitor C4 is connected to the gate of the first output transistor T22, one end of the second coupling capacitor C5 is connected to the fifth high potential line Vgh5, and the other end of the second coupling capacitor C5 is connected to the gate of the first frequency dividing transistor T18. Since the fifth high potential and the third high potential are arranged at intervals, they do not interfere with each other. When the first frequency dividing signal line jumps, due to the coupling effect of the second coupling capacitor C5, the waveform of the output of the fifth high potential line Vgh5 will have a jump ripple. However, the third high potential responsible for the output load is not affected when the first frequency dividing signal line jumps, thereby eliminating the technical problem of the waveform of the output of the third high potential line Vgh3 when the first frequency dividing signal line jumps, and improving the display effect of the display panel.

[0098] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0099] The technical solutions provided by the embodiments of the present application are described in detail above, and the principles and implementation modes of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and its core idea; those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, comprising a frequency division signal line, a plurality of gate driving groups, and a plurality of clock signal lines, each of the gate driving groups comprising a plurality of gate driving circuits cascaded, the frequency division signal line being configured to transmit a frequency division control signal to a plurality of the gate driving circuits, the gate driving circuit comprising: a stage transmission circuit configured to output the stage transmission signal of the current stage to the gate driving circuit of the next stage; an output circuit electrically connected to a first node and a second node in the stage transmission circuit, the output circuit being configured to output a gate control signal according to the frequency division control signal and the signals of the first node and the second node, the output circuit being electrically connected to the clock signal lines, and adjacent two stages of the gate driving circuits being connected to different clock signal lines; an output frequency division circuit having one end connected to the third node of the output circuit and the other end connected to one of the first node or the second node of the stage transmission circuit, the output frequency division circuit being configured to control the signal transmission between one of the first node and the second node and the output circuit according to the signal of one of the first node or the second node and the frequency division control signal; wherein in each of the clock signal lines, the width of the active level is H, and the width between the starting time of adjacent two active levels is greater than or equal to 8H. The driving circuit further comprises a plurality of high potential lines arranged at intervals, the number of the high potential lines being the same as the number of the gate driving circuits in the gate driving group. The output circuit of one of the gate driving circuits is connected to one of the high potential lines, and the high potential lines connected to any of the gate driving circuits in the gate driving group are different. Each of the stage transmission circuits is connected to two different clock signal lines, and the four clock signal lines connected to adjacent two stages of the stage transmission circuits are all different. The plurality of clock signal lines comprises at least a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, and the gate driving group comprises a first gate driving circuit, a second gate driving circuit, a third gate driving circuit, and a fourth gate driving circuit.

2. The drive circuit of claim 1, wherein, The first gate driving circuit and the third gate driving circuit are both electrically connected to two of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line, and the second gate driving circuit and the fourth gate driving circuit are both electrically connected to the other two of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. ​ 3. The drive circuit of claim 2, wherein, ​ 4. The drive circuit of claim 3, wherein, ​ ​ 5. The drive circuit of claim 4, wherein, The width between the start time of the active level of the first clock signal line and the start time of the active level of the second clock signal line, the width between the start time of the active level of the second clock signal line and the start time of the active level of the third clock signal line, and the width between the start time of the active level of the third clock signal line and the start time of the active level of the fourth clock signal line are all 2H.

6. The drive circuit of claim 5, wherein, Each of the gate drive circuits comprises a first transistor and a second transistor connected in series; wherein, the gate of the first transistor of the first gate drive circuit is electrically connected with the first clock signal line, and the drain of the second transistor of the first gate drive circuit is electrically connected with the third clock signal line; the gate of the first transistor of the second gate drive circuit is electrically connected with the second clock signal line, and the drain of the second transistor of the second gate drive circuit is electrically connected with the fourth clock signal line; the gate of the first transistor of the third gate drive circuit is electrically connected with the third clock signal line, and the drain of the second transistor of the third gate drive circuit is electrically connected with the first clock signal line; the gate of the first transistor of the fourth gate drive circuit is electrically connected with the fourth clock signal line, and the drain of the second transistor of the fourth gate drive circuit is electrically connected with the second clock signal line.

7. The drive circuit according to any one of claims 2 to 6, wherein The output circuit comprises a first coupling capacitor, one end of the first coupling capacitor is connected to the high potential line, and the other end of the first coupling capacitor is connected to the third node; In the gate drive group, the high potential line connected with any first coupling capacitor is the same.

8. The drive circuit of claim 7, wherein, The plurality of high potential lines comprises a first high potential line, a second high potential line, a third high potential line, a fourth high potential line and a fifth high potential line arranged at intervals; The output circuit further comprises a first output transistor, the gate of the first output transistor is electrically connected with the third node, the source of the first output transistor is electrically connected with one of the plurality of high potential lines, and the drain of the first output transistor is electrically connected with the gate output end of the gate drive circuit for outputting the gate control signal; The source of the first output transistor of the first gate drive circuit is electrically connected with the first high potential line, the source of the first output transistor of the second gate drive circuit is electrically connected with the second high potential line, the source of the first output transistor of the third gate drive circuit is electrically connected with the third high potential line, the source of the first output transistor of the fourth gate drive circuit is electrically connected with the fourth high potential line, and the first coupling capacitor of the first gate drive circuit, the second gate drive circuit, the third gate drive circuit and the fourth gate drive circuit is electrically connected with the fifth high potential line.

9. The drive circuit according to any one of claims 2 to 6, wherein, The output circuit comprises a first coupling capacitor, one end of the first coupling capacitor is connected to the high potential line, and the other end of the first coupling capacitor is connected to the third node; Any high potential line connected with the first coupling capacitor in the gate drive group is different.

10. The drive circuit of claim 9, wherein, The plurality of high potential lines comprises a first high potential line, a second high potential line, a third high potential line and a fourth high potential line arranged at intervals. The output circuit further comprises a first output transistor, a gate of the first output transistor is electrically connected with the third node, a source of the first output transistor is electrically connected with one of the plurality of high potential lines, and a drain of the first output transistor is electrically connected with a gate output terminal of the gate drive circuit for outputting the gate control signal. The first coupling capacitor of the first gate drive circuit and the source of the first output transistor are electrically connected with the first high potential line, the first coupling capacitor of the second gate drive circuit and the source of the first output transistor are electrically connected with the second high potential line, the first coupling capacitor of the third gate drive circuit and the source of the first output transistor are electrically connected with the third high potential line, and the first coupling capacitor of the fourth gate drive circuit and the source of the first output transistor are electrically connected with the fourth high potential line.

11. The drive circuit according to claim 8 or 10, wherein The stage transmission circuit comprises a stage transmission receiving circuit and a stage transmission output circuit, and the stage transmission output circuit and the stage transmission receiving circuit are connected to the first node and the second node. The gate drive circuit further comprises a stage transmission frequency division circuit, one end of the stage transmission frequency division circuit is connected to a fourth node with the stage transmission receiving circuit, and the other end of the stage transmission frequency division circuit is connected to one of the first node and the second node with the stage transmission output circuit, and the stage transmission frequency division circuit is used for controlling a signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output circuit to output the stage transmission signal of the current stage.

12. The drive circuit of claim 11, wherein, The frequency division control signal comprises a first frequency division signal and a second frequency division signal, and the frequency division signal line comprises a first frequency division signal line for transmitting the first frequency division signal and a second frequency division signal line for transmitting the second frequency division signal. The first frequency division signal line is electrically connected to the output frequency division circuit, and the second frequency division signal line is electrically connected to the stage transmission frequency division circuit.

13. The drive circuit of claim 12, wherein, The output frequency division circuit comprises: A first frequency division transistor, a source of the first frequency division transistor is electrically connected to the first node or the second node, and a drain of the control transistor is electrically connected to the third node. A second frequency division transistor, a gate of the second frequency division transistor is electrically connected to a fifth node of the stage transmission circuit, a source of the second frequency division transistor is electrically connected to the first frequency division signal line, and a drain of the second frequency division transistor is electrically connected to a gate of the first frequency division transistor.

14. The drive circuit of claim 13, wherein, The stage transmission frequency division circuit comprises: A third frequency division transistor, a gate of the third frequency division transistor is electrically connected to the second frequency division signal line, a source of the third frequency division transistor is electrically connected to the stage transmission receiving circuit, and a drain of the third frequency division transistor is electrically connected to the first node or the second node.

15. The drive circuit of claim 11, wherein, The stage transmission output circuit comprises: A first stage transmission transistor, a gate of the first stage transmission transistor being electrically connected with the first node, a source of the first stage transmission transistor being electrically connected with a high level source, and a drain of the first stage transmission transistor being electrically connected with a stage transmission output terminal in the gate drive circuit for outputting the stage transmission signal; A second stage transmission transistor, a gate of the second stage transmission transistor being electrically connected with the second node, a source of the second stage transmission transistor being electrically connected with a low level source, and a drain of the second stage transmission transistor being electrically connected with the stage transmission output terminal.

16. The drive circuit of claim 11, wherein, The output circuit comprises: A second output transistor, a gate of the second output transistor being electrically connected with the first node or the second node, a source of the second output transistor being electrically connected with a low level source, and a drain of the second output transistor being electrically connected with the gate output terminal.

17. The drive circuit of claim 11, wherein, The stage transmission receiving circuit comprises: An input circuit comprising an input transistor, a gate of the input transistor being loaded with a first type clock signal, a source of the input transistor being configured as an input terminal of the input circuit, and a drain of the input transistor being configured as an output terminal of the input circuit.

18. The drive circuit of claim 17, wherein, The stage transmission receiving circuit comprises: A first control circuit comprising a first transistor, a second transistor, a third transistor and a seventh transistor, a gate of the seventh transistor being electrically connected to a drain of the input transistor, a source of the seventh transistor being loaded with the first type clock signal, a gate of the first transistor being loaded with the first type clock signal, a source of the first transistor being connected to a low level source, a drain of the first transistor being electrically connected to a gate of the second transistor and a drain of the seventh transistor, a drain of the second transistor being electrically connected to a source of the third transistor, a source of the second transistor and a gate of the third transistor being both loaded with a second type clock signal, and a drain of the third transistor being electrically connected to the fourth node; A second control circuit comprising a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, a gate of the fourth transistor being loaded with a control signal, a source of the fourth transistor being loaded with a high level source, a drain of the fourth transistor being electrically connected to the second node, a gate of the fifth transistor being electrically connected to a drain of the first transistor, a source of the fifth transistor being loaded with a high level source, a drain of the fifth transistor being electrically connected to a source of the sixth transistor, a drain of the sixth transistor being loaded with the second type clock signal, a gate of the sixth transistor being loaded with the stage transmission signal of a higher level gate drive circuit, and the first capacitor being electrically connected between the gate and the drain of the sixth transistor.

19. The drive circuit of claim 18, wherein, The second control circuit further comprises: A tenth transistor, a source of the tenth transistor being loaded with the stage transmission signal of the higher level gate drive circuit, a gate of the tenth transistor being loaded with the first type clock signal, and a drain of the tenth transistor being electrically connected to a gate of the sixth transistor; An eleventh transistor, a gate and a source of the eleventh transistor are electrically connected to a gate of the sixth transistor, and a drain of the eleventh transistor is electrically connected to the second node.

20. A display panel, wherein, The display panel comprises the driving circuit as claimed in any one of claims 1 to 19.

Images