Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. In the display panel, a signal of an internal node is used as a cascaded transmission signal, so that the stability of an output signal of a gate driving circuit is improved, at least one of a first gate driving unit and a second gate driving unit is electrically connected to transistors in a second type of sub-pixels, and the stability of signal output ends of the first gate driving unit and the second gate driving unit can be further improved.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the existing display device has higher and higher requirements for display effect. In order to improve the display effect, the existing display device will adopt LTPO (Low Temperature Polysilicon Oxide) pixel circuit, but the LTPO pixel driving circuit needs more GOA (Gate On Array) circuit output signals, which will cause the power consumption of the display device to increase. In order to reduce the power consumption of the display device, CMOS (Complementary Metal Oxide Semiconductor) GOA circuit will be used to reduce the number of GOA circuits, and at the same time, the function of partition frequency division will be realized by using CMOS GOA circuit. However, in the process of using the display panel, it is found that when the output signal of the CMOS GOA circuit is used as a stage transfer signal, the fluctuation of the output signal of the CMOS GOA circuit will be large, which will affect the display effect.

[0003] Therefore, the existing CMOS GOA circuit has the technical problem that when the output signal is used as a stage transfer signal, the fluctuation of the output signal will be large. TECHNICAL PROBLEM

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem that the existing CMOS GOA circuit has the technical problem that when the output signal is used as a stage transfer signal, the fluctuation of the output signal will be large. TECHNICAL SOLUTION

[0005] To solve the above problems, the technical scheme provided by the present application is as follows:

[0006] The embodiments of the present application provide a display panel, which comprises:

[0007] The display part comprises a plurality of rows of first-type sub-pixels.

[0008] The load part is arranged on at least one side of the display part along the first direction, and comprises a plurality of rows of second-type sub-pixels.

[0009] The gate driving module comprises a first gate driving unit and a second gate driving unit arranged on two sides of the display part respectively along a second direction, the first gate driving unit comprises a plurality of cascaded first gate driving circuits, the second gate driving unit comprises a plurality of cascaded second gate driving circuits, an internal node of a previous stage first gate driving circuit is connected with a start signal line of a current stage first gate driving circuit, and an internal node of a previous stage second gate driving circuit is connected with a start signal line of a current stage second gate driving circuit.

[0010] At least one of the first gate driving circuit and the second gate driving circuit is electrically connected with a transistor in the second type of sub-pixel, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0011] Meanwhile, the display device provided by the embodiment of the present application comprises the display panel as any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] The technical scheme and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0013] Fig. 1 is a schematic diagram of a display device provided by the embodiment of the present application.

[0014] Fig. 2 is a timing diagram of output signals of a gate driving module of the display device in Fig. 1.

[0015] Fig. 3 is a first schematic diagram of a display panel provided by the embodiment of the present application.

[0016] Fig. 4 is a second schematic diagram of a display panel provided by the embodiment of the present application.

[0017] Fig. 5 is a circuit diagram of a first gate driving circuit and a second gate driving circuit provided by the embodiment of the present application.

[0018] Fig. 6 is a circuit diagram of a pixel driving circuit provided by the embodiment of the present application.

[0019] Fig. 7 is a third schematic diagram of a display panel provided by the embodiment of the present application.

[0020] Fig. 8 is a fourth schematic diagram of a display panel provided by the embodiment of the present application.

[0021] Fig. 9 is a fifth schematic diagram of a display panel provided by the embodiment of the present application.

[0022] Fig. 10 is a sixth schematic diagram of a display panel provided by the embodiment of the present application.

[0023] Fig. 11 is a timing diagram of output signals of a gate driving module of the display panel in Fig. 6. Embodiments of the present application

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0025] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0026] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" refers to direct connection, and "electrical connection" and "electrical connection" refer to direct connection or indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0027] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0028] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of the specific examples are described in the following disclosure. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application can repeatedly refer to reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can realize the application of other processes and / or the use of other materials.

[0029] The existing CMOS GOA circuit can have two signal output ends, and the output signal of one of the signal output ends can be used as the starting signal of the next stage CMOS GOA circuit. However, in actual use, it is found that the output signal of the signal output end can have abnormal fluctuations, resulting in distortion of the subsequent stage transmission signal and the subsequent output signal, thereby affecting the display effect. Therefore, the existing CMOS GOA circuit has the technical problem that when the output signal is used as the stage transmission signal, the output signal can have large fluctuations.

[0030] The embodiments of the present application aim at the above technical problems, and provide a display panel and a display device to solve the above technical problems.

[0031] FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application. FIG. 2 is a timing diagram of the output signal of the gate drive module of the display device in FIG. 1. FIG. 3 is a first schematic diagram of a display panel according to an embodiment of the present application. FIG. 4 is a second schematic diagram of a display panel according to an embodiment of the present application. FIG. 5 is a circuit diagram of a first gate drive circuit and a second gate drive circuit according to an embodiment of the present application. FIG. 6 is a circuit diagram of a pixel drive circuit according to an embodiment of the present application. FIG. 7 is a third schematic diagram of a display panel according to an embodiment of the present application. FIG. 8 is a fourth schematic diagram of a display panel according to an embodiment of the present application. FIG. 9 is a fifth schematic diagram of a display panel according to an embodiment of the present application. FIG. 10 is a sixth schematic diagram of a display panel according to an embodiment of the present application. FIG. 11 is a timing diagram of the output signal of the gate drive module of the display panel in FIG. 6.

[0032] As shown in FIG. 1, the present application provides a display device, which comprises a sub-pixel 101 and a gate drive module for driving the sub-pixel, the gate drive module comprises a CMOS GOA module and a non-CMOS GOA module, wherein the CMOS GOA module comprises a first module CMOS-T3 and a second module CMOS-T4, the first module CMOS-T3 comprises a first scan signal output end and a second scan signal output end, the second module CMOS-T4 comprises a third scan signal output end and a fourth scan signal output end, the non-CMOS GOA module comprises a third module EM-1 and a fourth module Pscan2-1, the first scan signal output end is connected with a compensation transistor in the sub-pixel 101, the second scan signal output end and the fourth scan signal output end are electrically connected with a switch transistor in the sub-pixel 101, the signals of the second scan signal output end and the fourth scan signal output end are the same, the third scan signal output end is connected with a reset transistor, the third module EM-1 and the fourth module Pscan2-1 are designed as one driving two (not shown in the figure), the output end of the third module EM-1 is connected with a first light-emitting transistor and a second light-emitting transistor in the sub-pixel 101, and the output end of the fourth module Pscan2-1 is connected with a first reset transistor and a second reset transistor in the sub-pixel 101, so as to realize the control of the gate drive module on the pixel driving circuit.

[0033] Specifically, in order to solve the problem that the signal fluctuation is large when the output signal is used as the stage transmission signal, the gate drive module makes the first module CMOS-T3 and the second module CMOS-T4 in the frontmost column generate the signal of the internal node as the stage transmission signal, and the signals of the first scan signal output end, the second scan signal output end, the third scan signal output end and the fourth scan signal output end are only used as the input signal of the sub-pixel and not as the stage transmission signal, so as to improve the stability of the output signal. However, in the actual test process, it is found that since the first module CMOS-T3 and the second module CMOS-T4 in the frontmost column only need to generate the signal of the internal node, the first scan signal output end and the second scan signal output end of the first module CMOS-T3 in the frontmost column are suspended, and the third scan signal output end and the fourth scan signal output end of the second module CMOS-T4 in the frontmost column are suspended, which leads to large fluctuation of the output signals of the first scan signal output end, the second scan signal output end, the third scan signal output end and the fourth scan signal output end, and further affects the display effect.

[0034] As shown in FIG. 2, which is a timing diagram of output signals of the display device in FIG. 1, the horizontal axis can be time, and the vertical axis can be voltage, in volts, where Pscan(3), Pscan(4), and Pscan(5) are output signals of the second scan signal output terminals of the third, fourth, and fifth rows, respectively, Nscan(3) is an output signal of the first and second scan signal output terminals of the third row, and Nscan(5) is an output signal of the first and second scan signal output terminals of the fifth row, and the signal of Nscan(5) is amplified, it can be seen that the output waveforms of Pscan(3) and Pscan(4) are abnormal, and the output waveforms of Nscan(3) and Nscan(5) are abnormal, which in turn leads to poor display. Therefore, the existing CMOS GOA circuit that uses internal nodes as level transmission signals has the technical problem of abnormal output waveforms caused by some signal output terminals being suspended.

[0035] Embodiments of the present application are directed to the above technical problems, and further provide a display panel and a display device to solve the above technical problems.

[0036] As shown in FIGS. 3-6, embodiments of the present application provide a display panel 1, which includes:

[0037] a display portion 11 including a plurality of rows of first-type sub-pixels 111;

[0038] a load portion 13 disposed on at least one side of the display portion 11 along a first direction Y, the load portion including a plurality of rows of second-type sub-pixels 112;

[0039] a gate drive module 12 including a first gate drive unit 121 and a second gate drive unit 122 disposed on both sides of the display portion 11 along a second direction X, the first gate drive unit 121 including a plurality of cascaded first gate drive circuits 121a, and the second gate drive unit 122 including a plurality of cascaded second gate drive circuits 122a, an internal node P(n-1) of an upper-stage first gate drive circuit 121a is connected to a start signal line STV of a current-stage first gate drive circuit 121a, and an internal node P(n-1) of an upper-stage second gate drive circuit 122a is connected to a start signal line STV of a current-stage second gate drive circuit 122a;

[0040] wherein at least one of the first gate drive circuit 121a and the second gate drive circuit 122a is electrically connected to a transistor in the second-type sub-pixel 112, and the included angle between the first direction Y and the second direction X is greater than 0 and less than or equal to 90 degrees.

[0041] The display panel provided by the embodiment of the present application connects the internal node of the first gate drive circuit of the previous stage with the start signal line of the first gate drive circuit of the current stage, and connects the internal node of the second gate drive unit of the previous stage with the start signal line of the second gate drive circuit of the current stage, so that the gate drive module can use the signal of the internal node as the stage transmission signal, thereby improving the stability of the output signal of the gate drive circuit. In addition, the present application sets a load part, which includes multiple rows of second-type sub-pixels, and at least one of the first gate drive unit and the second gate drive unit is electrically connected with the transistor in the second-type sub-pixel, so that the signal output end of at least one of the first gate drive unit and the second gate drive unit is connected with the load, thereby improving the stability of the signal output end of the first gate drive unit and the second gate drive unit.

[0042] Specifically, n is a positive integer and is greater than or equal to 1, and the value of n is the number of stages of the first gate drive circuit and the second gate drive circuit. For example, if the first gate drive circuit has M+N+1 stages, the value of n is a positive integer from 1 to M+N+1. Specifically, n can be greater than or equal to 3.

[0043] Specifically, the number of gate drive circuits in the first gate drive unit and the second gate drive unit can be the same to ensure that the impedance of the gate drive circuits is the same, but the embodiment of the present application is not limited thereto, and the number of gate drive circuits in the first gate drive unit and the second gate drive unit can also be different.

[0044] Specifically, the first gate drive circuit and the second gate drive circuit have the same structure, but since the first signal output end and the third signal output end do not drive the first-type sub-pixels in the current row, the number of sub-pixels connected to the signal output ends of the first gate drive circuit and the second gate drive circuit can be different.

[0045] Specifically, the display panel in the present application uses the internal node to output the stage transmission signal, which can solve the problem of large fluctuation of the output signal in the existing gate drive circuit. In addition, by setting the second-type sub-pixel, at least one of the first signal output end, the second signal output end, the third signal output end and the fourth signal output end is electrically connected with the transistor, which can avoid the problem of large fluctuation of the output signal caused by the signal output end of the gate drive circuit being suspended. It can be understood that although both solve the problem of large fluctuation of the output signal, using the internal node to replace the signal output end to solve the problem of the signal output end serving as both the output signal and the stage transmission signal at the same time. Connecting the signal output end with at least one transistor in the second-type sub-pixel solves the problem of large fluctuation of the output signal caused by the signal output end being suspended.

[0046] Specifically, as shown in FIG. 3, the display panel 1 includes a display area AA and a non-display area NA, the display part 11 is disposed in the display area AA, and the gate drive module 12, the load part 13 and the terminal part 14 are disposed in the non-display area NA.

[0047] In some embodiments, as shown in FIGS. 3-6, the display part 11 includes N rows of first-type sub-pixels 111, at least one of the first-type sub-pixels 111 includes a light-emitting device LED, a drive transistor T31, a switch transistor T32, a compensation transistor T33 and a reset transistor T34, the drive transistor T31 is configured to generate a drive current to drive the light-emitting device LED to emit light, a first electrode of the switch transistor T32 is configured to receive a data signal, a second electrode of the switch transistor T32 is connected with a first electrode of the drive transistor T31, a first electrode of the compensation transistor T33 is connected with a second electrode of the drive transistor T31, a first electrode of the reset transistor T34 is configured to receive a reset signal, and a second electrode of the reset transistor T34 and a second electrode of the compensation transistor T33 are connected with a gate electrode of the drive transistor T31;

[0048] The load part 13 includes M rows of second-type sub-pixels 112;

[0049] The first gate drive unit 121 includes at least (M+N) cascaded first gate drive circuits 121a, the second gate drive unit 122 includes at least (M+N) cascaded second gate drive circuits 122a, the first gate drive circuit 121a includes a first signal output end Nout1(n) and a second signal output end Pout1(n), and the second gate drive circuit 122a includes a third signal output end Nout2(n) and a fourth signal output end Pout2(n);

[0050] The first signal output end Nout1(n) in the (M+k)th first gate drive circuit 121a is electrically connected with the gate electrode of the compensation transistor T33 of the kth row of the first-type sub-pixels 111, the second signal output end Pout1(n) in the (M+k-1)th first gate drive circuit 121a is electrically connected with the gate electrode of the switch transistor T32 of the kth row of the first-type sub-pixels 111, the third signal output end Nout2(n) in the (M+k-3)th second gate drive circuit 122a is electrically connected with the gate electrode of the reset transistor T34 of the kth row of the first-type sub-pixels 111, and the fourth signal output end Pout2(n) in the (M+k-1)th second gate drive circuit 122a is electrically connected with the gate electrode of the switch transistor T32 of the kth row of the first-type sub-pixels 111;

[0051] At least one row of the second type of sub-pixel 112 includes at least one of the switch transistor T32, the compensation transistor T33 and the reset transistor T34, and at least one of the first signal output end Nout1(n), the second signal output end Pout1(n), the third signal output end Nout2(n) and the fourth signal output end Pout2(n) is electrically connected to the transistor in the corresponding second type of sub-pixel 112; N is greater than or equal to 2 and is a positive integer, k is greater than or equal to 1 and is a positive integer, M is greater than or equal to 2 and is a positive integer.

[0052] Specifically, taking M as 4 and k as 1 as an example, it can be seen from FIG. 4 that the first signal output end Nout1(n) in the fifth stage first gate drive circuit 121a is electrically connected to the gate of the compensation transistor T33 of the first row of the first type of sub-pixel 111, the second signal output end Pout1(n) in the fourth stage first gate drive circuit 121a is electrically connected to the gate of the switch transistor T32 of the first row of the first type of sub-pixel 111, the third signal output end Nout2(n) in the second stage second gate drive circuit 122a is electrically connected to the gate of the reset transistor T34 of the first row of the first type of sub-pixel 111, and the fourth signal output end Pout2(n) in the fourth stage second gate drive circuit 122a is electrically connected to the gate of the switch transistor T32 of the first row of the first type of sub-pixel 111.

[0053] Specifically, when the first signal output end, the second signal output end, the third signal output end and the fourth signal output end are connected to the transistor in the second type of sub-pixel, it means that the first signal output end in the current stage is connected to the compensation transistor in the previous row of the second type of sub-pixel, the second signal output end in the current stage is connected to the switch transistor in the current row of the second type of sub-pixel, the third signal output end in the current stage is connected to the reset transistor in the next two rows of the second type of sub-pixel, and the fourth signal output end in the current stage is connected to the switch transistor in the current row of the second type of sub-pixel. Therefore, the electrical connection between at least one of the first signal output end Nout1(n), the second signal output end Pout1(n), the third signal output end Nout2(n) and the fourth signal output end Pout2(n) and the transistor in the corresponding second type of sub-pixel 112 means that the first signal output end, the second signal output end, the third signal output end and the fourth signal output end are electrically connected to the corresponding transistor in the corresponding row of the second type of sub-pixel, for example, only one first signal output end is electrically connected to the transistor in the second type of sub-pixel, which means that the first signal output end is electrically connected to the compensation transistor in the previous row of the second type of sub-pixel.

[0054] The embodiment of the present application sets at least two rows of second-type sub-pixels, and sets at least one of a switch transistor, a compensation transistor and a reset transistor in at least one row of the second-type sub-pixels, so that when an internal node output stage signal of a gate driving circuit is transmitted, at least one signal output end of the gate driving circuit is electrically connected to a transistor, so that the signal output end has a load, the stability of the output signal of the signal output end is improved, the stability of each output signal and the stage transmission signal is improved, and the display effect of the display panel is improved.

[0055] In some embodiments, as shown in FIGS. 3-6, the load part 13 includes at least two rows of second-type sub-pixels 112, the at least two rows of second-type sub-pixels 112 are arranged in a direction away from the first row of first-type sub-pixels 111 and the second row of first-type sub-pixels 111, the first row of second-type sub-pixels 112 includes the compensation transistor T33, and the second row of second-type sub-pixels 112 includes the switch transistor T32 and the compensation transistor T33.

[0056] In the first stage of the first gate driving circuit 121a, the first signal output end Nout1(n) is electrically connected to the gate of the compensation transistor T33 of the first row of second-type sub-pixels 112, and the second signal output end Pout1(n) is electrically connected to the gate of the switch transistor T32 of the second row of second-type sub-pixels 112. In the second stage of the first gate driving circuit 121a, the first signal output end Nout1(n) is electrically connected to the gate of the compensation transistor T33 of the second row of second-type sub-pixels 112.

[0057] Specifically, by setting at least two rows of second-type sub-pixels and setting a compensation transistor in the first row of sub-pixels, the first signal output end in the first stage of the first gate driving circuit can be electrically connected to the compensation transistor in the first row of second-type sub-pixels, so that the stability of the output signal of the first signal output end in the first stage of the first gate driving circuit is improved. By setting a switch transistor and a compensation transistor in the second row of sub-pixels, the second signal output end in the first stage of the first gate driving circuit can be electrically connected to the switch transistor in the second row of second-type sub-pixels, so that the stability of the output signal of the second signal output end in the first stage of the first gate driving circuit is improved. The first signal output end in the second stage of the first gate driving circuit is electrically connected to the gate of the compensation transistor in the second row of second-type sub-pixels, so that the stability of the output signal of the second signal output end in the second stage of the first gate driving circuit is improved. Thus, the stability of the output signal of the gate driving module is improved, and the display stability of the display panel is improved.

[0058] Specifically, in the first row of the second type of sub-pixel, only the compensation transistor and the scan line connecting the gate of the compensation transistor and the first signal output terminal can be present, and no other transistor and connection wire can be present.

[0059] Specifically, in the second row of the second type of sub-pixel, only the switch transistor, the compensation transistor, the scan line connecting the gate of the compensation transistor and the first signal output terminal, the scan line connecting the gate of the switch transistor and the second signal output terminal can be present, and no other transistor and connection wire can be present.

[0060] In some embodiments, as shown in FIGS. 3 to 6, the load part 13 includes at least three rows of the second type of sub-pixel 112, the at least three rows of the second type of sub-pixel 112 are arranged in a direction away from the first row of the first type of sub-pixel 111 and the second row of the first type of sub-pixel 111, and the third row of the second type of sub-pixel 112 includes a switch transistor T32 and a compensation transistor T33.

[0061] The second signal output terminal Pout1(n) in the second stage of the first gate drive circuit 121a is electrically connected to the gate of the switch transistor T32 of the third row of the second type of sub-pixel 112, and the first signal output terminal Nout1(n) in the third stage of the first gate drive circuit 121a is electrically connected to the gate of the compensation transistor T33 in the third row of the second type of sub-pixel 112.

[0062] By arranging at least three rows of the second type of sub-pixel and arranging the switch transistor and the compensation transistor in the third row of the sub-pixel, the second signal output terminal in the second stage of the first gate drive circuit can be electrically connected to the switch transistor in the third row of the second type of sub-pixel, so as to improve the stability of the output signal of the second signal output terminal in the second stage of the first gate drive circuit. By electrically connecting the first signal output terminal in the third stage of the first gate drive circuit to the compensation transistor of the third row of the second type of sub-pixel, the stability of the output signal of the first signal output terminal in the third stage of the first gate drive circuit is improved, so as to improve the stability of the output signal of the gate drive module and the display stability of the display panel.

[0063] Specifically, the design of the first row of the second type of sub-pixel and the second row of the second type of sub-pixel can refer to the above embodiments, and the design of the first stage of the first gate drive circuit and the second stage of the first gate drive circuit can refer to the above embodiments.

[0064] Specifically, in the third row of the second type of sub-pixel, only the switch transistor, the compensation transistor, the scan line connecting the gate of the compensation transistor and the first signal output terminal, the scan line connecting the gate of the switch transistor and the second signal output terminal can be present, and no other transistor and connection wire can be present.

[0065] In some embodiments, as shown in FIGS. 3-6, the load part 13 includes at least four rows of second-type sub-pixels 112, the at least four rows of second-type sub-pixels 112 are arranged in a direction away from the first row of first-type sub-pixels 111 and the second row of first-type sub-pixels 111, and the fourth row of second-type sub-pixels 112 includes a switching transistor T32, a compensation transistor T33, and a reset transistor T34;

[0066] The second signal output end Pout1(n) in the third stage of the first gate drive circuit 121a is electrically connected to the gate of the switching transistor T32 in the fourth row of second-type sub-pixels 112, the first signal output end Nout1(n) in the fourth stage of the first gate drive circuit 121a is electrically connected to the gate of the compensation transistor T33 in the fourth row of second-type sub-pixels 112, and the second signal output end Pout1(n) in the fourth stage of the first gate drive circuit 121a is electrically connected to the gate of the switching transistor T32 in the first row of first-type sub-pixels 111.

[0067] The third signal output end Nout2(n) in the first stage of the second gate drive circuit 122a is electrically connected to the gate of the reset transistor T34 in the fourth row of second-type sub-pixels 112, and the third signal output end Nout2(n) in the second stage of the second gate drive circuit 122a is electrically connected to the gate of the reset transistor T34 in the first row of first-type sub-pixels 111.

[0068] The fourth row of the second type of sub-pixel can only have a switch transistor, the compensation transistor, the reset transistor, a scan line connecting the gate of the compensation transistor and the first signal output end, a scan line connecting the gate of the switch transistor and the second signal output end, and a scan line connecting the reset transistor and the third signal output end, without any other transistor and connection wire.

[0069] Specifically, the fourth row of the second type of sub-pixel can only have a switch transistor, the compensation transistor, the reset transistor, a scan line connecting the gate of the compensation transistor and the first signal output end, a scan line connecting the gate of the switch transistor and the second signal output end, and a scan line connecting the reset transistor and the third signal output end, without any other transistor and connection wire.

[0070] In some embodiments, as shown in FIGS. 3-6, the fourth signal output end Pout2(n) in the first stage of the second gate driving circuit 122a is electrically connected to the gate of the switch transistor T32 in the second row of the second type of sub-pixel 112, the fourth signal output end Pout2(n) in the second stage of the second gate driving circuit 122a is electrically connected to the gate of the switch transistor T32 in the third row of the second type of sub-pixel 112, the fourth signal output end Pout2(n) in the third stage of the second gate driving circuit 122a is electrically connected to the gate of the switch transistor T32 in the fourth row of the second type of sub-pixel 112, and the fourth signal output end Pout2(n) in the fourth stage of the second gate driving circuit 122a is electrically connected to the gate of the switch transistor T32 in the first row of the first type of sub-pixel 111.

[0071] The fourth signal output end in the first-stage second gate driving circuit is electrically connected with the gate of the switching transistor in the second-row second-type sub-pixel, the fourth signal output end in the second-stage second gate driving circuit is electrically connected with the gate of the switching transistor in the third-row second-type sub-pixel, the fourth signal output end in the third-stage second gate driving circuit is electrically connected with the gate of the switching transistor in the fourth-row second-type sub-pixel, the fourth signal output end in the fourth-stage second gate driving circuit is electrically connected with the gate of the switching transistor in the first-row first-type sub-pixel, and the stability of the output signal of the fourth signal output end in the fourth-stage second gate driving circuit is improved, so that the stability of the output signal of the gate driving module is improved, and the display stability of the display panel is improved.

[0072] Specifically, in the second-row second-type sub-pixel, only the switching transistor, the compensation transistor, the scan line connecting the gate of the compensation transistor and the first signal output end, the scan line connecting the gate of the switching transistor and the second signal output end, and the scan line connecting the gate of the switching transistor and the fourth signal output end can be present, and no other transistor and connection wire can be present.

[0073] Specifically, in the third-row second-type sub-pixel, only the switching transistor, the compensation transistor, the scan line connecting the gate of the compensation transistor and the first signal output end, the scan line connecting the gate of the switching transistor and the second signal output end, and the scan line connecting the gate of the switching transistor and the fourth signal output end can be present, and no other transistor and connection wire can be present.

[0074] Specifically, in the fourth-row second-type sub-pixel, only the switching transistor, the compensation transistor, the reset transistor, the scan line connecting the gate of the compensation transistor and the first signal output end, the scan line connecting the gate of the switching transistor and the second signal output end, the scan line connecting the gate of the switching transistor and the fourth signal output end, and the scan line connecting the reset transistor and the third signal output end can be present, and no other transistor and connection wire can be present.

[0075] Specifically, in order to ensure the uniform load in each second-type sub-pixel, the first row of second-type sub-pixels to the fourth row of second-type sub-pixels can only have the switching transistor, the compensation transistor, the reset transistor, the scan line connecting the gate of the compensation transistor and the first signal output end, the scan line connecting the gate of the switching transistor and the second signal output end, the scan line connecting the gate of the switching transistor and the fourth signal output end, and the scan line connecting the reset transistor and the third signal output end, without other transistors and connection wires.

[0076] Specifically, it can be understood that, since the gate of the compensation transistor of the first row of first-type sub-pixels is electrically connected with the first signal output end of the first gate drive circuit of the next row, and the gate of the reset transistor of the first row of first-type sub-pixels is electrically connected with the third signal output end of the second gate drive circuit of the two rows above, when the second gate drive circuit is set, at least two levels of second gate drive circuits need to be set before the first row of first-type sub-pixels to realize the normal driving of the first-type sub-pixels. Meanwhile, in order to ensure the electric field of the first row of first-type sub-pixels consistent with that of the first-type sub-pixels of other rows, and in order to ensure the stage transmission signal in the gate drive module not affected, a row of second-type sub-pixels and the gate drive circuit driving the row of second-type sub-pixels are added, at this time, at least three levels of second gate drive circuits need to be set before the first row of first-type sub-pixels, and in order to ensure the impedance of the left and right gate drive circuits consistent, the number of levels of the first gate drive circuit and the second gate drive circuit is the same, but since the gate of the compensation transistor of the first row of first-type sub-pixels is electrically connected with the first signal output end of the first gate drive circuit of the next row, the first signal output end of the first level of first gate drive circuit will have no load, therefore, a row of second-type sub-pixels are added to realize the load of the first signal output end of the first level of first gate drive circuit.

[0077] Based on the above considerations, when the first gate drive circuit, the second gate drive circuit and the second-type sub-pixel are set, at least four rows of second-type sub-pixels are set, and at least three levels of first gate drive circuits and at least three levels of second gate drive circuits are set before the first row of first-type sub-pixels, so that before the last row of first-type sub-pixels, the signal output ends of all first gate drive circuits and second gate drive circuits can be electrically connected to transistors, thereby improving the stability of the stage transmission signal and the output signal, and improving the display stability of the display panel.

[0078] It can be understood that since after driving the first-type sub-pixels in the last row, the subsequent stage transmission signals will not affect the sub-pixels in the display area even if there is a deviation, therefore, the design after the first gate drive circuit and the second gate drive circuit driving the first-type sub-pixels in the last row can not be limited, for example, a row or more of first gate drive circuits can be arranged after the first gate drive circuit driving the first-type sub-pixels in the last row, the first gate drive circuit is connected to the transistor or not connected to the transistor, or no first gate drive circuit is arranged, and the same applies to the second gate drive circuit. The following embodiments illustrate some cases.

[0079] In some embodiments, as shown in FIG. 7, at least part of the fourth signal output ends Pout2(n) in the second gate drive circuits 122a of the first to third stages are electrically connected to the second signal output ends Pout1(n) in the corresponding first gate drive circuits 121a of the first to third stages. By electrically connecting at least part of the fourth signal output ends in the first to third stage second gate drive circuits to the second signal output ends in the corresponding first to fourth stage first gate drive circuits, the load of the first to third stage first gate drive circuits and the first to third stage second gate drive circuits can be similar to or even the same as the load of the subsequent first gate drive circuits and second gate drive circuits, thereby improving the stability of signal transmission and the display stability of the display panel.

[0080] Specifically, the fourth signal output end of one of the second gate drive circuits in the first to third stages can be electrically connected to the second signal output end of the corresponding first gate drive circuit, for example, the fourth signal output end of the second gate drive circuit in the second stage is electrically connected to the second signal output end of the first gate drive circuit in the second stage, and the fourth signal output end of the second gate drive circuit in the first and third stages can not be electrically connected to the second signal output end of the corresponding first gate drive circuit. The fourth signal output end of two of the second gate drive circuits in the first to third stages can also be electrically connected to the second signal output end of the corresponding first gate drive circuit, for example, the fourth signal output end of the second gate drive circuit in the first stage is electrically connected to the second signal output end of the first gate drive circuit in the first stage, the fourth signal output end of the second gate drive circuit in the second stage is electrically connected to the second signal output end of the first gate drive circuit in the second stage, and the fourth signal output end of the second gate drive circuit in the third stage can not be electrically connected to the second signal output end of the corresponding first gate drive circuit. The fourth signal output end of three of the second gate drive circuits in the first to third stages can also be electrically connected to the second signal output end of the corresponding first gate drive circuit, i.e., the fourth signal output end of the second gate drive circuit in the first stage is electrically connected to the second signal output end of the first gate drive circuit in the first stage, the fourth signal output end of the second gate drive circuit in the second stage is electrically connected to the second signal output end of the first gate drive circuit in the second stage, and the fourth signal output end of the second gate drive circuit in the third stage is electrically connected to the second signal output end of the first gate drive circuit in the third stage.

[0081] Specifically, the number of switch transistors electrically connected to any of the fourth signal output ends of the second gate drive circuits in the first to third stages is less than or equal to the number of switch transistors in a row of second-type sub-pixels; the number of switch transistors electrically connected to any of the second signal output ends of the first gate drive circuits in the first to third stages is less than or equal to the number of switch transistors in a row of second-type sub-pixels.

[0082] Specifically, any of the fourth signal output ends Pout2(n) of the second gate drive circuits in the fourth to second-to-last stages is electrically connected to the second signal output end Pout1(n) of the corresponding first gate drive circuit 121a in the fourth to second-to-last stages.

[0083] Specifically, the number of switch transistors electrically connected to any of the second signal output ends Pout1(n) of the first gate drive circuits 121a in the fourth to second-to-last stages is equal to the number of switch transistors in a row of first-type sub-pixels.

[0084] Specifically, the fourth signal output end in the last-stage second gate drive circuit can be electrically connected with the second signal output end in the last-stage first gate drive circuit, or can not be electrically connected.

[0085] In some embodiments, as shown in FIG. 8, the fourth signal output end Pout2(n) in any of the first-stage to third-stage second gate drive circuits 122a is disconnected from the second signal output end Pout1(n) in the corresponding first-stage to third-stage first gate drive circuits. By disconnecting the fourth signal output end and the second signal output end, the fourth signal output end and the second signal output end can be respectively connected to different second-type sub-pixels, so that the signals of the fourth signal output end and the second signal output end are stable.

[0086] In some embodiments, as shown in FIG. 8, the number of switch transistors T32 connected to the second signal output end Pout1(n) in any of the first-stage to third-stage first gate drive circuits 121a is equal to the number of switch transistors T32 connected to the fourth signal output end Pout2(n) in the corresponding first-stage to third-stage second gate drive circuits 122a. By making the number of switch transistors electrically connected to the second signal output end equal to the number of switch transistors electrically connected to the fourth signal output end, the load connected to the first gate drive circuit is the same as the load connected to the second gate drive circuit, the output signals of the first gate drive circuit and the second gate drive circuit are the same, and the display stability of the display panel is improved.

[0087] In some embodiments, as shown in FIG. 9, the number of compensation transistors T33 connected to the first signal output end Nout1(n) in any of the first-stage to fourth-stage first gate drive circuits 121a is less than or equal to the number of compensation transistors T33 in a row of the second-type sub-pixels 112. By making the number of compensation transistors electrically connected to the first signal output end in any of the first-stage to fourth-stage first gate drive circuits less than the number of compensation transistors in a row of the second-type sub-pixels, the first signal output end in the first gate drive circuit can be electrically connected to a load, so that the stability of the output signal of the first signal output end is improved. If the number of compensation transistors electrically connected to the first signal output end in the first-stage to fourth-stage first gate drive circuits is equal to the number of compensation transistors in a row of the second-type sub-pixels, the number of compensation transistors electrically connected to the first signal output end in the first-stage to fourth-stage first gate drive circuits is equal to the number of compensation transistors electrically connected to the first signal output end in the first gate drive circuit of other stages, so that the load of the first-stage to fourth-stage first gate drive circuits is similar to or even the same as the load of the subsequent first gate drive circuit, thereby improving the stability of signal transmission and the display stability of the display panel.

[0088] Specifically, the number of the compensation transistors T33 connected to any of the first signal output terminals Noutl(n) in the fifth to the second last first gate drive circuit is equal to the number of the compensation transistors T33 in a row of the first type of sub-pixels 111.

[0089] In some embodiments, as shown in FIG. 10, the number of the reset transistors T34 electrically connected to the third signal output terminal Nout2(n) in the first second gate drive circuit 122a is less than or equal to the number of the reset transistors T34 in a row of the second type of sub-pixels 112. By making the number of the reset transistors electrically connected to the third signal output terminal in the first second gate drive circuit less than the number of the reset transistors in a row of the second type of sub-pixels, the third signal output terminal in the second gate drive circuit can be electrically connected to a load, thereby improving the stability of the output signal of the third signal output terminal. If the number of the reset transistors electrically connected to the third signal output terminal in the first second gate drive circuit is equal to the number of the reset transistors in a row of the second type of sub-pixels, the number of the reset transistors electrically connected to the third signal output terminal in the first second gate drive circuit can be equal to the number of the reset transistors electrically connected to the third signal output terminal in the second gate drive circuit, so that the load of the first second gate drive circuit is similar to or even the same as the load of the subsequent second gate drive circuit, thereby improving the stability of signal transmission and the display stability of the display panel.

[0090] Specifically, the number of the reset transistors T34 electrically connected to any of the third signal output terminals Nout2(n) in the second to the fifth second gate drive circuit 122a is equal to the number of the reset transistors T34 in a row of the second type of sub-pixels 112.

[0091] Specifically, the connection modes of the partial signal output terminals and the corresponding transistors are shown in FIGS. 7 to 10, respectively. It can be understood that the number of the signal output terminals of each first gate drive circuit is the same, and the number of the signal output terminals of each second gate drive circuit is the same. Accordingly, the designs of different signal output terminals in FIGS. 7 to 10 can be provided in the same gate drive circuit, that is, a first gate drive circuit can adopt the designs in FIGS. 7 and 9, or can adopt the designs in FIGS. 8 and 9, and a second gate drive circuit can adopt the designs in FIGS. 7 and 10, or can adopt the designs in FIGS. 8 and 10.

[0092] In some embodiments, as shown in FIG. 3 and FIG. 4, the display panel 1 further comprises a first test signal line 141, a second test signal line 142, a third test signal line 143 and a fourth test signal line 144, the first gate driving unit 121 comprises (M+N+1) first gate driving circuits 121a connected in cascade, the second gate driving unit 122 comprises (M+N+1) second gate driving circuits 122a connected in cascade, the first signal output end Nout1(n) in the (M+N+1)th first gate driving circuit 121a is connected to the first test signal line 141, the second signal output end Pout1(n) in the first gate driving circuit 121a is connected to the second test signal line 142, the third signal output end Nout2(n) in the (M+N+1)th second gate driving circuit 122a is connected to the third test signal line 143, and the fourth signal output end Pout2(n) in the (M+N+1)th second gate driving circuit 122a is connected to the fourth test signal line 144. By arranging the first test signal line, the second test signal line, the third test signal line and the fourth test signal line, each signal output end can be tested, and the problem of the gate driving circuit affecting the display can be prevented.

[0093] Specifically, the first test signal line, the second test signal line, the third test signal line and the fourth test signal line can be arranged in the non-display area, can be overlapped with other wires to form a parasitic capacitor, and each signal output end is equivalent to being connected to a load, thereby improving the signal stability.

[0094] In some embodiments, the first electrode of the switch transistor T32, the first electrode of the compensation transistor T33 and the first electrode of the reset transistor T34 in the second type of sub-pixel 112 are suspended, and the second electrode of the switch transistor T32, the second electrode of the compensation transistor T33 and the second electrode of the reset transistor T34 in the second type of sub-pixel are suspended. By suspending the first electrode and the second electrode of the switch transistor, the compensation transistor and the reset transistor in the second type of sub-pixel, the second type of sub-pixel can only serve as a load for each signal output end, and will not display, and the space occupied by the second type of sub-pixel can be reduced, thereby reducing the frame.

[0095] Specifically, when designing the structure in the second type of sub-pixel, only the transistors can be formed, but the first electrode and the second electrode of each transistor are not connected to other wires, thereby reducing the wires and structures in the second type of sub-pixel and reducing the space occupied by the second type of sub-pixel.

[0096] In some embodiments, as shown in FIG. 4, in the first direction Y, the first row of the second type of sub-pixel 112 is located in a different row from the first-stage first gate driving circuit 121a, and the first-stage first gate driving circuit 121a is located in the same row as the first-stage second gate driving circuit 122a. By locating the first row of the second type of sub-pixel in a different row from the first-stage first gate driving circuit, the first-stage first gate driving circuit can drive the first row of the second type of sub-pixel, and by locating the first-stage first gate driving circuit in the same row as the first-stage second gate driving unit, the number of stages of the gate driving units on the left and right sides is the same, the impedance of the gate driving circuits on the left and right sides is similar or even consistent, and the display effect is improved.

[0097] In some embodiments, the number of transistors in the second type of sub-pixel 112 is less than the number of transistors in the first type of sub-pixel 111, and the number of wires in the second type of sub-pixel 112 is less than the number of wires in the first type of sub-pixel 111. By reducing the number of transistors in the second type of sub-pixel to be less than the number of transistors in the first type of sub-pixel, and reducing the number of wires in the second type of sub-pixel to be less than the number of wires in the first type of sub-pixel, the space occupied by the second type of sub-pixel can be reduced, and the frame of the display panel can be reduced.

[0098] Specifically, as can be seen from the above embodiments, in some embodiments, the first row of the second type of sub-pixel only has a compensation transistor connected to the first signal output end in the first-stage first gate driving circuit, and at this time, only the compensation transistor and the wire connecting the gate of the compensation transistor and the first signal output end can be provided in the first row of the second type of sub-pixel. At this time, the space occupied by the first row of the second type of sub-pixel is smaller, thereby reducing the frame, and similarly, for the second type of sub-pixel in other rows, only the transistor electrically connected to the signal output end and the wire connecting the transistor and the signal output end can be provided.

[0099] Specifically, the first signal output end and the gate of the compensation transistor can be connected through the first scan line Nscan1, the second signal output end and the gate of the switch transistor can be connected through the second scan line Pscan, the third signal output end and the gate of the reset transistor can be connected through the third scan line Nscan2, and the fourth signal output end and the gate of the switch transistor can be connected through the second scan line Pscan. It can be understood that when the second signal output end and the fourth signal output end are not electrically connected, the second signal output end and the fourth signal output end can be connected to the gates of different switch transistors through different parts of the second scan line.

[0100] Specifically, it can be understood that the first scan line and the first signal output terminal can actually be different parts of the same trace, and the definition here is only for the purpose of illustrating that they belong to different parts, i.e., the first signal output terminal is the part of the trace corresponding to the gate drive module, and the first scan line is the part of the trace corresponding to the first type of sub-pixel and the second type of sub-pixel. Similarly, the other signal output terminals and the corresponding scan lines can be different parts of the same trace.

[0101] Specifically, the embodiments of the present application do not limit the specific structure of the gate drive circuit, and the structure of a gate drive circuit is specifically described here.

[0102] Specifically, taking the same structure of the first gate drive circuit 121a and the second gate drive circuit 122a as an example, the first signal output terminal Nout1(n) and the third signal output terminal Nout2(n) are the same signal output terminal of different gate drive circuits, the second signal output terminal Pout1(n) and the fourth signal output terminal Pout2(n) are the same signal output terminal of different gate drive circuits, and the structure of the first gate drive circuit 121a is described in the following embodiments. It can be understood that the structure of the second gate drive circuit can be referred to the structure description of the first gate drive circuit.

[0103] As shown in FIG. 5, the first gate drive circuit 121a includes:

[0104] The first control unit 10 includes a first control transistor T13 and a second control transistor T12, the first control transistor T13 is an oxide semiconductor transistor, the second control transistor T12 is a silicon semiconductor transistor, the gate of the first control transistor T13 and the gate of the second control transistor T12 are connected with an initial signal line STV, the first electrode of the first control transistor T13 and the first electrode of the second control transistor T12 are electrically connected to a first node K, the second electrode of the first control transistor T13 is connected with a second low potential signal line PVGL, and the second electrode of the second control transistor T12 is connected with a second high potential signal line PVGH;

[0105] The first output unit 30 includes a first output transistor T10, a second output transistor T9, a first low potential signal line NVGL, and a first high potential signal line NVGH. The first output transistor T10 is an oxide semiconductor transistor, and the second output transistor T9 is a silicon semiconductor transistor. A gate of the first output transistor T10 is electrically connected to the first node K, and a gate of the second output transistor T9 is electrically connected to the first node K. A first electrode of the first output transistor T10 and a first electrode of the second output transistor T9 are electrically connected to the first signal output terminal Noutl(n). A second electrode of the first output transistor T10 is electrically connected to the first low potential signal line NVGL, and a second electrode of the second output transistor T9 is electrically connected to the first high potential signal line NVGH.

[0106] The second control unit 20 includes a third control transistor T1, a fourth control transistor T3, a second low potential signal line PVGL, and a second high potential signal line PVGH. The third control transistor T1 is an oxide semiconductor transistor, and the fourth control transistor T3 is a silicon semiconductor transistor. A gate of the third control transistor T1 and a gate of the fourth control transistor T3 are electrically connected to the first node K. A first electrode of the third control transistor T1 and a first electrode of the fourth control transistor T3 are electrically connected to an internal node P(n) of the stage. A second electrode of the third control transistor T1 is electrically connected to the second low potential signal line PVGL, and a second electrode of the fourth control transistor T3 is electrically connected to the second high potential signal line PVGH.

[0107] The output control unit 60 includes a first switch transistor T4, a second switch transistor T5, and a third switch transistor T14. The first switch transistor T4 and the third switch transistor T14 are oxide semiconductor transistors, and the second switch transistor T5 is a silicon semiconductor transistor. A gate of the first switch transistor T4 is electrically connected to a second clock signal line XCK. A first electrode of the first switch transistor T4 and a first electrode of the second switch transistor T5 are electrically connected to each other. A second electrode of the first switch transistor T4 is electrically connected to the first node K. A gate of the second switch transistor T5 and a gate of the third switch transistor T14 are electrically connected to the first electrode of the third control transistor T1. A second electrode of the second switch transistor T5 is electrically connected to the second high potential signal line PVGH. A first electrode of the third switch transistor T14 is electrically connected to the first node K, and a second electrode of the third switch transistor T14 is electrically connected to the first low potential signal line NVGL.

[0108] The third control unit 801 includes a fifth control transistor T17 and a sixth control transistor T18. The fifth control transistor T17 is an oxide semiconductor transistor, and the sixth control transistor T18 is a silicon semiconductor transistor. The gate of the fifth control transistor T17 is connected to the second clock signal line XCK. The first electrode of the fifth control transistor T17 and the first electrode of the sixth control transistor T18 are connected to each other. The second electrode of the fifth control transistor T17 is electrically connected to the first node K. The gate of the sixth control transistor T18 is connected to the gate of the third switch transistor T14. The second electrode of the sixth control transistor T18 is connected to the second high potential signal line PVGH.

[0109] The fourth control unit 802 includes a seventh control transistor T21 and an eighth control transistor T22. The seventh control transistor T21 is an oxide semiconductor transistor, and the eighth control transistor T22 is a silicon semiconductor transistor. The gate of the seventh control transistor T21 is connected to the second clock signal line XCK. The first electrode of the seventh control transistor T21 and the first electrode of the eighth control transistor T22 are connected to each other. The second electrode of the seventh control transistor T21 is electrically connected to the first node K. The gate of the eighth control transistor T22 is connected to the gate of the third switch transistor T14. The second electrode of the eighth control transistor T22 is connected to the second high potential signal line PVGH.

[0110] Specifically, the first control transistor, the third control transistor, the first switch transistor, the third switch transistor, the fifth control transistor, the seventh control transistor, and the first output transistor are N-type transistors, the second control transistor, the fourth control transistor, the second switch transistor, the sixth control transistor, the eighth control transistor, and the second output transistor are P-type transistors, and the first control transistor, the third control transistor, the first switch transistor, the third switch transistor, the fifth control transistor, the seventh control transistor, and the first output transistor are double-gate transistors, but embodiments of the present application are not limited thereto, and they can be single-gate transistors.

[0111] Specifically, as shown in FIG. 5, the first control unit 10 further includes a ninth control transistor T2. The gate of the ninth control transistor T2 is connected to the second clock signal line XCK. The first electrode of the ninth control transistor T2 is connected to the first node K. The second electrode of the ninth control transistor T2, the first electrode of the first control transistor T13, and the first electrode of the second control transistor T12 are connected to the second node O.

[0112] Specifically, as shown in FIG. 5, the first gate drive circuit 121a further includes:

[0113] The second output unit 40 comprises a third output transistor T6, a fourth output transistor T7 and a first capacitor C1, a gate of the third output transistor T6 is connected to the third node Q, a first electrode of the third output transistor T6 is connected with a first electrode of the fourth output transistor T7, and the first electrode of the third output transistor T6 is connected with the second signal output terminal Pout1(n), a second electrode of the third output transistor T6 is connected with the first clock signal line CK, a gate of the fourth output transistor T7 is connected to the internal node P(n) of the current stage, a second electrode of the fourth output transistor T7 is connected with the second high potential signal line PVGH, a first plate of the first capacitor C1 is connected with the gate of the third output transistor T6, and a second plate of the first capacitor C1 is connected with the second signal output terminal Pout1(n);

[0114] The frequency division unit 50 comprises a first frequency division unit 501 and a second frequency division unit 502, the first frequency division unit comprises a first frequency division transistor T16, a second frequency division transistor T11 and a second capacitor C2, a gate of the first frequency division transistor T16 is connected to the internal node P(n) of the current stage, a first electrode of the first frequency division transistor T16, a first plate of the second capacitor C2 and a gate of the second frequency division transistor T11 are connected, a second electrode of the first frequency division transistor T16 is connected with the first frequency division signal line NLF, a first electrode of the second frequency division transistor T11 is connected with the second plate of the second capacitor C2 and the fourth node W, and a second electrode of the second frequency division transistor T11 is connected to the first node K; the second frequency division unit 502 comprises a third frequency division transistor T20, a fourth frequency division transistor T19 and a third capacitor C3, a gate of the third frequency division transistor T20 is connected to the internal node P(n) of the current stage, a first electrode of the third frequency division transistor T20, a first plate of the third capacitor C3 and a gate of the fourth frequency division transistor T19 are connected, a second electrode of the third frequency division transistor T20 is connected with the second frequency division signal line PLF, a first electrode of the fourth frequency division transistor T19 is connected with the second plate of the third capacitor C3 and the fifth node M, and a second electrode of the fourth frequency division transistor T19 is connected to the first node K;

[0115] The reset unit 70 comprises a reset transistor T15, a gate of the reset transistor T15 is connected with the control signal line Control, a first electrode of the reset transistor T15 is connected to the first node K, and a second electrode of the reset transistor T15 is connected with the high potential signal line PVGH;

[0116] The switch unit 90 comprises a fourth switch transistor T8, a gate of the fourth switch transistor T8 is connected with the switch signal line SC, the switch signal line SC is connected with the internal node P(n-2) of the first gate drive circuit 121a of the upper two stages, a first electrode of the fourth switch transistor T8 is connected to the third node Q, and a second electrode of the fourth switch transistor T8 is connected to the fifth node M.

[0117] Specifically, the third output transistor T6 and the fourth output transistor T7 are silicon semiconductor transistors, and the third output transistor T6 and the fourth output transistor T7 are P-type transistors.

[0118] Specifically, the first frequency division transistor T16 and the second frequency division transistor T11 are silicon semiconductor transistors, and the first frequency division transistor T16 and the second frequency division transistor T11 are P-type transistors.

[0119] Specifically, the third frequency division transistor T20 and the fourth frequency division transistor T19 are silicon semiconductor transistors, and the third frequency division transistor T20 and the fourth frequency division transistor T19 are P-type transistors.

[0120] Specifically, the reset transistor T15 is a silicon semiconductor transistor, and the reset transistor T15 is a P-type transistor.

[0121] Specifically, the fourth switch transistor T8 is a silicon semiconductor transistor, and the fourth switch transistor T8 is a P-type transistor.

[0122] Specifically, as shown in FIG. 5, the starting signal line STV of the first gate drive circuit 121a of the current stage is connected to the internal node P(n-1) of the first gate drive circuit 121a of the previous stage.

[0123] Specifically, as shown in FIGS. 3 to 6, the first type of sub-pixel 111 is provided with a pixel driving circuit 110, and the specific structure of the pixel driving circuit is not limited in the present application. Here, the structure of a pixel driving circuit is specifically described.

[0124] Specifically, the first type of sub-pixel has a complete structure of the pixel driving circuit 110, and the second type of sub-pixel can only have part of the structure of the pixel driving circuit, and can have a complete structure of the pixel driving circuit.

[0125] As shown in FIG. 6, the pixel driving circuit 110 includes a driving transistor T31, a switch transistor T32, a compensation transistor T33, a reset transistor T34, a first light-emitting transistor T35, a second light-emitting transistor T36, a first initialization transistor T37, and a second initialization transistor T38.

[0126] The gate of the switch transistor T32 is connected with the second scan line Pscan1, the first electrode of the switch transistor T32 is connected with the data signal line Data, the second electrode of the switch transistor T32 is connected with the first electrode of the drive transistor T31, the gate of the compensation transistor T33 is connected with the first scan line Nscan1, the second electrode of the compensation transistor T33 is connected with the second electrode of the reset transistor T34, the first electrode of the compensation transistor T33 is connected with the second electrode of the drive transistor T31, the gate of the reset transistor T34 is connected with the third scan line Nscan2, the first electrode of the reset transistor T34 is connected with the first initialization line Vi1, the gate of the first light-emitting transistor T35 is connected with the light-emitting control line EM, the first electrode of the first light-emitting transistor T35 is connected with the power high potential signal line VDD, the second electrode of the first light-emitting transistor T35 is connected with the first electrode of the drive transistor T31, the gate of the second light-emitting transistor T36 is connected with the light-emitting control line EM, the first electrode of the second light-emitting transistor T36 is connected with the second electrode of the drive transistor T31, the second electrode of the second light-emitting transistor T36 is connected with the light-emitting device LED, the gate of the first initialization transistor T37 is connected with the fourth scan line Pscan2, the first electrode of the first initialization transistor T37 is connected with the second initialization line Vi2, the second electrode of the first initialization transistor T37 is connected with the light-emitting device LED, the gate of the second initialization transistor T38 is connected with the fourth scan line Pscan2, the first electrode of the second initialization transistor T38 is connected with the third initialization line Vi3, and the second electrode of the second initialization transistor T38 is connected with the first electrode of the drive transistor T31.

[0127] Specifically, as shown in FIG. 6, the light-emitting device LED is connected with the power low potential signal line VSS, and the pixel driving circuit further comprises a storage capacitor Cst and a boost capacitor Cboost, one end of the storage capacitor Cst is connected with the power high potential signal line VDD, and the other end of the storage capacitor Cst is connected with the gate of the drive transistor T31; one end of the boost capacitor Cboost is connected with the gate of the switch transistor T32, and the other end of the boost capacitor Cboost is connected with the gate of the drive transistor T31.

[0128] Specifically, the gate driving module further comprises a gate driving unit for outputting the signal of the light-emitting control line EM and a gate driving unit for outputting the signal of the fourth scan line Pscan2, and the designs thereof can be respectively referred to the designs of the third module and the fourth module in FIG. 1, which will not be described herein again.

[0129] Specifically, the driving transistor T31, the switching transistor T32, the first light-emitting transistor T35, the second light-emitting transistor T36, the first initialization transistor T37 and the second initialization transistor T38 are silicon semiconductor transistors, and the compensation transistor T33 and the reset transistor T34 are oxide semiconductor transistors.

[0130] Specifically, the driving transistor T31, the switching transistor T32, the first light-emitting transistor T35, the second light-emitting transistor T36, the first initialization transistor T37 and the second initialization transistor T38 are P-type transistors, and the compensation transistor T33 and the reset transistor T34 are N-type transistors.

[0131] Specifically, the oxide semiconductor transistor can be a metal oxide transistor, and the silicon semiconductor transistor can be a low-temperature polysilicon transistor.

[0132] In some embodiments, the first electrode of the transistor in the above embodiments is a source electrode, and the second electrode is a drain electrode; or the first electrode of the transistor in the above embodiments is a drain electrode, and the second electrode is a source electrode.

[0133] It should be noted that the above embodiments are described by taking an example that each signal output end of each first gate drive circuit is electrically connected to a transistor, but the embodiments of the present application are not limited thereto, and part of the signal output ends can not be electrically connected to the transistors.

[0134] It should be noted that the output signals of the second signal output end and the fourth signal output end are the same, and the output signals of the first signal output end and the third signal output end can be the same.

[0135] Specifically, the above embodiments respectively describe the display panel from various circuits, various film layers, various structures and combinations thereof. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined, for example, at least part of the fourth signal output ends in the second gate drive circuits of the first to third stages are electrically connected to the second signal output ends in the corresponding first to third stage first gate drive circuits, and the number of compensation transistors electrically connected to any first signal output end in the first to fourth stage first gate drive circuits is less than or equal to the number of compensation transistors in one row of the second type of sub-pixels.

[0136] As shown in FIG. 11, FIG. 11 is a timing diagram of output signals of the display panel in FIG. 6, the horizontal coordinate can be time, and the vertical coordinate can be voltage, and the unit can be volt, wherein Pscan(3), Pscan(4) and Pscan(5) are respectively output signals of the second signal output end and the fourth signal output end of the third row, the fourth row and the fifth row, Nscan(3) is an output signal of the first signal output end and the third signal output end of the third row, and Nscan(5) is an output signal of the first signal output end and the third signal output end of the fifth row, and it can be seen from FIG. 11 that the output signal of the gate drive circuit in the present application is relatively stable.

[0137] Meanwhile, the display device provided in the embodiments of the present application comprises the display panel as described in any of the above embodiments.

[0138] According to the above embodiments, it can be known that:

[0139] The display panel and the display device provided in the embodiments of the present application are provided, the display panel is connected by connecting an internal node of a first gate drive circuit of a previous stage and a start signal line of a first gate drive circuit of a current stage, and connecting an internal node of a second gate drive unit of the previous stage and a start signal line of a second gate drive circuit of the current stage, so that the gate drive module can use the signal of the internal node as a stage transmission signal, and the stability of the output signal of the gate drive circuit is improved, and the present application is provided by setting a load part, the load part comprises a plurality of rows of second type sub-pixels, and at least one of the first gate drive unit and the second gate drive unit is electrically connected to a transistor in the second type sub-pixel, so that the signal output end of at least one of the first gate drive unit and the second gate drive unit is connected to the load, and the stability of the signal output end of the first gate drive unit and the second gate drive unit is improved.

[0140] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0141] The display panel and the display device provided in the embodiments of the present application are described in detail, and the principles and implementation manners of the present application are described by applying specific examples, and the above description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising: a display part comprising a plurality of rows of first type sub-pixels; a load part arranged at at least one side of the display part along a first direction, the load part comprising a plurality of rows of second type sub-pixels; a gate driving module comprising a first gate driving unit and a second gate driving unit arranged at two sides of the display part along a second direction respectively, the first gate driving unit comprising a plurality of cascaded first gate driving circuits, the second gate driving unit comprising a plurality of cascaded second gate driving circuits, an internal node of a previous stage first gate driving circuit being connected with a start signal line of a current stage first gate driving circuit, an internal node of a previous stage second gate driving circuit being connected with a start signal line of a current stage second gate driving circuit; wherein at least one of the first gate driving circuit and the second gate driving circuit is electrically connected with a transistor in the second type sub-pixel, and an included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

2. The display panel of claim 1, wherein, the display part comprising N rows of first type sub-pixels, at least one of the first type sub-pixels comprising a light emitting device, a driving transistor, a switching transistor, a compensation transistor and a reset transistor, the driving transistor being configured to generate a driving current to drive the light emitting device to emit light, a first electrode of the switching transistor being configured to receive a data signal, a second electrode of the switching transistor being connected with a first electrode of the driving transistor, a first electrode of the compensation transistor being connected with a second electrode of the driving transistor, a first electrode of the reset transistor being configured to receive a reset signal, a second electrode of the reset transistor and a second electrode of the compensation transistor being connected with a gate of the driving transistor; the load part comprising M rows of second type sub-pixels; the first gate driving unit comprising at least (M+N) cascaded first gate driving circuits, the second gate driving unit comprising at least (M+N) cascaded second gate driving circuits, the first gate driving circuit comprising a first signal output end and a second signal output end, the second gate driving circuit comprising a third signal output end and a fourth signal output end; wherein the first signal output end in the (M+k)th first gate driving circuit is electrically connected with a gate of the compensation transistor of the kth row of first type sub-pixels, the second signal output end in the (M+k-1)th first gate driving circuit is electrically connected with a gate of the switching transistor of the kth row of first type sub-pixels, the third signal output end in the (M+k-3)th second gate driving circuit is electrically connected with a gate of the reset transistor of the kth row of first type sub-pixels, and the fourth signal output end in the (M+k-1)th second gate driving circuit is electrically connected with a gate of the switching transistor of the kth row of first type sub-pixels. ​ At least one row of the second type of sub-pixel comprises at least one of the switch transistor, the compensation transistor and the reset transistor, and at least one of the first signal output end, the second signal output end, the third signal output end and the fourth signal output end is electrically connected to a transistor in the corresponding second type of sub-pixel; N is greater than or equal to 2 and is a positive integer, k is greater than or equal to 1 and is less than or equal to N and is a positive integer, and M is greater than or equal to 2 and is a positive integer.

3. The display panel of claim 2, wherein, The load part comprises at least two rows of second type of sub-pixels, the at least two rows of second type of sub-pixels are arranged in a direction away from the first row of first type of sub-pixels and the second row of first type of sub-pixels, the first row of second type of sub-pixels comprises the compensation transistor, and the second row of second type of sub-pixels comprises the switch transistor and the compensation transistor. The first signal output end in the first stage of the first gate drive circuit is electrically connected to the gate of the compensation transistor in the first row of second type of sub-pixels, the second signal output end in the first stage of the first gate drive circuit is electrically connected to the gate of the switch transistor in the second row of second type of sub-pixels, the first signal output end in the second stage of the first gate drive circuit is electrically connected to the gate of the compensation transistor in the second row of second type of sub-pixels.

4. The display panel of claim 3, wherein, The load part comprises at least three rows of second type of sub-pixels, the at least three rows of second type of sub-pixels are arranged in a direction away from the first row of first type of sub-pixels and the second row of first type of sub-pixels, and the third row of second type of sub-pixels comprises the switch transistor and the compensation transistor. The second signal output end in the second stage of the first gate drive circuit is electrically connected to the gate of the switch transistor in the third row of second type of sub-pixels, and the first signal output end in the third stage of the first gate drive circuit is electrically connected to the gate of the compensation transistor in the third row of second type of sub-pixels.

5. The display panel of claim 4, wherein, The load part comprises at least four rows of second type of sub-pixels, the at least four rows of second type of sub-pixels are arranged in a direction away from the first row of first type of sub-pixels and the second row of first type of sub-pixels, and the fourth row of second type of sub-pixels comprises the switch transistor, the compensation transistor and the reset transistor. The second signal output end in the third stage of the first gate drive circuit is electrically connected to the gate of the switch transistor in the fourth row of second type of sub-pixels, the first signal output end in the fourth stage of the first gate drive circuit is electrically connected to the gate of the compensation transistor in the fourth row of second type of sub-pixels, and the second signal output end in the fourth stage of the first gate drive circuit is electrically connected to the gate of the switch transistor in the first row of first type of sub-pixels. The third signal output end in the first stage of the second gate drive circuit is electrically connected to the gate of the reset transistor in the fourth row of second type of sub-pixels, and the third signal output end in the second stage of the second gate drive circuit is electrically connected to the gate of the reset transistor in the first row of first type of sub-pixels.

6. The display panel of claim 5, wherein, The fourth signal output end in the second gate drive circuit of the first stage is electrically connected with the gate of the switch transistor in the second type of sub-pixel of the second row, the fourth signal output end in the second gate drive circuit of the second stage is electrically connected with the gate of the switch transistor in the second type of sub-pixel of the third row, the fourth signal output end in the second gate drive circuit of the third stage is electrically connected with the gate of the switch transistor in the second type of sub-pixel of the fourth row, and the fourth signal output end in the second gate drive circuit of the fourth stage is electrically connected with the gate of the switch transistor in the first type of sub-pixel of the first row.

7. The display panel of claim 6, wherein, At least part of the fourth signal output end in the second gate drive circuit of the first stage to the third stage is electrically connected with the second signal output end in the corresponding first gate drive circuit of the first stage to the third stage.

8. The display panel of claim 6, wherein, Any fourth signal output end in the second gate drive circuit of the first stage to the third stage is disconnected with the second signal output end in the corresponding first gate drive circuit of the first stage to the third stage.

9. The display panel of claim 8, wherein, The number of switch transistors electrically connected with any second signal output end in the first gate drive circuit of the first stage to the third stage is equal to the number of switch transistors electrically connected with the fourth signal output end in the corresponding second gate drive circuit of the first stage to the third stage.

10. The display panel of claim 6, wherein, The number of compensation transistors electrically connected with any first signal output end in the first gate drive circuit of the first stage to the fourth stage is less than or equal to the number of compensation transistors in one row of the second type of sub-pixel.

11. The display panel of claim 6, wherein, The number of reset transistors electrically connected with the third signal output end in the second gate drive circuit of the first stage is less than or equal to the number of reset transistors in one row of the second type of sub-pixel.

12. The display panel of claim 2, wherein, The display panel further comprises a first test signal line, a second test signal line, a third test signal line and a fourth test signal line, the first gate drive unit comprises (M+N+1) first gate drive circuits connected in cascade, the second gate drive unit comprises (M+N+1) second gate drive circuits connected in cascade, the first signal output end in the (M+N+1)th first gate drive circuit is connected with the first test signal line, the second signal output end in the first gate drive circuit is connected with the second test signal line, the third signal output end in the (M+N+1)th second gate drive circuit is connected with the third test signal line, and the fourth signal output end in the (M+N+1)th second gate drive circuit is connected with the fourth test signal line.

13. The display panel of claim 2, wherein, The first electrode of the switch transistor, the first electrode of the compensation transistor and the first electrode of the reset transistor in the second type of sub-pixel are suspended, and the second electrode of the switch transistor, the second electrode of the compensation transistor and the second electrode of the reset transistor in the second type of sub-pixel are suspended.

14. The display panel of claim 1, wherein, In the first direction, the first row of the second type of sub-pixels is located in a different row from the first stage of the first gate driving circuit, and the first stage of the first gate driving unit is located in the same row as the first stage of the second gate driving circuit.

15. The display panel of claim 1, wherein, The number of transistors in the second type of sub-pixels is less than the number of transistors in the first type of sub-pixels, and the number of wires in the second type of sub-pixels is less than the number of wires in the first type of sub-pixels.

16. A display device comprising a display panel, the display panel comprising: a display portion including a plurality of rows of first type of sub-pixels; a load portion disposed on at least one side of the display portion along a first direction, the load portion including a plurality of rows of second type of sub-pixels; a gate driving module including a first gate driving unit and a second gate driving unit disposed on both sides of the display portion along a second direction, the first gate driving unit including a plurality of cascaded first gate driving circuits, and the second gate driving unit including a plurality of cascaded second gate driving circuits, an internal node of a previous stage of the first gate driving circuit being connected to a start signal line of a current stage of the first gate driving circuit, and an internal node of a previous stage of the second gate driving circuit being connected to a start signal line of a current stage of the second gate driving circuit; wherein at least one of the first gate driving circuit and the second gate driving circuit is electrically connected to a transistor in the second type of sub-pixels, and an included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The display portion includes N rows of first type of sub-pixels, at least one of the first type of sub-pixels includes a light emitting device, a driving transistor, a switching transistor, a compensation transistor, and a reset transistor, the driving transistor is configured to generate a driving current to drive the light emitting device to emit light, a first electrode of the switching transistor is configured to receive a data signal, a second electrode of the switching transistor is connected to a first electrode of the driving transistor, a first electrode of the compensation transistor is connected to a second electrode of the driving transistor, a first electrode of the reset transistor is configured to receive a reset signal, and a second electrode of the reset transistor and a second electrode of the compensation transistor are connected to a gate of the driving transistor.

17. The display device of claim 16, wherein, The load portion includes M rows of second type of sub-pixels. The first gate driving unit includes at least (M+N) cascaded first gate driving circuits, and the second gate driving unit includes at least (M+N) cascaded second gate driving circuits, the first gate driving circuit includes a first signal output end and a second signal output end, and the second gate driving circuit includes a third signal output end and a fourth signal output end. ​ The first signal output end in the first gate drive circuit of the (M+k)th stage is electrically connected with the gate of the compensation transistor of the first type of sub-pixel of the kth row, the second signal output end in the first gate drive circuit of the (M+k-1)th stage is electrically connected with the gate of the switch transistor of the first type of sub-pixel of the kth row, the third signal output end in the second gate drive circuit of the (M+k-3)th stage is electrically connected with the gate of the reset transistor of the first type of sub-pixel of the kth row, and the fourth signal output end in the second gate drive circuit of the (M+k-1)th stage is electrically connected with the gate of the switch transistor of the first type of sub-pixel of the kth row. At least one of the switch transistor, the compensation transistor and the reset transistor is included in at least one row of the second type of sub-pixel, and at least one of the first signal output end, the second signal output end, the third signal output end and the fourth signal output end is electrically connected with the transistor in the corresponding second type of sub-pixel. N is greater than or equal to 2 and is a positive integer, k is greater than or equal to 1 and is a positive integer, M is greater than or equal to 2 and is a positive integer.

18. The display device of claim 17, wherein, The load part includes at least two rows of the second type of sub-pixel, the at least two rows of the second type of sub-pixel are arranged in a direction away from the first row of the first type of sub-pixel to the second row of the first type of sub-pixel, the first row of the second type of sub-pixel includes the compensation transistor, and the second row of the second type of sub-pixel includes the switch transistor and the compensation transistor. The first signal output end in the first gate drive circuit of the first stage is electrically connected with the gate of the compensation transistor of the second type of sub-pixel of the first row, and the second signal output end in the first gate drive circuit of the first stage is electrically connected with the gate of the switch transistor of the second type of sub-pixel of the second row.

19. The display device of claim 18, wherein, The load part includes at least three rows of the second type of sub-pixel, the at least three rows of the second type of sub-pixel are arranged in a direction away from the first row of the first type of sub-pixel to the second row of the first type of sub-pixel, and the third row of the second type of sub-pixel includes the switch transistor and the compensation transistor. The second signal output end in the first gate drive circuit of the second stage is electrically connected with the gate of the switch transistor of the second type of sub-pixel of the third row, and the first signal output end in the first gate drive circuit of the third stage is electrically connected with the gate of the compensation transistor of the second type of sub-pixel of the third row.

20. The display device of claim 19, wherein, The load part includes at least four rows of the second type of sub-pixel, the at least four rows of the second type of sub-pixel are arranged in a direction away from the first row of the first type of sub-pixel to the second row of the first type of sub-pixel, and the fourth row of the second type of sub-pixel includes the switch transistor, the compensation transistor and the reset transistor. The second signal output end in the third stage of the first gate drive circuit is electrically connected with the gate of a switch transistor in the fourth row of the second type of sub-pixel, the first signal output end in the fourth stage of the first gate drive circuit is electrically connected with the gate of the compensation transistor in the fourth row of the second type of sub-pixel, and the second signal output end in the fourth stage of the first gate drive circuit is electrically connected with the gate of the switch transistor in the first row of the first type of sub-pixel. The third signal output end in the first stage of the second gate drive circuit is electrically connected with the gate of the reset transistor in the fourth row of the second type of sub-pixel, and the third signal output end in the second stage of the second gate drive circuit is electrically connected with the gate of the reset transistor in the first row of the first type of sub-pixel. The third signal output end in the first stage of the second gate drive circuit is electrically connected with the gate of the reset transistor in the fourth row of the second type of sub-pixel, and the third signal output end in the second stage of the second gate drive circuit is electrically connected with the gate of the reset transistor in the first row of the first type of sub-pixel.

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