3D vertical interconnection packaging structure and preparation method therefor

Abstract

The present invention provides a 3D vertical interconnection packaging structure and a preparation method therefor. Chip electrical connection structures each exposing a metal wiring layer on the side surface are formed, the plurality of chip electrical connection structures are stacked to form a chip stack structure, then a conductive adhesive layer is formed on the side surface of the chip stack structure, and the conductive adhesive layer connects the exposed metal wiring layers and is electrically connected to a substrate. The 3D vertical interconnection packaging structure of the present invention can realize 3D stack packaging without the need for misalignment, so that the packaging area is small, an expensive TSV process is not required, and the cost is low.

Description

3D vertical interconnection packaging structure and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and relates to a 3D vertical interconnection packaging structure and a preparation method thereof. BACKGROUND

[0002] Storage chip packaging is an important link in the semiconductor manufacturing process, which not only protects the chip from physical damage and environmental impact, but also ensures the connection of the chip with external circuits. With the development of technology, storage chip packaging technology is also constantly progressing to meet the needs of higher performance, higher density and smaller size.

[0003] Current storage chip packaging methods can be roughly divided into the following types: 1) wire bonding (Wire bond) packaging, which is a common packaging technology that connects the tiny pads on the storage chip through metal wires. This method is low in price, but the storage chips need to be stacked in staggered positions, and the packaging area is large; 2) through silicon via (TSV) packaging, which is a new interconnection technology applied in high-density three-dimensional packaging, and the interconnection of stacked storage chips is realized through TSV, but this method has high cost.

[0004] Therefore, it is necessary to provide a 3D vertical interconnection packaging structure and a preparation method thereof. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a 3D vertical interconnection packaging structure and a preparation method thereof, which solves the problems of large packaging area and high cost of chip stacking interconnection in the prior art.

[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a preparation method of a 3D vertical interconnection packaging structure, comprising the following steps:

[0007] providing a chip wafer;

[0008] forming a rewiring layer on the first surface of the chip wafer, the rewiring layer comprising a dielectric layer and a metal wiring layer, the metal wiring layer being electrically connected to the chips in the chip wafer;

[0009] forming a passivation protection layer covering the metal wiring layer on the rewiring layer;

[0010] performing a thinning process from the second surface of the chip wafer;

[0011] forming an adhesive film on the second surface of the chip wafer;

[0012] performing a cutting process to form an independently arranged chip electrical connection structure, and the side surface of the chip electrical connection structure exposes the metal wiring layer;

[0013] providing a substrate;

[0014] stacking a plurality of the chip electrical connection structures on the substrate in sequence from bottom to top based on the adhesive film to form a chip stack structure on the substrate;

[0015] forming a conductive adhesive layer on a side of the chip stack structure, the conductive adhesive layer connecting the exposed metal wiring layer, and the conductive adhesive layer being electrically connected to the substrate.

[0016] Optionally, the method of forming the conductive adhesive layer comprises one or a combination of glue coating method or inkjet printing method.

[0017] Optionally, the chip wafer comprises a memory chip wafer.

[0018] Optionally, the passivation layer formed comprises one or a combination of polyimide layer, silicon oxide layer or silicon nitride layer.

[0019] Optionally, the conductive adhesive layer formed is perpendicular to the substrate.

[0020] Optionally, the method of forming the chip electrical connection structures arranged independently comprises one or a combination of mechanical cutting or laser cutting.

[0021] The present application also provides a 3D vertical interconnection packaging structure, the 3D vertical interconnection packaging structure comprising:

[0022] a substrate;

[0023] a chip stack structure, the chip stack structure being located on the substrate and comprising a plurality of chip electrical connection structures stacked in sequence from bottom to top, the chip electrical connection structure comprising an adhesive film, a chip, a rewiring layer and a passivation layer stacked in sequence from bottom to top, the rewiring layer comprising a dielectric layer and a metal wiring layer, the metal wiring layer being electrically connected to the chip, and a side of the chip electrical connection structure exposing the metal wiring layer;

[0024] a conductive adhesive layer, the conductive adhesive layer being located on a side of the chip stack structure, the conductive adhesive layer connecting the exposed metal wiring layer and being electrically connected to the substrate.

[0025] Optionally, the chip comprises a memory chip.

[0026] Optionally, the passivation layer comprises one or a combination of polyimide layer, silicon oxide layer or silicon nitride layer.

[0027] Optionally, the conductive adhesive layer is perpendicular to the substrate.

[0028] As mentioned above, the 3D vertical interconnection packaging structure and the preparation method thereof of the present application form the chip electric connection structure with the side exposed metal wiring layer, and after stacking the chip electric connection structures to form the chip stack structure, the conductive adhesive layer is formed on the side of the chip stack structure to connect the exposed metal wiring layer and the substrate.

[0029] The 3D vertical interconnection packaging structure of the present application does not need to be misaligned to realize 3D stack packaging, so the packaging area is small, and the expensive TSV process is not needed, and the cost is low. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 shows the process flow diagram for preparing the 3D vertical interconnection packaging structure in the embodiment of the present application.

[0031] Figures 2-7 show the structure schematic diagram of each step in the preparation of the 3D vertical interconnection packaging structure in the embodiment of the present application.

[0032] BRIEF DESCRIPTION OF DRAWINGS 100 Chip wafer 200 Re-wiring layer 201 Dielectric layer 202 Metal wiring layer 300 Passivation layer 400 Adhesive film 500 Substrate 600 Conductive adhesive layer 110 Chip electric connection structure 120 Chip stack structure DETAILED DESCRIPTION

[0033] The embodiments of the present application will be described in detail below with specific reference to the drawings. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0034] As in the detailed description of the embodiments of the present application, the cross-sectional view of the device structure will be partially enlarged without the general proportion for the convenience of description, and the schematic diagram is only an example, which should not limit the scope of protection of the present application here. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual production.

[0035] For convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that these spatial relationship words are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. For example, the spatial relationship words can include embodiments in which the first and second features are arranged in direct contact, and embodiments in which other features are arranged between the first and second features such that the first and second features are not in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0036] It should be noted that the diagrams provided in the embodiments are only schematic and that the drawings are not drawn to scale. They are provided merely to illustrate the basic underlying inventive concept, and thus show only those components of the application that are necessary for an understanding of the application, whereas the actual number, shape and size of the components can be different in practice. The components of the drawings can be arranged in a different manner and can have a different shape and size than shown in the drawings.

[0037] As shown in FIG. 1, the embodiment provides a method for preparing a 3D vertical interconnection packaging structure, wherein FIGS. 2-7 schematically show the structure of each step in the preparation of the 3D vertical interconnection packaging structure. The following will introduce the preparation of the 3D vertical interconnection packaging structure in combination with the drawings.

[0038] First, referring to FIG. 2, step S1 is performed to provide a chip wafer 100.

[0039] Specifically, the chip wafer 100 can include, for example, a memory chip wafer, but the type of the chip wafer 100 is not limited to this. The size of the chip wafer 100 can include, for example, 4 inches, 6 inches, 8 inches, 12 inches, etc. The number and size of the chips on the chip wafer 100, the size and type of the chip wafer 100 are not limited herein. In the embodiment, the chip wafer 100 is taken as an example of a memory chip wafer.

[0040] Next, referring to FIG. 3, step S2 is performed to form a re-wiring layer 200 on the first surface of the chip wafer 100, the re-wiring layer 200 including a dielectric layer 201 and a metal wiring layer 202, the metal wiring layer 202 being electrically connected to the chips in the chip wafer 100.

[0041] Specifically, the material of the dielectric layer 201 in the re-wiring layer 200 can include polymers such as polybenzoxazole, polyimide, or inorganic dielectric materials such as silicon nitride, silicon oxide, etc., which are not limited here; the material of the metal wiring layer 202 can include aluminum, copper, tungsten, or their alloys, which are not limited here. The specific structure, material and preparation method of the re-wiring layer 200 are not limited here, and can be referred to the prior art, such as the process of photolithography, etching, electroplating or deposition, etc. to form the re-wiring layer 200.

[0042] One end of the metal wiring layer 202 formed is electrically connected with the chip in the chip wafer 100, and the other end of the metal wiring layer 202 extends outward with the dielectric layer 201 as support.

[0043] Next, referring to FIG. 4, step S3 is performed to form a passivation protective layer 300 covering the metal wiring layer 202 on the re-wiring layer 200.

[0044] Specifically, the passivation protective layer 300 can include one or a combination of polyimide layer, silicon oxide layer or silicon nitride layer to cover the metal wiring layer 202 and provide a flat surface through the passivation protective layer 300 to facilitate subsequent process.

[0045] Next, referring to FIG. 5, step S4 is performed to perform a thinning process from the second surface of the chip wafer 100. The thinning process can include chemical mechanical polishing (CMP), but is not limited to this to thin the chip wafer 100 and reduce the final packaging size.

[0046] Next, referring to FIG. 5, step S5 is performed to form an adhesive film 400 on the second surface of the chip wafer 100.

[0047] Specifically, the adhesive film 400 can use the NCF film commonly used in the semiconductor industry, but the type of the adhesive film 400 is not limited to this.

[0048] Next, referring to FIG. 5, step S6 is performed to perform a cutting process to form an independently arranged chip electrical connection structure 110, and the side surface of the chip electrical connection structure 110 exposes the metal wiring layer 202.

[0049] During the cutting process, one or a combination of mechanical cutting or laser cutting can be used, which can be selected as needed, and is not limited here. As shown in FIG. 5, in this embodiment, based on the film mounting process (Wafer mount), a mechanical cutting method is used for cutting and separating operation, but the cutting method is not limited to this.

[0050] After cutting, the wafer-level structure can be divided into a plurality of independently arranged chip electrical connection structures 110, and one end of the metal wiring layer 202 can be exposed on the side of the chip electrical connection structure 110, thereby facilitating subsequent electrical connection.

[0051] Next, referring to FIG. 6, step S7 is performed to provide a substrate 500.

[0052] Specifically, the substrate 500 can be a PCB substrate with an internal electrical connection layer, and opposite surfaces of the substrate 500 are provided with electrical leads, such as metal pads, for electrical connection, thereby facilitating subsequent electrical connection of the substrate 500 with other devices. The specific type of the substrate 500 is not limited here.

[0053] Next, referring to FIG. 6, step S8 is performed to stack a plurality of the chip electrical connection structures 110 on the substrate 500 in sequence from bottom to top based on the adhesive film 400, so as to form a chip stack structure 120 on the substrate 500.

[0054] Specifically, since the adhesive film 400 is of a sticky material, after a plurality of the chip electrical connection structures 110 are stacked in sequence from bottom to top in the vertical direction, the chip electrical connection structures 110 can be bonded from top to bottom through the adhesive film 400. Preferably, when the chip electrical connection structures 110 are bonded, each of the chip electrical connection structures 110 is aligned and operated from bottom to top, thereby minimizing the packaging area occupied by the chip stack structure 120 formed.

[0055] Next, referring to FIG. 7, step S9 is performed to form a conductive adhesive layer 600 on the side of the chip stack structure 120, the conductive adhesive layer 600 connects the exposed metal wiring layer 202, and the conductive adhesive layer 600 is electrically connected with the substrate 500.

[0056] The method for forming the conductive adhesive layer 600 can include one or a combination of glue coating and inkjet printing. After coating and curing, the conductive adhesive layer 600 can be stably fixed on the side of the chip stack structure 120, and the metal wiring layer 202 in each of the chip electrical connection structures 110 can be interconnected through the conductive adhesive layer 600, and the interconnection between the chip stack structure 120 and the substrate 500 can be achieved.

[0057] Further, the conductive adhesive layer 600 is preferably perpendicular to the substrate 500 to achieve vertical interconnection and shorten the transmission path of electrical signals.

[0058] Referring to FIG. 7, the application further provides a 3D vertical interconnection packaging structure, which comprises:

[0059] A substrate 500;

[0060] A chip stack structure 120 is located on the substrate 500, and includes a plurality of chip electrical connection structures 110 stacked in sequence from bottom to top, the chip electrical connection structure 110 includes an adhesive film 400, a chip, a rewiring layer 200 and a passivation layer 300 stacked in sequence from bottom to top, the rewiring layer 200 includes a dielectric layer 201 and a metal wiring layer 202, the metal wiring layer 202 is electrically connected with the chip, and the side surface of the chip electrical connection structure 110 exposes the metal wiring layer 202;

[0061] A conductive adhesive layer 600 is located on the side surface of the chip stack structure 120, the conductive adhesive layer 600 connects the exposed metal wiring layer 202 and is electrically connected with the substrate 500.

[0062] The 3D vertical interconnection packaging structure of the embodiment can realize 3D stack packaging without misalignment, has small packaging area, and does not need expensive TSV process, and has low cost.

[0063] The preparation method of the 3D vertical interconnection packaging structure can be prepared by the above-mentioned preparation method of the 3D vertical interconnection packaging structure, but is not limited to this, and the 3D vertical interconnection packaging structure is directly prepared by the above-mentioned preparation process, so that the preparation, material and specific structure of the 3D vertical interconnection packaging structure can be referred to the above-mentioned method.

[0064] As an example, the chip can include a storage chip, but is not limited to this.

[0065] As an example, the passivation layer 300 can include one or a combination of a polyimide layer, a silicon oxide layer or a silicon nitride layer, so as to cover the metal wiring layer 202 by the passivation layer 300 and provide a flat surface to facilitate subsequent process.

[0066] As an example, the conductive adhesive layer 600 is perpendicular to the substrate 500 to realize vertical interconnection and shorten the transmission path of the electrical signal.

[0067] In summary, the 3D vertical interconnection packaging structure and the preparation method thereof, the chip electrical connection structure with the side surface exposing the metal wiring layer is formed, and the conductive adhesive layer is formed on the side surface of the chip stack structure after the plurality of chip electrical connection structures are stacked to form the chip stack structure, the exposed metal wiring layer is connected by the conductive adhesive layer and is electrically connected with the substrate.

[0068] The 3D vertical interconnection packaging structure of the present application can realize 3D stack packaging without misalignment, so the packaging area is small, and the expensive TSV process is not needed, and the cost is low.

[0069] The above embodiments only illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a 3D vertical interconnect packaging structure, characterized in that, The method comprises the following steps: providing a chip wafer; forming a rewiring layer on a first surface of the chip wafer, the rewiring layer comprising a dielectric layer and a metal wiring layer, the metal wiring layer being electrically connected to a chip in the chip wafer; forming a passivation layer covering the metal wiring layer on the rewiring layer; performing a thinning process from a second surface of the chip wafer; forming an adhesive film on the second surface of the chip wafer; performing a cutting process to form a chip electrical connection structure arranged independently, and a side surface of the chip electrical connection structure exposing the metal wiring layer; providing a substrate; stacking a plurality of chip electrical connection structures on the substrate from bottom to top based on the adhesive film to form a chip stack structure on the substrate; forming a conductive adhesive layer on a side surface of the chip stack structure, the conductive adhesive layer being connected to the exposed metal wiring layer, and the conductive adhesive layer being electrically connected to the substrate.

2. The method of claim 1, wherein: The method of forming the conductive adhesive layer comprises one or a combination of a glue coating method or an inkjet printing method.

3. The method of claim 1, wherein: The chip wafer comprises a memory chip wafer.

4. The method of claim 1, wherein: The passivation layer formed comprises one or a combination of a polyimide layer, a silicon oxide layer, or a silicon nitride layer.

5. The method of claim 1, wherein: The conductive adhesive layer formed is perpendicular to the substrate.

6. The method of claim 1, wherein: The method of performing the cutting process to form the chip electrical connection structure arranged independently comprises one or a combination of mechanical cutting or laser cutting.

7. A 3D vertical interconnect package structure, characterized by, The 3D vertical interconnection packaging structure comprises: a substrate; a chip stack structure on the substrate, comprising a plurality of chip electrical connection structures stacked from bottom to top, the chip electrical connection structure comprising an adhesive film, a chip, a rewiring layer, and a passivation layer stacked from bottom to top, the rewiring layer comprising a dielectric layer and a metal wiring layer, the metal wiring layer being electrically connected to the chip, and a side surface of the chip electrical connection structure exposing the metal wiring layer; a conductive adhesive layer on a side surface of the chip stack structure, the conductive adhesive layer being connected to the exposed metal wiring layer and being electrically connected to the substrate.

8. The 3D vertical interconnect package structure of claim 7, wherein: The chip comprises a memory chip.

9. The 3D vertical interconnect package structure of claim 7, wherein: The passivation layer comprises one or a combination of a polyimide layer, a silicon oxide layer, or a silicon nitride layer.

10. The 3D vertical interconnect package structure of claim 7, wherein: The conductive adhesive layer is perpendicular to the substrate.

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