Semiconductor device, arithmetic unit, control system for arithmetic unit, and control method for arithmetic unit

Abstract

Provided is a novel semiconductor device. The semiconductor device has a first transistor (Mp1) and a second transistor (Mn1) on the first transistor (Mp1). The second transistor (Mn1) includes an oxide semiconductor in a channel-forming region. The second transistor (Mn1) has a back gate. The gate of the first transistor (Mp1) is electrically connected to the gate of the second transistor (Mn1). A first terminal of the first transistor (Mp1) is electrically connected to a first terminal of the second transistor (Mn1). A second terminal of the first transistor is electrically connected to a first wiring (VLD). A second terminal of the second transistor (Mn1) is electrically connected to a second wiring (VLS). The back gate of the second transistor (Mn1) is electrically connected to a third wiring (BGL). The first wiring (VLD) is supplied with a first potential. The second wiring (VLS) is supplied with a second potential. The third wiring (BGL) is supplied with the second potential in a first mode. The third wiring (BGL) is supplied with a third potential in a second mode. The first potential is higher than the second potential, and the third potential is lower than the second potential.

Description

Semiconductor device, arithmetic device, control system for arithmetic device, and control method for arithmetic device

[0001] One embodiment of the present invention relates to a semiconductor device, an arithmetic device, a control system for the arithmetic device, and a control method for the arithmetic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, and driving methods or manufacturing methods thereof.

[0003] It is known that a transistor including an oxide semiconductor in a channel formation region has an extremely small off-state current. For example, Patent Document 1 discloses a low-power processing unit (e.g., a CPU) that utilizes the low off-state current of the transistor. Furthermore, Patent Document 2 discloses a storage device (e.g., a main memory, a cache memory, etc.) that can store data for a long period of time by utilizing the low off-state current of the transistor.

[0004] Furthermore, for example, Patent Document 3 discloses a technique for increasing the density of an integrated circuit by stacking the transistors.

[0005] JP 2012-257187 A JP 2011-151383 A International Publication No. 2021 / 053473

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with high operation speed.An object of one embodiment of the present invention is to provide a semiconductor device with high reliability.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a method for driving the semiconductor device.An object of one embodiment of the present invention is to provide an arithmetic device including the semiconductor device, a control system for the arithmetic device, or a control method for the arithmetic device.

[0008] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0009] (1) One aspect of the present invention is a semiconductor device including a first transistor and a second transistor over the first transistor, the second transistor including an oxide semiconductor in a channel formation region, the second transistor having a back gate, a gate of the first transistor electrically connected to a gate of the second transistor, a first terminal of the first transistor electrically connected to a first terminal of the second transistor, a second terminal of the first transistor electrically connected to a first wiring, a second terminal of the second transistor electrically connected to a second wiring, and a back gate of the second transistor electrically connected to a third wiring, a first potential is applied to the first wiring, a second potential is applied to the second wiring, a second potential is applied to the third wiring in a first mode, and a third potential is applied to the third wiring in a second mode, the first potential is higher than the second potential, and the third potential is lower than the second potential.

[0010] (2) In the above (1), a fourth potential may be applied to the third wiring in the third mode, and the fourth potential may be higher than the second potential.

[0011] (3) In the above (1) or (2), the first transistor may include silicon in a channel formation region.

[0012] (4) In the above (1) or (2), the first transistor may be a p-channel transistor, and the second transistor may be an n-channel transistor.

[0013] (5) In the above (1) or (2), the oxide semiconductor may contain indium oxide.

[0014] (6) One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a wiring region. The wiring region includes a first conductive layer and a second conductive layer. The wiring region is located over the first transistor and the second transistor. A gate of the first transistor is electrically connected to a gate of the second transistor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor. A second terminal of the first transistor is electrically connected to the first conductive layer. A second terminal of the second transistor is electrically connected to the second conductive layer. A channel formation region of the first transistor is provided in a substrate. A channel formation region of the second transistor is provided in a semiconductor layer over the substrate. The semiconductor layer includes an oxide semiconductor.

[0015] (7) In the above (6), the second transistor may have a back gate, the wiring region may have a third conductive layer, and the back gate may be electrically connected to the third conductive layer.

[0016] (8) In the above (7), a first potential may be applied to the first conductive layer, a second potential may be applied to the second conductive layer, a second potential may be applied to the third conductive layer in the first mode, and a third potential may be applied to the third conductive layer in the second mode, the first potential being higher than the second potential, and the third potential being lower than the second potential.

[0017] (9) In the above (8), a fourth potential may be applied to the third conductive layer in the third mode, and the fourth potential may be higher than the second potential.

[0018] (10) In any one of the above (6) to (9), the substrate may contain silicon.

[0019] (11) In any one of (6) to (9), the first transistor may be a p-channel transistor, and the second transistor may be an n-channel transistor.

[0020] (12) In any one of the above (6) to (9), the oxide semiconductor may contain indium oxide.

[0021] (13) One embodiment of the present invention is an arithmetic device including an arithmetic unit, a control unit, and an acquiring unit. The arithmetic unit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor over the first transistor. The first transistor is a p-channel transistor. The second transistor is an n-channel transistor. The second transistor includes an oxide semiconductor in a channel formation region. The second transistor has a back gate. A gate of the first transistor is electrically connected to a gate of the second transistor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor. A second terminal of the first transistor is electrically connected to a first wiring. A second terminal of the second transistor is electrically connected to a second wiring. A back gate of the second transistor is electrically connected to a third wiring. The acquiring unit has a function of acquiring temperature information. The control unit has a function of applying a potential based on the temperature information to the third wiring.

[0022] (14) In addition, in the above (13), the control unit may have a function of applying a first potential to the third wiring when the temperature indicated by the temperature information is less than a predetermined reference value, and a function of applying a second potential smaller than the first potential to the third wiring when the temperature indicated by the temperature information is equal to or greater than the reference value.

[0023] (15) In the above (13) or (14), the oxide semiconductor may contain indium oxide.

[0024] (16) Another aspect of the present invention is a control system for a computing device, comprising the computing device described in (13) or (14) above and a sensor, wherein the sensor has a function of outputting temperature information based on the temperature of the computing device or the temperature of the environment in which the computing device is installed, and the acquisition unit has a function of acquiring the temperature information from the sensor.

[0025] (17) One embodiment of the present invention is a method for controlling an arithmetic device having a CMOS circuit, the CMOS circuit including a first p-channel transistor and a second n-channel transistor, the second transistor including an oxide semiconductor in a channel formation region, the second transistor having a back gate, and changing a potential applied to the back gate of the second transistor based on temperature information.

[0026] (18) In addition, in the above (17), a first potential may be applied to the back gate of the second transistor when the temperature indicated by the temperature information is less than a predetermined reference value, and a second potential smaller than the first potential may be applied to the back gate of the second transistor when the temperature indicated by the temperature information is equal to or greater than the reference value.

[0027] (19) In the above (17) or (18), the temperature information may be based on the temperature of the computing device or the temperature of the environment in which the computing device is installed.

[0028] According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high operation speed can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a driving method of the semiconductor device can be provided. According to one embodiment of the present invention, an arithmetic device including the semiconductor device, a control system for the arithmetic device, or a control method for the arithmetic device can be provided.

[0029] Note that the above effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0030] FIG. 1A is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 1B is a circuit symbol illustrating an example of the configuration of a semiconductor device. FIG. 1C is a schematic diagram illustrating an example of the configuration of a semiconductor device. FIGS. 2A to 2C are timing charts illustrating an example of the operation of a semiconductor device. FIG. 3A is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 3B is a circuit symbol illustrating an example of the configuration of a semiconductor device. FIG. 3C is a schematic diagram illustrating an example of the configuration of a semiconductor device. FIG. 4A is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 4B is a circuit symbol illustrating an example of the configuration of a semiconductor device. FIG. 4C is a schematic diagram illustrating an example of the configuration of a semiconductor device. FIGS. 5A, 5C, and 5E are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 5B, 5D, and 5F are circuit symbols illustrating an example of the configuration of a semiconductor device. FIGS. 6A and 6C are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIG. 6B is a circuit symbol illustrating an example of the configuration of a semiconductor device. FIG. 7 is a perspective schematic diagram illustrating an example of the configuration of a semiconductor device. FIGS. 8A and 8B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 9A is a top view illustrating an example of the configuration of a semiconductor device. 9B to 9D are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 10 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIGS. 11A to 11C are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 12A is a top view illustrating an example of the configuration of a semiconductor device. FIGS. 12B to 12D are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIGS. 13A and 13B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 13C is a cross-sectional view illustrating an indium oxide film. FIGS. 14A and 14B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIGS. 15A and 15B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIGS. 16A and 16B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIGS. 17A and 17B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIGS. 18A and 18B are block diagrams illustrating an example of a control system for a computing device. FIG. 19 is a flowchart illustrating an example of a control method for a computing device. FIG. 20 is a flowchart illustrating an example of a control method for a computing device. FIG. 21 is a circuit diagram illustrating an example of the configuration of a semiconductor device.FIG. 22 is a diagram showing various types of storage devices by tier. FIG. 23 is a schematic diagram explaining an example of the configuration of a storage device. FIGS. 24A and 24B are diagrams showing an example of electronic components. FIGS. 25A and 25B are diagrams showing an example of electronic equipment. FIGS. 25C to 25E are diagrams showing an example of a mainframe computer. FIG. 26A is a diagram showing an example of space equipment. FIG. 26B is a diagram showing an example of a storage system applicable to a data center. FIGS. 26C and 26D are diagrams showing an example of electronic equipment. FIGS. 27A1 to 27A7 and 27B1 to 27B6 are diagrams explaining electrical connections.

[0031] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include electronic circuits including semiconductor elements, chips equipped with electronic circuits, electronic components with chips housed in packages, and electronic devices equipped with electronic components. Furthermore, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0032] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0033] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0034] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0035] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0036] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0037] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0038] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0039] In this specification and the like, the voltage between the gate and the source (gate-source) (based on the source potential unless otherwise specified) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source potential unless otherwise specified) may be referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source potential unless otherwise specified) may be referred to as the "backgate voltage." Furthermore, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) may be referred to as the "drain current." Note that, in an n-channel transistor, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchangeable with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" in a p-channel transistor, as appropriate. Furthermore, in an n-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage can be interchanged with descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage in a p-channel transistor, as appropriate.

[0040] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may be collectively referred to as leakage current.

[0041] In this specification and the like, one of the source or drain (also referred to as two input / output terminals) of a transistor may be referred to as a first terminal, and the other of the source or drain of the transistor may be referred to as a second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. One terminal of a capacitor (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other terminal of the capacitor (also referred to as the other of the pair of terminals) may be referred to as a second terminal. One terminal of a display element may be referred to as a first terminal, and the other terminal of the display element may be referred to as a second terminal. One terminal of a liquid crystal element may be referred to as a first terminal, and the other terminal of the liquid crystal element may be referred to as a second terminal. One terminal of a light-emitting element may be referred to as a first terminal, and the other terminal of the light-emitting element may be referred to as a second terminal. One terminal of a light-receiving element may be referred to as a first terminal, and the other terminal of the light-receiving element may be referred to as a second terminal. In addition, one of the anode or cathode of the diode (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other of the anode or cathode of the diode (also referred to as the other of the pair of terminals) may be referred to as a second terminal.

[0042] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one embodiment of the present invention can be used in an arithmetic processing unit, a memory device, a control device, a computer, or the like. For example, at least a part of the semiconductor device according to one embodiment of the present invention can be used in a logic circuit included in an arithmetic processing unit, a memory device, a control device, a computer, or the like.

[0043] <Structure Example of Semiconductor Device> As one embodiment of the present invention, a semiconductor device that can be used for a logic circuit will be described.

[0044] 1A to 1C are a circuit diagram, a circuit symbol, and a schematic diagram, respectively, illustrating a semiconductor device 100 of one embodiment of the present invention.

[0045] As shown in FIG. 1A, the semiconductor device 100 includes a transistor Mn1 and a transistor Mp1.

[0046] Here, the transistor Mn1 has two gates (a gate and a back gate) that face each other with a channel formation region therebetween.

[0047] In this specification, one of the gate and the back gate may be referred to as a first gate, and the other may be referred to as a second gate. Also, the terms gate and back gate may be used interchangeably.

[0048] The gate of transistor Mn1 is connected to the gate of transistor Mp1. One of the source or drain of transistor Mn1 is connected to one of the source or drain of transistor Mp1. The gate of transistor Mn1 and the gate of transistor Mp1 are connected to wiring IL. One of the source or drain of transistor Mn1 and one of the source or drain of transistor Mp1 are connected to wiring OL. The back gate of transistor Mn1 is connected to wiring BGL. The other of the source or drain of transistor Mn1 is connected to wiring VLS. The other of the source or drain of transistor Mp1 is connected to wiring VLD.

[0049] In the semiconductor device 100, for example, the transistor Mn1 is an n-channel transistor and the transistor Mp1 is a p-channel transistor. This allows the semiconductor device 100 to have a function of performing a negation operation (also referred to as a NOT operation). Thus, the semiconductor device 100 can be referred to as a negation circuit (also referred to as a NOT circuit).

[0050] As shown in FIG. 1B, the semiconductor device 100 may be represented by a circuit symbol.

[0051] Each of the wirings IL, OL, and BGL functions as, for example, a signal line. For example, a signal output from a circuit (such as another logic circuit) provided outside the semiconductor device 100 is input to an input terminal (here, the gate of the transistor Mn1 and the gate of the transistor Mp1) of the semiconductor device 100 via the wiring IL. Therefore, it can be said that the wiring IL has a function of transmitting a signal input from outside the semiconductor device 100. Furthermore, for example, a signal output from an output terminal (here, the source or drain of the transistor Mn1 and the source or drain of the transistor Mp1) of the semiconductor device 100 is input to a circuit (such as a logic circuit different from the above) provided outside the semiconductor device 100 via the wiring OL. Therefore, it can be said that the wiring OL has a function of transmitting a signal output to outside the semiconductor device 100. Furthermore, for example, a signal (also referred to as a control signal) output from a circuit (such as a control circuit) provided outside the semiconductor device 100 is input to a control terminal (here, the back gate of the transistor Mn1) of the semiconductor device 100 via the wiring BGL. Therefore, it can be said that the wiring BGL has a function of transmitting a control signal input from outside the semiconductor device 100.

[0052] Each of the wiring VLD and the wiring VLS functions as, for example, a power supply line. For example, a high power supply potential (such as a potential H described later) and a low power supply potential (such as a potential L described later) are output from a circuit (such as a power supply circuit) provided outside the semiconductor device 100. The high power supply potential is applied to the other of the source and the drain of the transistor Mp1 via the wiring VLD, and the low power supply potential is applied to the other of the source and the drain of the transistor Mn1 via the wiring VLS. Thus, the wiring VLD can be said to have a function of transmitting a high power supply potential applied from outside the semiconductor device 100, and the wiring VLS can be said to have a function of transmitting a low power supply potential applied from outside the semiconductor device 100.

[0053] Here, the threshold voltage of the transistor Mn1 is shifted depending on the back-gate voltage (potential difference between the back-gate (corresponding to the wiring BGL) and the other of the source and the drain (corresponding to the wiring VLS)). For example, when the back-gate voltage is lower than 0 V, the threshold voltage becomes larger (also referred to as a plus-shift) than when the back-gate voltage is 0 V. Furthermore, when the back-gate voltage is higher than 0 V, the threshold voltage becomes smaller (also referred to as a minus-shift) than when the back-gate voltage is 0 V.

[0054] As a result, for example, by reducing the back-gate voltage of the transistor Mn1 (for example, by reducing the potential applied to the wiring BGL), the off-state current of the transistor Mn1 can be reduced. Therefore, the power consumption of the semiconductor device 100 can be reduced. Furthermore, for example, by increasing the back-gate voltage of the transistor Mn1 (for example, by increasing the potential applied to the wiring BGL), the on-state current of the transistor Mn1 can be increased. Therefore, the operating speed of the semiconductor device 100 can be improved.

[0055] In the semiconductor device 100, the transistor Mn1 may be a p-channel transistor, and the transistor Mp1 may be an n-channel transistor. In this case, descriptions regarding the positive / negative relationship of voltage and the magnitude relationship of potential may be interpreted differently as appropriate. For example, "high potential" and "low potential" may be interpreted differently as appropriate. Furthermore, for example, "increasing potential" and "decreasing potential" may be interpreted differently as appropriate.

[0056] An example of the operation of the semiconductor device 100 will be described later.

[0057] For example, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor included in the semiconductor device 100. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0058] Furthermore, various types of transistors can be used as the transistors that constitute the semiconductor device 100. For example, MOS field effect transistors, junction field effect transistors, bipolar transistors, or the like can be used.

[0059] Transistors of various structures can be used as transistors constituting the semiconductor device 100. For example, transistors of various structures can be used, such as top-gate transistors (e.g., planar transistors and staggered transistors), bottom-gate transistors (e.g., inverted planar transistors and inverted staggered transistors), dual-gate transistors (structures in which gates are arranged on both sides (e.g., above and below) of a channel formation region), FIN transistors, TRI-GATE transistors, and GAA transistors (gate-all-around transistors). Furthermore, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0060] One embodiment of the present invention is a semiconductor device 100 in which an OS transistor (a transistor including an oxide semiconductor in a channel formation region) is used as the transistor Mn1 and a Si transistor (a transistor including silicon in a channel formation region) is used as the transistor Mp1.

[0061] The OS transistor has a characteristic of having an extremely small off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 aA (1×10 −１８A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor, the off-state current per 1 μm of channel width in a room temperature environment can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２ Therefore, it can be said that the off-state current of an OS transistor is smaller than that of a Si transistor by about 10 orders of magnitude.

[0062] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor can operate stably and achieve high reliability even in a high-temperature environment.

[0063] Furthermore, an OS transistor has a high withstand voltage between the source and the drain (also referred to as drain withstand voltage). Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even when driven at high voltage.

[0064] Furthermore, since OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, they can be easily integrated. Furthermore, since OS transistors can be manufactured using the same manufacturing equipment as Si transistors, OS transistors can be manufactured at low cost.

[0065] For example, as shown in FIG. 1C, in the semiconductor device 100, a layer LAY2 in which a transistor Mn1 is provided can be disposed above a layer LAY1 in which a transistor Mp1 is provided.

[0066] Here, various oxide semiconductors can be used for the OS transistor. When an OS transistor is used as the transistor Mn1 included in the semiconductor device 100, an oxide semiconductor that exhibits low off-state current and high on-state current is preferably used. By reducing the off-state current of the transistor Mn1, for example, a current flowing from the wiring VLD to the wiring VLS through the transistors Mp1 and Mn1 in a steady state (also referred to as static current consumption) can be reduced, thereby reducing power consumption. Furthermore, by increasing the on-state current of the transistor Mn1, for example, the fall time of an output signal can be shortened, thereby improving the operating speed. An example of an oxide semiconductor that exhibits low off-state current and high on-state current is indium oxide.

[0067] Note that the oxide semiconductor that can be used for the OS transistor will be described in detail later.

[0068] [Operation Example] Next, the operation of the semiconductor device 100 will be described. The semiconductor device 100 can be operated in various modes depending on the back gate voltage (i.e., corresponding to the potential applied to the wiring BGL) applied to the transistor Mn1. Here, a first mode, a second mode, and a third mode will be described as examples of the operation modes of the semiconductor device 100.

[0069] In the following description of the operation, the potential of a signal applied to the wiring IL is either a potential L (sometimes simply referred to as "L") or a potential H (sometimes simply referred to as "H") that is higher than the potential L. The potential L is a potential that can turn the transistor Mn1 off and the transistor Mp1 on. The potential H is a potential that can turn the transistor Mn1 on and the transistor Mp1 off.

[0070] A potential H is applied to the wiring VLD, and a potential L is applied to the wiring VLS.

[0071] At this time, for example, the potential H can be made to correspond to a logical value of "1", and the potential L can be made to correspond to a logical value of "0".

[0072] In the first mode, the back-gate voltage of the transistor Mn1 is set to 0 V during operation of the semiconductor device 100. That is, in the first mode, the potential applied to the wiring BGL is set to the same as the potential of the wiring VLS. In the second mode, the back-gate voltage of the transistor Mn1 is set to be lower than 0 V during operation of the semiconductor device 100. That is, in the second mode, the potential applied to the wiring BGL is set to be lower than the potential of the wiring VLS. In the third mode, the back-gate voltage of the transistor Mn1 is set to be higher than 0 V during operation of the semiconductor device 100. That is, in the third mode, the potential applied to the wiring BGL is set to be higher than the potential of the wiring VLS.

[0073] In this specification, the first mode may be referred to as a normal mode, the second mode may be referred to as a low-leakage mode, a low-power consumption mode, or a low-noise mode, and the third mode may be referred to as a low-delay mode or a high-speed mode.

[0074] Fig. 2A is a timing chart illustrating an example of operation of the semiconductor device 100 in a first mode (mode 1). Fig. 2B is a timing chart illustrating an example of operation of the semiconductor device 100 in a second mode (mode 2). Fig. 2C is a timing chart illustrating an example of operation of the semiconductor device 100 in a third mode (mode 3).

[0075] 2A to 2C each show the potential of each wiring, and also show the current Icc that flows from the wiring VLD to the wiring VLS through the transistors Mp1 and Mn1.

[0076] 2A to 2C , a signal obtained by inverting the logical value of a signal input from the wiring IL to the semiconductor device 100 is output to the wiring OL from the semiconductor device 100. In this way, the semiconductor device 100 has a function of performing a negation operation.

[0077] In the semiconductor device 100, in a steady state (corresponding to a period in which input and output signals do not change), a current (also referred to as a quiescent current ileak) steadily flows from the wiring VLD to the wiring VLS through the transistors Mp1 and Mn1. At this time, the value of the quiescent current ileak depends on the smaller of the off-state currents of the transistors Mp1 and Mn1. For example, when the off-state current of the transistor Mn1 is smaller than the off-state current of the transistor Mp1, the value of the quiescent current ileak depends on the off-state current of the transistor Mn1.

[0078] Therefore, for example, by reducing the off-state current of the transistor Mn1, the static current consumption i.e.k can be reduced. In other words, for example, when a signal is stopped by clock gating or the like, the static current consumption i.e.k can be reduced. This allows the power consumption of the semiconductor device 100 to be reduced.

[0079] For example, in the second mode shown in FIG. 2B , the potential applied to the wiring BGL is set lower than the potential L (i.e., the back-gate voltage of the transistor Mn1 is set lower than 0 V). This can reduce the off-state current of the transistor Mn1 compared to the first mode shown in FIG. 2A (when the potential applied to the wiring BGL is set to the potential L (i.e., when the back-gate voltage of the transistor Mn1 is set to 0 V)). This can reduce the value of the static current consumption i in the second mode (see FIG. 2B ) compared to the value of the static current consumption i in the first mode (see FIG. 2A ). Therefore, the power consumption of the semiconductor device 100 can be reduced.

[0080] Furthermore, in the semiconductor device 100, in a transient state (corresponding to a period when input and output signals change), a current (also referred to as a shoot-through current ipeak) transiently flows from the wiring VLD to the wiring VLS through the transistors Mp1 and Mn1. At this time, the value of the shoot-through current ipeak depends on the smaller of the on-state currents of the transistors Mp1 and Mn1. For example, when the on-state current of the transistor Mn1 is smaller than the on-state current of the transistor Mp1, the value of the shoot-through current ipeak depends on the on-state current of the transistor Mn1.

[0081] Therefore, for example, by reducing the on-current of the transistor Mn1, the value of the through current ipeak can be reduced.

[0082] Here, the through-current ipeak may affect the operation of other circuits, other devices, other equipment, etc. as conductive noise propagating through the power supply lines (wiring VLD and wiring VLS) and as radiated noise propagating through space. In other words, noise caused by the through-current ipeak may cause malfunctions or destruction of other circuits, other devices, other equipment, etc. Therefore, it is preferable that the value of the through-current ipeak is small. By reducing the value of the through-current ipeak and suppressing the noise caused by the through-current ipeak, it is possible to take measures against electromagnetic interference (EMI) in the semiconductor device 100, for example.

[0083] For example, in the second mode shown in FIG. 2B , the potential applied to the wiring BGL is set to be lower than the potential L (i.e., the back-gate voltage of the transistor Mn1 is set to be lower than 0 V). This can reduce the on-state current of the transistor Mn1 compared to the first mode shown in FIG. 2A (when the potential applied to the wiring BGL is set to the potential L (i.e., when the back-gate voltage of the transistor Mn1 is set to 0 V)). This can reduce the value of the through-current ipeak in the second mode (see FIG. 2B ) compared to the value of the through-current ipeak in the first mode (see FIG. 2A ). This can reduce noise caused by the through-current ipeak and suppress malfunctions and damage to other circuits, devices, and equipment.

[0084] Furthermore, in the semiconductor device 100, it takes time for the signal output to the wiring OL to change in a transient state. The time required for the signal output to the wiring OL to change depends on the on-state currents of the transistors Mp1 and Mn1. For example, the rise time of the signal output to the wiring OL depends on the on-state current of the transistor Mp1. For example, the fall time (also referred to as the fall time t fall ) of the signal output to the wiring OL depends on the on-state current of the transistor Mn1.

[0085] Therefore, for example, by increasing the on-state current of the transistor Mn1, the fall time t fall can be shortened. By shortening the fall time t fall, for example, even if the frequency of a signal input from the wiring IL is increased, a signal whose logical value is inverted from the input signal can be output to the wiring OL. This can improve the operating speed of the semiconductor device 100.

[0086] For example, in the third mode shown in FIG. 2C , the potential applied to the wiring BGL is set to be higher than the potential L (i.e., the back-gate voltage of the transistor Mn1 is set to be higher than 0 V). This allows the on-state current of the transistor Mn1 to be larger than that in the first mode shown in FIG. 2A (when the potential applied to the wiring BGL is set to the potential L (i.e., when the back-gate voltage of the transistor Mn1 is set to 0 V)). This allows the signal fall time tfall in the third mode (see FIG. 2C ) to be shorter than the signal fall time tfall in the first mode (see FIG. 2A ). Therefore, the operating speed of the semiconductor device 100 can be improved.

[0087] In one embodiment of the present invention, the power consumption of the semiconductor device 100 can be reduced by applying a potential to the back gate of the transistor Mn1 in the semiconductor device 100 (corresponding to the second mode).In another embodiment of the present invention, the noise generated from the semiconductor device 100 can be reduced by applying a potential to the back gate of the transistor Mn1 in the semiconductor device 100 (corresponding to the second mode).In another embodiment of the present invention, the operating speed of the semiconductor device 100 can be improved by applying a potential to the back gate of the transistor Mn1 in the semiconductor device 100 (corresponding to the third mode).

[0088] [NAND Circuit (NAND Circuit)] FIGS. 3A to 3C are a circuit diagram, a circuit symbol, and a schematic diagram, respectively, illustrating a semiconductor device 101 of one embodiment of the present invention.

[0089] As shown in FIG. 3A, the semiconductor device 101 includes a transistor Mn1, a transistor Mn2, a transistor Mp1, and a transistor Mp2.

[0090] Here, each of the transistors Mn1 and Mn2 has two gates (a gate and a back gate) that face each other with a channel formation region therebetween.

[0091] The gate of transistor Mn1 is connected to the gate of transistor Mp1. The gate of transistor Mn2 is connected to the gate of transistor Mp2. One of the source or drain of transistor Mn1 is connected to one of the source or drain of transistor Mp1 and one of the source or drain of transistor Mp2. The other of the source or drain of transistor Mn1 is connected to one of the source or drain of transistor Mn2. The gates of transistor Mn1 and transistor Mp1 are connected to wiring IL1. The gates of transistor Mn2 and transistor Mp2 are connected to wiring IL2. One of the source or drain of transistor Mn1, one of the source or drain of transistor Mp1, and one of the source or drain of transistor Mp2 are connected to wiring OL. The back gates of transistor Mn1 and transistor Mn2 are connected to wiring BGL. The other of the source or drain of transistor Mn2 is connected to wiring VLS. The other of the source and the drain of the transistor Mp1 and the other of the source and the drain of the transistor Mp2 are connected to the wiring VLD.

[0092] In the semiconductor device 101, for example, the transistors Mn1 and Mn2 are n-channel transistors, and the transistors Mp1 and Mp2 are p-channel transistors. This allows the semiconductor device 101 to have a function of performing a negative AND operation (also referred to as a NAND operation). Therefore, the semiconductor device 101 can be referred to as a negative AND circuit (also referred to as a NAND circuit).

[0093] As shown in FIG. 3B, the semiconductor device 101 may be represented by a circuit symbol.

[0094] Furthermore, for example, as shown in FIG. 3C, in the semiconductor device 101, a layer LAY2 in which the transistors Mn1 and Mn2 are provided can be disposed on a layer LAY1 in which the transistors Mp1 and Mp2 are provided.

[0095] Note that for the transistors Mn1 and Mn2 included in the semiconductor device 101, the description of the transistor Mn1 included in the semiconductor device 100 can be referred to as appropriate. For the transistors Mp1 and Mp2 included in the semiconductor device 101, the description of the transistor Mp1 included in the semiconductor device 100 can be referred to as appropriate. For the wirings IL1 and IL2, the description of the wiring IL can be referred to as appropriate. For the wiring OL, the description of the wiring OL can be referred to as appropriate. For the wiring BGL, the description of the wiring BGL can be referred to as appropriate. For the wirings VLD and VLS, the description of the wirings VLD and VLS can be referred to as appropriate. For an operation example of the semiconductor device 101, the operation example of the semiconductor device 100 can be referred to as appropriate. Therefore, the description may be omitted here.

[0096] One embodiment of the present invention allows the semiconductor device 101 to operate in various modes as shown in the above-described operation examples. For example, by operating the semiconductor device 101 in the second mode, the power consumption of the semiconductor device 101 can be reduced. Furthermore, by operating the semiconductor device 101 in the second mode, noise generated from the semiconductor device 101 can be reduced. Furthermore, by operating the semiconductor device 101 in the third mode, the operating speed of the semiconductor device 101 can be improved.

[0097] [NOR Circuit (NOR Circuit)] FIGS. 4A to 4C are a circuit diagram, a circuit symbol, and a schematic diagram, respectively, illustrating a semiconductor device 102 of one embodiment of the present invention.

[0098] As shown in FIG. 4A, the semiconductor device 102 includes a transistor Mn1, a transistor Mn2, a transistor Mp1, and a transistor Mp2.

[0099] Here, each of the transistors Mn1 and Mn2 has two gates (a gate and a back gate) that face each other with a channel formation region therebetween.

[0100] The gate of transistor Mn1 is connected to the gate of transistor Mp1. The gate of transistor Mn2 is connected to the gate of transistor Mp2. One of the source or drain of transistor Mn1 is connected to one of the source or drain of transistor Mn2 and one of the source or drain of transistor Mp1. The other of the source or drain of transistor Mp1 is connected to one of the source or drain of transistor Mp2. The gates of transistors Mn1 and Mp1 are connected to wiring IL1. The gates of transistors Mn2 and Mp2 are connected to wiring IL2. One of the source or drain of transistor Mn1, one of the source or drain of transistor Mn2, and one of the source or drain of transistor Mp1 are connected to wiring OL. The back gates of transistors Mn1 and Mn2 are connected to wiring BGL. The other of the source and the drain of the transistor Mn1 and the other of the source and the drain of the transistor Mn2 are connected to a wiring VLS. The other of the source and the drain of the transistor Mp2 is connected to a wiring VLD.

[0101] In the semiconductor device 102, for example, the transistors Mn1 and Mn2 are n-channel transistors, and the transistors Mp1 and Mp2 are p-channel transistors. This allows the semiconductor device 102 to have a function of performing a negative OR operation (also referred to as a NOR operation). Therefore, the semiconductor device 102 can be referred to as a negative OR circuit (also referred to as a NOR circuit).

[0102] As shown in FIG. 4B, the semiconductor device 102 may be represented by a circuit symbol.

[0103] Furthermore, for example, as shown in FIG. 4C, in the semiconductor device 102, a layer LAY2 in which the transistors Mn1 and Mn2 are provided can be disposed on a layer LAY1 in which the transistors Mp1 and Mp2 are provided.

[0104] Note that for the transistors Mn1 and Mn2 included in the semiconductor device 102, the description of the transistor Mn1 included in the semiconductor device 100 can be referred to as appropriate. For the transistors Mp1 and Mp2 included in the semiconductor device 102, the description of the transistor Mp1 included in the semiconductor device 100 can be referred to as appropriate. For the wirings IL1 and IL2, the description of the wiring IL can be referred to as appropriate. For the wiring OL, the description of the wiring OL can be referred to as appropriate. For the wiring BGL, the description of the wiring BGL can be referred to as appropriate. For the wirings VLD and VLS, the description of the wirings VLD and VLS can be referred to as appropriate. For an operation example of the semiconductor device 102, the operation example of the semiconductor device 100 can be referred to as appropriate. Therefore, the description may be omitted here.

[0105] One embodiment of the present invention allows the semiconductor device 102 to operate in various modes as shown in the above-described operation examples. For example, by operating the semiconductor device 102 in the second mode, the power consumption of the semiconductor device 102 can be reduced. Furthermore, by operating the semiconductor device 102 in the second mode, noise generated from the semiconductor device 102 can be reduced. Furthermore, by operating the semiconductor device 102 in the third mode, the operating speed of the semiconductor device 102 can be improved.

[0106] [Other Logic Circuits] In one embodiment of the present invention, at least part of the semiconductor device 100 (corresponding to a NOT circuit), the semiconductor device 101 (corresponding to a NAND circuit), and the semiconductor device 102 (corresponding to a NOR circuit) described above can be applied to various logic circuits. For example, the semiconductor device 101 can be applied to a NAND circuit having three or more inputs. Furthermore, for example, the semiconductor device 102 can be applied to a NOR circuit having three or more inputs. Furthermore, for example, at least part of the semiconductor device 100, the semiconductor device 101, and the semiconductor device 102 described above can be applied to various logic circuits such as a logical AND circuit (also referred to as an AND circuit), a logical OR circuit (also referred to as an OR circuit), an exclusive OR circuit (also referred to as an XOR circuit), an exclusive NOR circuit (also referred to as an XNOR circuit), an analog switch, and a clocked inverter.

[0107] 5A is a circuit diagram illustrating an example of a logical product circuit of one embodiment of the present invention. The semiconductor device 103 capable of performing a logical product operation includes, for example, one NAND circuit (corresponding to the semiconductor device 101) and one NOT circuit (corresponding to the semiconductor device 100). Note that the semiconductor device 103 may be represented by a circuit symbol as shown in FIG. 5B.

[0108] 5C is a circuit diagram illustrating an example of an OR circuit of one embodiment of the present invention. The semiconductor device 104 capable of performing an OR operation includes, for example, one NOR circuit (corresponding to the semiconductor device 102) and one NOT circuit (corresponding to the semiconductor device 100). Note that the semiconductor device 104 may be represented by a circuit symbol, as shown in FIG.

[0109] 5E is a circuit diagram illustrating an example of a clocked inverter according to one embodiment of the present invention. The semiconductor device 105 that can function as a clocked inverter includes, in addition to the semiconductor device 100 described above, a transistor Mn2 between the transistor Mn1 and a wiring VLS and a transistor Mp2 between the transistor Mp1 and a wiring VLD. The other of the source or the drain of the transistor Mn1 is connected to one of the source or the drain of the transistor Mn2. The other of the source or the drain of the transistor Mn2 is connected to the wiring VLS. The other of the source or the drain of the transistor Mp1 is connected to one of the source or the drain of the transistor Mp2. The other of the source or the drain of the transistor Mp2 is connected to the wiring VLD. The gate of the transistor Mn1 is connected to the wiring CLA. The gate of the transistor Mp2 is connected to the wiring CLB.

[0110] The semiconductor device 105 can have a function of performing a negation operation by, for example, applying a potential that turns on the transistor Mn2 and the transistor Mp2 to the wiring CLA and the wiring CLB. The semiconductor device 105 can also have a function of setting the output to high impedance by, for example, applying a potential that turns off the transistor Mn2 and the transistor Mp2 to the wiring CLA and the wiring CLB. Note that the semiconductor device 105 may be represented by a circuit symbol, as shown in FIG. 5F.

[0111] In addition, according to one embodiment of the present invention, by using various logic circuits such as the above-described semiconductor device 100, the semiconductor device 101, the semiconductor device 102, the semiconductor device 103, the semiconductor device 104, and the semiconductor device 105, various logic circuits such as a latch, a flip-flop, a register, a shift register, and a counter can be realized.

[0112] 6A is a circuit diagram illustrating an example of a flip-flop of one embodiment of the present invention. The semiconductor device 110 that can function as a flip-flop includes, for example, four NOT circuits (corresponding to the semiconductor device 100) and four clocked inverters (corresponding to the semiconductor device 105). An input terminal of the semiconductor device 110 is connected to a wiring DL. An output terminal of the semiconductor device 110 is connected to a wiring QL. A clock terminal of the semiconductor device 110 is connected to a wiring CKL.

[0113] The semiconductor device 110 can function as, for example, a positive edge triggered D flip-flop. That is, for example, the semiconductor device 110 can have a function of holding the state of a signal input from a wiring DL and changing the signal output to a wiring OL at the rising edge of a signal applied to a wiring CKL. Note that the semiconductor device 110 may be represented by a circuit symbol as shown in FIG. 6B .

[0114] 6C is a circuit diagram illustrating an example of a shift register of one embodiment of the present invention. The semiconductor device 111 that can function as a shift register includes, for example, a plurality of (e.g., four) flip-flops (corresponding to the semiconductor device 110) and one NOT circuit (corresponding to the semiconductor device 100). An input terminal of the semiconductor device 111 is connected to a wiring SPL. A plurality of output terminals of the semiconductor device 111 are connected to a plurality of wirings OL (e.g., wirings OL[1] to OL[4]), respectively. A clock terminal of the semiconductor device 111 is connected to a wiring CKL.

[0115] The semiconductor device 111 can have a function of sequentially outputting a signal input from the wiring SPL to each of the wirings OL[1] to OL[4] at both the rising and falling timings of a signal applied to the wiring CKL, for example.

[0116] According to one embodiment of the present invention, the logic circuit can be operated in various modes as shown in the above-described operation examples. For example, by operating the logic circuit in the second mode, the power consumption of the logic circuit can be reduced. Furthermore, by operating the logic circuit in the second mode, the noise generated from the logic circuit can be reduced. Furthermore, by operating the logic circuit in the third mode, the operating speed of the logic circuit can be improved.

[0117] Another embodiment of the present invention is an arithmetic processing unit using any of the above-described logic circuits such as the semiconductor device 100, the semiconductor device 101, the semiconductor device 102, the semiconductor device 103, the semiconductor device 104, and the semiconductor device 105. Another embodiment of the present invention is a memory device using any of the above-described logic circuits such as the semiconductor device 100, the semiconductor device 101, the semiconductor device 102, the semiconductor device 103, the semiconductor device 104, and the semiconductor device 105. Another embodiment of the present invention is a control device using any of the above-described logic circuits such as the semiconductor device 100, the semiconductor device 101, the semiconductor device 102, the semiconductor device 103, the semiconductor device 104, and the semiconductor device 105. Another embodiment of the present invention is an electronic computer using any of the above-described logic circuits such as the semiconductor device 100, the semiconductor device 101, the semiconductor device 102, the semiconductor device 103, the semiconductor device 104, and the semiconductor device 105.

[0118] In one embodiment of the present invention, by using the logic circuit in a processor, a storage device, a control device, a computer, or the like, the logic circuit can be operated in various modes as shown in the above-described operation examples. For example, by operating the logic circuit in the second mode, power consumption of the processor, the storage device, the control device, the computer, or the like using the logic circuit can be reduced. Furthermore, by operating the logic circuit in the second mode, noise generated from the processor, the storage device, the control device, the computer, or the like using the logic circuit can be reduced. Furthermore, by operating the logic circuit in the third mode, the operating speed of the processor, the storage device, the control device, the computer, or the like using the logic circuit can be improved.

[0119] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0120] Embodiment 2 In this embodiment, a structural example of a transistor that can be used in the semiconductor device described in the above embodiment will be described.

[0121] <Structure Example of Semiconductor Device> For the semiconductor device of one embodiment of the present invention, transistors with various structures can be used. In addition, a structure in which transistors with various structures are stacked can be used.

[0122] FIG. 7 is a schematic perspective view of a semiconductor device 100A including a transistor 310 and a transistor 200. Note that some elements, such as insulating layers, are omitted from FIG. 7. FIGS. 8A and 8B are cross-sectional views of the semiconductor device 100A. Note that FIG. 8A illustrates a cross-sectional view of the transistor 310 and the transistor 200 in the channel length direction (illustrated as the X direction). FIG. 8B illustrates a cross-sectional view of the transistor 310 and the transistor 200 in the channel width direction (illustrated as the Y direction).

[0123] As shown in FIGS. 7, 8A, and 8B, the transistor 200 is provided above the transistor 310 (illustrated as the Z direction).

[0124] Here, the semiconductor device 100A corresponds to the semiconductor device 100 described in the above-described embodiment 1. Therefore, the transistor 310 corresponds to the transistor Mp1, and the transistor 200 corresponds to the transistor Mn1.

[0125] As shown in FIG. 8A , one of the source and drain of the transistor 310 (corresponding to the low-resistance region 314b here) is connected to one of the source and drain of the transistor 200 (corresponding to the conductive layer 242b here) through a conductive layer 328b, a conductive layer 330b, a conductive layer 356b, a conductive layer 218b, a conductive layer 246b, a conductive layer 248b, a conductive layer 243b, or the like. These conductive layers have a region functioning as a wiring OL. The other of the source and drain of the transistor 310 (corresponding to the low-resistance region 314a here) is connected to a conductive layer 330a through a conductive layer 328a or the like. These conductive layers have a region functioning as a wiring VLD. The other of the source and drain of the transistor 200 (corresponding to the conductive layer 242a here) is connected to a conductive layer 248a through a conductive layer 243a or the like. These conductive layers have a region functioning as a wiring VLS. 8B , the gate electrode of the transistor 310 (corresponding to the conductive layer 316 here) is connected to the gate electrode of the transistor 200 (corresponding to the conductive layer 205 here) through a conductive layer 328c, a conductive layer 330c, a conductive layer 356c, and the like. These conductive layers have a region that functions as a wiring IL. The back gate electrode of the transistor (corresponding to the conductive layer 260 here) has a region that functions as a wiring BGL.

[0126] The conductive layer may be formed of a conductor having a function as a plug or wiring.

[0127] In this specification and the like, a conductor that functions as a plug or wiring may have multiple components collectively assigned the same reference symbol. The wiring and the plug may be integrated. That is, a portion of the conductor may function as a wiring and a portion of the conductor may function as a plug.

[0128] For each plug or wiring, a conductive material such as a metal material, an alloy material, a nitride material, or an oxide material can be used in a single layer or a laminated layer.

[0129] In particular, it is preferable to use a high-melting-point material that has both heat resistance and conductivity for each plug or wiring. Examples of such materials include tungsten and molybdenum. It is also preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. Examples of such materials include aluminum and copper.

[0130] [Transistor 310] The transistor 310 will be described.

[0131] As shown in Figures 8A and 8B, the transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315 functioning as a gate insulating film, a semiconductor region 313 functioning as a channel formation region, a low-resistance region 314a functioning as one of the source region and the drain region, and a low-resistance region 314b functioning as the other of the source region and the drain region.

[0132] The transistor 310 also has an element isolation layer 318 buried in the substrate 311. The element isolation layer 318 is provided between two adjacent transistors 310.

[0133] The substrate 311 may be, for example, a semiconductor substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Other examples include a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Other examples include a substrate in which a semiconductor is provided on an insulator substrate, or a substrate in which a semiconductor is provided on a conductor substrate. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0134] In this embodiment, a case where a single crystal silicon substrate is used as the substrate 311 will be described as an example.

[0135] The transistor 310 may be either a p-channel type or an n-channel type. For example, by connecting the gate of an n-channel transistor 310 and the gate of a p-channel transistor 310, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0136] Here, for example, when the semiconductor device 100A is applied to the semiconductor device 100 described in the first embodiment, the transistor 310 can be a p-channel transistor.

[0137] 8B , the transistor 310 can have a so-called Fin structure in which the top surface and the side surfaces in the channel width direction of a semiconductor region 313 made of a part of a substrate 311 are covered with a conductive layer 316 via an insulating layer 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 310. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 310.

[0138] The transistor 310 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby the region, the low-resistance region 314a that serves as one of the source and drain regions, and the low-resistance region 314b that serves as the other of the source and drain regions. Alternatively, the transistor 310 may be formed of a material containing, for example, germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 310 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing. Alternatively, the transistor 310 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide, gallium aluminum arsenide, or the like.

[0139] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0140] For example, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used as the conductive layer 316. Alternatively, for example, a conductive material such as a metal material, an alloy material, or an oxide material can be used.

[0141] Note that the work function is determined by the material of a conductor; therefore, the threshold voltage of a transistor can be adjusted by selecting the material of the conductor.

[0142] For example, a material such as titanium nitride or tantalum nitride is preferably used as the conductive layer 316. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a stack of metal materials such as tungsten or aluminum. In particular, in terms of heat resistance, it is preferable to use a stack of tungsten, for example.

[0143] An insulating layer 320 , an insulating layer 322 , an insulating layer 324 , and an insulating layer 326 are stacked in this order to cover the transistor 310 .

[0144] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride is preferably used for the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. In particular, silicon oxide or silicon oxynitride is preferably used because of its thermal stability.

[0145] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0146] The insulating layer 322 may function as a planarizing film that planarizes steps caused by the transistor 310 or the like provided thereunder. For example, the top surface of the insulating layer 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0147] As the insulating layer 324, it is preferable to use an insulator having barrier properties that prevent impurities such as hydrogen from diffusing from the substrate 311 or the transistor 310, which are located below the insulating layer 324, to a region located above the insulating layer 324.

[0148] The insulator having a barrier property against hydrogen can be, for example, silicon nitride formed by chemical vapor deposition (CVD), or a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0149] Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor, such as the transistor 200 described later, the characteristics of the semiconductor element may deteriorate. Therefore, an insulator that suppresses hydrogen diffusion is preferably used between a region where the transistor 200 is provided and a region where the transistor 310 is provided. Specifically, the insulator that suppresses hydrogen diffusion is an insulator that releases a small amount of hydrogen.

[0150] The insulating layer 326 preferably has a lower dielectric constant than the insulating layer 324. For example, the relative dielectric constant of the insulating layer 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 324. By using a material with a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings.

[0151] Conductive layers 328 (such as conductive layers 328a, 328b, and 328c) are embedded in the insulating layers 320 and 322. Conductive layers 330 (such as conductive layers 330a, 330b, and 330c) are embedded in the insulating layers 324 and 326.

[0152] Each of the conductive layer 328 and the conductive layer 330 functions as a plug or a wiring.

[0153] 8A and 8B , an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. In addition, a conductive layer 356 (conductive layer 356b, conductive layer 356c, etc.) is embedded in the insulating layer 350, the insulating layer 352, and the insulating layer 354.

[0154] The conductive layer 356 functions as a plug or a wiring. For example, the same material as the conductive layer 328 and the conductive layer 330 can be used for the conductive layer 356. In particular, it is preferable to use a conductor having a barrier property against hydrogen.

[0155] The insulating layers 350, 352, and 354 can be formed using materials similar to those of the insulating layers 324, 322, and 326. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0156] Here, a conductor having a barrier property against hydrogen is formed in the opening of the insulating layer 350 having a barrier property against hydrogen. With this structure, the transistor 310 and the transistor 200 can be separated by the conductor having a barrier property against hydrogen. Therefore, diffusion of hydrogen from the transistor 310 to the transistor 200 can be suppressed.

[0157] For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Alternatively, a stack of tantalum nitride and highly conductive tungsten may be used. By using a stack of tantalum nitride and tungsten as the conductor, the conductor can suppress the diffusion of hydrogen while maintaining the conductivity of the wiring.

[0158] That is, by forming the conductive layer 356 as a stack of tantalum nitride and tungsten, diffusion of hydrogen from the transistor 310 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer of the conductive layer 356 having a barrier property against hydrogen be in contact with the insulating layer 350 having a barrier property against hydrogen.

[0159] Although the wiring layer including the conductive layer 356 has been described here, the present invention is not limited to this. The wiring layer including the conductive layer 356 does not necessarily have to be provided, or two or more wiring layers similar to the wiring layer including the conductive layer 356 may be provided.

[0160] Note that the transistor 310 illustrated in FIGS. 8A and 8B is an example and is not limited to this configuration.

[0161] An insulating layer 212, an insulating layer 214, and an insulating layer 216 are stacked in this order over the insulating layer 354 and the conductive layer 356. The transistor 200 is provided over the insulating layer 216. An insulating layer 275, an insulating layer 280, an insulating layer 282, an insulating layer 283, and an insulating layer 285 are stacked in this order to cover the transistor 200.

[0162] In the insulating layer 212, the insulating layer 214, and the insulating layer 216, for example, a conductive layer 218 (such as the conductive layer 218b) is embedded.

[0163] The conductive layer 218 functions as a plug or a wiring. For the conductive layer 218, for example, the same materials as those of the conductive layer 328 and the conductive layer 330 can be used.

[0164] In particular, the conductive layer 218 and a region in contact with the insulating layer 214 are preferably made of a conductor that has a barrier property against both oxygen and impurities such as hydrogen and water. With such a structure, the transistor 310 and the transistor 200 can be separated by a conductor that has a barrier property against both oxygen and impurities such as hydrogen and water, and diffusion of hydrogen from the transistor 310 to the transistor 200 can be suppressed.

[0165] An insulating layer 288 is provided on the insulating layer 285 .

[0166] The parasitic capacitance generated between wirings can be reduced by using, for example, a material with a relatively low dielectric constant as the insulating layer 288. For example, the same material as the insulating layer 212 or the insulating layer 216 can be used as the insulating layer 288.

[0167] For example, conductive layers 246 (such as conductive layer 246b) are embedded in insulating layers 275, 280, 282, 283, and 285. Furthermore, for example, conductive layers 248 (such as conductive layers 248a and 248b) are embedded in insulating layer 288.

[0168] Each of the conductive layers 246 and 248 functions as a plug or a wiring.

[0169] [Transistor 200] A configuration example of the transistor 200 will be described with reference to FIGS. 9A to 12D.

[0170] 9A is a top view of the transistor 200. FIG. 9B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 9A , and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 9C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 9A , and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 9D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 9A . Note that some elements are omitted in the top view of FIG. 9A for clarity. Some elements may also be omitted in the subsequent top views.

[0171] The transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a layer 229 on the insulating layer 224, a semiconductor layer 230 covering the layer 229, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0172] In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating film. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating film. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0173] Here, for example, when the semiconductor device 100A is applied to the semiconductor device 100 shown in the above-mentioned first embodiment, the first gate electrode of the transistor 200 can be used as the back gate of the transistor Mn1, and the second gate electrode of the transistor 200 can be used as the gate of the transistor Mn1.

[0174] An insulating layer 275 is provided over the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 reaching the insulating layer 222 and the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275, and the opening 289 overlaps with a region between the conductive layer 242a and the conductive layer 242b. In a top view, a side surface of the insulating layer 280 in the opening 289 coincides with a side surface of the conductive layer 242a and a side surface of the conductive layer 242b.

[0175] The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the top end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided over the insulating layer 282. An insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0176] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243a and 241a are provided in the openings. The insulating layer 241a is provided in contact with the inner wall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243b and 241b are provided in the openings. The insulating layer 241b is provided in contact with the inner wall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided on the transistor 200 to the source or drain of the transistor 200.

[0177] In the semiconductor layer 230, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed, as in the transistor 200. That is, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0178] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in a semiconductor layer 230 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 includes a metal oxide, the semiconductor layer 230 can be referred to as a metal oxide layer.

[0179] An OS transistor has an oxygen vacancy (V Ｏ The presence of oxygen vacancies and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region is made i-type (intrinsic) or substantially i-type.

[0180] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0181] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced. Since an OS transistor has a small off-state current, the power consumption of a semiconductor device can be sufficiently reduced.

[0182] Here, when an excessive amount of oxygen is supplied to the channel formation region of the semiconductor layer 230, electron traps due to the excess oxygen are formed in the insulating layer 250. As a result, the OS transistor is more likely to experience positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0183] Therefore, in one embodiment of the present invention, the impurity concentration in the channel formation region of the semiconductor layer 230 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the channel formation region of the semiconductor layer 230. Furthermore, it is preferable to reduce the excessive amount of oxygen in the channel formation region of the semiconductor layer 230.

[0184] The semiconductor layer 230 preferably includes indium oxide. In this case, the semiconductor layer 230 includes indium and oxygen. For example, the semiconductor layer 230 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide (also referred to as the indium (In) content), the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor can have a large on-state current and high frequency characteristics.

[0185] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. In polycrystalline films, crystal grain boundaries are observed.

[0186] When a metal oxide contains indium and zinc, the metal oxide may have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0187] In a crystalline oxide semiconductor layer, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film that is highly permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film that has a lower barrier property against one or both of hydrogen and oxygen than, for example, an IGZO film.

[0188] 9A to 9D show an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can have a stacked structure of two or more layers. For example, when the semiconductor layer 230 has a two-layer structure of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 230 described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path. That is, the first semiconductor layer has a channel formation region on the surface on the second semiconductor layer side and in the vicinity thereof.

[0189] The above-described structure can reduce carriers trapped at the interface of the first semiconductor layer and its vicinity. In addition, the channel can be located away from the surface of the insulating layer 250, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0190] Examples of metal oxides that can be used for the second semiconductor layer include indium gallium oxide (In—Ga oxide), In—Zn oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0191] Specifically, the In-Zn oxide used in the second semiconductor layer can have a composition of In:Zn = 1:1 [atomic ratio] or thereabouts, In:Zn = 2:1 [atomic ratio] or thereabouts, or In:Zn = 4:1 [atomic ratio] or thereabouts. Furthermore, the IGZO used in the second semiconductor layer can have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or thereabouts, In:Ga:Zn = 1:3:2 [atomic ratio] or thereabouts, or In:Ga:Zn = 1:3:4 [atomic ratio] or thereabouts. Note that a composition in the vicinity includes a range of plus or minus 30% of the desired atomic ratio.

[0192] The crystallinity of the metal oxide included in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0193] The layer 229 has crystals. The layer 229 functions as a seed or a nucleus when a process for increasing the crystallinity of the semiconductor layer 230 is performed. In other words, the layer 229 functions as a seed or a nucleus when crystals of the semiconductor layer 230 grow. In this specification and the like, the layer 229 or the crystals of the layer 229 can be referred to as a seed crystal or a crystal nucleus. Furthermore, since the layer 229 has crystals, the layer 229 can be referred to as a crystalline portion.

[0194] Here, the crystals of indium oxide have a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the layer 229 preferably has, for example, a hexagonal or trigonal crystal structure. In this case, the layer 229 has crystals whose crystal orientation with respect to the surface or the surface where the layer 229 is to be formed is <001>, so that the semiconductor layer 230 can be formed having crystals whose crystal orientation is <111>. When the crystals of the layer 229 have a <001> crystal orientation with respect to the surface or the surface where the layer 229 is to be formed, the c-axis of the crystals is perpendicular to the surface or the surface where the layer 229 is to be formed. Note that a crystal with a hexagonal or trigonal crystal structure can sometimes be referred to as a crystal with a layered structure. Therefore, the above structure can be regarded as a structure in which the semiconductor layer 230 having crystals with a cubic crystal structure is formed on the layer 229 having crystals with a layered structure. That is, it can be thought of as a layered structure fabricated using heteroepitaxial growth techniques or heteroepitaxial growth-like techniques.

[0195] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0196] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a film containing the crystal or the surface on which the crystal is formed. For example, a crystal with a crystal orientation of <100> is said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is formed.

[0197] Specifically, zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide can be used for the layer 229. It is preferable to use In—Ga—Zn oxide for the layer 229. In this case, the layer 229 contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to use a composition in which the atomic ratio of In:Ga:Zn is 1:1:1 or thereabouts, or a composition in which the atomic ratio of In:Ga:Zn is 1:3:2 or thereabouts. Metal oxides with these compositions are suitable for the layer 229 because they easily form a layered structure.

[0198] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like are likely to have a CAAC structure. When an oxide having a CAAC structure is used for the layer 229, the c-axis of the crystal nuclei is perpendicular to the surface of the layer 229 or a surface on which the layer 229 is formed. In other words, by using an oxide that is likely to have a CAAC structure for the layer 229, it is possible to improve the controllability of the crystal orientation of the crystal nuclei.

[0199] When an oxide that easily has a CAAC structure is used for the layer 229, the semiconductor layer 230 can be formed having crystals with a <111> crystal orientation.

[0200] The layer 229 can also be made of an oxide having a cubic crystal structure. When the crystal of the layer 229 has the same crystal structure as the crystal of the semiconductor layer 230, the semiconductor layer 230 can be epitaxially grown using the layer 229 as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. Note that crystals of oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, the Group 3 elements in the crystals are primarily present as trivalent cations. Therefore, the layer 229 preferably contains at least one element that can become a trivalent cation. The element that can become a trivalent cation contained in the layer 229 is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0201] For example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. can be used for the layer 229. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0202] Alternatively, indium oxide may be used for the layer 229. By using indium oxide for the layer 229, the semiconductor layer 230 can be homoepitaxially grown using the layer 229 as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystals in the layer 229 and the crystal orientation of the crystals in the semiconductor layer 230 coincide with each other.

[0203] There is no particular limitation on the material that can be used for the layer 229. An insulating material, a semiconductor material, or a conductive material may be used for the layer 229. When a semiconductor material is used for the layer 229, the layer 229 may be considered as part of the semiconductor layer 230.

[0204] 9A shows an example in which the layer 229 has a circular shape when viewed from above. Note that one embodiment of the present invention is not limited to this. When viewed from above, the layer 229 can have, for example, a substantially circular shape such as a circular or elliptical shape, a polygonal shape such as a triangular shape, a quadrilateral shape (including a rectangular shape, a rhombic shape, and a square shape), a pentagonal shape, or a star-shaped polygonal shape, or a polygonal shape with rounded corners. When sputtered particles are used for the layer 229, the layer 229 can have a triangular or hexagonal shape when viewed from above.

[0205] The layer 229 may have a tapered shape. For example, the angle between the top surface of the insulating layer 224 and the side surface of the layer 229 may be less than 90°, preferably 30° or more and less than 90°. By tapering the layer 229, the coverage of the semiconductor layer 230 can be improved and defects such as voids can be reduced. Furthermore, crystal growth of the semiconductor layer 230 can be promoted.

[0206] 9A and 9B show an example in which an island-shaped layer 229 is provided. Note that one embodiment of the present invention is not limited to this. For example, the layer 229 may have a region extending along the top surface of the insulating layer 224.

[0207] 9B shows an example in which the layer 229 is provided in contact with the top surface of the insulating layer 224. Note that one embodiment of the present invention is not limited to this. For example, the layer 229 may be provided so as to fill a recessed portion provided in the insulating layer 224. This can flatten the top surface of the insulating layer 224 and improve the crystallinity of the semiconductor layer 230. Note that the recessed portion may be an opening that penetrates the insulating layer 224. The layer 229 filled in the recessed portion may have an extending region.

[0208] The thickness of the layer 229 is preferably thin. For example, the thickness of the layer 229 is preferably thinner than the thickness of the semiconductor layer 230. Specifically, the layer 229 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm. By reducing the thickness of the layer 229, the step generated between the layer 229 and the insulating layer 224 is reduced. Therefore, the coverage of the semiconductor layer 230 is improved, and defects such as voids can be reduced. Furthermore, crystal growth of the semiconductor layer 230 can be promoted. The layer 229 may be in a layered or granular form.

[0209] 9A to 9D, the opening where the conductive layer 243a is provided is provided so as to overlap with the layer 229. With this structure, miniaturization and high integration of the transistor can be achieved.

[0210] 9A to 9D . For example, an opening where the conductive layer 243a is provided may be provided so as not to overlap with the layer 229. In this case, for example, the layer 229 may be located on a line connecting the conductive layers 243a and 243b and may be located between the layer 229 and the conductive layer 260 in a top view. Alternatively, for example, the layer 229 may not be located on a line connecting the conductive layers 243a and 243b. Such a structure can improve the shape of the opening. Therefore, contact defects can be suppressed, and a highly reliable transistor can be provided.

[0211] Although not shown, the transistor 200 may not include, for example, the layer 229. For example, the layer 229 may be provided outside the transistor formation region, and the layer 229 may be removed after treatment to increase the crystallinity of the semiconductor layer 230 is performed.

[0212] 10 to 11C are enlarged cross-sectional views of the transistor 200 shown in FIGS. 9A to 9D in the channel length direction.

[0213] By providing an insulating layer containing excess oxygen near the oxide semiconductor layer and performing heat treatment, oxygen can be supplied from the insulating layer to the oxide semiconductor layer, thereby reducing oxygen vacancies. However, excessive oxygen supplied to the source or drain region may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface may cause variations in the characteristics of the transistor. Furthermore, excessively large amounts of oxygen supplied from the insulating layer to the oxide semiconductor layer may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and reducing their conductivity.

[0214] First, it is preferable to form at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen near the semiconductor layer 230, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230 and its vicinity.

[0215] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0216] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a higher hydrogen barrier property.

[0217] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating film.

[0218] 10 , by providing an insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from layers below the transistor 200. Furthermore, by providing an insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0219] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0220] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0221] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0222] In this manner, by surrounding the transistor 200 from above and below with barrier insulating layers against hydrogen, diffusion of hydrogen into the oxide semiconductor can be reduced, and the hydrogen concentration in the channel formation region can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0223] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0224] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0225] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283 having a barrier property against oxygen are formed on the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 can be adjusted.

[0226] 10 shows an example in which the semiconductor layer 230 has a single-layer structure. Note that the semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 11A, the semiconductor layer 230 can have a two-layer structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1.

[0227] 11A illustrates a structure in which the insulating layer 250 is in contact with the top surface of the semiconductor layer 230_2, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 11B , a structure can be adopted in which the semiconductor layer 230_2 in a region overlapping with the opening 289 is removed and the insulating layer 250 is in contact with the side surface of the semiconductor layer 230_2 and the top surface of the semiconductor layer 230_1. With such a structure, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be suitably applied to the semiconductor layer 230_1.

[0228] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layers 242 a, 242 b, and 260 from being oxidized.

[0229] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0230] 9B shows an example in which the insulating layer 250 has a single layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0231] For example, as shown in FIG. 10, the insulating layer 250 preferably has a stacked structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2.

[0232] The insulating layer 250_1 can be formed using any of the materials applicable to the insulating layer 250. For example, the insulating layer 250_1, which has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has a function of capturing or adhering oxygen, thereby preventing the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Furthermore, this structure can reduce the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the semiconductor layer 230, thereby reducing oxygen vacancies in the channel formation region of the semiconductor layer 230.

[0233] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, thereby preventing an excessive positive shift of the transistor 200 and improving reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which can reduce the on-state current or the field-effect mobility of the transistor 200.

[0234] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a transistor with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the transistor can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0235] Furthermore, a high-k material with a high dielectric constant can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating film. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating film.

[0236] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using an ALD method. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1. Alternatively, hafnium oxide has a high function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1.

[0237] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0238] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the gate leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0239] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0240] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. This allows the electrical characteristics and reliability of the transistor 200 to be improved. The insulating layer 250 can also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0241] 11C , a structure in which an insulating layer 250_4 is provided over the insulating layer 250_2 may be used. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0242] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0243] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0244] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-described thickness in at least a portion thereof.

[0245] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0246] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 289 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0247] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0248] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, one embodiment of the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. When the insulating layer 250 includes one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the transistor can be simplified and productivity can be improved.

[0249] The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is preferably provided so as to extend in the channel width direction as shown in FIGS. 9A and 9C . With such a structure, the conductive layer 205 functions as a wiring when a plurality of transistors are provided.

[0250] 10 , the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom and inner wall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 that is formed to conform to the shape of the opening. Here, the height of the top surface of the conductive layer 205 is the same as the height of the top surface of the insulating layer 216.

[0251] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0252] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, oxidation of the conductive layer 205_2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0253] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0254] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be adjusted by controlling the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0255] 10 shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, but one embodiment of the present invention is not limited to this. The conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film over the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided over the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 can be prevented from diffusing into the conductive layer 205.

[0256] The insulating layer 224 functions as a second gate insulating film together with the insulating layers 221 and 222 .

[0257] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0258] The insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0259] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 9C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230.

[0260] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 12A to 12D, the insulating layer 224 may not be formed into an island shape, but may have a shape in which an opening is formed in a part of it. Figures 12A to 12D correspond to Figures 9A to 9D, respectively, and are the same as Figures 9A to 9D except for the shape of the insulating layer 224.

[0261] 12A to 12D, the thickness of the insulating layer 224 in a region that does not overlap with the semiconductor layer 230 is thinner than the thickness of the region that overlaps with the semiconductor layer 230. In addition, an opening is formed in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250. When multiple transistors are provided on the same substrate, by forming the insulating layer 224 in this manner, the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0262] In the insulating layer 224 shown in Figures 12A to 12D, an opening is formed in the region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250, but a configuration without such an opening may be used.

[0263] The conductive layers 242a and 242b are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0264] For the conductive layers 242a and 242b, it is preferable to use a nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, ITO, ITSO, or In—Zn oxide may also be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0265] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the above-mentioned conductive material may be used for the lower layer (layer having a large contact area with the semiconductor layer 230) of the conductive layer 242a and the conductive layer 242b, and a conductive material with higher conductivity may be used for the upper layer of the conductive layer 242a and the conductive layer 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer. Alternatively, ITO or ITSO may be used for the lower layer, and tungsten may be used for the upper layer.

[0266] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side and upper surface of the semiconductor layer 230 via the insulating layer 250. The height of the upper surface of the conductive layer 260 is the same as the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0267] The inner wall of the opening 289 may be perpendicular to the upper surface of the insulating layer 222 or may have a tapered shape. By making the inner wall tapered, the coverage of the insulating layer 250 provided in the opening 289 can be improved and defects such as voids can be reduced.

[0268] 9A and 9C, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0269] 9C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0270] 10, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed on the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2.

[0271] For example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0272] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0273] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0274] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, which will be described later in the section [Insulating Layer]. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0275] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0276] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0277] The conductive layers 243a and 243b are preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 243a and 243b may have a stacked structure.

[0278] 10, the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a has a conductive layer 243a1 formed to fit the shape of the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b has a conductive layer 243b1 formed to fit the shape of the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0279] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material applicable to the conductive layer 205_1. By providing the conductive layer 243a1 and the conductive layer 243b1, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 may be formed using a conductive material applicable to the conductive layer 243a and the conductive layer 243b.

[0280] 9B, the height of the upper surfaces of the conductive layers 243a and 243b is the same as the height of the upper surface of the insulating layer 285. Furthermore, as shown in Fig. 10, the lower part of the conductive layer 243a may be formed so as to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 243b may be formed so as to be embedded in the conductive layer 242b.

[0281] The insulating layers 241a and 241b may be barrier insulating layers applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, and 275. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0282] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with an inner wall of an opening such as the insulating layer 280 and a second insulating layer therein are preferably formed by combining a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0283] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0284] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0285] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0286] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0287] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 13A shows the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 13B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0288] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 13B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 13A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 13A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 13A.

[0289] 13A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0290] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0291] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0292] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0293] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 13A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0294] By using the above technical concept, a transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a large on-current (in other words, high mobility); (2) a small off-current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, a transistor having indium oxide in this specification and the like has high mobility, a small off-current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0295] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 13B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 13A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0296] Unless otherwise specified, normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to the state in which the value of drain current (Id) × channel length (Lch) ÷ channel width (Wch) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0297] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0298] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0299] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above indium oxide film has high field-effect mobility and high reliability.

[0300] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0301] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0302] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0303] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0304] Unless otherwise specified, the channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating film, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

[0305] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0306] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0307] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0308] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 13C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２In some cases, oxygen atoms are released as oxygen vacancies (Vo) in the film. If oxygen vacancies (Vo) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0309] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0310] Furthermore, as shown in FIG. 13C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0311] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0312] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and smaller off-state current than a Si transistor.

[0313]

[0314] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0315] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0316] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0317] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0318] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0319] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0320] Embodiment 4 A semiconductor device according to one embodiment of the present invention will be described with reference to drawings.

[0321] The semiconductor device described in this embodiment can be applied to the semiconductor device 100 described in the above-described Embodiment 1. In addition, the semiconductor device described in this embodiment can also be said to be a modified example of the semiconductor device 100A described in the above-described Embodiment 2. Therefore, the above description can be referred to as appropriate, and detailed description here may be omitted.

[0322] 14A is a cross-sectional view of a semiconductor device 100B including a transistor 310, a transistor 200A, and a wiring region 287. Note that Fig. 14A illustrates cross-sectional views of the transistor 310 and the transistor 200A in the channel length direction.

[0323] When the semiconductor device 100B is applied to the semiconductor device 100 described in the first embodiment, the transistor 310 corresponds to the transistor Mp1, and the transistor 200A corresponds to the transistor Mn1.

[0324] For the transistor 310, the description of the transistor 310 in Embodiment 2 can be referred to as appropriate.

[0325] 12A to 12D in the above-described Embodiment 2. The transistor 200A differs from the transistor 200 in that the transistor 200A does not include the insulating layer 221, the insulating layer 222, and the layer 229. Therefore, for the transistor 200A, the description of the transistor 200 in the above-described Embodiment 2 can be referred to as appropriate.

[0326] The semiconductor device 100B can be considered a modification of the semiconductor device 100A shown in FIG. 8A and other drawings of the second embodiment. The semiconductor device 100B differs from the semiconductor device 100A in that it includes a transistor 200A instead of the transistor 200. The semiconductor device 100B also differs from the semiconductor device 100A in that it does not include a wiring layer (corresponding to a region where the insulating layer 324, the insulating layer 326, the conductive layer 330, the insulating layer 350, the insulating layer 352, the insulating layer 354, the conductive layer 356, and the like) between the transistor 310 and the transistor 200A. The semiconductor device 100B also differs from the semiconductor device 100A in that it does not include the insulating layer 212 and the insulating layer 214 below the transistor 200A. Furthermore, the semiconductor device 100B differs from the semiconductor device 100A in that it has a wiring region 287 (corresponding to a region where an insulating layer 288 and a conductive layer 248 (conductive layer 248a, conductive layer 248b, conductive layer 248c, conductive layer 248d, conductive layer 248e, etc.) are provided) on the transistor 200A.

[0327] The wiring region 287 includes a conductive layer 248a, a conductive layer 248b, a conductive layer 248c, a conductive layer 248d, and a conductive layer 248e. These conductive layers function as wirings. The wiring region 287 may also be referred to as a wiring layer.

[0328] Note that the transistor 200A may have at least some of the insulating layer 221, the insulating layer 222, the layer 229, etc. The semiconductor device 100B may have at least some of the insulating layer 324, the insulating layer 326, the conductive layer 330, the insulating layer 350, the insulating layer 352, the insulating layer 354, the conductive layer 356, the insulating layer 212, the insulating layer 214, etc.

[0329] 14A , one of the source and drain of the transistor 310 (here, corresponding to the low-resistance region 314b) is connected to a conductive layer 248b provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. One of the source and drain of the transistor 200A (here, corresponding to the conductive layer 242b) is connected to the conductive layer 248b provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248b has a region that functions as a wiring OL.

[0330] The other of the source and the drain of the transistor 310 (here, this corresponds to the low-resistance region 314a) is connected to a conductive layer 248c provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248c has a region functioning as a wiring VLD.

[0331] The other of the source and the drain of the transistor 200 (corresponding to the conductive layer 242a here) is connected to a conductive layer 248a provided in a wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248a has a region functioning as a wiring VLS.

[0332] Furthermore, the gate electrode of the transistor 310 (corresponding to the conductive layer 316 here) is connected to the gate electrode of the transistor 200 (corresponding to the conductive layer 205 here) through one or more conductive layers functioning as a plug or a wiring. The conductive layer 316 and the conductive layer 205 have a region functioning as a wiring IL. Although not shown, the conductive layer 316 and the conductive layer 205 may be connected to a conductive layer 248d provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248d has a region functioning as a wiring IL.

[0333] A back gate electrode of the transistor (here, this corresponds to the conductive layer 260) is connected to a conductive layer 248e provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248e has a region functioning as a wiring BGL.

[0334] The semiconductor device 100B does not have at least some of the insulating layer 324, the insulating layer 326, the conductive layer 330, the insulating layer 350, the insulating layer 352, the insulating layer 354, the conductive layer 356, the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, and the layer 229, and therefore can reduce process costs compared to the semiconductor device 100A shown in FIG. 8A etc. of the above-described second embodiment.

[0335] Furthermore, the semiconductor device 100B does not have at least some of the insulating layer 324, the insulating layer 326, the conductive layer 330, the insulating layer 350, the insulating layer 352, the insulating layer 354, the conductive layer 356, the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, and the layer 229, thereby reducing the parasitic capacitance and parasitic resistance of the conductive layers functioning as plugs or wirings. This reduces signal delays caused by the parasitic capacitance and voltage drops caused by the parasitic resistance. Therefore, the semiconductor device 100B can achieve at least one of improved operating speed and reduced power consumption compared to the semiconductor device 100A shown in FIG. 8A and other figures of the second embodiment.

[0336] Furthermore, since the transistor 200A has a back gate, the semiconductor device 100B can be operated in various modes, for example, as in the operation example described in the first embodiment. For example, by operating the semiconductor device 100B in the second mode, the power consumption of the semiconductor device 100B can be reduced. For example, by operating the semiconductor device 100B in the second mode, the noise generated by the semiconductor device 100B can be reduced. For example, by operating the semiconductor device 100B in the third mode, the operating speed of the semiconductor device 100B can be improved.

[0337] 14B is a cross-sectional view of a semiconductor device 100C including a transistor 310, a transistor 200A, and a wiring region 287. Note that FIG. 14B illustrates cross-sectional views of the transistor 310 and the transistor 200A in the channel length direction.

[0338] The semiconductor device 100C is a modified example of the semiconductor device 100B described above, and can also be considered a modified example of the semiconductor device 100A shown in Figure 8A etc. of the above-described second embodiment. The semiconductor device 100C differs from the semiconductor device 100B in that it does not have the insulating layer 322, the insulating layer 216, or the conductive layer 205.

[0339] The semiconductor device 100C may have a configuration including at least a part of the insulating layer 322, the insulating layer 216, the conductive layer 205, and the like.

[0340] In the semiconductor device 100C, the conductive layer 316 has a region that functions as the gate electrode of the transistor 310 and a region that functions as the gate electrode of the transistor 200A. In other words, the semiconductor device 100C can be said to have a structure in which the transistor 310 and the transistor 200A share one conductive layer.

[0341] The semiconductor device 100C has a structure in which the transistor 310 and the transistor 200A share one conductive layer (corresponding to the conductive layer 316 here) as a conductive layer having a region functioning as a gate electrode of each transistor, and therefore does not need to include the insulating layer 322, the insulating layer 216, and the conductive layer 205. Therefore, the semiconductor device 100C can achieve a reduction in process cost compared to the semiconductor device 100B described above.

[0342] Furthermore, since the transistor 200A has a back gate, the semiconductor device 100C can be operated in various modes, for example, as in the operation example described in the first embodiment. For example, by operating the semiconductor device 100C in the second mode, the power consumption of the semiconductor device 100C can be reduced. For example, by operating the semiconductor device 100C in the second mode, the noise generated by the semiconductor device 100C can be reduced. For example, by operating the semiconductor device 100C in the third mode, the operating speed of the semiconductor device 100C can be improved.

[0343] 15A is a cross-sectional view illustrating a semiconductor device 100Da including a transistor 300, a transistor 200Aa, and a wiring region 287. Note that Fig. 15A illustrates cross-sectional views of the transistor 300 and the transistor 200Aa in the channel length direction.

[0344] The transistor 300 has a so-called planar structure and is a variation of the transistor 310 described in Embodiment 2. Therefore, the semiconductor device 100Da may include the transistor 300 having a planar structure instead of the transistor 310 having a Fin structure.

[0345] The transistor 200Aa is a modification of the above-described transistor 200A and does not include the insulating layer 216 and the conductive layer 205. In this case, the transistor 200Aa does not include a back gate and includes a region in which the conductive layer 260 functions as a gate electrode.

[0346] In the semiconductor device 100Da, the transistor 200Aa is disposed beside the transistor 300, not above it. In this case, the semiconductor layer 230 having the channel formation region of the transistor 200Aa is provided so as to be in contact with the top surface of the insulating layer 315 having a region that functions as the gate insulating film of the transistor 300, but not to overlap with the transistor 300.

[0347] 15A , one of the source or drain of the transistor 300 (here, corresponding to the low-resistance region 314b) is connected to one of the source or drain of the transistor 200Aa (here, corresponding to the conductive layer 242b). The conductive layer 242b is connected to a conductive layer 248b provided in the wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 248b has a region that functions as wiring OL.

[0348] The other of the source and the drain of the transistor 300 (here, this corresponds to the low-resistance region 314a) is connected to a conductive layer 242d and a conductive layer 248c provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248c has a region functioning as a wiring VLD.

[0349] The other of the source and the drain of the transistor 200Aa (corresponding to the conductive layer 242a here) is connected to a conductive layer 248a provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248a has a region that functions as a wiring VLS.

[0350] Furthermore, the gate electrode of the transistor 300 (corresponding to the conductive layer 242c here) is connected to the conductive layer 248d provided in the wiring region 287 through one or more conductive layers functioning as a plug or wiring. The gate electrode of the transistor 200Aa (corresponding to the conductive layer 260 here) is connected to the conductive layer 248d provided in the wiring region 287 through one or more conductive layers functioning as a plug or wiring. The conductive layer 248d has a region that functions as the wiring IL. In other words, the two conductive layers 248d shown in FIG. 15A may be a continuous conductive layer. This is indicated by a thick dashed line in the drawing.

[0351] Here, the conductive layers 242a, 242b, 242c, and 242d may be formed in the same process. In other words, the semiconductor device 100Da can be said to have a configuration in which the conductive layers 242a, 242b, 242c, and 242d are located at the same height.

[0352] The semiconductor device 100Da can be configured such that some of the components of the transistor 200Aa and some of the components of the transistor 300 are located at the same height. That is, some of the components of the transistor 200Aa and some of the components of the transistor 300 can be formed in the same process. This allows the semiconductor device 100Da to reduce process costs.

[0353] 15B is a cross-sectional view illustrating a semiconductor device 100Db including a transistor 300, a transistor 200Ab, and a wiring region 287. Note that Fig. 15B illustrates cross-sectional views of the transistor 300 and the transistor 200Ab in the channel length direction.

[0354] The semiconductor device 100Db is a modification of the semiconductor device 100Da described above, and includes a transistor 200Ab instead of the transistor 200Aa. The transistor 200Ab has a configuration similar to that of the transistor 200A described above. That is, the transistor 200Ab has a back gate. In this case, the conductive layer 205 has a region that functions as a gate electrode, and the conductive layer 260 has a region that functions as a back gate electrode.

[0355] Here, the insulating layer 216 and the conductive layer 205 are provided to be in contact with the top surface of the insulating layer 315, which has a region that functions as a gate insulating film of the transistor 300. The conductive layer 205 has a region that functions as a gate electrode of the transistor 200Ab and a region that functions as a gate electrode of the transistor 300. In other words, the two conductive layers 205 shown in FIG. 15B may be a continuous conductive layer. This is indicated by a thick dashed line in the drawing.

[0356] 15B , the gate electrode of the transistor 300 and the gate electrode of the transistor 200Ab (here, this corresponds to the conductive layer 205) are connected to a conductive layer 248d provided in a wiring region 287 via a conductive layer 242c and one or more conductive layers functioning as a plug or wiring. The conductive layer 248d has a region that functions as a wiring IL.

[0357] The back gate electrode (here, this corresponds to the conductive layer 260) of the transistor 200Ab is connected to a conductive layer 248e provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248e has a region functioning as a wiring BGL.

[0358] Here, the conductive layers 242a, 242b, 242c, and 242d may be formed in the same process. In other words, the semiconductor device 100Db can be said to have a configuration in which the conductive layers 242a, 242b, 242c, and 242d are located at the same height.

[0359] The semiconductor device 100Db can be configured such that some of the components of the transistor 200Ab and some of the components of the transistor 300 are located at the same height. That is, some of the components of the transistor 200Ab and some of the components of the transistor 300 can be formed in the same process. This allows the semiconductor device 100Db to achieve reduced process costs compared to the semiconductor device 100B and the semiconductor device 100C described above.

[0360] Furthermore, since the transistor 200Ab has a back gate, the semiconductor device 100Db can be operated in various modes, for example, as in the operation example shown in the first embodiment described above. For example, by operating the semiconductor device 100Db in the second mode, the power consumption of the semiconductor device 100Db can be reduced. For example, by operating the semiconductor device 100Db in the second mode, the noise generated by the semiconductor device 100Db can be reduced. For example, by operating the semiconductor device 100Db in the third mode, the operating speed of the semiconductor device 100Db can be improved.

[0361] 16A is a cross-sectional view of a semiconductor device 100Ea including a transistor 300, a transistor 200Ba, and a wiring region 287. Note that FIG. 16A illustrates a cross-sectional view of the transistor 300 in the channel length direction.

[0362] The semiconductor device 100Ea includes an insulating layer 210 over the transistor 300, a transistor 200Ba over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 277, an insulating layer 278 over the insulating layer 277, and insulating layers 282, 283, 285, and 288 over the insulating layer 278. The insulating layer 210, the insulating layer 280, the insulating layer 277, the insulating layer 278, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 288 function as interlayer films.

[0363] The transistor 200Ba includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the conductive layer 220.

[0364] In the transistor 200Ba, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. The conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating film, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode.

[0365] An opening 290 is provided in the insulating layer 280 and the conductive layer 240 to reach the conductive layer 220 .

[0366] The opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290, and the opening in the region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290. Although not shown, the shape and size of the opening 290 in a top view may differ depending on the layer. Furthermore, although not shown, for example, when the shape of the opening 290 in a top view is circular, the openings in each layer may or may not be concentric.

[0367] At least some of the components of the transistor 200Ba are disposed within the opening 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least a portion of each is located within the opening 290. Furthermore, the portions of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are disposed within the opening 290 are provided so as to reflect the shape of the opening 290.

[0368] The semiconductor layer 230 is provided in contact with the bottom and inner wall of the opening 290. The semiconductor layer 230 has a recess that reflects the shape of the opening 290. The semiconductor layer 230 has a portion located on the conductive layer 240 and a portion located on the conductive layer 220 within the opening 290.

[0369] The insulating layer 250 is provided so as to cover the semiconductor layer 230. The insulating layer 250 is also provided on the insulating layer 280 so as to cover the top and side surfaces of the semiconductor layer 230. The insulating layer 250 has a recess that reflects the shape of the recess that the semiconductor layer 230 has.

[0370] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region within the opening 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0371] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200Ba. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0372] The semiconductor layer 230 is provided inside the opening 290. The transistor 200Ba has a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located on the bottom and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located on the top, and thus current flows in the vertical direction. In other words, a channel is formed along the inner wall of the opening 290.

[0373] The transistor 200Ba includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the semiconductor layer 230 including a channel formation region. That is, the transistor 200Ba can be said to be an OS transistor.

[0374] The insulating layer 277 is provided so as to be located on the insulating layer 250. The insulating layer 277 is also provided with an opening 270 that reaches the insulating layer 250 at a position overlapping the opening 290. The conductive layer 260 is arranged so that at least a portion thereof is located within the opening 270. The conductive layer 260 contacts the insulating layer 250 within the opening 270.

[0375] The conductive layer 260 is provided so as to fill the openings 290 and 270. The conductive layer 260 has a portion that faces the semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0376] The shapes applicable to the opening 270 are the same as the shapes applicable to the opening 290 .

[0377] The conductive layer 220 and the conductive layer 240 can each include, for example, a conductive material that can be used for the conductive layer 260. The insulating layer 210, the insulating layer 277, and the insulating layer 278 can each include, for example, an insulating material that can be used for the insulating layer 280.

[0378] As one aspect of the present invention, a recess may be provided in the conductive layer 220. In other words, the conductive layer 220 may have a recess, the bottom of which corresponds to the upper surface of the recess in the conductive layer 220, and the inner wall of which corresponds to the side surface of the recess in the conductive layer 220.

[0379] At this time, the opening 290 overlaps with the recessed portion of the conductive layer 220. Here, the bottom of the opening 290 includes the bottom of the recessed portion of the conductive layer 220, and the inner wall of the opening 290 includes the inner wall of the recessed portion of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0380] By providing a recess in the conductive layer 220 at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be made lower than the height of the top surface of the conductive layer 220 in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, as compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0381] The semiconductor layer 230 contacts the upper surface and side surfaces of the conductive layer 220 in the recesses of the conductive layer 220, as well as the upper surface of the conductive layer 240. The recesses of the conductive layer 220 can increase the area of ​​contact between the semiconductor layer 230 and the conductive layer 220. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220 can be reduced.

[0382] As one embodiment of the present invention, the transistor 200Ba may have a structure in which the insulating layer 225 is provided between the insulating layer 280 and the semiconductor layer 230 .

[0383] The insulating layer 225 is provided along at least a part of the inner wall of the opening 290. The insulating layer 225 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0384] For the insulating layer 225, for example, an insulating material applicable to the insulating layer 250 can be used.

[0385] In this case, the conductive layer 220 may have a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom of the first recess is located lower (closer to the insulating layer 210) than the bottom of the second recess. The insulating layer 225 contacts the upper and side surfaces of the conductive layer 220 in the recess (specifically, the second recess) of the conductive layer 220, and also contacts the side surfaces of the insulating layer 280 and the conductive layer 240 within the opening 290. The semiconductor layer 230 contacts the upper and side surfaces of the conductive layer 220 in the recess (specifically, the first recess) of the conductive layer 220, the side surfaces and upper surface of the insulating layer 225, and the upper surface of the conductive layer 240.

[0386] As described above, the transistor 200Ba can have a channel formation region, a source region, and a drain region formed in the opening 290. This allows the area occupied by the transistor 200Ba to be reduced compared to a so-called planar transistor such as the above-described transistor 200A, and therefore allows for a high degree of integration of the semiconductor device.

[0387] Although not shown, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically within the opening 290. Therefore, the side surface of the conductive layer 260 located at the center faces the side surface of the semiconductor layer 230 via the insulating layer 250. That is, in a top view, the entire periphery of the semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200Ba is determined by the length of the periphery of the semiconductor layer 230. That is, it can be said that the channel width of the transistor 200Ba is determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a top view).

[0388] Increasing the width of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, the area occupied by the transistor 200Ba is roughly determined by the width of the opening 290. Reducing the width of the opening 290 reduces the area occupied by the transistor 200Ba, thereby enabling a semiconductor device to be highly integrated.

[0389] When the opening 290 is formed using photolithography, the width of the opening 290 is limited by the exposure limit of photolithography, making further miniaturization difficult. The width of the opening 290 is set by the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided within the opening 290. The width of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in top view, the width of the opening 290 corresponds to the diameter of the opening 290, and the channel width can be calculated as "the width of the opening 290 x π."

[0390] The channel length of the transistor 200Ba is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200Ba is determined by the thickness of the insulating layer 280 on the conductive layer 220. In this case, the channel length corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side.

[0391] The channel length of the transistor 200Ba can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200Ba can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200Ba, thereby improving the frequency characteristics.

[0392] Note that the channel length of the transistor 200Ba does not affect the area occupied by the transistor 200Ba, for example, the area of ​​the transistor 200Ba in a top view, because the channel length is determined by the thickness of the insulating layer 280 on the conductive layer 220. Setting the channel length of the transistor 200Ba to, for example, 1 μm or less, 500 nm or less, or 300 nm or less can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0393] From the above, it is preferable that the channel length of the transistor 200Ba is 0.1 nm or more, 1 nm or more, or 5 nm or more, and 1 μm or less, 500 nm or less, or 300 nm or less.

[0394] The channel length of the transistor 200Ba is preferably at least shorter than the channel width of the transistor 200Ba. The channel length of the transistor 200Ba is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width of the transistor 200Ba. With this structure, a transistor with good electrical characteristics and high reliability can be realized.

[0395] As described above, by forming the opening 290 so as to have a circular shape in top view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 230 uniform, allowing a gate electric field to be applied uniformly to the semiconductor layer 230.

[0396] Although this embodiment illustrates an example in which the opening 290 is circular in top view, one embodiment of the present invention is not limited thereto. In top view, the opening 290 can be, for example, a circle, an approximately circle such as an ellipse, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180°) or a convex polygon (a polygon with all interior angles equal to or less than 180°). In top view, the opening 290 is preferably circular. By forming the opening 290 circular, processing accuracy can be improved and openings of minute sizes can be formed. In this specification and the like, a circle is not limited to a perfect circle.

[0397] 16A , one of the source or drain of the transistor 300 (here, corresponding to the low-resistance region 314b) is connected to one of the source or drain of the transistor 200Ba (here, corresponding to the conductive layer 220). The one of the source or drain of the transistor 200Ba (here, corresponding to the conductive layer 220) is connected to a conductive layer 248b provided in the wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 248b has a region that functions as a wiring OL.

[0398] The other of the source and the drain of the transistor 300 (here, this corresponds to the low-resistance region 314a) is connected to a conductive layer 248c provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248c has a region functioning as a wiring VLD.

[0399] The other of the source and the drain of the transistor 200Ba (here, this corresponds to the conductive layer 240) is connected to a conductive layer 248a provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248a has a region that functions as a wiring VLS.

[0400] The gate electrode of the transistor 300 (corresponding to the conductive layer 316 here) is connected to a conductive layer 248d provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The gate electrode of the transistor 200Ba (corresponding to the conductive layer 260 here) is connected to the conductive layer 248d provided in the wiring region 287 through one or more conductive layers functioning as a plug or a wiring. The conductive layer 248d has a region that functions as a wiring IL.

[0401] By using the transistor 200Ba, the semiconductor device 100Ea can reduce the area occupied by the transistor compared to when a so-called planar transistor is used, thereby enabling the semiconductor device 100Ea to be highly integrated.

[0402] Furthermore, by using the transistor 200Ba, the semiconductor device 100Ea can easily reduce the channel length of the transistor and increase the channel width of the transistor compared to when a so-called planar transistor is used. In other words, it can be said that the on-state current of the transistor can be easily increased. Therefore, the operating speed of the semiconductor device 100Ea can be improved.

[0403] 16B is a cross-sectional view illustrating a semiconductor device 100Eb including a transistor 300, a transistor 200Bb, and a wiring region 287. Note that FIG. 16B illustrates a cross-sectional view of the transistor 300 in the channel length direction.

[0404] The semiconductor device 100Eb is a modification of the semiconductor device 100Ea described above, and further includes an insulating layer 281. The insulating layer 281 functions as an interlayer film. The transistor 200Bb is a modification of the transistor 200Ba described above, and further includes a conductive layer 255.

[0405] The conductive layer 255 is located on the insulating layer 280, and the insulating layer 281 is located on the conductive layer 255 and the insulating layer 280. Furthermore, the conductive layer 240 is located on the insulating layer 281.

[0406] At this time, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0407] In transistor 200Bb, the semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating film, the conductive layer 220 functions as one of the source electrode and the drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating film.

[0408] The semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 225 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of this region functions as a channel formation region of the transistor 200Bb.

[0409] Since the transistor 200Bb includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200Bb can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0410] Note that in the transistor 200Bb, one of the conductive layer 255 and the conductive layer 260 may be used as a gate electrode and the other may be used as a backgate electrode.

[0411] The conductive layer 255 may include, for example, a conductive material that can be used for the conductive layer 260. The insulating layer 281 may include, for example, an insulating material that can be used for the insulating layer 280.

[0412] In the semiconductor device 100Eb, the conductive layer 255 can be used as a gate electrode, and the conductive layer 260 can be used as a back gate electrode.

[0413] 16B , the gate electrode of transistor 300 (corresponding to conductive layer 316 here) is connected to the gate electrode of transistor 200Bb (corresponding to conductive layer 255 here) through one or more conductive layers functioning as a plug or wiring. The gate electrode of transistor 200Bb (corresponding to conductive layer 255 here) is connected to conductive layer 248d provided in wiring region 287 through one or more conductive layers functioning as a plug or wiring. Conductive layer 248d has a region that functions as wiring IL.

[0414] The back gate electrode (here, this corresponds to the conductive layer 260) of the transistor 200Bb is connected to a conductive layer 248e provided in the wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 248e has a region functioning as a wiring BGL.

[0415] The semiconductor device 100Eb uses the transistor 200Bb, which reduces the area occupied by the transistor compared to when a so-called planar transistor is used, and therefore the semiconductor device 100Eb can be more highly integrated than the semiconductor device 100B and the semiconductor device 100C described above.

[0416] Furthermore, by using the transistor 200Bb, the semiconductor device 100Eb can easily reduce the channel length of the transistor and increase the channel width of the transistor compared to when a so-called planar transistor is used. In other words, it can be said that the on-state current of the transistor is easily increased. Therefore, the semiconductor device 100Eb can achieve an improved operating speed compared to the semiconductor device 100B and the semiconductor device 100C described above.

[0417] Furthermore, since the transistor 200Bb has a back gate, the semiconductor device 100Eb can be operated in various modes, for example, as in the operation example described in the first embodiment. For example, by operating the semiconductor device 100Eb in the second mode, the power consumption of the semiconductor device 100Eb can be reduced. For example, by operating the semiconductor device 100Eb in the second mode, the noise generated by the semiconductor device 100Eb can be reduced. For example, by operating the semiconductor device 100Eb in the third mode, the operating speed of the semiconductor device 100Eb can be improved.

[0418] 17A is a cross-sectional view illustrating a semiconductor device 100Fa including a transistor 300, a transistor 200Ca, and a wiring region 287. Note that FIG. 17A illustrates a cross-sectional view of the transistor 300 in the channel length direction.

[0419] The semiconductor device 100Fa is a modification of the semiconductor device 100Ea described above. The semiconductor device 100Fa includes a transistor 200Ca, which is a modification of the transistor 200Ba, and the conductive layer 260 is disposed so as to overlap the conductive layer 316.

[0420] The transistor 200Ca has an opening 290 that reaches the conductive layer 316. The conductive layer 260 having a region that functions as the gate electrode of the transistor 200Ca is in contact with the conductive layer 316 having a region that functions as the gate electrode of the transistor 300 at the opening 290.

[0421] 17A , the gate electrode of transistor 300 (corresponding to conductive layer 316 here) is connected to the gate electrode of transistor 200Ca (corresponding to conductive layer 260 here). The conductive layer 260 is connected to a conductive layer 248d provided in a wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 248d has a region that functions as wiring IL.

[0422] In the semiconductor device 100Fa, the gate electrode of the transistor 300 and the gate electrode of the transistor 200Ca can be provided so as to overlap each other. Therefore, the semiconductor device 100Fa can be more highly integrated than the semiconductor device 100Ea described above.

[0423] 17B is a cross-sectional view illustrating a semiconductor device 100Fb including a transistor 300, a transistor 200Cb, and a wiring region 287. Note that FIG. 17B illustrates a cross-sectional view of the transistor 300 in the channel length direction.

[0424] The semiconductor device 100Fb is a modification of the semiconductor device 100Eb described above. The semiconductor device 100Fb includes a transistor 200Cb, which is a modification of the transistor 200Bb, and the conductive layer 260 is disposed so as to overlap the conductive layer 316.

[0425] The transistor 200Cb has an opening 290 that reaches the conductive layer 316. The conductive layer 260 having a region that functions as the gate electrode of the transistor 200Cb is in contact with the conductive layer 316 having a region that functions as the gate electrode of the transistor 300 at the opening 290.

[0426] 17B , the gate electrode of transistor 300 (corresponding to conductive layer 316 here) is connected to the gate electrode of transistor 200Cb (corresponding to conductive layer 260 here). The conductive layer 260 is connected to a conductive layer 248d provided in a wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 248d has a region that functions as wiring IL.

[0427] The back gate electrode (here, this corresponds to the conductive layer 255) of the transistor 200Cb is connected to a conductive layer 248e provided in the wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 248e has a region functioning as a wiring BGL.

[0428] In the semiconductor device 100Fb, the gate electrode of the transistor 300 and the gate electrode of the transistor 200Cb can be provided so as to overlap each other. Therefore, the semiconductor device 100Fb can be highly integrated compared to the semiconductor device 100Eb described above.

[0429] Furthermore, since the transistor 200Cb has a back gate, the semiconductor device 100Fb can be operated in various modes, for example, as in the operation example shown in the first embodiment described above. For example, by operating the semiconductor device 100Fb in the second mode, the power consumption of the semiconductor device 100Fb can be reduced. For example, by operating the semiconductor device 100Fb in the second mode, the noise generated by the semiconductor device 100Fb can be reduced. For example, by operating the semiconductor device 100Fb in the third mode, the operating speed of the semiconductor device 100Fb can be improved.

[0430] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0431] Embodiment 5 In this embodiment, an arithmetic device (also referred to as an arithmetic processing device) using the semiconductor device described in the above embodiment, a control system for the arithmetic device, and a control method for the arithmetic device will be described.

[0432] <Configuration Example of Arithmetic Device and Control System of Arithmetic Device> FIGS. 18A and 18B are block diagrams illustrating a control system 160 of a arithmetic device according to one embodiment of the present invention.

[0433] 18A , the control system 160 includes a calculation device 150 and a sensor 161. The calculation device 150 includes at least a calculation unit 151, a control unit 152, and an acquisition unit 153.

[0434] The arithmetic unit 151 has various logic circuits described above in Embodiment 1. Fig. 18A illustrates a NOT circuit (corresponding to the semiconductor device 100) as a representative of the logic circuits included in the arithmetic unit 151. That is, the arithmetic unit 151 has a logic circuit configured with a CMOS circuit, and an n-channel transistor (corresponding to the transistor Mn1) that configures the CMOS circuit has a backgate.

[0435] Note that for a logic circuit such as the semiconductor device 100 in which an n-channel transistor has a back gate, the description of the above-described first embodiment can be referred to as appropriate.

[0436] The control unit 152 has the function of changing the potential applied to the back gate of the n-channel transistor (corresponding to the wiring BGL connected to the back gate of the transistor Mn1) of the calculation unit 151 based on the information (such as temperature information) acquired by the acquisition unit 153.

[0437] The acquisition unit 153 has a function of acquiring information (such as temperature information) from the sensor 161 .

[0438] The control unit 152 may include, for example, a reference voltage generator (for example, a bandgap reference circuit), an operational amplifier, and a comparator. This allows the potential to be applied to the back gate of the n-channel transistor included in the calculation unit 151 to be controlled by comparing a reference potential generated by the reference voltage generator with a potential based on information acquired by the acquisition unit 153.

[0439] The control unit 152 may also include, for example, an analog-to-digital converter and a digital-to-analog converter. This allows, for example, the potential applied to the back gate of the n-channel transistor included in the calculation unit 151 to be controlled by a digital signal. The analog-to-digital converter may be included in the acquisition unit 153.

[0440] The sensor 161 may have a function of outputting temperature information based on, for example, the temperature of the computing device 150, or may have a function of outputting temperature information based on the temperature of the environment in which the computing device 150 is installed.

[0441] For example, the sensor 161 may be provided in the periphery of the arithmetic device 150. By providing the sensor 161 having the function of outputting temperature information in the periphery of the arithmetic device 150, a signal based on the temperature around the arithmetic device 150 can be output to the acquisition unit 153. Furthermore, for example, the sensor 161 may be provided inside the arithmetic device 150. By providing the sensor 161 having the function of outputting temperature information in the arithmetic device 150, a signal based on the temperature inside the arithmetic device 150 (for example, the arithmetic unit 151) can be output to the acquisition unit 153.

[0442] As a sensor (also called a temperature sensor) having a function of outputting temperature information, for example, a resistance temperature detector (e.g., platinum, nickel, or copper), a thermistor, a thermocouple, an IC temperature sensor, etc. Also, for example, a configuration having a semiconductor temperature sensor (e.g., a silicon diode temperature sensor), or a configuration having a bandgap circuit, etc. can be used.

[0443] In this case, if the temperature sensor has a positive temperature coefficient, the value of the temperature information acquired by the acquisition unit 153 has a positive correlation with the temperature. That is, when the temperature indicated by the temperature information increases, the value of the temperature information increases, and when the temperature indicated by the temperature information decreases, the value of the temperature information decreases. Also, if the temperature sensor has a negative temperature coefficient, the value of the temperature information acquired by the acquisition unit 153 has a negative correlation with the temperature. That is, when the temperature indicated by the temperature information increases, the value of the temperature information decreases, and when the temperature indicated by the temperature information decreases, the value of the temperature information increases. In the following explanation, it is assumed that the temperature sensor has a positive temperature coefficient.

[0444] In the control system 160 shown in FIG. 18A , for example, the control unit 152 can control the potential applied to the back gate of the n-channel transistor included in the calculation unit 151 based on temperature information acquired by the acquisition unit 153 from the sensor 161. In this case, the control unit 152 can have a function of lowering the potential applied to the back gate of the n-channel transistor included in the calculation unit 151 when the value of the temperature information acquired by the acquisition unit 153 increases. Furthermore, the control unit 152 can have a function of raising the potential applied to the back gate of the n-channel transistor included in the calculation unit 151 when the value of the temperature information acquired by the acquisition unit 153 decreases. This allows the operation of the logic circuit included in the calculation unit 151 to be optimized depending on, for example, the temperature of the calculation device 150 or the temperature of the environment in which the calculation device 150 is installed. The control of operation will be described in detail later.

[0445] 18B, in the control system 160, the arithmetic device 150 may have an oscillator 154. Note that in FIG. 18B, a flip-flop (corresponding to the semiconductor device 110) is illustrated as a representative of the logic circuit included in the arithmetic device 151.

[0446] The oscillator 154 has a function of providing a clock signal to the arithmetic unit 151. For example, the oscillator 154 has a function of providing a clock signal to a clock terminal of a flip-flop included in the arithmetic unit 151 (corresponding to the wiring CKL connected to the clock terminal of the semiconductor device 110).

[0447] The oscillator 154 can be configured using, for example, a ring oscillator, a voltage controlled oscillator, and a phase locked loop.

[0448] In this case, the oscillator 154 may have a function of changing the frequency of the clock signal based on a control signal provided from the controller 152. The controller 152 may also have a function of providing the oscillator 154 with a control signal based on information (such as temperature information) acquired by the acquirer 153.

[0449] 18B , for example, the control unit 152 can control the potential applied to the back gate of the n-channel transistor in the calculation unit 151 and the frequency of the clock signal applied to the calculation unit 151 based on temperature information acquired by the acquisition unit 153 from the sensor 161. In this case, the control unit 152 can have a function of, for example, lowering the potential applied to the back gate of the n-channel transistor in the calculation unit 151 and lowering the frequency of the clock signal provided from the oscillation unit 154 to the calculation unit 151 when the value of the temperature information acquired by the acquisition unit 153 increases. Furthermore, the control unit 152 can have a function of, for example, raising the potential applied to the back gate of the n-channel transistor in the calculation unit 151 and raising the frequency of the clock signal provided from the oscillation unit 154 to the calculation unit 151 when the value of the temperature information acquired by the acquisition unit 153 decreases. This allows the operation of the logic circuit in the calculation unit 151 to be optimized depending on, for example, the temperature of the calculation device 150 or the temperature of the environment in which the calculation device 150 is installed. The control of the operation will be described in detail later.

[0450] <Example of a Method for Controlling the Arithmetic Device> Next, a method for controlling the arithmetic device 150 will be described.

[0451] Here, as an example, it is assumed that in the control system 160, the sensor 161 has a function of outputting temperature information.

[0452] The n-channel transistors constituting the logic circuit of the operating unit 151 have, for example, an off-state current that increases with an increase in temperature and decreases with a decrease in temperature, and the n-channel transistors constituting the logic circuit of the operating unit 151 have, for example, a threshold voltage that decreases with an increase in temperature and increases with a decrease in temperature.

[0453] [Example 1 of Control Method] Using the control system 160 shown in FIG. 18A, control of the operation of the logic circuit included in the arithmetic unit 151 will be described.

[0454] Here, the sensor 161 is assumed to be provided in the vicinity of the arithmetic device 150. That is, the sensor 161 is assumed to output a signal based on the temperature around the arithmetic device 150 to the acquisition unit 153. Therefore, in the control system 160, the arithmetic device 150 can control the operation of the logic circuit included in the arithmetic unit 151 based on the temperature around the arithmetic device 150.

[0455] At this time, in the control system 160, when the value of the temperature information acquired by the acquisition unit 153 from the sensor 161 in the arithmetic device 150 increases, for example, the control unit 152 can decrease the potential applied to the back gate of the n-channel transistor in the arithmetic device 151. Also, in the control system 160, when the value of the temperature information acquired by the acquisition unit 153 from the sensor 161 in the arithmetic device 150 decreases, for example, the control unit 152 can increase the potential applied to the back gate of the n-channel transistor in the arithmetic device 151.

[0456] For example, when the temperature of the environment in which the arithmetic device 150 is installed rises, the off-state current of the n-channel transistor increases. When the off-state current of the n-channel transistor increases, the static current consumption in the steady state increases during operation of the logic circuit of the arithmetic unit 151, and power consumption increases. Therefore, it is advisable to have the control unit 152 lower the potential applied to the back gate of the n-channel transistor. This reduces the off-state current, thereby reducing the static current consumption and suppressing the increase in power consumption.

[0457] Furthermore, for example, when the temperature of the environment in which the arithmetic device 150 is installed drops, the threshold voltage of the n-channel transistor increases. When the threshold voltage of the n-channel transistor increases, malfunctions become more likely to occur in the operation of the logic circuit of the arithmetic unit 151 due to increased circuit delay, increased minimum operating voltage, and decreased stability. Therefore, it is preferable for the control unit 152 to increase the potential applied to the back gate of the n-channel transistor. This lowers the threshold voltage, thereby suppressing increases in circuit delay, increased minimum operating voltage, and decreased stability, making it less likely for malfunctions to occur.

[0458] Fig. 19 is a flowchart illustrating an example of the operation of the arithmetic device 150. An example of a procedure for control based on temperature information acquired by the arithmetic device 150 from the sensor 161 will be described using the flowchart shown in Fig. 19.

[0459] In the following description, the reference value TH1 is assumed to be greater than the reference value TH2. For example, the reference value TH1 can be set to a value greater than room temperature (25° C.), and the reference value TH2 can be set to a value smaller than room temperature. The potential VBG1 is assumed to be smaller than the potential VBG2, and the potential VBG2 is assumed to be smaller than the potential VBG3. For example, the potential VBG1 can be set to a potential smaller than the source potential (corresponding to the potential applied to the wiring VLS) of the n-channel transistor included in the computing unit 151, the potential VBG2 can be set to the same potential as the source potential, and the potential VBG3 can be set to a potential greater than the source potential.

[0460] In step S11 , the acquisition unit 153 acquires the temperature information TS from the sensor 161 .

[0461] In step S12, the control unit 152 determines whether the temperature information TS is equal to or greater than a reference value TH1.

[0462] If the temperature information TS is equal to or greater than the reference value TH1 in step S12, the control unit 152 applies the potential VBG1 to the back gate of the n-channel transistor in the calculation unit 151 in step S13, and the process ends.

[0463] If the temperature information TS is not equal to or greater than the reference value TH1 in step S12, it is determined in step S14 whether the temperature information TS is equal to or greater than a reference value TH2.

[0464] If the temperature information TS is equal to or greater than the reference value TH2 in step S14, the control unit 152 applies the potential VBG2 to the back gate of the n-channel transistor in the calculation unit 151 in step S15, and the process ends.

[0465] If the temperature information TS is not equal to or greater than the reference value TH2 in step S14, the control unit 152 applies the potential VBG3 to the back gate of the n-channel transistor in the calculation unit 151 in step S16, and the process ends.

[0466] By repeatedly executing the above procedure, for example, at predetermined time intervals, the control unit 152 can optimize the operation of the logic circuit of the calculation unit 151 based on the temperature information around the calculation device 150 acquired by the acquisition unit 153.

[0467] For example, step S13 is executed when the temperature of the environment in which the arithmetic device 150 is installed rises from room temperature to a reference value TH1 or higher. As a result, the potential applied to the back gate of the n-channel transistor falls from potential VBG2 to potential VBG1. This makes it possible to suppress an increase in power consumption due to a rise in temperature.

[0468] Furthermore, for example, step S16 is executed when the temperature of the environment in which the arithmetic device 150 is installed drops from room temperature to below the reference value TH2. As a result, the potential applied to the back gate of the n-channel transistor rises from potential VBG2 to potential VBG3. This suppresses increases in circuit delay, increases in the minimum operating voltage, and decreases in stability that accompany temperature drops, making it less likely that malfunctions will occur.

[0469] The operation of the logic circuit of the calculation unit 151 as a result of executing step S13 corresponds to the second mode described in the above-mentioned embodiment 1. The operation of the logic circuit of the calculation unit 151 as a result of executing step S15 corresponds to the first mode described in the above-mentioned embodiment 1. The operation of the logic circuit of the calculation unit 151 as a result of executing step S16 corresponds to the third mode described in the above-mentioned embodiment 1.

[0470] Note that, although an example has been described in which the operation of the arithmetic device 150 is controlled to execute one of three operation modes (first mode, second mode, and third mode) using two reference values ​​(reference value TH1 and reference value TH2), the present invention is not limited to this. For example, the operation of the arithmetic device 150 may be controlled to execute one of two operation modes using one reference value, or may be controlled to execute one of four or more operation modes using three or more reference values. Furthermore, the potential applied to the back gate of the n-channel transistor may be controlled to change continuously with temperature changes.

[0471] [Example 2 of Control Method] Using the control system 160 shown in FIG. 18B, control of the operation of the logic circuit included in the arithmetic unit 151 will be described.

[0472] Here, the sensor 161 is assumed to be provided inside the arithmetic device 150. That is, the sensor 161 is assumed to be able to output a signal based on the temperature inside the arithmetic device 150 (here, the arithmetic unit 151) to the acquisition unit 153. Therefore, in the control system 160, the arithmetic device 150 can control the operation of the logic circuit included in the arithmetic unit 151 based on the temperature of the arithmetic unit 151.

[0473] At this time, in the control system 160, for example, when the value of the temperature information acquired by the acquisition unit 153 from the sensor 161 in the arithmetic device 150 increases, the control unit 152 can lower the potential applied to the back gate of the n-channel transistor in the arithmetic device 151, thereby lowering the frequency of the clock signal provided from the oscillation unit 154 to the arithmetic device 151. Also, in the control system 160, for example, when the value of the temperature information acquired by the acquisition unit 153 from the sensor 161 decreases in the arithmetic device 150, the control unit 152 can raise the potential applied to the back gate of the n-channel transistor in the arithmetic device 151, thereby raising the frequency of the clock signal provided from the oscillation unit 154 to the arithmetic device 151.

[0474] For example, if the temperature rises due to heat generation associated with power consumption during operation of the logic circuit included in the arithmetic unit 151, there is a growing concern that malfunctions due to thermal runaway may occur. Therefore, the control unit 152 may lower the potential applied to the back gate of the n-channel transistor. This reduces the off-state current, thereby reducing the static current consumption in the steady state. Furthermore, the on-state current may be reduced, thereby reducing the through-current in the transient state. Furthermore, the control unit 152 may lower the frequency of the clock signal provided from the oscillator 154 to the arithmetic unit 151. This reduces the operating frequency of the arithmetic unit 151. In this way, by reducing the static current consumption, the through-current, and the operating frequency in the logic circuit included in the arithmetic unit 151, heat generation associated with power consumption and temperature increases due to heat generation can be suppressed, thereby making malfunctions due to thermal runaway less likely to occur.

[0475] Thereafter, when the temperature of the calculation unit 151 drops and the concern of malfunction due to thermal runaway is eliminated, the control unit 152 can increase the potential applied to the back gate of the n-channel transistor, thereby increasing the frequency of the clock signal given to the calculation unit 151 from the oscillation unit 154.

[0476] Fig. 20 is a flowchart illustrating an example of the operation of the arithmetic device 150. An example of a procedure for control performed by the arithmetic device 150 based on temperature information acquired from the sensor 161 will be described using the flowchart shown in Fig. 20.

[0477] In the following description, the reference value TH is assumed to be greater than room temperature and smaller than the temperature at which thermal runaway occurs. The potential VBG_B is assumed to be smaller than the potential VBG_A. For example, the potential VBG_A1 can be set to the same potential as the source potential (corresponding to the potential applied to the wiring VLS) of the n-channel transistor included in the computing unit 151, and the potential VBG_B can be set to a potential smaller than the source potential. The frequency FCK_B is assumed to be smaller than the frequency FCK_A.

[0478] Before the following process starts, a potential VBG_A is applied to the back gate of the n-channel transistor included in the calculation unit 151, and the frequency of the clock signal applied from the oscillation unit 154 to the calculation unit 151 is the frequency FCK_A. This state can also be called a normal state.

[0479] In step S21, the acquisition unit 153 acquires the temperature information TS from the sensor 161.

[0480] In step 22, the control unit 152 determines whether the temperature information TS is equal to or greater than the reference value TH.

[0481] If the temperature information TS is not equal to or greater than the reference value TH in step S22, the process ends.

[0482] If the temperature information TS is equal to or greater than the reference value TH in step S22, in step S23, the control unit 152 applies a potential VBG_B to the back gate of the n-channel transistor in the calculation unit 151, and sets the frequency of the clock signal applied from the oscillation unit 154 to the calculation unit 151 to the frequency FCK_B.

[0483] In step S24 , the acquisition unit 153 acquires the temperature information TS from the sensor 161 .

[0484] In step 25, the control unit 152 determines whether the temperature information TS is equal to or greater than the reference value TH.

[0485] If the temperature information TS is equal to or greater than the reference value TH in step S25, the process returns to step S24.

[0486] If the temperature information TS is not equal to or greater than the reference value TH in step S25, the control unit 152 applies a potential VBG_A to the back gate of the n-channel transistor in the calculation unit 151 in step S26, and sets the frequency of the clock signal applied from the oscillation unit 154 to the calculation unit 151 to the frequency FCK_A. The process ends.

[0487] By repeatedly executing the above procedure, for example, at predetermined time intervals, the control unit 152 can prevent thermal runaway from occurring in the logic circuit of the calculation unit 151 based on the temperature information of the calculation unit 151 acquired by the acquisition unit 153.

[0488] For example, when the temperature of the calculation unit 151 becomes equal to or higher than the reference value TH, step S23 is executed. As a result, the potential applied to the back gate of the n-channel transistor decreases from potential VBG_A to potential VBG_B, and the frequency of the clock signal applied from the oscillator 154 to the calculation unit 151 decreases from frequency FCK_A to frequency FCK_B. This makes it possible to suppress heat generation due to power consumption. This state can also be called an overheated state. The overheated state is maintained until the temperature of the calculation unit 151 becomes less than the reference value TH.

[0489] Thereafter, when the temperature of the calculation unit 151 becomes lower than the reference value TH, step S26 is executed. As a result, the potential applied to the back gate of the n-channel transistor increases from potential VBG_B to potential VBG_A, and the frequency of the clock signal applied from the oscillator 154 to the calculation unit 151 increases from frequency FCK_B to frequency FCK_A. In other words, the normal state is restored.

[0490] Although the above description is of an example in which the operation of the arithmetic device 150 uses one reference value (reference value TH) to control the potential applied to the back gate of the n-channel transistor included in the arithmetic unit 151 and the frequency of the clock signal applied to the arithmetic unit 151, the present invention is not limited to this. For example, the operation of the arithmetic device 150 may use two or more reference values ​​to perform stepwise control depending on the degree of temperature rise due to heat generation.

[0491] In one embodiment of the present invention, in the arithmetic device 150, as described in Embodiment 1, OS transistors are used as n-channel transistors in a logic circuit (such as the semiconductor device 100 or 110) included in the arithmetic unit 151, and Si transistors are used as p-channel transistors. In this case, an oxide semiconductor having a large on-state current is preferably used for the OS transistor in order to increase the operation speed. Examples of oxide semiconductors having a large on-state current include indium oxide.

[0492] Note that any of the various logic circuits (such as the semiconductor device 100 and the semiconductor device 110) described in Embodiment 1 may be used for at least one of the control unit 152, the acquiring unit 153, and the oscillator 154. For example, the control unit 152 and the acquiring unit 153 may each use an oxide semiconductor that provides an OS transistor with a small on-state current, since the operating speed may be slower than that of the operating unit 151. This can reduce the through current in a transient state, thereby reducing power consumption. Furthermore, for example, the oscillator 154 may use an oxide semiconductor that provides an OS transistor with a large on-state current, since the operating speed can be increased, similarly to the operating unit 151.

[0493] Here, an example of an oscillator that can be used for the oscillation section 154 will be described.

[0494] 21 is a circuit diagram illustrating an example of an oscillator of one embodiment of the present invention. The semiconductor device 120 includes three semiconductor devices 100 (semiconductor devices 100[1] to 100[3]) that configure a ring-shaped closed circuit and one semiconductor device 100 (semiconductor device 100[4]) that outputs a clock signal generated by the closed circuit to the outside. Therefore, the semiconductor device 120 can function as a ring oscillator. Note that the number of semiconductor devices 100 that configure the ring-shaped closed circuit is not limited to three and may be an odd number of five or more.

[0495] The output terminal of the semiconductor device 100[1] is connected to the input terminal of the semiconductor device 100[2]. The output terminal of the semiconductor device 100[2] is connected to the input terminal of the semiconductor device 100[3]. The output terminal of the semiconductor device 100[3] is connected to the input terminal of the semiconductor device 100[1] and the input terminal of the semiconductor device 100[4]. The output terminal of the semiconductor device 100[4] is connected to a wiring CKL. Furthermore, the back gate of an n-channel transistor (transistor Mn1) included in each of the semiconductor devices 100[1] to 100[4] is connected to a wiring BGL.

[0496] In the semiconductor device 120, a clock signal is output to the wiring CKL. At this time, the frequency of the clock signal output from the semiconductor device 120 changes depending on the potential applied to the wiring BGL. For example, when the potential applied to the wiring BGL increases, the threshold voltage of the transistor Mn1 decreases and the on-state current increases. As a result, the operating speed of the semiconductor device 120 increases and the frequency of the clock signal increases. Furthermore, for example, when the potential applied to the wiring BGL decreases, the threshold voltage of the n-channel transistor increases and the on-state current decreases. As a result, the operating speed of the semiconductor device 120 decreases and the frequency of the clock signal decreases. In this way, the semiconductor device 120 can function as a voltage-controlled oscillator.

[0497] Therefore, by using the semiconductor device 120 in the oscillator 154 , it is possible to change the frequency of the clock signal given to the arithmetic unit 151 based on the control signal given from the control unit 152 .

[0498] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with other embodiments, etc.

[0499] Embodiment 6 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention is, for example, a memory device including an oxide semiconductor.

[0500] <Example of Hierarchical Structure of Storage Devices> Generally, computers and the like use various storage devices depending on the application. FIG. 22 shows various storage devices by hierarchy. The higher the storage device, the faster the operating speed is required, while the lower the storage device, the larger the storage capacity and recording density are required. FIG. 22 shows, from the top layer to the bottom, a register, a cache memory, a main memory, and storage. The cache memory may also include, from top to bottom, a primary cache (L1), a secondary cache (L2), and a tertiary cache (L3). While an example having up to a tertiary cache is shown here, a lower-level cache memory may also be included. The lowest-level cache memory may also be called an LLC (Last Level Cache) or an FLC (Final Level Cache). For example, a storage class memory may be included between the main memory and the storage.

[0501] Registers integrated into arithmetic processing units (also called processors) such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), and TPUs (Tensor Processing Units) are used to temporarily store the results of calculations performed by cores. They also have the function of retaining setting information for the arithmetic processing units. For this reason, they are frequently accessed by the arithmetic processing units. Therefore, registers are required to have high operating speeds.

[0502] For example, a static random access memory (SRAM) is used as the cache memory. The cache memory has the function of duplicating and storing a portion of the data stored in the main memory. By storing a copy of frequently used data, the speed of accessing the data can be increased. The cache memory is required to have a faster operating speed than the main memory.

[0503] The main memory may be, for example, a dynamic random access memory (DRAM). The main memory has a function of storing programs and data read from storage. The main memory is required to have a larger storage capacity and a higher recording density than cache memory.

[0504] Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires large storage capacity and high recording density. For example, a hard disk drive (HDD) or a solid state drive (SSD) located on top of an HDD can be used as the storage. For example, a large-capacity, non-volatile storage device such as a NAND flash memory (e.g., 3D NAND) can be used as the SSD.

[0505] A memory device according to one embodiment of the present invention (for example, a memory device using an oxide semiconductor) is excellent in that it has high operation speed, is capable of retaining data for a long period of time, has high rewrite endurance, and can be driven at a low voltage.

[0506] A storage device according to one aspect of the present invention is suitable as a storage device located in an area target1 that includes a tier where a cache memory is located, a tier where a main memory is located, and a tier where a storage is located, because it is capable of retaining data for a long period of time. In other words, a storage device according to one aspect of the present invention is suitable for use in an area target1 that includes, in addition to the area where the main memory is located, the boundary area between the main memory and the storage, and the boundary area between the main memory and the cache memory.

[0507] Therefore, for example, it is preferable to replace a DRAM used in a main memory with a storage device according to one embodiment of the present invention. Here, since DRAM requires a refresh operation and is a destructive readout storage device, it consumes more power than other storage devices. Therefore, by not using DRAM, it is possible to reduce power consumption. It is also preferable to replace, for example, a portion of an SRAM used in a cache memory and a portion of a 3D NAND used in storage with a storage device according to one embodiment of the present invention.

[0508] For example, a memory device according to one embodiment of the present invention includes a capacitor including a ferroelectric material, which enables data retention for a long time. Therefore, when the memory device is used as a replacement for a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0509] Furthermore, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a layer where the cache memory is located and a layer where the register is located, because the storage device according to one embodiment of the present invention has a high operating speed and can achieve excellent write and read operations. In other words, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a part of the area where the cache memory is located and an area where the register is located.

[0510] Therefore, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a register included in a CPU, a GPU, an NPU, etc. Also, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a cache memory (such as L1, L2, L3, LLC, and FLC).

[0511] One embodiment of the present invention can be configured without using a DRAM, which has conventionally been used as a main memory or the like. In this case, a storage device according to one embodiment of the present invention can be used in place of the DRAM. Such a configuration can dramatically reduce power consumption (for example, by one hundredth or one thousandth or less). Furthermore, the storage device according to one embodiment of the present invention may be stacked on a processor such as a CPU, a GPU, or an NPU. Such a configuration in which a processor and a storage device are stacked may be referred to as a monolithic stack. By configuring the processor and the storage device as a monolithic stack, for example, the power consumption required for data access between the processor and the storage device can be significantly reduced. Therefore, global warming can be mitigated by deploying information processing devices including supercomputers (also referred to as high performance computers (HPCs)), computers, servers, and the like, to which such a configuration is applied, all over the world.

[0512] As one embodiment of the present invention, for example, the semiconductor device 100 described in Embodiment 1 or the semiconductor device 100A described in Embodiment 2 can be used as at least a part of an arithmetic processing device such as a CPU, a GPU, an NPU, or a TPU. In addition, various semiconductor devices described in Embodiment 4 can be used.

[0513] <Configuration Example of Memory Device> A memory device 700 according to one embodiment of the present invention will be described. At least a part of the memory device 700 can be used as a memory device located in the area target1 including a layer where the cache memory is located, a layer where the main memory is located, and a layer where the storage is located in FIG. 22 . Furthermore, the semiconductor device 100 described in Embodiment 1 or the semiconductor device 100A described in Embodiment 2 can be used for at least a part of the memory device 700. Furthermore, various semiconductor devices described in Embodiment 4 can be used.

[0514] 23 is a block diagram illustrating an example of the configuration of a memory device 700. The memory device 700 shown in FIG.

[0515] The memory array 721 has a plurality of memory cells 741. The plurality of memory cells 741 are arranged in a matrix of M rows and N columns, where M is an integer equal to or greater than 1, and N is an integer equal to or greater than 1.

[0516] In Figure 23, as representative examples, memory cell 741[1,1] arranged in the first row and first column, memory cell 741[1,N] arranged in the first row and Nth column, memory cell 741[M,1] arranged in the Mth row and first column, and memory cell 741[M,N] arranged in the Mth row and Nth column are shown.

[0517] In addition, Figure 23 shows, as representative examples, wiring WL[1] connected to N memory cells 741 arranged in the first row, wiring WL[M] connected to N memory cells 741 arranged in the Mth row, wiring BL[1] connected to M memory cells 741 arranged in the first column, and wiring BL[N] connected to M memory cells 741 arranged in the Nth column.

[0518] The drive circuit 722 includes a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 includes a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

[0519] In one embodiment of the present invention, for example, a Si transistor (a transistor including silicon in a channel formation region) can be used as a transistor included in the driver circuit 722. Therefore, for example, a CMOS circuit (e.g., a circuit operating complementarily, a CMOS logic gate, or a CMOS logic circuit) formed by connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor can be used as the driver circuit 722.

[0520] Alternatively, for example, a CMOS circuit in which the gate of an n-channel OS transistor and the gate of a p-channel Si transistor are connected may be used for the driver circuit 722. For example, the semiconductor device 100 described in Embodiment 1 may be used for at least a part of the driver circuit 722.

[0521] As the Si transistor, for example, at least a part of the transistor 310 described in Embodiment 2 can be used. In addition, for example, at least a part of various transistors provided over the substrate 311 described in Embodiment 4 can be used.

[0522] As the OS transistor, for example, at least a part of the transistor 200 described in Embodiment 2 can be used. Alternatively, for example, at least a part of various transistors including the semiconductor layer 230 described in Embodiment 4 can be used.

[0523] Furthermore, although not shown, the memory device 700 may have a configuration in which the memory array 721 has a plurality of sense amplifiers arranged in a matrix, and a plurality of memory cells 741 are stacked on the sense amplifiers. With such a configuration, the data stored in the memory array 721 can be read out in a massively parallel manner by simultaneously accessing the plurality of sense amplifiers.

[0524] For example, a signal is supplied to each of the terminal BW, terminal CE, terminal GW, terminal MCK, terminal WAKE, terminal ADDR, terminal WDA, terminal PON1, and terminal PON2 from outside the storage device 700. In addition, for example, a signal is output from the terminal RDA to outside the storage device 700.

[0525] For example, a clock signal is applied to terminal MCK. Furthermore, a control signal is applied to each of terminal BW, terminal CE, and terminal GW. A chip enable signal is applied to terminal CE. A global write enable signal is applied to terminal GW. A byte write enable signal is applied to terminal BW. An address signal is applied to terminal ADDR. Write data is applied to terminal WDA. Read data is applied to terminal RDA. A power gating control signal is applied to terminals PON1 and PON2. The signals applied to terminals PON1 and PON2 may be generated by, for example, control circuit 772.

[0526] The control circuit 772 has a function of controlling the operation of the memory device 700. The control circuit 772 has a function of performing a logical operation on signals provided to the terminals CE, GW, and BW, respectively, to determine an operation mode (e.g., a write operation or a read operation) of the memory device 700. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the operation mode is executed.

[0527] The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the driver circuit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal provided to a terminal MCK in accordance with a signal provided to a terminal WAKE. For example, a signal that controls whether or not the clock signal provided to the terminal MCK is input to the voltage generation circuit 773 is provided to the terminal WAKE.

[0528] The peripheral circuit 781 has a function of writing and reading data to and from the memory cells 741. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the memory cells 741, etc. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0529] The row decoder 782 and the column decoder 784 have the function of decoding an address signal applied to the terminal ADDR. The row decoder 782 has the function of specifying a row to be accessed. The column decoder 784 has the function of specifying a column to be accessed. The row driver 783 has the function of selecting the row specified by the row decoder 782 and applying a desired signal to, for example, the corresponding memory cell 741. The column driver 785 has the function of selecting the column specified by the column decoder 784 and applying a desired signal to, for example, the corresponding memory cell 741.

[0530] The data driver 786 has a function of writing and reading data to and from the memory cells 741 selected by the row driver and the column driver. The input circuit 787 has a function of holding data provided to a terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the memory cells 741 via the data driver 786. The data stored in the memory cells 741 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has a function of holding the read data (data Dout). It also has a function of outputting the held data from a terminal RDA to outside the memory device 700.

[0531] In the memory device 700 shown in Figure 23, for example, the row driver 783 has the function of supplying desired signals to the wirings WL[1] to WL[M], and the column driver 785 and the data driver 786 have the function of exchanging data with the wirings BL[1] to BL[N].

[0532] The power switch 761 has a function of controlling whether or not the potential applied to the terminal VMD is supplied to the peripheral circuit 771. The power switch 762 has a function of controlling whether or not the potential applied to the terminal VMH is supplied to the row driver 783. Here, for example, a high power supply potential (e.g., potential VDD) for operating the drive circuit 722 is applied to the terminal VMD, and a low power supply potential (e.g., potential VSS) is applied to the terminal VMS. Also, for example, a high power supply potential (e.g., a potential higher than potential VDD) for operating the memory cell 741 and the like is applied to the terminal VMH. The power switch 761 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON1. The power switch 762 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON2.

[0533] Here, it is preferable to use transistors with small off-state current as each of the power switches 761 and 762. This can reduce the current that flows through the power switches when the power switches are turned off, for example, and therefore reduce power consumption in the power-off state. It is also preferable to use transistors with large on-state current as each of the power switches 761 and 762. This can reduce loss when the power switches are turned on, for example, and therefore reduce power consumption in the power-on state.

[0534] As a transistor with low off-state current, for example, an OS transistor may be used for each of the power switch 761 and the power switch 762. Various oxide semiconductors can be used for the OS transistor. In particular, it is preferable to use an oxide semiconductor that exhibits low off-state current and high on-state current. Examples of oxide semiconductors that exhibit low off-state current and high on-state current include indium oxide. For details about oxide semiconductors that can be used for OS transistors and indium oxide, which is one of the oxide semiconductors, see the above description.

[0535] Note that the circuits and terminals of the driver circuit 722 can be appropriately selected or omitted. Other circuits and terminals may be appropriately added.

[0536] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0537] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0538] [Electronic Component] Fig. 24A is a perspective view of an electronic component 5700 and a substrate (mounting substrate 5704) on which the electronic component 5700 is mounted. The electronic component 5700 shown in Fig. 24A has a semiconductor device 5710 inside a mold 5711. Fig. 24A omits some parts to show the interior of the electronic component 5700. The electronic component 5700 has lands 5712 on the outside of the mold 5711. The lands 5712 are connected to electrode pads 5713. The electrode pads 5713 are connected to the semiconductor device 5710 by wires 5714. The electronic component 5700 is mounted on, for example, a printed circuit board 5702. A plurality of such electronic components are combined and connected on the printed circuit board 5702 to complete the mounting substrate 5704.

[0539] The semiconductor device 5710 also includes a layer 5715 having an operation core and a layer 5716 having a memory. For example, an n-channel transistor and a p-channel transistor can be used for both the layer 5715 and the layer 5716. For example, a CMOS circuit may be configured using a p-channel transistor for the layer 5715 and an n-channel transistor for the layer 5716. However, one embodiment of the present invention is not limited thereto, and a structure may be used in which both an n-channel transistor and a p-channel transistor are used for the layer 5715 and an n-channel transistor is used for the layer 5716.

[0540] Alternatively, for example, a Si transistor may be used for the layer 5715 and an OS transistor may be used for the layer 5716 .

[0541] Here, for example, the transistor Mp1 included in the semiconductor device 100 described in Embodiment 1 can be used as a p-channel transistor used in the layer 5715, and the transistor Mn1 included in the semiconductor device 100 described in Embodiment 1 can be used as an n-channel transistor used in the layer 5716. Furthermore, for example, the transistor 310 included in the semiconductor device 100A described in Embodiment 2 can be used as a p-channel transistor used in the layer 5715, and the transistor 200 included in the semiconductor device 100A described in Embodiment 2 can be used as an n-channel transistor used in the layer 5716. Furthermore, for example, various transistors provided over the substrate 311 described in Embodiment 4 can be used as p-channel transistors used in the layer 5715, and various transistors having the semiconductor layer 230 described in Embodiment 4 can be used as n-channel transistors used in the layer 5716.

[0542] The memory-containing layer 5716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the processor core-containing layer 5715 and the memory-containing layer 5716 can be a monolithically stacked configuration. In a monolithically stacked configuration, the processor cores and memories of each layer can be connected to each other without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the processor core-containing layer 5715 and the memory-containing layer 5716, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster. Part of the function of the processor core-containing layer 5715 (part of the computing function) may be provided in a part of the memory-containing layer 5716.

[0543] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0544] It is also preferable that the memory cell arrays included in the memory-containing layer 5716 are formed using OS transistors, and the memory cell arrays are monolithically stacked. By monolithically stacking the memory cell arrays, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time. The access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory-containing layer 5716, it is more difficult to achieve a monolithically stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithically stacked structure.

[0545] That is, OS transistors have an excellent effect of enabling a wider memory bandwidth than Si transistors.

[0546] The semiconductor device 5710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon, silicon carbide, and gallium nitride. For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0547] 24B is a perspective view of an electronic component 5730. The electronic component 5730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 5730 has an interposer 5731 provided on a package substrate 5732 (printed circuit board), and a semiconductor device 5735 and a plurality of semiconductor devices 5710 provided on the interposer 5731.

[0548] In the electronic component 5730, the semiconductor device 5710 can be used as, for example, a memory device such as a high bandwidth memory (HBM). The semiconductor device 5735 can be used as, for example, an integrated circuit (e.g., an arithmetic unit, a control unit, an arithmetic processing unit, or a signal processing unit) such as a CPU, a GPU, an NPU, a TPU, or an FPGA (Field Programmable Gate Array).

[0549] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 5732. For example, a silicon interposer or a resin interposer can be used for the interposer 5731.

[0550] The interposer 5731 has a plurality of wirings and functions to connect a plurality of integrated circuits with different terminal pitches via each of the plurality of wirings. The plurality of wirings are provided in a single layer or multiple layers. The interposer 5731 also functions to connect the integrated circuits provided on the interposer 5731 to electrodes provided on the package substrate 5732. For these reasons, the interposer 5731 is sometimes referred to as a "rewiring substrate" or "intermediate substrate." The interposer 5731 may also be provided with through electrodes, which may be used to connect the integrated circuits to the package substrate 5732. When a silicon interposer is used for the interposer 5731, TSVs may also be used as the through electrodes.

[0551] It is preferable to use a silicon interposer as the interposer 5731. A silicon interposer does not require an active element, and therefore can be manufactured at lower cost than an integrated circuit. Furthermore, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0552] To achieve a wide memory bandwidth, an HBM needs to connect many wires. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0553] Furthermore, for example, SiP or MCM using a silicon interposer is less likely to suffer from a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer for a 2.5D package (2.5-dimensional packaging) in which multiple integrated circuits are arranged side by side on an interposer.

[0554] On the other hand, for example, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 5730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithically stacked configuration using OS transistors is preferable. Also, a composite structure may be used in which a memory cell array stacked using TSVs and a monolithically stacked memory cell array are combined.

[0555] The substrate on which the electronic component 5730 is mounted may be provided with a heat sink (heat dissipation plate) overlapping the electronic component 5730. When a heat sink is provided, it is preferable that the height of the integrated circuit provided on the interposer 5731 be the same. For example, it is preferable that the height of the electronic component 5730 be the same as that of the semiconductor device 5710 and the semiconductor device 5735.

[0556] In order to mount the electronic component 5730 on another substrate, the package substrate 5732 may have electrodes 5733 on its bottom. FIG. 24B shows an example in which the electrodes 5733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a ball grid array (BGA) method. The electrodes 5733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a pin grid array (PGA) method.

[0557] The electronic component 5730 can be mounted on other substrates using various mounting methods, not limited to BGA or PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0558] 25A is a perspective view of an electronic device 6500. The electronic device 6500 shown in FIG. 25A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes, for example, a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from an arithmetic processing device, a memory device, and the like. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502 or the control device 6509, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0559] FIG. 25B is a perspective view of an electronic device 6600. The electronic device 6600 shown in FIG. 25B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes, for example, a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from an arithmetic processing device, a memory device, and the like. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615 or the control device 6616, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6616 is preferable because power consumption can be reduced.

[0560] [Mainframe] Fig. 25C is a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 25C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0561] Fig. 25D is a perspective view illustrating an example configuration of a computer 5620. In Fig. 25D, the computer 5620 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals (not shown). A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0562] PC card 5621 shown in Figure 25E is an example of a processing board equipped with, for example, a processing unit and a storage device. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 25E illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0563] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe (Peripheral Component Interconnect Express).

[0564] Each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for supplying power or inputting signals to the PC card 5621. Furthermore, each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for outputting signals calculated by the PC card 5621. Examples of standards for each of the connection terminals 5623, 5624, and 5625 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). Furthermore, when a video signal is output from each of the connection terminals 5623, 5624, and 5625, examples of the respective standards include High-Definition Multimedia Interface (HDMI (registered trademark)).

[0565] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0566] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include a CPU, a GPU, an NPU, a TPU, and an FPGA. For example, the electronic component 5730 described above can be used as the semiconductor device 5627.

[0567] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 5700 described above can be used as the semiconductor device 5628.

[0568] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0569] [Space Equipment] The semiconductor device of one embodiment of the present invention can be used in space equipment such as equipment that processes and stores information, for example.

[0570] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space.

[0571] Fig. 26A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 26A also shows a planet 6804 in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0572] 26A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0573] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0574] The solar panel 6802 generates the power necessary for the operation of the satellite 6800 when irradiated with sunlight. However, for example, in a situation where the solar panel 6802 is not irradiated with sunlight or where the amount of sunlight irradiating the solar panel 6802 is small, the solar panel 6802 generates less power. Therefore, the satellite 6800 may not generate the power necessary for its operation. In order to operate the satellite 6800 even in a situation where the power generated by the solar panel 6802 is small, the satellite 6800 may be provided with a secondary battery 6805. The solar panel 6802 may also be called a solar cell module.

[0575] The satellite 6800 can generate a signal. The signal is transmitted via the antenna 6803. Furthermore, for example, a receiver installed on the ground or another satellite can receive the signal. For example, the receiver can measure the position of the receiver by receiving the signal transmitted by the satellite 6800. As described above, the satellite 6800 can constitute a satellite positioning system.

[0576] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more devices selected from an arithmetic processing device, a storage device, and the like. Note that the control device 6807 is preferably a semiconductor device including an OS transistor, which is one embodiment of the present invention. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor is preferable because it has high reliability even in an environment where radiation may be incident.

[0577] That is, an OS transistor has an excellent effect of being more radiation resistant than a Si transistor.

[0578] The artificial satellite 6800 may also be configured to include a sensor. For example, the artificial satellite 6800 may be configured to include a visible light sensor, thereby enabling it to have the function of detecting sunlight reflected from an object on the ground. The artificial satellite 6800 may also be configured to include a thermal infrared sensor, thereby enabling it to have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 may function as, for example, an earth observation satellite.

[0579] Although an artificial satellite is shown here as an example of space equipment, the present invention is not limited thereto. The semiconductor device of one embodiment of the present invention can be used in space equipment such as a spaceship, a space capsule, or a space probe, for example.

[0580] [Data Center] The semiconductor device according to one embodiment of the present invention can be used in a storage system applied to a data center, for example. The data center is required to perform long-term management of data, for example, by ensuring the immutability of data. Managing long-term data requires, for example, the installation of storage and servers for storing huge amounts of data, the securing of a stable power source for retaining the data, or the securing of cooling equipment required for retaining the data. Therefore, for example, the data center building needs to be enlarged.

[0581] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, for example, it is possible to reduce the size of the storage system, the size of the power supply for storing data, and the scale of the cooling equipment. Therefore, it is possible to reduce the space required for the data center.

[0582] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and peripheral modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0583] Fig. 26B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 26B has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0584] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0585] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to write or read data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to write or read data.

[0586] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0587] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing the cache memory can be reduced and the power consumption of the cache memory can be reduced.Furthermore, by using a stacked memory cell array, the cache memory can be miniaturized.

[0588] [Head-Mountable Electronic Device] A semiconductor device according to one aspect of the present invention can be used in head-mountable electronic devices (sometimes called wearable devices, headsets, etc.), such as devices for VR, devices for AR, devices for SR (Substitutional Reality), devices for MR (Mixed Reality), and devices that implement spatial computing such as spatial computers.

[0589] 26C and 26D , an example of a head-mountable electronic device will be described. These electronic devices have at least one of the following functions: a function for displaying AR content, a function for displaying VR content, a function for displaying SR content, a function for displaying MR content, and a function for displaying spatial computing content. By having an electronic device with the function for displaying at least one of AR, VR, SR, MR, spatial computing, or other content, it is possible to enhance the sense of immersion felt by the user.

[0590] 26C shows the appearance of an electronic device 8710. The electronic device 8710 includes an attachment portion 8711, a lens 8712, a main body 8713, a display portion 8714, and a cable 8715. The attachment portion 8711 includes a battery 8716 built therein.

[0591] A cable 8715 supplies power from a battery 8716 to the main body 8713. The main body 8713 includes a wireless receiver and can display received image information such as image data on a display portion 8714. A camera provided in the main body 8713 captures the movements of the user's eyeballs, eyelids, and the like, and calculates the user's line of sight based on the information, thereby allowing the user's line of sight to be used as an input means.

[0592] The attachment portion 8711 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8713 may have a function of recognizing the user's line of sight by detecting a current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 8713 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The attachment portion 8711 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying biological information of the user on the display portion 8714. The attachment portion 8711 may also detect the movement of the user's head and change the image displayed on the display portion 8714 in accordance with the movement.

[0593] 26D shows the appearance of the electronic device 8720. The electronic device 8720 is a goggle-type information processing device.

[0594] The electronic device 8720 includes a housing 8721, operation buttons 8723, a band-shaped fixture 8724, and two display units 8722. The two display units 8722 allow a user to view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. The fixture 8724 is also provided with a battery 8725. While the battery 8725 may be provided in the housing 8721, providing the battery 8725 in the fixture 8724 is preferable because the center of gravity of the electronic device 8720 can be shifted rearward, improving the wearing comfort for the user. In addition to the battery 8725, a driver circuit for operating the display unit 8722 may be provided in the fixture 8724 to adjust the center of gravity of the electronic device 8720.

[0595] The operation button 8723 has a function of a power button, etc. In addition to the operation button 8723, other buttons may be provided.

[0596] Note that the semiconductor device of one embodiment of the present invention can be applied to any one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers to reduce power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0597] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0598] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0599] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0600] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0601] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 27A1 and 27A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 27A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0602] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 27A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 27A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0603] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 27A6 and 27A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 27A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 27A6 and 27A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0604] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0605] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 27B1, 27B2, and 27B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 27B4 and 27B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 27B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0606] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0607] Note that even when independent components are shown connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0608] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which current flows from drain to source, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0609] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0610] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, a "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric sandwiched between the electrodes. A "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance" or "capacitance." Conversely, terms such as "capacitance" or "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, terms such as "pair of electrodes," "pair of wirings," "pair of terminals," "pair of conductive layers," "pair of conductors," "pair of conductive regions," and "pair of regions" of a "capacitive element" can sometimes be interchangeable. The capacitance value may be, for example, 0.05 fF to 10 pF, or may be, for example, 1 pF to 10 μF.

[0611] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). The transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. That is, a transistor can transmit and receive an electric signal or generate a potential interaction between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. The gate is a control terminal that controls the amount of current flowing in the channel formation region. The two terminals that function as a source and a drain are input / output terminals that input or output a current flowing in the channel formation region.

[0612] Note that one of the two input / output terminals functions as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, in this specification, the terms "source" and "drain" are interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0613] Depending on the structure, a transistor may have a terminal called a back gate (also referred to as a back gate terminal, back gate region, or back gate electrode) in addition to the three terminals described above. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as, for example, a first gate, a second gate, a third gate, or the like.

[0614] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor having a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high...

Claims

a first transistor and a second transistor on the first transistor; the second transistor includes an oxide semiconductor in a channel formation region; the second transistor has a back gate; a gate of the first transistor electrically connected to a gate of the second transistor; a first terminal of the first transistor electrically connected to a first terminal of the second transistor; a second terminal of the first transistor electrically connected to a first wiring; a second terminal of the second transistor is electrically connected to a second wiring; a back gate of the second transistor is electrically connected to a third wiring; A first potential is applied to the first wiring, A second potential is applied to the second wiring, the third wiring is applied with the second potential in the first mode; a third potential is applied to the third wiring in the second mode; the first potential is higher than the second potential; the third potential is lower than the second potential; Semiconductor device. 　 In claim 1, a fourth potential is applied to the third wiring in a third mode; the fourth potential is higher than the second potential; Semiconductor device. 　 In claim 1 or claim 2, the first transistor includes silicon in a channel formation region; Semiconductor device. 　 In claim 1 or claim 2, the first transistor is a p-channel transistor, the second transistor is an n-channel transistor; Semiconductor device. 　 In claim 1 or claim 2, the oxide semiconductor contains indium oxide; Semiconductor device. 　 a first transistor, a second transistor, and a wiring region; the wiring region includes a first conductive layer and a second conductive layer; the wiring region is located above the first transistor and the second transistor; a gate of the first transistor electrically connected to a gate of the second transistor; a first terminal of the first transistor electrically connected to a first terminal of the second transistor; a second terminal of the first transistor electrically connected to the first conductive layer; a second terminal of the second transistor electrically connected to the second conductive layer; a channel formation region of the first transistor is provided in a substrate; a channel formation region of the second transistor is provided in a semiconductor layer on the substrate; the semiconductor layer includes an oxide semiconductor; Semiconductor device. 　 In claim 6, the second transistor has a back gate; the wiring region includes a third conductive layer; the back gate is electrically connected to the third conductive layer. Semiconductor device. 　 In claim 7, a first potential is applied to the first conductive layer; a second potential is applied to the second conductive layer; the third conductive layer is applied with the second potential in a first mode; a third potential is applied to the third conductive layer in a second mode; the first potential is higher than the second potential; the third potential is lower than the second potential; Semiconductor device. 　 In claim 8, a fourth potential is applied to the third conductive layer in a third mode; the fourth potential is higher than the second potential; Semiconductor device. 　 In any one of claims 6 to 9, the substrate comprises silicon; Semiconductor device. 　 In any one of claims 6 to 9, the first transistor is a p-channel transistor, the second transistor is an n-channel transistor; Semiconductor device. 　 In any one of claims 6 to 9, the oxide semiconductor contains indium oxide; Semiconductor device. 　 The apparatus includes a calculation unit, a control unit, and an acquisition unit, the arithmetic unit has a semiconductor device, the semiconductor device includes a first transistor and a second transistor on the first transistor; the first transistor is a p-channel transistor, the second transistor is an n-channel transistor, the second transistor includes an oxide semiconductor in a channel formation region; the second transistor has a back gate; a gate of the first transistor electrically connected to a gate of the second transistor; a first terminal of the first transistor electrically connected to a first terminal of the second transistor; a second terminal of the first transistor electrically connected to a first wiring; a second terminal of the second transistor is electrically connected to a second wiring; a back gate of the second transistor is electrically connected to a third wiring; the acquisition unit has a function of acquiring temperature information, the control unit has a function of applying a potential based on the temperature information to the third wiring. Computing device. 　 In claim 13, the control unit has a function of applying a first potential to the third wiring when the temperature indicated by the temperature information is lower than a predetermined reference value, and a function of applying a second potential lower than the first potential to the third wiring when the temperature indicated by the temperature information is equal to or higher than the reference value. Computing device. 　 In claim 13 or claim 14, the oxide semiconductor contains indium oxide; Computing device. 　 A system comprising the arithmetic device according to claim 13 or 14 and a sensor, the sensor has a function of outputting the temperature information based on the temperature of the arithmetic device or the temperature of the environment in which the arithmetic device is installed; The acquisition unit has a function of acquiring the temperature information from the sensor. Control system of the computing device. 　 A method for controlling an arithmetic device having a CMOS circuit, comprising: the CMOS circuit has a first p-channel transistor and a second n-channel transistor; the second transistor includes an oxide semiconductor in a channel formation region; the second transistor has a back gate; changing a potential applied to a back gate of the second transistor based on temperature information; A method for controlling a computing device. 　 In claim 17, applying a first potential to a back gate of the second transistor when the temperature indicated by the temperature information is lower than a predetermined reference value; applying a second potential lower than the first potential to the back gate of the second transistor when the temperature indicated by the temperature information is equal to or higher than the reference value; A method for controlling a computing device. 　 In claim 17 or claim 18, The temperature information is based on the temperature of the computing device or the temperature of the environment in which the computing device is installed. A method for controlling a computing device.

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