Circuit board, and semiconductor package comprising same

Abstract

According to an embodiment of the present invention, disclosed is a circuit board comprising: a first insulating layer; a second insulating layer disposed on the first insulating layer and including a through hole; and an insulating member at least partially embedded in an inner wall forming the through hole of the second insulating layer, wherein the insulating member includes a first region embedded in the inner wall and a second region disposed inside the through hole, and the width of the first region in the horizontal direction is greater than the width of the second region in the horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as substrates become more sophisticated, there is an increasing demand for substrates with large-area, thick cavities or through-holes that can mount various types of components (e.g., chips).

[0007] An embodiment of the present invention implements a circuit board in which a large-area through-hole can be easily formed through an insulating member, and a semiconductor package including the same.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability due to uniform thickness and shape over a large area through an insulating member of a rigid aromatic structure that is less subject to physical / chemical deformation at high temperatures by lamination.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved structural reliability by reducing the time and cost required for manufacturing a through hole or cavity through peeling of an insulating member and reducing the risk of damage to the upper surface of the insulating layer exposed by the through hole.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer and including a through hole; and an insulating member at least partially embedded in an inner wall forming the through hole of the second insulating layer; wherein the insulating member includes a first region embedded in the inner wall and a second region disposed inside the through hole, and a width in a horizontal direction of the first region is greater than a width in a horizontal direction of the second region.

[0012] It may include a first electrode portion disposed on the upper surface of the first insulating layer.

[0013] The thickness of the insulating member in the vertical direction may be greater than or equal to the thickness of the first electrode portion in the vertical direction.

[0014] The above first electrode portion may be misaligned in a vertical direction with respect to the insulating member.

[0015] The through hole of the second insulating layer can expose the upper surface of the first insulating layer.

[0016] Each of the first insulating layer and the second insulating layer includes an upper surface and a lower surface, and the insulating member can be disposed between the upper surface of the first insulating layer and the lower surface of the second insulating layer along the edge of the through hole.

[0017] The first region may overlap the second insulating layer in the vertical direction, and the second region may be misaligned with the second insulating layer in the vertical direction.

[0018] The above second region may overlap the above through hole in a vertical direction.

[0019] The minimum thickness of the first region may be greater than the minimum thickness of the second region.

[0020] The above insulating member may be misaligned in a vertical direction with respect to the through hole.

[0021] The above insulating member may include an exposed surface exposed by the through hole.

[0022] The above exposed surface may include a groove formed in a direction from the center of the through hole toward the edge.

[0023] The above second region may have a step portion.

[0024] The above insulating member can be overlapped horizontally with the first electrode portion.

[0025] The second insulating layer may not overlap at least partially in the vertical direction with the insulating member.

[0026] An embodiment of the present invention provides a circuit board in which a large-area through-hole can be easily formed through an insulating member, and a semiconductor package including the same.

[0027] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability due to uniform thickness and shape over a large area through an insulating member of a rigid aromatic structure that is less subject to physical / chemical deformation at high temperatures by lamination.

[0028] In addition, since the embodiment enables the production of a through hole or cavity without forming a stopper or the like by peeling off an insulating material, the time and cost required for forming a through hole are reduced, and the risk of damage to the upper surface of the insulating layer exposed by the through hole is reduced, thereby providing a circuit board with improved structural reliability and a semiconductor package including the same.

[0029] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0030] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0031] Figure 2 is an enlarged view of part K1 in Figure 1,

[0032] Figure 3 is a plan view of a circuit board according to the first embodiment of the present invention.

[0033] Figure 4 is a drawing taken along line II' in Figure 3,

[0034] Fig. 5 is a plan view of a circuit board according to a modified example of Fig. 3,

[0035] Figure 6 is a drawing taken along the line JJ' in Figure 5.

[0036] Figures 7a to 7g are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0037] Figures 8a to 8c are photographs showing a method for manufacturing a circuit board according to the first embodiment.

[0038] Fig. 9 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0039] Figure 10 is an enlarged view of K2 in Figure 9,

[0040] Fig. 11 is a plan view of a circuit board according to a second embodiment of the present invention.

[0041] Fig. 12 is a cross-sectional view of a circuit board according to a modified example of Fig. 10,

[0042] Fig. 13 is a plan view of a circuit board according to a modified example of Fig. 10,

[0043] Fig. 14 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0044] Figure 15 is an enlarged view of K3 in Figure 14,

[0045] Fig. 16 is a cross-sectional view of a circuit board according to the fourth embodiment of the present invention.

[0046] Figure 17 is an enlarged view of K4 in Figure 16,

[0047] Fig. 18 is a photograph of a cross-section of a first insulating layer, a second insulating layer, a through hole, and an insulating member in a circuit board according to an embodiment.

[0048] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0049] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0050] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0051] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0052] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0054] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0055] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may include or be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0056] The circuit board may include a plurality of laminated insulating layers, circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the circuit patterns arranged within each of the insulating layers.

[0057] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of the above-mentioned. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0058] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0059] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0060] Hereinafter, a circuit board according to an embodiment of the present invention may include a first build-up layer and a second build-up layer disposed on the first build-up layer. In addition, each build-up layer may include at least one insulating layer. For example, the first build-up layer and the second build-up layer may each include a plurality of laminated insulating layers. That is, the circuit board may be formed of insulating layers of the first build-up layer and the second build-up layer (or the upper build-up layer and / or the lower build-up layer). In addition, the upper build-up layer and the lower build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole in the upper build-up layer may increase (increase) toward the top. In a coreless layer, the upper build-up layer and the lower build-up layer may be distinguished by the direction in which the width or area of ​​the via hole increases. Accordingly, the width or area of ​​the via hole in the lower build-up layer may decrease (increase) toward the top. In addition, in the case of having a core layer, each build-up layer may correspond to an insulating layer other than the core layer. For example, when a core layer exists in a circuit board, an upper build-up layer may be arranged on top of the core layer, and a lower build-up layer may be arranged under the core layer. In this case, each of the upper build-up layer and the lower build-up layer includes multiple insulating layers.

[0061] In addition, as described above, the build-up layer is a different layer from the above-described protective layer (e.g., solder resist layer), and the uppermost / lowest surface of the build-up layer (or insulating layer) corresponds to the uppermost / lowest surface of the build-up layer (insulating layer) disposed on the top, and does not mean the uppermost / lowest surface of the protective layer. In other words, the uppermost surface of the insulating layer of the circuit board means the uppermost / lowest surface of the build-up layer, not the protective layer. Furthermore, the build-up layer may be a different layer from the protective layer. A detailed description of this will be provided later.

[0062] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of a portion K1 in FIG. 1, FIG. 3 is a plan view of a circuit board according to the first embodiment of the present invention, and FIG. 4 is a view taken along line II' in FIG. 3.

[0063] Referring to FIGS. 1 and 2, a circuit board (100) according to the first embodiment may include an insulating layer (110), an electrode portion (120), and an insulating member (DM). Furthermore, the circuit board (100) may further include a protective layer (not shown) disposed on the electrode portion (120), and a semiconductor chip disposed within a through hole (TH).

[0064] First, the insulating layer (110) may include a plurality of insulating layers. For example, the insulating layer (110) may include a first insulating layer (111) and a second insulating layer (112). Furthermore, the insulating layer (110) may include a third insulating layer (113), a fourth insulating layer (114), and a fifth insulating layer (115). The second insulating layer (112) may be disposed on the first insulating layer (111), which is an insulating layer having an upper surface (US1) exposed by a through hole (TH). Furthermore, at least one insulating layer (e.g., the fifth insulating layer (115)) may be disposed under the first insulating layer (111). Although only the fifth insulating layer (115) is depicted as being disposed under the first insulating layer (111) in the drawing, a plurality of insulating layers may be disposed otherwise. Additionally, although only the third insulating layer (113) and the fourth insulating layer (114) are shown on top of the second insulating layer (112), at least one insulating layer may be disposed on the second insulating layer (112).

[0065] The first insulating layer (111) may include an upper surface (US1) and a lower surface (BS1) (or bottom surface).

[0066] And the second insulating layer (112) may be positioned on the upper side of the first insulating layer (111). The second insulating layer (112) may include an upper surface (US2) and a lower surface (BS2) (or bottom surface). The lower surface (BS2) of the second insulating layer (112) may be in contact with the upper surface (US1) of the first insulating layer (111), and may form the same surface.

[0067] The third insulating layer (113) may be positioned on top of the second insulating layer (112). The upper surface (US2) of the second insulating layer (112) may be in contact with the lower surface of the third insulating layer (113), and may form the same surface.

[0068] The fourth insulating layer (114) may be placed on top of the third insulating layer (113). The upper surface of the third insulating layer (113) may be in contact with the lower surface of the fourth insulating layer (114), and may form the same surface.

[0069] The fifth insulating layer (115) may be positioned below the first insulating layer (111). The upper surface of the fifth insulating layer (115) may be in contact with the lower surface (BS1) of the first insulating layer (111), and may form the same surface.

[0070] For example, the fifth insulating layer (115), the first insulating layer (111), the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114) can be sequentially arranged along the stacking direction or the vertical direction (X-axis direction).

[0071] And the insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0072] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0073] Additionally, each insulating layer may be made of the same or different materials. For example, the first to third insulating layers may be made of the same or different materials.

[0074] The electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0075] As an example, the electrode portion (120) may include a wiring electrode and a via electrode. The wiring electrode may include a wiring (or circuit pattern, pattern) and a pad arranged on an insulating layer. The via electrode may be positioned within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0076] In addition, the pads arranged on the outside of the electrode portion (120) can be bonded to semiconductor elements, substrates, boards, etc. with solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern in order to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. In addition, the pads arranged on the inside function to connect the via electrodes and the circuit pattern. When the via electrodes are arranged with a width wider than the circuit pattern, pads having a width wider than the circuit pattern are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad directly in contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad directly in contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, but should also be understood as a concave or convex surface that may appear depending on various processes.

[0077] As an example, the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), a third electrode portion (123), a fourth electrode portion (124), and a fifth electrode portion (125). The electrode portion may include a wiring portion and a via electrode. Each electrode portion may include a wiring electrode (wiring portion) and a via electrode.

[0078] The first electrode portion (121) may include a first wiring portion (121a) and a first via electrode (121b). In addition, the second electrode portion (122) may include a second wiring portion (122a) and a second via electrode (122b). In addition, the third electrode portion (123) may include a third wiring portion (123a) and a third via electrode (123b). In addition, the fourth electrode portion (124) may include a fourth wiring portion (124a) and a fourth via electrode (124b). In addition, the fifth electrode portion (125) may include a fifth wiring portion (125a) and a fifth via electrode (125b).

[0079] The first electrode portion (121) may be positioned on the second insulating layer (112). The first electrode portion (121) may be positioned on the upper surface (US1) of the first insulating layer (111). In addition, the first wiring portion (121a) and the first via electrode (121b) may be positioned on the first insulating layer (111). The first via electrode (121b) may penetrate at least a portion of the second insulating layer (112).

[0080] The second electrode portion (122) may be located in the first insulating layer (111). The second electrode portion (122) may be located on the upper surface of the fifth insulating layer (115) or the lower surface of the first insulating layer (111) within the first insulating layer (111). The second wiring portion (122a) and the second via electrode (122b) may be located within the first insulating layer (111). The second via electrode (122b) may penetrate at least a portion of the first insulating layer (111).

[0081] The third electrode portion (123) may be located in the third insulating layer (113). The third electrode portion (123) may be located on the upper surface of the second insulating layer (112) within the third insulating layer (113). The third wiring portion (123a) and the third via electrode (123b) may be located within the third insulating layer (113), and the third via electrode (123b) may penetrate at least a portion of the third insulating layer (113).

[0082] The fourth electrode portion (124) may be located in the fourth insulating layer (114). The fourth electrode portion (124) may be located on the upper surface of the third insulating layer (113) within the fourth insulating layer (114). The fourth wiring portion (124a) and the fourth via electrode (124b) may be located within the fourth insulating layer (114), and the fourth via electrode (124b) may penetrate at least a portion of the fourth insulating layer (114).

[0083] The fifth electrode portion (125) may be located in the fifth insulating layer (115). The fifth electrode portion (125) may be located below the lower surface (BS1) of the first insulating layer (111) within the fifth insulating layer (115). The fifth wiring portion (125a) and the fifth via electrode (125b) may be located within the fifth insulating layer (115), and the fifth via electrode (125b) may penetrate at least a portion of the fifth insulating layer (115).

[0084] A protective layer (not shown) may be further disposed on the top or bottom of the insulating layer (110). The protective layer may include an upper protective layer and a lower protective layer. The upper protective layer may be located on the top of the insulating layer. The lower protective layer may be located on the bottom of the insulating layer. For example, as in FIG. 3, a protective layer (SR) may be present at the top, but if there is no protective layer (absence), the upper insulating layer (e.g., the fourth insulating layer (114)) may be visible in a planar view.

[0085] The protective layer can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer can be formed of a material that has insulating properties for electrical connection. The protective layer can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the protective layer can include any one of a photo solder resist layer, a cover-lay, and a polymer material. And the insulating layer or protective layer located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, the circuit board, etc. In addition, the protective layer may include a connection groove for electrical connection with each electrode unit, chip, die, etc.

[0086] The insulating member (DM) may be positioned on the first insulating layer (111). The insulating member (DM) may be positioned between the upper surface (US1) of the first insulating layer (111) (or the lower surface of the second insulating layer) and the upper surface (US2) of the second insulating layer (112). In addition, the insulating member (DM) may be embedded in the inner wall (IP) forming the through hole (TH) of the second insulating layer (112).

[0087] The insulating member (DM) may be formed of a material with excellent adhesive strength, heat resistance, and chemical resistance. The insulating member (DM) may have rigidity due to its aromatic structure. In addition, the insulating member (DM) may be a polymer film. For example, the insulating member (DM) may include a polyimide (PI) material. With this configuration, the formation of the through-hole (TH) (or cavity) can be facilitated. Furthermore, damage to the circuit board, etc., can be suppressed during the formation of the through-hole (TH) (or cavity). A detailed description thereof will be provided below.

[0088] Referring further to FIGS. 3 and 4, the insulating layer on the first insulating layer (111) may include a through hole (TH). For example, the through hole (TH) may penetrate from the insulating layer (110) to the upper surface of the first insulating layer (111). Accordingly, the through hole (TH) may penetrate the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114). Accordingly, the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114) may include the through hole (TH). In addition, the upper surface (US1) of the first insulating layer (111) may be partially exposed by the through hole (TH). In particular, the first wiring portion (121a) disposed on the upper surface (US1) of the first insulating layer (111) may also be exposed by the through hole (TH) of the insulating layer (110). In a circuit board (100), a through hole (TH) may be called a ‘cavity’, a ‘home’, a ‘recess’, etc.

[0089] And the insulating member (DM) may be partially embedded in the inner wall (IP) forming the through hole (TH) in the insulating layer (110). In particular, the insulating member (DM) may be at least partially embedded in the inner wall (IP) forming the through hole (TH) of the second insulating layer (112). That is, the insulating member (DM) may be disposed between the upper surface (US1) of the first insulating layer (111) and the lower surface (BS2) of the second insulating layer (112) along the edge of the through hole (TH).

[0090] The insulating member (DM) may be positioned between the upper surface (or the lower surface of the second insulating layer) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). And, it may overlap with the second insulating layer (112) in the horizontal direction (Y-axis direction). The insulating member (DM) may not overlap with the first insulating layer (111), the third insulating layer (113), the fourth insulating layer (114), and the fifth insulating layer (115) other than the second insulating layer (112) in the horizontal direction (Y-axis direction).

[0091] In addition, the insulating member (DM) and the through hole (TH) may be positioned on an insulating layer in which the expansion direction of the via electrode changes. Specifically, the width (Wa) of the second via electrode (122b) in the first insulating layer (111) may increase along the stacking direction or the vertical direction (X-axis direction). That is, the width (or diameter) of the second via electrode (122b) may gradually decrease from the upper surface (US1) of the first insulating layer (111) toward the lower surface (BS1) of the first insulating layer (111). In addition, the width of the second via electrode (122b) at the uppermost surface may be greater than the width at the lowermost surface. In this case, the expansion direction of the width of the second via electrode (122b) may be a vertical direction.

[0092] In contrast, the width (Wb) of the fifth via electrode (125b) may decrease along the stacking direction or the vertical direction (X-axis direction). That is, the width (or diameter) of the fifth via electrode (125b) may gradually increase from the upper surface of the fifth insulating layer (115) toward the lower surface of the fifth insulating layer (115). In addition, the width of the fifth via electrode (125b) at the uppermost surface may be smaller than the width at the lowermost surface. In this case, the direction of expansion of the width of the fifth via electrode (125b) may be the opposite direction to the vertical direction.

[0093] In this way, in the embodiment, the direction of expansion of the width of the via electrode may change at the bottom of the through hole (TH). In the drawing, the structure is illustrated in which the expansion directions of the via electrodes in the first insulating layer (111) and the fifth insulating layer (115) are opposite to each other. However, the present invention is not limited thereto, and when an insulating layer other than the first insulating layer (111) and the fifth insulating layer (115) is arranged at the bottom of the fifth insulating layer, the expansion directions may change between adjacent insulating layers.

[0094] Accordingly, since the insulating member (DM) is positioned on the upper portion of the insulating layer whose expansion direction changes, the first wiring portion (121a) and the insulating member (DM) can be arranged on the upper surface of one insulating layer (e.g., the first insulating layer). In addition, by peeling off the insulating member (DM), a portion of the upper surface (US1) of the first insulating layer (111) and the first wiring portion (121a) can be exposed.

[0095] In this way, a connection between the semiconductor chip mounted in the through hole (TH) and the first wiring portion (121a) can be made, and peeling through the insulating material (DM) can also be easily implemented.

[0096] And the insulating member (DM) according to the embodiment may include a first region (AR1) embedded in the inner wall (IP) and a second region (AR2) disposed inside the through hole (TH). That is, the second region (AR2) may correspond to a region of the insulating member (DM) other than the first region (AR1). The first region (AR1) may overlap with the second insulating layer (112) in the vertical direction (X-axis direction). The second region (AR2) may be misaligned with the second insulating layer (112) in the vertical direction (X-axis direction). Alternatively, the second region (AR2) may not overlap with the second insulating layer (112) in the vertical direction (X-axis direction). The second region (AR2) may overlap with the through hole (TH) in the vertical direction (X-axis direction).

[0097] According to an embodiment, the width (W1) in the horizontal direction (Y-axis direction) of the first region (AR1) may be greater than the width (W2) in the horizontal direction (Y-axis direction) of the second region (AR2). That is, the insulating member (DM) may have a wider width in a region embedded in the inner wall (IP) of the through hole (TH) than in a region where it is not embedded. In addition, the insulating member (DM) may be arranged to be vertically misaligned with respect to the first electrode portion (121), particularly the first wiring portion (121a) within the through hole (TH).

[0098] By this configuration, damage to the first insulating layer (111) can be prevented during the physical, mechanical, and chemical processes of forming the through hole (TH). Furthermore, damage to the first wiring portion (121a) arranged within the insulating member (DM) can also be prevented, and external exposure of the first wiring portion (121a) located on the upper surface (US1) of the first insulating layer (111) within the second insulating layer (112) can be suppressed.

[0099] In addition, the first region (AR1) and the second region (AR2) in the insulating member (DM) arranged along the edge of the through hole (TH) may be the same or different depending on the position of the inner wall in the through hole (TH). For example, the width (W1a) of the first region (AR1) in one region may be different from the width (W1b) of the first region (AR1) in another region. In addition, the width (W2a) of the second region (AR2) in one region may be different from the width (W2b) of the second region (AR2) in another region. In this way, the widths of the first region (AR1) and the second region (AR2) vary along the edge of the through hole (TH), thereby compensating for deformation due to heat, etc., throughout the circuit board.

[0100] In addition, as described above, a first electrode portion (121) may be arranged on the upper surface (US1) of the first insulating layer (111). In particular, the first wiring portion (121a) of the first electrode portion (121) may be in contact with the upper surface (US1) on the upper surface (US1) of the first insulating layer (111). That is, the first wiring portion (121a) and the insulating member (DM) may be positioned on the same surface (e.g., the upper surface (US1)).

[0101] And according to an embodiment, the thickness (t1) of the insulating member (DM) in the vertical direction (X-axis direction) may be greater than or equal to the thickness (t2) of the first electrode portion (121), particularly, the first wiring portion (121a) in the vertical direction (X-axis direction). Accordingly, the insulating member (DM) may overlap with the first electrode portion (121) in the horizontal direction (Y-axis direction). In particular, the insulating member (DM) may overlap with the first wiring portion (121a) of the first electrode portion (121) in the horizontal direction (Y-axis direction). In other words, at least a portion of the insulating member (DM) may overlap with the first wiring portion (121a) in the horizontal direction (Y-axis direction). Conversely, the first wiring portion (121a) may overlap with the insulating member (DM) in the horizontal direction (Y-axis direction). However, a portion of the insulating member (DM) may not overlap with the first wiring portion (121a) in the horizontal direction (Y-axis direction). Accordingly, when peeling is performed by the insulating member (DM), exposure of the first wiring portion (121a) and the exposed surface (EA) of the upper surface of the first insulating layer (111) can be easily implemented.

[0102] In addition, both the first wiring portion (121a) and the insulating member (DM) can be in contact with the upper surface (US1) of the first insulating layer (111). By this configuration, the first wiring portion (121a) may not be damaged in a mechanical cutting process such as trimming when forming a through hole (TH) (or cavity), and the upper insulating layer may be easily removed except for the exposed first wiring portion (121a). That is, since the first wiring portion (121a) and the insulating layer (110) are not bonded within the through hole (TH), the insulating member (DM) may be peeled off regardless of the bonding force therebetween. As a result, the formation of the through hole (TH) in the insulating layer may be performed more easily.

[0103] The insulating member (DM) may include an exposed surface exposed by a through hole (TH). The exposed surface may be located in the second region (AR2). Furthermore, the upper surface of the second region (AR2) may correspond to the exposed surface. In this case, the exposed surface may be vertically parallel to or offset from the upper surface of the first region (AR1). For example, the exposed surface may be located lower than the upper surface of the first region (AR1).

[0104] Fig. 5 is a plan view of a circuit board according to a modified example of Fig. 3, and Fig. 6 is a view taken along the line JJ' in Fig. 5.

[0105] Referring to FIGS. 5 and 6, a circuit board according to a modified example may include an insulating layer, an electrode portion, and an insulating member as described above. Except for the contents described below, the above contents may be equally applied.

[0106] First, as described above, the first region (AR1) and the second region (AR2) in the insulating member (DM) arranged along the edge of the through hole (TH) may have the same or different shapes (e.g., thickness, width, etc.) depending on the position of the inner wall in the through hole (TH).

[0107] Furthermore, the minimum thickness (T1a) of the first region (AR1) and the minimum thickness (T1b) of the second region (AR2) may be different. The minimum thickness (T1a) of the first region (AR1) may be greater than or equal to the minimum thickness (T1b) of the second region (AR2). That is, the minimum thickness (T1b) of the second region (AR2) may be less than or equal to the minimum thickness (T1a) of the first region (AR1).

[0108] For example, when the minimum thickness (T1b) in the second region (AR2) is smaller than the minimum thickness (T1a) in the first region (AR1), the upper surface (or exposed surface) of the second region (AR2) may be located lower than the upper surface of the first region (AR1).

[0109] And the minimum thickness (T1b) in the second region (AR2) may be different from the thickness (T2) of the first wiring portion (121a). For example, the minimum thickness (T1b) in the second region (AR2) may be greater than the thickness (T2) of the first wiring portion (121a). Accordingly, when forming the through hole (TH), damage to the first wiring portion (121a) can be easily suppressed. In addition, the minimum thickness (T1b) in the second region (AR2) may be less than the thickness (T2) of the first wiring portion (121a). For example, the second region (AR2) may not exist. Accordingly, the separation or release of the insulating member (DM) can be easily performed, and the formation of the through hole (TH) can be easily performed. This difference between the minimum thickness of the first region (AR1) and the minimum thickness of the second region (AR2) can be implemented in at least a portion of the insulating member (DM).

[0110] The second region (AR2) may be disposed in contact with the upper surface of the first insulating layer (111) or spaced apart from the upper surface of the first insulating layer (111) in a vertical direction (X-axis direction). For example, in the insulating member (DM), the second region (AR2) may have a structure in which at least a portion thereof floats above the first insulating layer (111) or is in contact with the first insulating layer (111).

[0111] And the insulating member (DM) may have a closed-loop shape or structure along the edge of the through hole (TH). For example, the first region (AR1) and / or the second region (AR2) of the insulating member (DM) may have a closed-loop structure.

[0112] For example, the insulating member (DM) can have various shapes depending on the shape of the through hole (TH). If the chip mounted in the through hole (TH) is rectangular in plan view, both the through hole (TH) and the insulating member (DM) can be rectangular in plan view. Accordingly, the insulating member (DM) can have a shape such as a square ring.

[0113] At this time, the insulating member (DM) may have a closed-loop structure in at least some areas. In particular, the first area (AR1) of the insulating member (DM) may have a closed-loop shape or structure. Accordingly, the formation of a through-hole (TH) or cavity by detaching the insulating member (DM) from the circuit board can be more easily achieved.

[0114] In addition, the second region (AR2) of the insulating member (DM) may not have a closed-loop shape or structure. That is, the second region (AR2) of the insulating member (DM) may be spaced apart along the edge of the through hole (TH). As a result, the second region (AR2) may have an open-loop structure. As a result, as described above, the width of the second region (AR2) in one region may be different from the width of the second region (AR2) in another region. In this way, the width of the second region (AR2) varies along the edge of the through hole (TH), thereby compensating for deformation due to heat, etc., throughout the circuit board.

[0115] FIGS. 7A to 7G are drawings explaining a method for manufacturing a circuit board according to the first embodiment, and FIGS. 8A to 8C are photographs showing a method for manufacturing a circuit board according to the first embodiment.

[0116] A method for manufacturing a circuit board according to a first embodiment may include a step of forming a first insulating layer and a second electrode portion within the first insulating layer, a step of forming an insulating member on the first insulating layer, a step of laminating a second insulating layer on the first insulating layer and forming a first electrode portion on the second insulating layer, and a step of trimming an edge of the insulating member and detaching the interior to form a through hole.

[0117] First, referring to Fig. 7a, each insulating layer can be formed. For example, a first insulating layer (111) can be formed. The first insulating layer (111) can be a core layer, but this example is described based on a coreless substrate. Accordingly, the first insulating layer (111) can be formed, and a second electrode portion (122) can be formed within the first insulating layer (111).

[0118] Referring to FIG. 7b, an insulating member (DM') may be formed on the first insulating layer (111). The insulating member (DM') may include a release film that is at least partially separated during the separation process as described above. The insulating member (DM') may be disposed on the upper surface of the first insulating layer (111). The insulating member (DM') may cover the first wiring portion of the first electrode portion on the first insulating layer (111). That is, the insulating member (DM') may be formed after the first wiring portion is formed on the upper surface of the first insulating layer (111).

[0119] Furthermore, as shown in Fig. 8a, an insulating member (DM') may be formed in an area where formation of a through-hole is desired. For example, a mounting area (CA) where formation of a through-hole is required for chip mounting and a non-mounting area (NCA) where formation of a through-hole is unnecessary may be formed on a large-area circuit board. In such a large-area circuit board, an insulating member (DM') corresponding to a through-hole or chip may be applied on the first insulating layer (111) in the mounting area (CA).

[0120] Referring to Fig. 7c, a second insulating layer (112) can be laminated on the first insulating layer (112). Then, a first electrode portion (121) can be formed on the second insulating layer (112). In particular, a first via electrode (121b) can be formed on the second insulating layer (112).

[0121] Each of the electrode portions described above can be formed by forming a plating layer, performing mask and patterning, and then performing plating through exposure and curing. For example, a mask can be formed on the first insulating layer (111) and the plating layer on the upper side of the first insulating layer (111). For example, the mask can be a dry film. Then, exposure and development, etc. can be performed on the mask to form an open area. In other words, patterning can be performed on the dry insulating member (film). The mask can be placed in an area other than a position where the first wiring portion is formed. Furthermore, a curing process of the mask can be performed after the open area is formed by exposure, etc. And plating can be performed on the open area of ​​the mask. That is, a plating layer can be formed corresponding to the position of each electrode portion. For example, various processes such as chemical plating can be applied to the plating layer. Next, after removing the mask, etching can be performed on a portion or the entire area corresponding to the first wiring portion. The etching on a portion of the area can be performed using an additional mask, etc. Accordingly, a first wiring section can be formed.

[0122] And as described above, after the insulating member (DM') is formed, the second insulating layer (112) can be laminated. A plating layer may be formed on the second insulating layer (112). And as described above, a mask may be formed and patterning may be performed on the mask. At this time, the mask may be placed in an area other than a via for the via electrode. And a via may be formed in the second insulating layer (112) by a method such as etching. The via may be formed by various methods. For example, via formation may be performed by a laser. And as described above, plating may be performed on the via and removal of the plating layer may be performed. The above-described contents may be applied to the formation of such an electrode portion.

[0123] Referring to FIGS. 7d ​​and 7e, a plating layer or additional insulating layer may be further laminated on the second insulating layer. Furthermore, a pad for electrical connection may be formed on the top of the insulating layer.

[0124] After the first electrode portion is formed on the second insulating layer, the edges of the insulating member may be trimmed and the interior may be detached to form a through hole. For example, to form the through hole, trimming may be performed along the edges of the lower insulating member (DM'). At this time, trimming may be performed in segments.

[0125] For example, trimming can be performed up to the insulating member (DM'). Then, the insulating layer and electrode portion located inside the area where trimming is performed and the insulating member (DM') exposed by trimming can all be separated from the first insulating layer.

[0126] As another example, primary trimming can be performed up to the first electrode portion located on the upper portion of the insulating member (DM'). In particular, a metal line for performing trimming can be formed in an area vertically overlapping the insulating member (DM'). The primary trimming can be performed up to the metal line.

[0127] Secondary trimming can be performed up to the upper surface of the first insulating layer (111). The aforementioned metal line can be removed. Accordingly, the insulating member (DM') can be penetrated or removed by the secondary trimming.

[0128] Referring to Fig. 8b, trimming may be performed corresponding to each insulating member. That is, trimming may be performed along the edge of the insulating member (DM') corresponding to the aforementioned mounting area (CA). Trimming may not be performed for the non-mounting area (NCA). In addition, such trimming may expose the upper surface of the first insulating layer.

[0129] Referring to Fig. 7f, the insulating layer and insulating member located within the trimmed area can be separated. Accordingly, a through hole (TH) or cavity can be formed. As described above, the insulating member (DM) embedded in the inner wall of the through hole (TH) (or cavity) may remain.

[0130] Referring to Fig. 7g, unlike Fig. 7f, the insulating layer and the insulating member located inside the area where trimming is performed can be separated. As in Fig. 7f, a through hole (TH) or a cavity may be formed. However, there may not be an insulating member that vertically overlaps the through hole (TH). That is, the second region may not exist. For example, when the through hole or cavity is formed, the second region may be separated, or the second region may be removed by a laser or the like. Accordingly, for example, the second region of the insulating member may remain in some areas, and the second region of the insulating member may not exist in other areas.

[0131] Additionally, a protective layer may be formed on the uppermost insulating layer. Furthermore, an opening area may be formed in the protective layer for electrical connection to a chip or substrate, etc.

[0132] In addition, as shown in Fig. 8c, trimming can be performed to separate insulating members, insulating layers, etc. located inside the exposed first insulating layer (111). The separation can be performed sequentially or in batches for the area where trimming is performed.

[0133] In the area where detachment is performed, the upper surface of the first insulating layer (111) and the first wiring portion (121a) may be exposed by the through hole (TH). In addition, the insulating member (DM) may also be positioned on the first insulating layer (111) along the edge of the through hole (TH).

[0134] And in some areas, only trimming may be performed. In areas where only trimming is performed, the insulating material (DM') may be exposed by the ring-shaped groove or inner wall (IP) of the planar closed loop.

[0135] FIG. 9 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, FIG. 10 is an enlarged view of K2 in FIG. 9, and FIG. 11 is a plan view of a circuit board according to a second embodiment of the present invention.

[0136] Referring to FIGS. 9 to 11, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and an insulating member (DM). Furthermore, the circuit board (100) may further include a protective layer (not shown) disposed on the electrode portion (120), and a semiconductor chip disposed within a through hole (TH). Except for the contents described below, the above-described contents may be equally applied.

[0137] According to the present embodiment, the insulating member (DM) may include only the first region. The insulating member (DM) may not overlap with the through hole (TH) or the cavity in the vertical direction (X-axis direction). In addition, the end surface of the insulating member (DM) may be flush with the inner wall (IP) of the through hole (TH).

[0138] Accordingly, the length (L2) in the horizontal direction (Y-axis direction) from the end surface of the insulating member (DM) to the first wiring portion inside the through hole (TH) may be the same as the length (L1) in the horizontal direction (Y-axis direction) from the inner wall (IP) to the first wiring portion inside the through hole (TH).

[0139] And the maximum length of the through hole (TH) or the gap (gap1) between the facing inner walls (IP) may be equal to the gap (gap2) between the facing insulating members.

[0140] Fig. 12 is a cross-sectional view of a circuit board according to a modified example of Fig. 10, and Fig. 13 is a plan view of a circuit board according to a modified example of Fig. 10.

[0141] Referring to FIGS. 12 and 13, a circuit board (100B) according to a modified example may include an insulating layer (110), an electrode portion (120), and an insulating member (DM).

[0142] In this modified example, the insulating member (DM) may be embedded outside the through hole (TH) with respect to the inner wall (IP) of the through hole (TH). That is, one end of the insulating member (DM) may be spaced apart from the area closest to the center of the through hole (TH) on the inner wall (IP). In addition, the minimum distance in the horizontal direction between the inner wall (IP) and the first wiring portion (121a) within the through hole (TH) may be smaller than the minimum distance in the horizontal direction between the first wiring portion (121a) within the through hole (TH) and the insulating member (DM).

[0143] In addition, the insulating member (DM) may be positioned misaligned with the through hole (TH) in the vertical direction (X-axis direction). Furthermore, the insulating member (DM) may also be misaligned with at least a portion of the second insulating layer (112) in the vertical direction. For example, the second insulating layer may be positioned in a horizontal region between the insulating member (DM) and the first wiring portion (121a) in the through hole (TH). Along the horizontal direction, one end of the second insulating member (DM) closest to the first wiring portion (121a) in the through hole (TH), a portion of the second insulating layer (112), and the first wiring portion (121a) may be arranged in this order (or in the opposite order).

[0144] Accordingly, the insulating member (DM) may not be exposed by the through hole (TH). The upper surface of the first insulating layer (111) exposed by the through hole (TH) and the insulating member (DM) may be spaced apart from each other in the horizontal direction.

[0145] This configuration increases the exposed surface area of ​​the first insulating layer, thereby securing space for electrical connections. Furthermore, it can provide improved cleaning effects by allowing the cleaning agent to accumulate in processes such as desmear.

[0146] Fig. 14 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, and Fig. 15 is an enlarged view of K3 in Fig. 14.

[0147] Referring to FIGS. 14 and 15, a circuit board (100C) according to the third embodiment may include an insulating layer (110), an electrode portion (120), and an insulating member (DM). Furthermore, the circuit board (100) may further include a protective layer (not shown) disposed on the electrode portion (120), and a semiconductor chip disposed within a through hole (TH). Except for the contents described below, the above-described contents may be equally applied.

[0148] In a circuit board according to an embodiment, an insulating member (DM) may include an exposed surface exposed by a through hole (TH). The exposed surface may be located in a second region (AR2). In addition, an upper surface of the second region (AR2) may correspond to the exposed surface. In this case, the exposed surface may be vertically parallel to or misaligned with an upper surface of the first region (AR1). For example, the exposed surface may be located lower than the upper surface of the first region (AR1). Accordingly, the exposed surface may overlap with the through hole (TH) in a vertical direction (X-axis direction).

[0149] The exposed surface may include a groove (G) formed in a direction from the center of the through hole (TH) toward the edge. Alternatively, the second region may have a step portion. Accordingly, the exposed surface may also have a step structure. Accordingly, the second region (AR2) may have multiple regions with different thicknesses in the vertical direction.

[0150] Accordingly, the minimum thickness of the first region (AR1) and the minimum thickness of the second region (AR2) may be different. The minimum thickness of the first region (AR1) may be greater than the minimum thickness of the second region (AR2). In addition, at least a portion of the upper surface (or exposed surface) of the second region (AR2) may be positioned lower than the upper surface of the first region (AR1). By this configuration, when a mold or the like is formed within the through hole (TH) after the chip is mounted in the through hole (TH) and electrically connected to the first wiring portion, the contact area with the insulating member may increase. As a result, the reliability of the circuit board may be improved.

[0151] Additionally, the minimum thickness in the second region (AR2) may be different from the thickness of the first wiring portion (121a). As a result, damage to the first wiring portion (121a) can be easily suppressed.

[0152] Fig. 16 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, and Fig. 17 is an enlarged view of K4 in Fig. 16.

[0153] Referring to FIGS. 16 and 17, a circuit board (100D) according to the fourth embodiment may include an insulating layer (110), an electrode portion (120), and an insulating member (DM). Furthermore, the circuit board (100) may further include a protective layer (not shown) disposed on the electrode portion (120), and a semiconductor chip disposed within a through hole (TH). Except for the contents described below, the above-described contents may be equally applied.

[0154] In particular, in the present embodiment, the insulating layer (110) may include a first insulating layer (111) which is a core layer, an upper build-up layer (UB), and a lower build-up layer (LB). The upper build-up layer (UB) and the lower build-up layer (UB) may each include a plurality of insulating layers. For example, the upper build-up layer (UB) may include a second insulating layer (112) to a fifth insulating layer (115). The lower build-up layer (LB) may include a sixth insulating layer (116) to a ninth insulating layer (119). The number of each insulating layer of the build-up layer and the number of electrode portions within the insulating layer may be changed depending on the thickness or design of the substrate. For example, the first insulating layer (111) may be a copper clad laminate (CCL). And the other insulating layers may be made of PPG.

[0155] Furthermore, the thickness (Ta) of the first insulating layer (111), which is the core layer, may be greater than the thickness (Tb) of the second insulating layer (112) on the first insulating layer (111). Furthermore, a plurality of insulating layers having a thinner thickness than the first insulating layer (111) may include a through hole (TH) (or cavity). The through hole (TH) may be formed in the upper build-up layer (UB) and / or the lower build-up layer (LB). The first wiring portion (121a) exposed by the through hole (TH) may be electrically connected to a chip mounted in the through hole (TH). In addition, the upper surface of the first insulating layer (111), which is the core layer, may be exposed by the through hole (TH). In addition, the insulating member (DM) may be located between the upper surface of the first insulating layer (111), which is the core layer, and the upper surface of the second insulating layer (112). And the insulating member (DM) is in contact with the upper surface of the first insulating layer (111) and can be embedded in the inner wall of the through hole (TH). Thus, as the type and number of components in a substrate applied to high-performance communications increase, even if the size and thickness of the circuit board increase, a cavity or through hole can be easily formed in the insulating layer while maintaining the thickness of the substrate as thin as possible.

[0156] In addition, although the via electrodes of each insulating layer are depicted as being connected while vertically overlapping each other in the drawing, it is not limited to this structure. In other words, it should be understood that the wiring section of each insulating layer is electrically connected to the wiring section or via electrode of another insulating layer through the via electrode.

[0157] Fig. 18 is a photograph of a cross-section of a first insulating layer, a second insulating layer, a through hole, and an insulating member in a circuit board according to an embodiment. Furthermore, Fig. 18 shows a photograph of an insulating layer, CCL, laminated on the second insulating layer (112) instead of the third and fourth insulating layers.

[0158] Referring to Fig. 18, as described above, an insulating member (DM) is embedded in the inner wall (IP) of the through hole (TH). Furthermore, it can be seen that a first region (AR1) of the insulating member (DM) is misaligned vertically with respect to the cavity. Furthermore, a second region (AR2) may be exposed by the through hole (TH).

[0159] And the first region (AR1) may have a wider width in the horizontal direction than the second region (AR2). The first wiring portion, etc., arranged on the upper surface of the first insulating layer (111) exposed by the through hole (TH) may not be covered by the insulating layer. As a result, since almost no residue of the insulating material remains, the deterioration of electrical characteristics due to residue of the insulating material during peeling can be suppressed. Furthermore, a cavity can be easily formed by peeling only the insulating material.

[0160] Additionally, the semiconductor package may include a connecting member.

[0161] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and can be placed between the semiconductor elements and the circuit board. For example, the connecting member can be embedded in the circuit board, or can be placed on the circuit board. When embedded in the circuit board, it can have the advantage of reducing the thickness of the semiconductor package. The connecting member can be formed of silicon, but is not limited thereto, and can be formed of an organic material, and since it functions to electrically interconnect a plurality of semiconductor elements, it can be referred to as a bridge.

[0162] Additionally, the connecting member may be placed on a circuit board. When placed on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a redistribution layer may be placed between the molding member and the semiconductor element.

[0163] The connecting member may be referred to as a bridge substrate. For example, the connecting member may include a redistribution layer and may function to horizontally electrically connect a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device must have is generally very large, the connecting member may include a redistribution layer. Since the semiconductor package and the semiconductor device have greatly different circuit pattern widths and widths, a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width and width of the circuit pattern of the semiconductor package and the width and width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0164] Furthermore, the circuit board according to the embodiment can be divided into a package substrate and an interposer corresponding to the lower substrate according to the function of the circuit board, and applied thereto. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the area of ​​the circuit board increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of a circuit board with a high number of laminated layers, the yield of the circuit board can be improved by separating it into an interposer and a package substrate. In addition, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads of the package substrate having an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0165] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0166] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0167] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0168] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0169] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0170] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer and including a through hole; and Including an insulating member at least partially embedded in the inner wall forming a through hole of the second insulating layer; The insulating member includes a first region embedded in the inner wall, and a second region disposed inside the through hole, A circuit board having a width in the horizontal direction of the first region greater than a width in the horizontal direction of the second region.

2. In paragraph 1, A circuit board including a first electrode portion disposed on the upper surface of the first insulating layer.

3. In paragraph 2, A circuit board in which the vertical thickness of the insulating member is greater than or equal to the vertical thickness of the first electrode portion.

4. In paragraph 2, A circuit board in which the first electrode portion is misaligned in a vertical direction with respect to the insulating member.

5. In paragraph 1, A circuit board in which the through hole of the second insulating layer exposes the upper surface of the first insulating layer.

6. In paragraph 1, Each of the first insulating layer and the second insulating layer includes an upper surface and a lower surface, A circuit board in which the insulating member is disposed between the upper surface of the first insulating layer and the lower surface of the second insulating layer along the edge of the through hole.

7. In paragraph 1, The first region overlaps the second insulating layer in a vertical direction, The second region is a circuit board that is misaligned in the vertical direction with the second insulating layer.

8. In paragraph 1, The above second region is a circuit board that vertically overlaps the through hole.

9. In paragraph 1, A circuit board wherein the minimum thickness of the first region is greater than the minimum thickness of the second region.

10. In paragraph 1, The above insulating member is a circuit board that is misaligned in a vertical direction with respect to the through hole.

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