Ferroelectric semiconductor devices and methods of fabricating thereof

Abstract

Described herein is a method of fabricating a ferroelectric material, comprising the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized surface to provide a film; and annealing the film at a temperature between 700°C and 900°C, thereby forming a metal oxide layer on top of the semiconductor substrate, wherein the interface between the semiconductor substrate and the metal oxide layer does not contain any remnant oxidized surface, and a ferroelectric material and a ferroelectric transistor or capacitor comprising said ferroelectric material.

Description

[0001]Attorney Docket No.047162-5365-00WO TITLE OF THE INVENTION FERROELECTRIC SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THEREOF CROSS REFERENCE TO RELATED APPLICATIONS The present application claims priority to U.S. Provisional Patent Application No. 63 / 649,705, filed May 20, 2024, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION The total energy of computing is exponentially growing and rapidly approaching the world’s total energy production, even with innovations that continue to improve the energy efficiency of computing. This challenge arises from the sheer speed at which the demand for computing is increasing and the fact that it is becoming increasingly challenging to make energy-efficient devices out of conventional transistors. The main challenge with present transistors and ferroelectric materials is growing a suitable material that is 1) sufficiently thin to allow for aggressive scaling of devices, 2) easily fabricated using commercial semiconductor fabrication process, and 3) reliably fabricated over a large Silicon (Si) wafer area. Well-studied ferroelectric materials to date such as BaTiO3and Zr- doped HfO2each have limitations in the above aspects. For example, BaTiO3is reported to be ferroelectric at 1 nanometer (nm)-thickness but only when grown on a specific oxide substrate NdGaO3. This makes the BaTiO3impractical as the ability to grow on Si is crucial for commercialization and BaTiO3is in general challenging to grow on Si. The Zr-doped HfO2has been integrated with Si and is reported to be ferroelectric at the thickness of 1 nm. However, it needs to be grown on at least 1 nm thick SiO2 on top of Si, which increases the total thickness of the system to at least 2 nm. Moreover, both systems as well as majority of the reported ferroelectric oxide systems need to be “epitaxial”, which complicates the growth of these materials to varying degrees. Thus, there is a need in the art for compositions and methods for energy-efficient transistors and ferroelectric materials. This invention satisfies this unmet need. Attorney Docket No.047162-5365-00WO SUMMARY OF THE INVENTION Discussed herein are methods of fabricating a ferroelectric material, comprising the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized surface to provide a film; and annealing the film at a temperature between 700˚C and 900˚C, thereby forming a metal oxide layer on top of the semiconductor substrate, wherein the interface between the semiconductor substrate and the metal oxide layer does not contain any remnant oxidized surface. In some examples, the metal is deposited in a single layer of lattice unit cells. In some examples, the step of annealing the film comprises the step of heating the film to a temperature of about 750˚C. In some examples, the semiconductor substrate comprises silicon. In some examples, the semiconductor substrate comprises germanium. In some examples, the step of treating the semiconductor substrate with an oxidant comprises the step of treating the semiconductor substrate with ultraviolet radiation and ozone. In some examples, the metal is selected from the group consisting of zirconium, hafnium, and combinations thereof. In some examples, the metal is zirconium. Also discussed herein is a ferroelectric material produced using the method. Further discussed herein is a ferroelectric material, comprising: a silicon substrate; and a ferroelectric layer comprising at least one metal oxide; wherein the ferroelectric layer is a single layer of lattice unit cells; and wherein the interface between the silicon substrate and the ferroelectric layer does not comprise silicon oxide. In some examples, the silicon substrate is a wafer. In some examples, the at least one metal oxide comprises an oxide of a metal selected from the group consisting of zirconium, hafnium, and combinations thereof. In some examples, the at least one metal oxide comprises ZrO2. In some examples, the ferroelectric layer has a thickness of a single atomic monolayer. In some examples, the ferroelectric material further comprises a gate oxide. In some examples, the gate oxide is Al2O3. Also discussed herein are applications of the ferroelectric material, including but not limited to, ferroelectric transistors and capacitors comprising the ferroelectric material. Attorney Docket No.047162-5365-00WO BRIEF DESCRIPTION OF THE DRAWINGS The following detailed description of embodiments of the invention will be better understood when read in conjunction with the appended drawings. It should be understood that the invention is not limited to the precise arrangements and instrumentalities of the embodiments shown in the drawings. Fig.1, depicts a novel process disclosed herein for growing the thinnest possible ferroelectric material directly on Silicon (Si) substrate. Fig.2, comprising Fig.2A and Fig.2B, depicts capacitance-voltage (C-V) curves. Fig. 2A depicts C-V measurements for Al2O3 / Si. Fig.2B depicts C-V measurements for Al2O3 / ML ZrO2 / Si. Different curves correspond to different thickness of the Al2O3layer. The measurements are done at 1 MHz frequency and 50 nm thick Pt is deposited on top of the Al2O3 as the electrode. The Pt pad is 120 um in diameter. Fig.3 depicts 1 / Coxvs. Al2O3Thickness for Al2O3 / Si films for Pt pad diameters of 90 and 120 um. Dashed lines indicate linear fit of the data for the 5 ~ 20 nm thickness. Fig.4 depicts 1 / Cox vs. Al2O3 Thickness for Al2O3 / ML ZrO2 / Si films, with Pt pad diameters of 90 and 120 um. Dashed lines indicate linear fit of the data for the 5 ~ 20 nm thickness. Fig.5 depicts flatband voltages of Al2O3 / Si. The measurements were done at 1 MHz frequency and 50 nm thick Pt was deposited on top of the Al2O3as the electrode. The Pt pad was 120 um in diameter. Horizontal and vertical dashed lines indicate the flatband capacitances and voltages, respectively. Fig.6, comprising Fig.6A through Fig.6D, depicts experimental measurements for Al2O3 / ML ZrO2 / Si. Fig.6A depicts measured C-V. Fig.6B depicts extracted ^^. Fig.6C depicts extracted P-V curves. Fig.6D depicts extracted P-Eoxcurves for Al2O3 / ML ZrO2 / Si. The measurements were done at 1 MHz frequency and 50 nm thick Pt was deposited on top of the Al2O3 as the electrode. The Pt pad was 120 um in diameter. Dotted lines in Fig.6B and Fig. 6C correspond to the negatively going voltage sweep. Fig.7 depicts C-V curves as a function of reaction temperature for Zr + SiO2-> Si + ZrO2. Attorney Docket No.047162-5365-00WO DETAILED DESCRIPTION Definitions Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used herein, each of the following terms has the meaning associated with it in this section. The articles “a” and “an” are used herein to refer to one or to more than one (i.e., to at least one) of the grammatical object of the article. By way of example, “an element” means one element or more than one element. “About” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, ±1%, or ±0.1% from the specified value, as such variations are appropriate to perform the disclosed methods. Throughout this disclosure, various aspects of the invention can be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible sub-ranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 2.7, 3, 4, 5, 5.3, and 6. This applies regardless of the breadth of the range. This disclosure provides novel ferroelectric materials, compositions comprising such materials, and methods of making such materials, derived, in part, from the unexpected result that ferroelectric materials grown using the disclosed method may have thicknesses of less than or about the thickness of a single atomic monolayer with a clean interface between the grown ferroelectric material and semiconductor substrate. The novel materials and methods described herein are uniquely suited for use in / on capacitors or transistors such as ferroelectric transistor (FeFET). FeFET incorporates Attorney Docket No.047162-5365-00WO ferroelectric material which has polarization that can be switched into “up” or “down” directions by applying external voltage. Once switched, this polarization retains the direction even when the external voltage is no longer applied. When incorporated into a transistor to create a FeFET, the non-volatile characteristic of a ferroelectric material allows the FeFET to retain “on” state even without continuously applying external power. This significantly reduces the power consumption of the transistor. Also, this allows the FeFET to be used simultaneously as a non- volatile memory, allowing in-memory computing architecture that can further reduce power consumption. In some examples, the method involves depositing only the Zr metal on top of thin silicon oxide (SiO2) covered silicon (Si) and annealing to form the monolayer zirconium oxide (ZrO2) and remove SiO2 simultaneously. This process leaves ZrO2 on Si with an interface that is abrupt and clean (no presence of remnant SiO2), which is important for the ferroelectric properties. This process solves the aforementioned challenges as it 1) produces the thinnest possible ferroelectric material system (thickness in between 0.5 nm and 1 nm) that is highly scalable, 2) can be incorporated into current conventional semiconductor fabrication processes easily, and 3) can reliably produce ferroelectric films over a large Si wafer area. The disclosed film growth can be considered unusual and novel for the following reasons. First, the majority of the films grown on Si involve either growing on SiO2covered Si or on a buffer layer covered Si. This invention grows films directly on Si, which is both advantageous and nontrivial. In addition, the step wherein the SiO2 layer is deliberately reacted with the deposited zirconium (Zr) metal layer to form the final product is highly unusual. Typically, the SiO2layer is left intact in between the film layer and the Si substrate. It is widely believed that reacting two different layers at high temperatures to form the final product is a less ideal process compared to depositing only the final product on a clean surface. However, this process surprisingly shows that such a reactive growth leads to a functional ferroelectric film with a clean interface. In fact, the reacting temperature can be tuned to adjust the ferroelectric properties of this material system in a reproducible and well-defined manner. This process can grow ferroelectric materials that are at the ultimate thickness limit of only a single atomic layer. The thickness of the ferroelectric material grown with this invention is estimated to be 0.5 nm. For comparison, the thinnest ferroelectric material reported to date Attorney Docket No.047162-5365-00WO has thickness in range of 1.5 ~ 2 nm. Such reduction in thickness is possible because this process eliminates the SiO2 layer on top of Si substrate that is present for previously reported ferroelectric materials. Further, the process allows reliable fabrication of ferroelectric film that is only a single atomic layer thick. At the same time, this process is easy to incorporate into conventional semiconductor fabrication processes. At the ultrathin limit of a single atomic layer, it is often challenging to achieve homogeneous and functionally ferroelectric film reliably over a large wafer area. To achieve growth of ultrathin functional oxides, sophisticated and costly deposition methods such as molecular beam epitaxy (MBE) and pulsed laser deposition (PLD) are typically required. In addition, for depositing a single atomic layer, the substrate surface typically needs to be cleaned thoroughly using ultra-high vacuum (UHV) processes. Such requirements hinder integration into conventional semiconductor production. This process does not require UHV cleaning of the Si substrate prior to deposition. In the case of this invention, the Zr metal can be deposited on the SiO2 covered Si by e-beam deposition methods. Moreover, by controlling the annealing temperature, the ferroelectric properties of the film can be controlled in a repeatable and reliable fashion. Using advanced x-ray characterization techniques, it has been shown that key physical properties of the film such as Zr valence state and interface roughness can be reliably controlled. These properties are directly correlated to the ferroelectric performance of the material system. In addition, prototype capacitors fabricated using this invention are reliably ferroelectric over a wide area of almost 0.2 mm2. This invention is expected to enable practical manufacture of the ferroelectric material on Si using commercialized technologies. The monolayer ferroelectric ZrO2on Si grown using this invention can be easier to fabricate in scale with currently commercialized technologies and more reliably ferroelectric. This invention can lead to fabrication of FeFET devices that may show significantly lower power consumption, faster operation speed, and non-volatile functionality that enables in- memory computing. Such devices may replace significant portion of the devices based on conventional transistor designs. As this invention is easy to integrate into conventional semiconductor production, the cost of adopting this invention will be low for major Attorney Docket No.047162-5365-00WO semiconductor companies. The low cost of adoption can accelerate the commercialization of products using this invention. Ferroelectric Materials Described herein is a ferroelectric material, comprising: a semiconductor substrate; and a ferroelectric layer comprising at least one metal oxide; wherein the ferroelectric layer is a single layer of lattice unit cells. In some examples, the ferroelectric material comprises: a silicon substrate; and a ferroelectric layer comprising at least one metal oxide; wherein the ferroelectric layer is a single layer of lattice unit cells; and wherein the interface between the silicon substrate and the ferroelectric layer does not comprise silicon oxide. In some examples, the semiconductor substrate comprises silicon, aluminum, germanium, gallium, sapphire, indium, phosphorus, oxides thereof, or combinations thereof. In some examples, the semiconductor substrate comprises silicon. In some examples, the semiconductor substrate comprises germanium. In some examples, the semiconductor substrate comprises a metal which is easily oxidized. In some examples, the at least one metal oxide comprises an oxide of a metal selected from zirconium, hafnium, cerium, platinum, palladium, rhodium, barium, magnesium, aluminum, lead, titanium, lithium, niobium, potassium, sodium, molybdenum, and combinations thereof. In some examples, the at least one metal oxide is ZrO2. In some examples, the ferroelectric layer is crystalline. In some examples, the ferroelectric layer is amorphous. In some examples, the ferroelectric layer is polycrystalline. In some examples, the ferroelectric layer is noncentrosymmetric. In some examples, the ferroelectric layer is piezoelectric. In some examples, the ferroelectric layer is centrosymmetric. In some examples, the ferroelectric layer has a polar crystal structure. In some examples, the ferroelectric layer conducts electricity. In some examples, the ferroelectric layer is homogenous. In some examples, the ferroelectric layer partially covers the surface of the substrate. In some examples, the ferroelectric layer completely covers the surface of the substrate. In some examples, the ferroelectric layer covers both sides of a double-sided substrate. In some examples, the ferroelectric layer has a thickness of a single molecular layer or a partial molecular layer, wherein the value of the thickness of the layer is a direct result of the composition of the layer. For example, ferroelectric layer comprising ZrO2 may have a thickness Attorney Docket No.047162-5365-00WO which is different from a ferroelectric layer comprising HfO2 due to differences in atomic radii of zirconium and hafnium. In some examples, the ferroelectric layer has a thickness of less than about 15 Å. In some examples, the ferroelectric layer has a thickness of less than about 14 Å. In some examples, the ferroelectric layer has a thickness of less than about 13 Å. In some examples, the ferroelectric layer has a thickness of less than about 12 Å. In some examples, the ferroelectric layer has a thickness of less than about 11 Å. In some examples, the ferroelectric layer has a thickness of less than about 10 Å. In some examples, the ferroelectric layer has a thickness of less than about 9 Å. In some examples, the ferroelectric layer has a thickness of less than about 8 Å. In some examples, the ferroelectric layer has a thickness of less than about 7 Å. In some examples, the ferroelectric layer has a thickness of less than about 6 Å. In some examples, the ferroelectric layer has a thickness of less than about 5 Å. In some examples, the ferroelectric layer has a thickness of less than about 4 Å. In some examples, the ferroelectric layer has a thickness of less than about 3 Å. In some examples, the ferroelectric layer has a thickness of less than about 2 Å. In some examples, the ferroelectric layer has a thickness of less than about 1 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 12 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 11 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 10 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 9 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 8 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 7 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 6 Å. In some examples, the ferroelectric layer has a thickness of 1 Å to 5 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 12 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 12 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 10 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 9 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 8 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 7 Å. In some examples, the ferroelectric layer has a Attorney Docket No.047162-5365-00WO thickness of 2 Å to 6 Å. In some examples, the ferroelectric layer has a thickness of 2 Å to 5 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 10 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 9 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 8 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 7 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 6 Å. In some examples, the ferroelectric layer has a thickness of 3 Å to 5 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 10 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 9 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 8 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 7 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 6 Å. In some examples, the ferroelectric layer has a thickness of 4 Å to 5 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 14 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 13 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 15 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 10 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 9 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 8 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 7 Å. In some examples, the ferroelectric layer has a thickness of 5 Å to 6 Å. In some examples, the ferroelectric layer has a thickness of or less than about 1 Å. In some examples, the ferroelectric layer has a thickness of or less than about 2 Å. In some examples, the ferroelectric layer has a thickness of or less than about 3 Å. In some examples, the ferroelectric layer has a thickness of or less than about 4 Å. In some examples, the ferroelectric layer has a thickness of or less than about 5 Å. In some examples, the ferroelectric layer has a Attorney Docket No.047162-5365-00WO thickness of or less than about 6 Å. In some examples, the ferroelectric layer has a thickness of or less than about 7 Å. In some examples, the ferroelectric layer has a thickness of or less than about 8 Å. In some examples, the ferroelectric layer has a thickness of or less than about 9 Å. In some examples, the ferroelectric layer has a thickness of or less than about 10 Å. In some examples, the ferroelectric layer has a thickness of or less than about 11 Å. In some examples, the ferroelectric layer has a thickness of or less than about 12 Å. In some examples, the ferroelectric layer has a thickness of or less than about 13 Å. In some examples, the ferroelectric layer has a thickness of or less than about 14 Å. In some examples, the ferroelectric layer has a thickness of or less than about 15 Å. In some examples, an interface is present between the ferroelectric layer and the semiconductor substrate. In some examples, the interface does not contain any oxidized metal. In some examples, the interface does not contain any oxidized semiconductor substrate. In some examples, the interface does not contain any silicon oxide. In some examples, the interface does not contain any silicon dioxide. In some examples, a film may comprise the ferroelectric material. Any embodiment relating to the ferroelectric material described herein is equally applicable to any embodiment relating to a film comprising the ferroelectric material. In some examples, the ferroelectric material further comprises an additional dielectric layer. In some examples, the additional dielectric layer separates the gate terminal from the source and drain terminals. In some examples, the additional dielectric layer separates the gate terminal from the conductive channel. In some examples, the additional dielectric layer is formed by oxidizing the semiconductor substrate. In some examples, the additional dielectric layer is formed by thermal oxidation of the semiconductor substrate. In some examples, the additional dielectric layer is formed by thermal oxidation of a layer of metal. In some examples, the additional dielectric layer has a thickness of 1 to 200 nm. In some examples, the additional dielectric layer has a thickness of 5 to 200 nm. In some examples, the additional dielectric layer has a thickness of 10 to 200 nm. In some examples, the additional dielectric layer has a thickness of 15 to 200 nm. In some examples, the additional dielectric layer has a thickness of 20 to 200 nm. In some examples, the additional dielectric layer has a thickness of 25 to 200 nm. In some examples, the additional dielectric layer has a thickness of 30 to 200 nm. In some examples, the additional dielectric layer has a thickness of 35 to 200 nm. Attorney Docket No.047162-5365-00WO In some examples, the additional dielectric layer has a thickness of 40 to 200 nm. In some examples, the additional dielectric layer has a thickness of 45 to 200 nm. In some examples, the additional dielectric layer has a thickness of 50 to 200 nm. In some examples, the additional dielectric layer has a thickness of 55 to 200 nm. In some examples, the additional dielectric layer has a thickness of 60 to 200 nm. In some examples, the additional dielectric layer has a thickness of 65 to 200 nm. In some examples, the additional dielectric layer has a thickness of 70 to 200 nm. In some examples, the additional dielectric layer has a thickness of 75 to 200 nm. In some examples, the additional dielectric layer has a thickness of 80 to 200 nm. In some examples, the additional dielectric layer has a thickness of 85 to 200 nm. In some examples, the additional dielectric layer has a thickness of 90 to 200 nm. In some examples, the additional dielectric layer has a thickness of 95 to 200 nm. In some examples, the additional dielectric layer has a thickness of 100 to 200 nm. In some examples, the additional dielectric layer has a thickness of 110 to 200 nm. In some examples, the additional dielectric layer has a thickness of 120 to 200 nm. In some examples, the additional dielectric layer has a thickness of 130 to 200 nm. In some examples, the additional dielectric layer has a thickness of 140 to 200 nm. In some examples, the additional dielectric layer has a thickness of 150 to 200 nm. In some examples, the additional dielectric layer has a thickness of 160 to 200 nm. In some examples, the additional dielectric layer has a thickness of 170 to 200 nm. In some examples, the additional dielectric layer has a thickness of 180 to 200 nm. In some examples, the additional dielectric layer has a thickness of 190 to 200 nm. In some examples, the additional dielectric layer has a thickness of 1 to 100 nm. In some examples, the additional dielectric layer has a thickness of 5 to 100 nm. In some examples, the additional dielectric layer has a thickness of 10 to 100 nm. In some examples, the additional dielectric layer has a thickness of 15 to 100 nm. In some examples, the additional dielectric layer has a thickness of 20 to 100 nm. In some examples, the additional dielectric layer has a thickness of 25 to 100 nm. In some examples, the additional dielectric layer has a thickness of 30 to 100 nm. In some examples, the additional dielectric layer has a thickness of 35 to 100 nm. In some examples, the additional dielectric layer has a thickness of 40 to 100 nm. In some examples, the additional dielectric layer has a thickness of 45 to 100 nm. In some examples, the additional dielectric layer has a thickness of 50 to 100 nm. In some examples, the additional dielectric layer has a thickness of 55 to 100 nm. In some examples, the additional dielectric layer has a thickness of 60 to 100 nm. In some examples, the Attorney Docket No.047162-5365-00WO additional dielectric layer has a thickness of 65 to 100 nm. In some examples, the additional dielectric layer has a thickness of 70 to 100 nm. In some examples, the additional dielectric layer has a thickness of 75 to 100 nm. In some examples, the additional dielectric layer has a thickness of 80 to 100 nm. In some examples, the additional dielectric layer has a thickness of 85 to 100 nm. In some examples, the additional dielectric layer has a thickness of 90 to 100 nm. In some examples, the additional dielectric layer has a thickness of 95 to 100 nm. In some examples, the ferroelectric material further comprises a gate oxide. In some examples, the gate oxide comprises an oxide of a metal selected from aluminum, silicon, tungsten, molybdenum, tantalum, or titanium. In some examples, the gate oxide is Al2O3. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 1.0 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.9 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.8 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.7 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.6 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.5 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.4 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.3 mm2. In some examples, the ferroelectric material is ferroelectric over an area of about 0.1 mm2to about 0.2 mm2. In some examples, provided herein is a ferroelectric transistor comprising a ferroelectric material described herein. In some examples, the ferroelectric material is non-volatile. In some examples, provided herein is a capacitor comprising a ferroelectric material described herein. Method of Making a Ferroelectric Material Also described herein is a method of fabricating a ferroelectric material, comprising the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized surface to provide a film; and annealing the film. For example, the method of fabricating a ferroelectric material may comprise the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized Attorney Docket No.047162-5365-00WO surface to provide a film; and annealing the film at a temperature between 700˚C and 900˚C, thereby forming a metal oxide layer on top of the semiconductor substrate, wherein the interface between the semiconductor substrate and the metal oxide layer does not contain any remnant oxidized surface. Fig.1 depicts a flowchart of an exemplary process 100 for growing the thinnest possible ferroelectric material directly on semiconductor substrate. In some examples, the ferroelectric material is a single atomic layer (monolayer) of a metal oxide. The process in detail is as follows: the first step 110 is to clean a semiconductor substrate, such as a wafer of semiconductor substrate, using techniques such as conventional wet-etching techniques. Next, in step 120 a thin (below 1 nm) metal oxide layer is regrown on top of the cleaned wafer to form an oxidized surface. In step 130, a monolayer of metal is then deposited on top of the oxidized surface, using a technique such as e-beam deposition. Lastly, in step 140, the film consisting of metal-oxidized surface-semiconductor substrate is annealed at an optimal temperature that allows a reaction of the elemental metal and metal oxide. This final step leaves a clean interface between the two layers. In step 110, the semiconductor substrate comprises silicon, aluminum, germanium, gallium, sapphire, indium, phosphorus, oxides thereof, or combinations thereof. In some examples, the semiconductor substrate comprises silicon. In some examples, the semiconductor substrate comprises a metal which is easily oxidized. In some examples, the semiconductor substrate is a flat surface. In some examples, the semiconductor substrate is curved. In some examples, the semiconductor substrate is double- sided. In some examples, step 110 is performed by submerging the semiconductor substrate in an etchant. Exemplary etchants include, but are not limited to, Piranha solution, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, potassium hydroxide, ammonium fluoride, and buffered oxide solution. In step 120, the metal oxide layer is regrown on top of the cleaned wafer by treating the semiconductor substrate with an oxidant to form an oxidized surface. Exemplary oxidants and methods of oxidation include, but are not limited to, ultraviolet (UV) radiation, ozone, UV- ozone exposure, and molecular oxygen. In some examples, step 120 is performed in the absence of solvent. In some examples, step 120 is performed using a chemical oxidant. Exemplary Attorney Docket No.047162-5365-00WO chemical oxidants include, but are not limited to, ozone, peroxides, strong inorganic acids, oxygen, perborates, oxides, nitrates, hypochlorite, bleach, and halogens. In some examples, only a section of the surface of the semiconductor substrate is treated with an oxidant. In some examples, the entirety of the surface of the semiconductor substrate is treated with an oxidant. In some examples, both sides of a double-sided semiconductor substrate are treated with an oxidant. In some examples, the semiconductor substrate is treated prior to treating the semiconductor substrate with an oxidant. In step 130, the metal is selected from the group consisting of zirconium, hafnium, cerium, platinum, palladium, rhodium, barium, magnesium, aluminum, lead, titanium, lithium, niobium, potassium, sodium, and molybdenum. In some examples, the metal is zirconium. In some examples, the metal is deposited using e-beam deposition. In some examples, the metal is deposited using molecular beam epitaxy. In some examples, the metal is deposited using pulsed layer deposition. In some examples, the metal is deposited using any deposition method known in the art. In some examples, the substrate is cleaned prior to the deposition of the metal. In some examples, the metal is deposited in a single layer of lattice unit cells. In step 140, the film is heated to a temperature of at least 500˚C. In some examples, the film is heated to a temperature of 500˚C to 1000 ˚C. In some examples, the film is heated to a temperature of 600˚C to 1000 ˚C. In some examples, the film is heated to a temperature of 700˚C to 1000 ˚C. In some examples, the film is heated to a temperature of 500˚C to 900 ˚C. In some examples, the film is heated to a temperature of 600˚C to 900 ˚C. In some examples, the film is heated to a temperature of 700˚C to 900 ˚C. In some examples, the film is heated to a temperature of 750˚C to 900 ˚C. In some examples, the film is heated to a temperature of 700˚C to 800 ˚C. In some examples, the film is heated to a temperature of about 750˚C. In some examples, step 140 induces a chemical reaction between the oxidized surface and the metal. In some examples, the chemical reaction forms a metal oxide layer on top of the semiconductor substrate. In some examples, the interface between the metal oxide layer and the semiconductor substrate does not contain any remnant oxidized surface. The ferroelectric material described herein may also be produced using the method. EXPERIMENTAL EXAMPLES Attorney Docket No.047162-5365-00WO The invention is further described in detail by reference to the following experimental examples. These examples are provided for purposes of illustration only, and are not intended to be limiting unless otherwise specified. Thus, the invention should in no way be construed as being limited to the following examples, but rather, should be construed to encompass any and all variations which become evident as a result of the teaching provided herein. Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the following illustrative examples, make and utilize the present invention and practice the claimed methods. The following working examples therefore are not to be construed as limiting in any way the remainder of the disclosure. Example 1: Development of a Monolayer Ferroelectric ZrO2 Extracting ML ZrO2 Dielectric Constant The present experiments were developed from continued efforts to obtain polarization data for the monolayer (ML) ZrO2-Si system. The problem was approached as follows. The thickness of the Al2O3 layer in the Al2O3 / ML ZrO2 / Si film stacks was varied to obtain the Al2O3and ML ZrO2dielectric constants and obtain the polarization – voltage (P-V) loop. Using the measured capacitance – voltage (C-V) curves of the ML ZrO2system, the P-V loop was derived as a function of a-Al2O3 thickness, which indicated spontaneous polarization of at least 20 μC / cm2in the ML ZrO2. The Al2O3dielectric constant was extracted from a set of C-V curves (Fig.2A) with varying Al2O3thickness by fitting the 1 / Coxvs. Al2O3thickness data (Fig.3). The dielectric constant derived from the linear fit is about 11, which is similar to the values for bulk Al2O3. However, the dielectric constant drops to about 6 for 3 nm thick Al2O3. Applying the same process to a set of C-V curves for ML ZrO2with varying Al2O3thickness (Fig.2B), the dielectric constant of ML ZrO2 was extracted. The 1 / Cox vs. Al2O3 values for the ML ZrO2 films were found to have a linear fit (Fig.4), where the following equation is the oxide capacitance inaccumulation for the Al2O3 / monolayer (ML) ZrO2 / Si film stack.ି^^ = ^ ௗಲ^మೀయ + ௗೋ^ೀమ Attorney Docket No.047162-5365-00WO From the fit, the average value of ML ZrO2 dielectric constant was estimated to be 22. Like data for the a-Al2O3 only measurements, it was seen that for 3 nm thick Al2O3, the ML ZrO2 measured dielectric constant drops. Obtaining ML ZrO2 P-V Curve from the C-V Measurements To explore ferroelectric properties of the ML ZrO2– Si system, a polarization – voltage (P-V) loop was extracted from the measured C-V curves. This can be done using the following relations: ఙೞ ௗೋ^^ = ^^ − ^^^ − ^൫ ^^൯ ^ೀమఌబఌೋ^ೀమ + ி^^, (1)(5) isthe capacitance of the Si surface, and ^^is the Si surface potential. Rearranging equation (1), polarization was obtained as a function of the gate voltage: ^൫ ൯ = ఌబఌೋ^ೀమ ఙೞ^^ ^^^ −^^ + ி^^ − ^. (7) First, ^^was calculated as a function of the gate voltage using equation (3) and the measured C-V curve. Then, equation (4) is used to obtain ^^as a function of^^. For each value of ^^, equation (5) is solved to obtain ^^. It was noted that the Coxhas been fit for each Attorney Docket No.047162-5365-00WO thickness to match so that ^^in accumulation is the same for each thickness, which should solely depend on the Si doping level. For this adjustment, the ^^^ଶைଷ values in equation (2) were varied, while the ^^^ைଶ and^^^ைଶ values were kept constant at 1 nm and 20 respectively. The fitted ^^^ଶைଷ values were 9.88,9.18, 10.46, 10.1, and 6.35 for Al2O3 thicknesses of 20, 15, 10, 5, and 3 nm respectively. Finally, the flatband voltages ( ி^^) were calculated using the C-V data from Al2O3 on Sifilms following a previously described procedure (Dogan et al., 2018, Nano Lett., 18, 241). CFB / Coxvalues were first calculated, wherein the flat band capacitance (per area) wascalculated using the following equation:−1^ 1 ^ ^ி^ = ൬^^^ + ^ ^^2^^(^^−^^)^ ,^ௌis the Si dielectric constant, e is the electron charge,^^andௗ^are acceptor and donordensities in Si respectively. For the p-type Si substrates used in this experiment, ^^ ≅8.5 × 1018^^ିଷ and ௗ^ ≅ 0. From the obtained CFB / Cox values, the flatband voltage VFB waslocated on the measured C-V curves. Table 1 shows the flatband voltages obtained for various Al2O3 films. The flatband capacitances and voltages are marked on the C-V curves in Fig.5. Table 1. Flatband voltages for Al2O3 / Si films with varying thickness. Al2O3 Thickness (nm) Cox (mF / m2) CFB (mF / m2) CFB / Cox VFB (V) 20 4.425 4.174 0.943 -0.17 14.7 6.020 5.566 0.924 -0.16 9.7 9.124 8.118 0.900 -0.12 5.1 17.353 14.045 0.809 -0.06 3.4 26.029 19.233 0.739 0.46 Using the above information and equation (8), the P-V loops for Al2O3 / ML ZrO2 / Si were obtained for Al2O3 thickness ranging from 10 to 20 nm (Fig.6). These thicknesses were fully analyzed because the leakage current for the 3.4 and 5.1 nm-thick a-Al2O3was large and affected the analysis. It was noted that this P-V loop is a partial loop, since the full range of ^^cannot be extracted from the high-frequency C-V data deep into accumulation and inversion. The capacitance calculated from equations (3), (4), and (5) describe quasi-static capacitance. Thus, by using the high-frequency C-V data and the above equations, ^^in the inversion region Attorney Docket No.047162-5365-00WO could not be extracted. The remaining portion of the P-V loop could be obtained by doing similar experiments using n-type Si. The downward slope in ^^and divergence of P near the negative end of the Vgsweep range was since the ^^is calculated from Cs in equation (4), which diverges as measured C approaches Coxnear the end of the voltage sweep range. The polarization P vs. total field in the oxide layers (ZrO2+ Al2O3) was plotted (Fig.6D), which suggested estimated coercive field on the order of 2 MV / cm. The extracted P-V curves show spontaneous polarization of about 50 μC / cm2for the ML ZrO2. The consistency of the polarization as a function of thickness indicates a characteristic P- V loop of the ML ZrO2interface. These values are estimates since the shift in the P-V curve cannot be determined from a partial P-V loop. For more accurate determination of the spontaneous polarization, similar analysis using quasi-static C-V measurements or high- frequency C-V measurements on n-type Si are needed. Further, C-V measurements performed on a MOS capacitor stack (Pt (50 nm) / Al2O3(2.6 nm) / ML ZrO2 / Si (001) indicated an optimal reaction temperature of 750˚C (Fig.7). This example is concluded by reporting the following properties of ML ZrO2. Importantly, the consistency of the polarization as a function of thickness indicates a characteristic P-V loop of the ML ZrO2 interface. The ML ZrO2 dielectric constant is estimated to be 22, from the C-V measurements of Al2O3 / ML ZrO2 / Si with varying Al2O3thickness. Partial P-V curve of the ML ZrO2system is derived from the C-V measurements. The P-V curves indicate spontaneous polarization of about 50 μC / cm2for the ML ZrO2 system, assuming 1 nm thickness for the ML ZrO2 and dielectric constant of 20. The disclosures of each and every patent, patent application, and publication cited herein are hereby incorporated herein by reference in their entirety. While this invention has been disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of this invention may be devised by others skilled in the art without departing from the true spirit and scope of the invention. The appended claims are intended to be construed to include all such embodiments and equivalent variations.

Claims

Attorney Docket No.047162-5365-00WO CLAIMS What is claimed is:

1. A method of fabricating a ferroelectric material, comprising the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized surface to provide a film; and annealing the film at a temperature between 700˚C and 900˚C, thereby forming a metal oxide layer on top of the semiconductor substrate, wherein the interface between the semiconductor substrate and the metal oxide layer does not contain any remnant oxidized surface.

2. The method of claim 1, wherein the metal is deposited in a single layer of lattice unit cells.

3. The method of claim 1, wherein the step of annealing the film comprises the step of heating the film to a temperature of about 750˚C.

4. The method of claim 1, wherein the semiconductor substrate comprises silicon.

5. The method of claim 1, wherein the semiconductor substrate comprises germanium.

6. The method of claim 1, wherein the step of treating the semiconductor substrate with an oxidant comprises the step of treating the semiconductor substrate with ultraviolet radiation and ozone.

7. The method of claim 1, wherein the metal is selected from the group consisting of zirconium, hafnium, and combinations thereof.

8. The method of claim 1, wherein the metal is zirconium.Attorney Docket No.047162-5365-00WO 9. A ferroelectric material produced using the method of claim 1.

10. A ferroelectric material, comprising: a silicon substrate; and a ferroelectric layer comprising at least one metal oxide; wherein the ferroelectric layer is a single layer of lattice unit cells; and wherein the interface between the silicon substrate and the ferroelectric layer does not comprise silicon oxide.

11. The ferroelectric material of claim 10, wherein the silicon substrate is a wafer.

12. The ferroelectric material of claim 10, wherein the at least one metal oxide comprises an oxide of a metal selected from the group consisting of zirconium, hafnium, and combinations thereof.

13. The ferroelectric material of claim 10, wherein the at least one metal oxide comprises ZrO2.

14. The ferroelectric material of claim 10, wherein the ferroelectric layer has a thickness of a single atomic monolayer.

15. The ferroelectric material of claim 10, wherein the ferroelectric material further comprises a gate oxide.

16. The ferroelectric material of claim 15, wherein the gate oxide is Al2O3.

17. A ferroelectric transistor comprising the ferroelectric material of claim 10.

18. A capacitor comprising the ferroelectric material of claim 10.

Images