Bus circuit for two master devices, and bus control method and apparatus for two master devices

Abstract

Provided in the embodiments of the present application are a bus circuit for two master devices, and a bus control method and apparatus for two master devices. The bus circuit comprises a first master device, a first bus buffer, a second master device, a second bus buffer, an input / output expander, a watchdog, a NOT gate and a bus control chip, wherein the first master device is connected to the first bus buffer by means of an integrated circuit bus, and the first bus buffer is connected to the bus control chip by means of the integrated circuit bus; the second master device is connected to the second bus buffer by means of the integrated circuit bus, and the second master device is further connected to the input / output expander by means of the integrated circuit bus; the input / output expander is further connected to the first master device, and the input / output expander is further connected to the watchdog; the watchdog is further connected to the NOT gate; the NOT gate is further connected to the first bus buffer; and the watchdog is further connected to the second bus buffer. By means of the present application, the conflict problem in the related art of two master devices competing for bus control rights is solved.

Description

Bus circuit, bus control method and device for dual master devices

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202410696816.6, filed on May 31, 2024, entitled "Bus Circuit, Bus Control Method and Apparatus for Dual Master Devices", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computers, and more specifically, to a bus circuit, bus control method, and apparatus for a dual-master device. Background Technology

[0004] SMBUS (System Management Bus) is a low-speed serial bus developed based on the I2C (Inter-Integrated Circuit) bus. It is mainly used to connect various devices and sensors inside a computer to monitor and manage the status and performance of these devices.

[0005] In server systems, the Baseboard Management Controller (BMC) manages a complex SMBUS topology network. After the server is powered on, the BMC can monitor system temperature, voltage, fans, power supply, etc., via SMBUS and make corresponding adjustments. However, for management purposes, the BIOS (Basic Input Output System) may also access some devices on the bus via SMBUS at times. This can lead to a situation where two masters compete for control of the SMBUS bus.

[0006] There is currently no effective solution to the above problems. Summary of the Invention

[0007] This application provides a bus circuit, bus control method, and apparatus for dual-master devices, so as to at least solve the conflict problem of dual-master devices competing for bus control in related technologies.

[0008] According to one embodiment of this application, a dual-master bus circuit is provided, including: a first master device, a first bus buffer, a second master device, a second bus buffer, an input / output expander, a watchdog timer, a NOT gate, and a bus control chip; the first master device is connected to the first bus buffer via an integrated circuit bus, and the first bus buffer is connected to the bus control chip via an integrated circuit bus; the second master device is connected to the second bus buffer via an integrated circuit bus, and the second master device is also connected to the input / output expander via an integrated circuit bus; the input / output expander is also connected to the first master device, and the input / output expander is also connected to the watchdog timer; the watchdog timer is also connected to the NOT gate, the NOT gate is also connected to the first bus buffer, and the watchdog timer is also connected to the second bus buffer.

[0009] In one exemplary embodiment, the bus circuit further includes: a slave device; the slave device is connected to the bus control chip via an integrated circuit bus.

[0010] In one exemplary embodiment, the watchdog includes a watchdog timer configured to monitor the duration for which the second master device polls the control slave device.

[0011] In one exemplary embodiment, the first master device is connected to the first bus buffer via an integrated circuit bus, including: the first master device is connected to the first bus buffer via a first data line and a first clock line.

[0012] In one exemplary embodiment, the second master device is connected to the second bus buffer via an integrated circuit bus, and the second master device is also connected to the input / output expander via the integrated circuit bus, including: the second master device is connected to the second bus buffer and the input / output expander via a second data line; the second master device is connected to the second bus buffer and the input / output expander via a second clock line.

[0013] In one exemplary embodiment, the input / output expander is further connected to a first master device, including: a general-purpose input / output port of the first master device is connected to a first port of the first master device; the input / output expander is further connected to a watchdog timer, including: a second port of the input / output expander is connected to the watchdog timer.

[0014] In one exemplary embodiment, the first master device is a platform control unit, and the second master device is a baseboard management controller.

[0015] According to another embodiment of this application, a bus control method for a dual-master device is provided, applied to the bus circuit of the dual-master device described above, comprising: before the first master device requests control rights from the bus control chip, the first master device sets a first signal output from a general-purpose input / output port low to reserve control rights from the bus control chip; before the second master device polls the slave device, the second master device reads that the first signal of the first port is low, determines that the first master device has reserved control rights from the bus control chip, and the second master device abandons polling the slave device, wherein the first master device sends the first signal to the first port of the input / output expander through the general-purpose input / output port.

[0016] In an exemplary embodiment, when the first signal read is low, the method further includes: the second master device stopping sending a second signal to the watchdog to control the watchdog's timer to stop counting; and when the watchdog's timer stops counting for a period exceeding a preset time threshold, the watchdog outputs a third signal to control the first bus buffer to turn on and the second bus buffer to turn off.

[0017] In one exemplary embodiment, the preset time threshold is greater than twice the duration of the second master device polling the slave device.

[0018] In an exemplary embodiment, the method further includes: when a preset waiting time is reached, the first master device requests control from the bus control chip, wherein the preset waiting time is longer than the time for the second master device to poll and control the slave device.

[0019] In one exemplary embodiment, after the first master device requests control from the bus control chip, the method further includes: the first master device reading target information from the slave device; and after the first master device completes reading the target information from the slave device, the first master device sets the first signal output by the general-purpose input / output port high.

[0020] In one exemplary embodiment, after the first master device sets the first signal output from the general-purpose input / output port high, the method further includes: before the second master device polls the slave device, the second master device reads that the first signal of the first port is high, the second master device sends a second signal to the watchdog timer to control the watchdog timer to perform a counting operation, and the watchdog timer outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

[0021] In one exemplary embodiment, the method further includes: when the second master device is in a suspended state or the second master device is in an infinite loop state, the watchdog timer stops counting; when the duration for which the watchdog timer stops counting exceeds a preset time threshold, the watchdog outputs a third signal to control the first bus buffer to be turned on and the second bus buffer to be turned off.

[0022] In an exemplary embodiment, after the first master device requests control from the bus control chip, the method further includes: if the first master device occupies control, the second master device monitors the duration of the first master device occupying control; if the duration of the first master device occupying control exceeds a preset duration threshold, the second master device sends a second signal to the watchdog timer to control the watchdog timer to perform a counting operation, and the watchdog outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

[0023] In an exemplary embodiment, the preset duration threshold is the sum of the preset waiting time from the first master device to the request for control and the duration of the second master device polling the slave device.

[0024] According to another embodiment of this application, a bus control device for dual master devices is provided, comprising: a reservation module configured to, before a first master device requests control rights from a bus control chip, set a first signal output from a general-purpose input / output port low to reserve control rights from the bus control chip; and a determination module configured to, before a second master device polls a slave device, read that the first signal of a first port is low, determine that the first master device has reserved control rights from the bus control chip, and the second master device abandons polling the slave device, wherein the first master device sends the first signal to a first port of an input / output expander through the general-purpose input / output port.

[0025] According to another embodiment of this application, a computer non-volatile readable storage medium is also provided, wherein a computer program is stored in the computer non-volatile readable storage medium, and the computer program is configured to execute the steps in any of the above method embodiments when running.

[0026] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0027] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0028] According to this application, a first master device is connected to a first bus buffer via an integrated circuit bus, and the first bus buffer is connected to a bus control chip via an integrated circuit bus; a second master device is connected to a second bus buffer via an integrated circuit bus, and the second master device is also connected to an input / output expander via an integrated circuit bus; the input / output expander is also connected to the first master device, and the input / output expander is also connected to a watchdog timer; the watchdog timer is also connected to an NOT gate, the NOT gate is also connected to the first bus buffer, and the watchdog timer is also connected to the second bus buffer.

[0029] Since the input / output expander enables the first master device to handshake with the second master device, allowing the first master device to reserve control of the bus control chip, the conflict problem of dual master devices competing for bus control in related technologies can be resolved, reducing conflicts between master devices and improving system stability. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the structure of a dual-master direct-connect bus;

[0031] Figure 2 is a schematic diagram of the structure of the dual-master isolated connection bus;

[0032] Figure 3 is a schematic diagram of the bus circuit of a dual-master device according to an embodiment of this application;

[0033] Figure 4 is a schematic diagram of the structure of a dual-master device control bus according to an embodiment of this application;

[0034] Figure 5 is a hardware structure block diagram of the computing device of a bus control method for dual-master devices according to an embodiment of this application;

[0035] Figure 6 is a flowchart of a bus control method for dual-master devices according to an embodiment of this application;

[0036] Figure 7 is a flowchart of a BIOS request for control according to an embodiment of this application;

[0037] Figure 8 is a flowchart of the BMC in a suspended state according to an embodiment of this application;

[0038] Figure 9 is a flowchart of BIOS control timeout according to an embodiment of this application;

[0039] Figure 10 is a structural block diagram of a bus control device for a dual-master device according to an embodiment of this application. Detailed Implementation

[0040] The following is an explanation of some of the English text in this application:

[0041] I2C: Inter-Integrated Circuit, a two-wire serial communication bus.

[0042] BMC: Baseboard Management Controller, a standalone system-on-a-chip on a server motherboard.

[0043] BIOS: Basic Input Output System, in this application it refers to BIOS firmware.

[0044] PCH: Platform Controller Hub, Intel's integrated southbridge, a controller that Intel has separated some functions from the CPU. In this article, the BIOS firmware process is executed by the PCH.

[0045] SMBUS (System Management Bus) is a low-speed serial bus that originated from Intel. It is an I2C-based protocol that provides a standardized way for hardware components such as motherboards, sensors, and power management chips to communicate with each other, aiming to simplify system management tasks.

[0046] The I2C bus is an integrated circuit bus that requires at least one data line (SDA) and one clock line (SCL) in hardware. Multiple devices can be connected to the bus, primarily divided into master and slave devices, each with a unique address. An I2C bus allows for multiple master devices. When two or more master devices are ready to transmit data simultaneously, the bus provides a collision detection and arbitration mechanism to ensure that only one master device communicates at a time.

[0047] In a server system, the BMC manages a complex SMBUS topology network. After the server is powered on, the BMC monitors the system's temperature, voltage, fans, power supply, etc., through SMBUS and makes corresponding adjustments. However, for management purposes, the BIOS may also access some devices on the bus through SMBUS at times. This can lead to a situation where two master devices (also called dual masters, i.e., the BIOS and the BMC) compete for control of the SMBUS bus.

[0048] Currently, there are two main types of circuit connection methods for dual-master device control:

[0049] Figure 1 is a schematic diagram of a dual-master direct-connect bus. As shown in Figure 1, the SDA / SCL pins of the PCH and the SDA / SCL pins of the BMC are connected in parallel to the SMBUS bus on the motherboard. The signal waveforms transmitted and received by the BMC on the bus can be transmitted to the pins of the PCH. However, in this connection method, both master devices are directly connected to the SMBUS without any isolation. This can easily cause abnormal fluctuations in the pins of one master device to be transmitted to the entire SMBUS, thereby interfering with the normal communication of the other master device.

[0050] Figure 2 is a schematic diagram of the dual-master isolated connection bus. As shown in Figure 2, the PCA9641 chip (2 I2 master channels and 1 I2C slave channel) is used to isolate the two master devices, allowing the two master devices (BMC and PCH) to compete for control of the PCA9641. At any given time, only one master device can communicate with the slave channel. Although the BIOS code only requests SMBUS bus control at a specific time during the Power-On Self-Test (POST) process, this time is random for the BMC. The BIOS's request can occur at any moment during the POST phase. When the BIOS requests SMBUS control, if the BMC is already using the SMBUS, the BMC's communication will not be interrupted, and the BIOS will be unable to obtain control of the current SMBUS. This can lead to resource allocation errors or display abnormalities in the BIOS because the BIOS cannot obtain slave information at the specified time.

[0051] Alternatively, during the POST phase, the BIOS request has a higher priority. To avoid the BIOS failing to acquire control of the SMBUS, the BMC chooses to relinquish polling monitoring and release the SMBUS bus during the POST process. In this case, the BIOS can request control of the PCA9641 at any time during the entire POST process, thereby accessing the slave device. However, this leads to a problem: the BMC loses real-time monitoring and control of the slave device during the POST process.

[0052] In addition, the PCA9641 chip itself also has functions for automatic disconnection upon timeout and automatic disconnection upon bus hangup. However, the hangup determination is based on the bus idle state timeout. Bus idle state timeout refers to a prolonged period without data transmission or communication activity on the bus, exceeding a preset time limit. This situation may indicate a fault or communication failure between communication devices, requiring troubleshooting and repair. In practical applications, when the BMC I2C process malfunctions or the slave device hangs, the SCL / SDA signals are either constantly high (same as idle) or constantly low. The PCA9641 can determine the timeout and automatically disconnect the connection between the master and slave. However, when the slave device malfunctions, the SCL or SDA signals are in an oscillating state. In this case, the PCA9641 will not be able to determine the timeout and will not automatically disconnect the connection between the master and slave.

[0053] In summary, this application proposes a bus circuit for dual-master devices. By using a PCA9555 expander, a PCA9617 bus buffer, a watchdog timer (WDT), and NOT gates, along with code modifications to the BMC / BIOS, it enables the BIOS to reserve control of the PCA9641, the BMC to actively relinquish control of the PCA9641, and to force the BMC or BIOS to lose control of the PCA9641. This resolves the conflict problem of dual-master devices competing for SMBUS bus control in related technologies.

[0054] It should be noted that this application only describes the PCA9641 chip and SMBUS bus as optional embodiments. In practical applications, it is not limited to the PCA9641 chip and SMBUS bus, and it also applies to other bus contention conflicts in dual-master devices.

[0055] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0057] This embodiment provides a bus circuit for a dual-master device. Figure 3 is a schematic diagram of the structure of the bus circuit for a dual-master device according to an embodiment of this application. As shown in Figure 3, the circuit includes: a first master device, a first bus buffer, a second master device, a second bus buffer, an input / output expander, a watchdog timer, a NOT gate, and a bus control chip. The first master device is connected to the first bus buffer via an integrated circuit bus, and the first bus buffer is connected to the bus control chip via an integrated circuit bus. The second master device is connected to the second bus buffer via an integrated circuit bus, and the second master device is also connected to the input / output expander via an integrated circuit bus. The input / output expander is also connected to the first master device, and the input / output expander is also connected to the watchdog timer. The watchdog timer is also connected to the NOT gate, the NOT gate is also connected to the first bus buffer, and the watchdog timer is also connected to the second bus buffer.

[0058] The first master device and the second master device mentioned above can be any two master devices, such as BMC, BIOS (PCH), etc.

[0059] As an alternative implementation, the first master device is a platform control unit, and the second master device is a baseboard management controller.

[0060] The first and second buffers mentioned above can be PCA9617 bus buffers. The PCA9617 bus buffer is an I2C bus buffer that can expand the number of nodes on an I2C bus. It allows users to connect multiple slave devices on the I2C bus while maintaining bus performance and stability. The PCA9617 also provides voltage level shifting functionality, enabling communication between different voltage levels. This makes it ideal for applications requiring long-distance transmission or communication between different voltage systems.

[0061] The aforementioned bus control chip can be a PCA9641 chip. The PCA9641 chip is an I2C bus level shifter and voltage level shifter, configured to communicate between different levels and voltages. In this embodiment, the PCA9641 is an SMBus bus controller chip, which can be configured to control and manage devices and communications on the SMBus bus. In summary, the PCA9641 is part of the SMBus bus and is configured to manage and control communication and devices on the SMBus bus.

[0062] The aforementioned input / output expander can be the PCA9555 bus I / O expander. The PCA9555 bus I / O expander is a 16-bit I2C bus I / O (Input / Output) expander that provides 16 GPIO ports and supports cascading connections. It can communicate with microprocessors or other peripheral devices via the I2C bus. It can be configured to control and monitor various external devices, such as LEDs (Light Emitting Diodes), buttons, and sensors. This chip can be widely used in industrial control, automation systems, instrumentation, and communication equipment.

[0063] The aforementioned watchdog timer can be a type of watchdog timer. The working principle of an electronic device watchdog timer is based on a combination of a timer and a reset circuit. When the electronic device is working normally, the watchdog timer periodically receives signals from the device, thus maintaining its count. If the electronic device stops working due to a malfunction or other reasons, the timer will no longer receive signals, and the counting will stop. Once the timer count stops for more than a preset time threshold, the reset circuit will automatically trigger, restarting the electronic device and preventing the system from remaining unresponsive for an extended period. In summary, the working principle of an electronic device watchdog timer is to monitor the normal operating status of the system through a timer, and when a system malfunction occurs, it automatically triggers the reset circuit to restart the system, thereby ensuring the stability and reliability of the system.

[0064] An I2C channel switch (PCA9617 bus buffer) is added to the connection channel between the PCA9641 chip and the two master devices, allowing each master device to connect to the bus through a separate buffer. Simultaneously, a watchdog timer and a NOT gate logic circuit are used to control the on / off state of the two PCA9617 bus buffers, ensuring that only one PCA9617 bus buffer is active at any given time. This means that only one master device can establish a connection with the PCA9641 chip at any given time. The watchdog timer monitors the duration of BMC polling, preventing the PCA9641 from failing to detect timeouts and thus not automatically disconnecting the master and slave devices.

[0065] At the same time, an input / output expander is set up and configured to connect two master devices and a watchdog timer. Through the bus I / O expander, a handshake signal is added between the two master devices, which can realize the handshake communication between the two master devices and provide a reservation channel for the master device BIOS, so that the BIOS can reserve control of the bus from the BMC.

[0066] As an optional implementation, the bus circuit also includes: a slave device; the slave device is connected to the bus control chip via an integrated circuit bus.

[0067] As an optional implementation, the first master device is connected to the first bus buffer via an integrated circuit bus, including: the first master device is connected to the first bus buffer via a first data line and a first clock line.

[0068] As an optional implementation, the second master device is connected to the second bus buffer via an integrated circuit bus, and the second master device is also connected to the input / output expander via an integrated circuit bus, including: the second master device is connected to the second bus buffer and the input / output expander via a second data line; the second master device is connected to the second bus buffer and the input / output expander via a second clock line.

[0069] As an optional implementation, the input / output expander is also connected to the first master device, including: the general-purpose input / output port of the first master device is connected to the first port of the first master device; the input / output expander is also connected to the watchdog timer, including: the second port of the input / output expander is connected to the watchdog timer.

[0070] The circuit described above can effectively resolve the conflict between the BMC and BIOS in competing for control of the PCA9641, thereby reducing conflicts between devices and improving system stability.

[0071] As an optional implementation, Figure 4 is a schematic diagram of the dual-master device control bus according to an embodiment of this application. As shown in Figure 4, the BMC uses the pins of the PCA9555 to complete handshake and watchdog timer feeding. At the same time, it uses the SMBUS polling process to read and write the PCA9555. The cycle of the BMC completing normal polling can be denoted as T0, the watchdog timeout duration as T1, the time taken for the BIOS to complete one round of I2C read as T2, and the cycle of the PCA9641 automatically disconnecting idle as T3 = 100ms. The time interval from the BIOS's reservation to requesting control of the PCA9641 is t0 > T0. The BMC's watchdog timer feeding cycle is t1 = T0 < (T1 / 2). It is set that if the BIOS occupies the bus for a duration t2 > t0 + T2, the BIOS is deemed to have timed out. The polling scheme is as follows:

[0072] The BMC maintains its connection with the PCA9641 by feeding the watchdog timer. If the watchdog timer stops, the connection between the BMC and the PCA9641 is disconnected, and a connection is established between the PCH and the PCA9641. Before the BIOS needs to request control of the PCA9641, it notifies the BMC of the GPIO signal status to make a reservation. Meanwhile, the BMC's normal polling will not be interrupted. Before the next polling begins, the BMC first reads the status of IO_0 of the PCA9555 to determine whether the BIOS has reserved control. Furthermore, if the BIOS times out and occupies the PCA9641 (i.e., the BIOS occupies the bus for a duration t2 > t0 + T2), the BMC can disconnect the PCH from the PCA9641 by refeeding the watchdog timer.

[0073] It's important to note that in BMC (Body Management System), "feeding the dog" typically refers to periodically sending specific commands or signals to monitors or devices within the system to ensure its proper functioning. This process is similar to feeding a pet, regularly providing necessary food or resources to maintain its health and vitality. In BMC, the "feeding the dog" process helps monitor the system's operational status and allows for necessary recovery or restart measures in the event of problems or crashes.

[0074] The watchdog timer's overflow duration refers to the time interval at which the watchdog timer overflows. A watchdog timer is a hardware device configured to monitor the system's operational status. When the system malfunctions or stops responding, the watchdog timer will trigger a system restart if it does not receive a response from the system within a preset time interval. The watchdog timer's overflow duration is typically determined by system designers based on system stability and response requirements, generally ranging from a few seconds to several minutes. A shorter overflow duration allows for faster detection of system faults and triggering of restarts, but may increase the number of system restarts; a longer overflow duration reduces the number of system restarts, but may lead to delayed system responses when faults occur. In summary, the watchdog timer's overflow duration needs to be set and adjusted reasonably based on system requirements and stability.

[0075] The first and second master devices in the method embodiments provided in this application can be executed in a server device or similar computing device, as shown in FIG5. The computing device can be a control unit or a baseboard management controller.

[0076] Figure 5 is a hardware structure block diagram of a computing device for a bus control method for a dual-master device according to an embodiment of this application. As shown in Figure 5, the computing device may include one or more (only one is shown in Figure 5) processors 502 (processors 502 may include, but are not limited to, microprocessors MCUs (Microcontroller Units) or programmable gate arrays (FPGAs), etc.) and a memory 504 configured to store data. The computing device may also include a transmission device 506 configured for communication functions and an input / output device 508. Those skilled in the art will understand that the structure shown in Figure 5 is merely illustrative and does not limit the structure of the server device described above. For example, the computing device may include more or fewer components than shown in Figure 5, or have a different configuration than that shown in Figure 5.

[0077] The memory 504 can be configured to store computer programs, such as application software programs and modules, like the computer program corresponding to the bus control method for dual-master devices in this embodiment. The processor 502 executes various functional applications and data processing by running the computer programs stored in the memory 504, thus implementing the aforementioned method. The memory 504 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 504 may include memory remotely located relative to the processor 502, and these remote memories can be connected to the computing device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0078] Transmission device 506 is configured to receive or transmit data via a network. Examples of such networks may include a wireless network provided by a communication provider for the server device. In one example, transmission device 506 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, transmission device 506 may be a Radio Frequency (RF) module configured to communicate wirelessly with the Internet.

[0079] This embodiment provides a bus control method for a dual-master device, applied to the bus circuit of the aforementioned dual-master device. Figure 6 is a flowchart of the bus control method for a dual-master device according to an embodiment of this application. As shown in Figure 6, the process includes the following steps:

[0080] In step S602, before the first master device requests control of the bus control chip, the first master device sets the first signal output by the general input / output port low to reserve control from the bus control chip.

[0081] The first master device mentioned above can be the BIOS (PCH), the bus control chip mentioned above can be the PCA9641 chip, the general purpose input / output port mentioned above can be the GPIO port of the BIOS, and the first signal mentioned above can be a level signal. Before the BIOS requests control of the PCA9641 chip, the BIOS reserves control of the PCA9641 chip by setting the GPIO port to a low level.

[0082] In step S604, before the second master device polls the slave device, the second master device reads that the first signal of the first port is low, determines that the first master device has reserved control rights from the bus control chip, and the second master device relinquishes the polling control of the slave device. The first master device sends the first signal to the first port of the input / output expander through the general purpose input / output port.

[0083] The second master device mentioned above can be the BMC, and the first port mentioned above can be the IO_0 port of the PCA9555 bus IO expander. Before the BMC polls and controls the slave device, it needs to read the level signal of the IO_0 port of the bus IO expander. If the level signal of the IO_0 port is low, it means that the BIOS has reserved the control of the PCA9641 chip. At this time, the BMC gives up the polling control of the slave device. The level signal of the IO_0 port is the level signal sent by the first device through the GPIO port.

[0084] Through the above steps, handshake communication between the BIOS and BMC is realized, enabling the BIOS to obtain control of the bus control chip by reservation. This solves the conflict problem of dual master devices competing for bus control in related technologies and improves system stability.

[0085] The entities that perform the above steps can be servers, terminals, etc., but are not limited to these.

[0086] As an optional implementation, when the first signal read is low, the method further includes: the second master device stops sending a second signal to the watchdog to control the watchdog's timer to stop counting; if the watchdog's timer stops counting for a period exceeding a preset time threshold, the watchdog outputs a third signal to control the first bus buffer to turn on and the second bus buffer to turn off.

[0087] The second signal mentioned above can be a trigger signal, and the third signal can be a logic value, such as 0 or 1. The watchdog timer can receive the trigger signal sent by the BMC through the IO-1 port of the PCA9555 bus IO expander, thereby establishing a connection between the BMC and the bus control chip, and realizing the BMC's polling control of the slave device. When the BMC stops sending trigger signals to the watchdog timer, the watchdog timer stops, disconnecting the BMC from the bus control chip. If the watchdog timer stops counting for a period exceeding a preset time threshold, the watchdog timer outputs the corresponding logic value, which controls the first bus buffer to turn on and the second bus buffer to turn off through a NOT gate logic circuit. By adding a watchdog timer, polling control of the bus control chip by dual master devices is realized, ensuring that only one master device can control the bus control chip at any given time.

[0088] As an optional implementation, the method further includes: when a preset waiting time is reached, the first master device requests control from the bus control chip, wherein the preset waiting time is longer than the time for the second master device to poll and control the slave device.

[0089] The preset waiting time can be the time interval t0 between the BIOS's reservation and its request for control of the bus control chip. The time interval for the second master device to poll the slave device can be the cycle T0 of the BMC completing normal polling. When the preset waiting time t0 is greater than the cycle T0 of the BMC completing normal polling, the BIOS requests control of the bus control chip from the bus control chip.

[0090] As an optional implementation, after the first master device requests control from the bus control chip, the method further includes: the first master device reading target information from the slave device; after the first master device finishes reading the target information from the slave device, the first master device sets the first signal output by the general-purpose input / output port high.

[0091] As an optional implementation, after the first master device sets the first signal output from the general-purpose input / output port high, the method further includes: before the second master device polls the slave device, the second master device reads that the first signal of the first port is high, the second master device sends a second signal to the watchdog to control the watchdog timer to perform a counting operation, and the watchdog outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

[0092] After the BIOS finishes reading the device information, it releases control of the bus control chip and sets the GPIO port to high level. Before the BMC polls again, the read value IO_0 port is high level. At this time, a trigger signal is sent to the watchdog timer to reset the timer. The second bus buffer is turned on and the first bus buffer is turned off through the NOT gate logic circuit. The BMC then obtains control of the bus control chip and executes the current polling.

[0093] As an optional implementation, the method further includes: when the second master device is in a suspended state, or when the second master device is in an infinite loop state, the watchdog timer stops counting; when the watchdog timer stops counting for a period exceeding a preset time threshold, the watchdog outputs a third signal to control the first bus buffer to be turned on and the second bus buffer to be turned off.

[0094] When the BMC is in a suspended state or in an infinite loop state, the BMC cannot send a trigger signal to the watchdog timer. In this case, the watchdog timer outputs a third signal to control the first bus buffer to turn on and the second bus buffer to turn off, thereby solving the problem that the BIOS cannot obtain the bus after the BMC has suspended the bus.

[0095] As an optional implementation, after the first master device requests control from the bus control chip, the method further includes: if the first master device occupies control, the second master device monitors the duration of the first master device occupying control; if the duration of the first master device occupying control exceeds a preset duration threshold, the second master device sends a second signal to the watchdog timer to control the watchdog timer to perform a counting operation, and the watchdog outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

[0096] The duration T2 of the first master device (BIOS) control bus control chip is limited. When the BIOS occupies control of the bus control device, the BMC will monitor the duration of the BIOS's control. If the monitored duration of the BIOS's control exceeds the preset duration threshold, it is determined that the BIOS control has timed out or that the BIOS has malfunctioned (is in a suspended state). At this time, the BMC can directly send a trigger signal to the watchdog timer to shut down the first bus buffer, turn on the second bus buffer, and regain control of the bus control chip. This can solve the problem that the BMC cannot obtain the bus after the BIOS has suspended the bus or the BIOS has timed out its bus control.

[0097] As an optional implementation, Figure 7 is a flowchart of the BIOS request for control according to an embodiment of this application. As shown in Figure 7, the process is as follows:

[0098] Before requesting control of the PCA9641, the BIOS first sets the GPIO low to reserve control with the BMC;

[0099] Before each polling, the BMC reads the value IO_0 to determine if the BIOS has already reserved it. If the value IO_0 is 0, it means that the BIOS has already reserved it. In this case, the BMC abandons this polling and abandons feeding the watchdog. At this time, U8 is disconnected and U7 is turned on.

[0100] After waiting for time t0, the BIOS requests control of the PCA9641. The waiting time t0 is longer than the cycle time of one normal polling operation by the BMC.

[0101] The BIOS acquires control of the PCA9641 and releases control of the PCA9617 after completing the information reading, while simultaneously setting the GPIO high.

[0102] Before the BMC polls again, if the read value IO_0 is 1, then the dog feed is executed. At this time, U8 is turned on and U7 is turned off. The BMC requests control of the PCA9641 and executes this polling.

[0103] As an optional implementation, Figure 8 is a flowchart of the BMC in a suspended state according to an embodiment of this application. As shown in Figure 8, the process is as follows:

[0104] When the BIOS requests control, if the BMC is in a suspended state, the BMC cannot feed the watchdog. At this time, the watchdog circuit will disconnect U8 and turn on U7. The PCA9641 will automatically disconnect the connection between the master and slave devices and remain idle after the SDA / SCL waveform remains unchanged for 100ms. After that, the BIOS can normally request control of the PCA9641.

[0105] Alternatively, if the BMC cannot exit a polling loop during the BIOS's request for control, the BMC will also be unable to feed the watchdog. In this case, the watchdog circuit will disconnect U8 and turn on U7. The PCA9641 will automatically disconnect the connection between the master and slave devices and remain idle after the SDA / SCL waveform remains unchanged for 100ms. After that, the BIOS can normally request control of the PCA9641.

[0106] As an optional implementation, Figure 9 is a flowchart of BIOS control timeout according to an embodiment of this application. As shown in Figure 9, the process is as follows:

[0107] After the BIOS requests control, the BMC can monitor and determine whether the BIOS has timed out its control of the PCA9641. Since the BIOS can only normally hold control of the PCA9641 for a limited time, if the BMC determines that the BIOS has timed out its control, it can be assumed that the BIOS is malfunctioning or is in a suspended state. The BIOS cannot actively release control of the PCA9641. In this case, the BMC can disconnect U7 and connect U8 by restoring the dog feed and re-request control of the PCA9641.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0109] This embodiment also provides a bus control device for dual-master devices, configured to implement the above embodiments and optional implementations, details of which will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0110] Figure 10 is a structural block diagram of a bus control device for dual master devices according to an embodiment of this application. As shown in Figure 10, the device includes: a setting module 1002, set in the first master device, configured to set a first signal output from a general-purpose input / output port low before the first master device requests control rights from the bus control chip, so as to reserve control rights from the bus control chip; and a reading module 1004, set in the second master device, configured to read the first signal of the first port as low before the second master device polls the slave device, determine that the first master device has reserved control rights from the bus control chip, and give up polling the slave device, wherein the first master device sends the first signal to the first port of the input / output expander through the general-purpose input / output port.

[0111] In one exemplary embodiment, the second master device is further configured to stop sending a second signal to the watchdog when the first signal read by the second master device is low, so as to control the watchdog timer to stop counting; and if the duration for which the watchdog timer stops counting exceeds a preset time threshold, the watchdog outputs a third signal to control the first bus buffer to turn on and the second bus buffer to turn off.

[0112] In one exemplary embodiment, the first master device is further configured to request control from the bus control chip when a preset waiting time is reached, wherein the preset waiting time is longer than the time for the second master device to poll and control the slave device.

[0113] In one exemplary embodiment, the first master device is further configured to read target information from the slave device;

[0114] After the first master device finishes reading the target information from the slave device, the first master device is also configured to set the first signal output from the general purpose input / output port high.

[0115] In one exemplary embodiment, the second master device is further configured to read that the first signal of the first port is high before the second master device polls the control slave device, the second master device sends a second signal to the watchdog to control the watchdog timer to perform a counting operation, and the watchdog outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

[0116] In one exemplary embodiment, the watchdog is further configured to control a timer to stop counting when the second master device is in a hung state or in an infinite loop state, and to output a third signal when the duration for which the timer stops counting exceeds a preset time threshold, so as to control the first bus buffer to turn on and the second bus buffer to turn off.

[0117] In one exemplary embodiment, the second master device is further configured to monitor the duration of the first master device's occupation of control when the first master device occupies control; if the duration of the first master device's occupation of control exceeds a preset duration threshold, the second master device is further configured to send a second signal to the watchdog timer to control the watchdog timer to perform a counting operation, and the watchdog timer is further configured to output a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

[0118] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0119] Embodiments of this application also provide a computer non-volatile readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0120] In one exemplary embodiment, the aforementioned non-volatile readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0121] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0122] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0123] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0124] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0125] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0126] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A bus circuit for dual-master devices, Its features are, Includes: a first master device, a first bus buffer, a second master device, a second bus buffer, an input / output expander, a watchdog timer, NOT gates, and a bus control chip; The first master device is connected to the first bus buffer via an integrated circuit bus, and the first bus buffer is connected to the bus control chip via an integrated circuit bus. The second master device is connected to the second bus buffer via an integrated circuit bus, and the second master device is also connected to the input / output expander via an integrated circuit bus; The input / output expander is also connected to the first master device, and the input / output expander is also connected to the watchdog. The watchdog timer is also connected to the NOT gate, the NOT gate is also connected to the first bus buffer, and the watchdog timer is also connected to the second bus buffer.

2. The bus circuit for a dual-master device according to claim 1, characterized in that, The bus circuit also includes: a slave device; The slave device is connected to the bus control chip via an integrated circuit bus.

3. The bus circuit for a dual-master device according to claim 2, characterized in that, The watchdog includes a watchdog timer, which is configured to monitor the duration for which the second master device polls and controls the slave device.

4. The bus circuit for a dual-master device according to claim 1, characterized in that, The first master device is connected to the first bus buffer via an integrated circuit bus, including: the first master device is connected to the first bus buffer via a first data line and a first clock line.

5. The bus circuit for a dual-master device according to claim 1, characterized in that, The second master device is connected to the second bus buffer via an integrated circuit bus, and the second master device is also connected to the input / output expander via an integrated circuit bus, including: the second master device is connected to the second bus buffer and the input / output expander via a second data line; the second master device is connected to the second bus buffer and the input / output expander via a second clock line.

6. The bus circuit for a dual-master device according to claim 1, characterized in that, The input / output expander is also connected to the first master device, including: the general-purpose input / output port of the first master device is connected to the first port of the first master device; The input / output expander is also connected to the watchdog timer, including: a second port of the input / output expander is connected to the watchdog timer.

7. The circuit according to any one of claims 1 to 6, characterized in that, The first main device is the platform control unit, and the second main device is the baseboard management controller.

8. A bus control method for a dual-master device, characterized in that, The bus circuit applied to the dual-master device according to any one of claims 1 to 7 comprises: Before the first master device requests control of the bus control chip, the first master device sets the first signal output by the general input / output port low to reserve control of the bus control chip. Before the second master device polls the slave device, the second master device reads that the first signal on the first port is low, determines that the first master device has reserved the control right with the bus control chip, and the second master device gives up polling the slave device. The first master device sends the first signal to the first port of the input / output expander through the general-purpose input / output port.

9. The method according to claim 8, characterized in that, If the first signal read is low, the method further includes: The second master device stops sending a second signal to the watchdog timer to control the watchdog timer to stop counting. If the watchdog timer stops counting for a period of time exceeding a preset time threshold, the watchdog timer outputs a third signal to control the first bus buffer to turn on and the second bus buffer to turn off.

10. The method according to claim 9, characterized in that, The preset time threshold is greater than twice the duration for which the second master device polls and controls the slave device.

11. The method according to claim 8, characterized in that, The method further includes: When the preset waiting time is reached, the first master device requests control from the bus control chip, wherein the preset waiting time is longer than the time for the second master device to poll and control the slave device.

12. The method according to claim 9, characterized in that, After the first master device requests control from the bus control chip, the method further includes: The first master device reads the target information from the slave device; After the first master device finishes reading the target information from the slave device, the first master device sets the first signal output by the general-purpose input / output port high.

13. The method according to claim 9, characterized in that, After the first master device sets the first signal output from the general purpose input / output port high, the method further includes: Before the second master device polls the control slave device, the second master device reads that the first signal of the first port is high, the second master device sends the second signal to the watchdog to control the watchdog timer to perform a counting operation, and the watchdog outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

14. The method according to claim 8, characterized in that, The method further includes: If the second master device is in a suspended state or in an infinite loop state, the watchdog timer stops counting. If the watchdog timer stops counting for a period of time exceeding a preset time threshold, the watchdog outputs a third signal to control the first bus buffer to turn on and the second bus buffer to turn off.

15. The method according to claim 9, characterized in that, After the first master device requests control from the bus control chip, the method further includes: When the first master device occupies the control right, the second master device monitors the duration for which the first master device occupies the control right; If the first master device occupies the control for a duration exceeding a preset duration threshold, the second master device sends the second signal to the watchdog timer to control the watchdog timer to perform a counting operation. The watchdog timer outputs a fourth signal to control the first bus buffer to disconnect and the second bus buffer to turn on.

16. The method according to claim 15, characterized in that, The preset time threshold is the sum of the preset waiting time from the first master device reserving the control right to the application for the control right, and the time for the second master device to poll and control the slave device.

17. A bus control device for dual-master devices, characterized in that, A bus control method for a dual-master device according to any one of claims 8 to 16, comprising: The setting module, located in the first master device, is configured to set a first signal output from the general input / output port low before the first master device requests control from the bus control chip, so as to reserve control from the bus control chip. The reading module, located in the second master device, is configured to read the first signal of the first port as low before the second master device polls and controls the slave device, determine that the first master device has reserved the control right with the bus control chip, and give up polling and controlling the slave device. The first master device sends the first signal to the first port of the input / output expander through the general-purpose input / output port.

18. A computer non-volatile readable storage medium, characterized in that, The computer non-volatile readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 8 to 16.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 8 to 16.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 8 to 16.

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