Memory management method and computing device cluster

Abstract

Provided are a memory management method and a computing device cluster. The method is applied to a first node, wherein a CPU of the first node occupies a memory region of a second node by means of a first connector of the first node and a second connector of the second node, so as to store data. The method comprises: a CPU determining to release a memory region; when the state of the memory region is a valid state, changing the state of the memory region to an OFF state, wherein a first connector is used for dropping, when the state of the memory region is the OFF state, data that the CPU requests to write into the memory region; and the CPU notifying a second node that the memory region is released. In the solution, an OFF state is newly added, wherein when a memory region is in the OFF state, a second node is notified that the memory region is released, without executing an invalid data caching process, thereby reducing the time for returning a memory.

Description

A memory management method and a computing device cluster

[0001] This application claims priority to Chinese Patent Application No. 202410698767.X, filed on May 31, 2024, entitled "A Memory Management Method and a Computing Device Cluster", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to a memory management method and a computing device cluster. Background Technology

[0003] In some applications, computing devices can borrow idle memory from other devices to store data. By borrowing memory, the utilization rate of idle storage resources can be improved.

[0004] For computing devices, after borrowing external memory, the device's cache stores data mapped to that external memory. When the computing device no longer needs to use the external memory, it must first mark this data as invalid and then notify other devices to return the memory. Typically, invalidating cached data takes a long time, which significantly increases the time it takes for the computing device to return the memory. Summary of the Invention

[0005] This application provides a memory management method and a computing device cluster that can solve the problem of long memory return times.

[0006] In a first aspect, this application provides a memory management method. The method is applied to a first node, which includes a central processing unit (CPU) and a first connector. The first connector is communicatively connected to a second connector in a second node. The CPU is used to occupy a memory region of the second node to store data via the first connector and the second connector.

[0007] The method includes: the CPU determining to release the memory region; if the memory region is in a valid state, modifying the state of the memory region to a closed state; the first connector being used to drop the data requested by the CPU to be written to the memory region if the memory region is in the closed state; and the CPU sending a notification message to the second node, the notification message indicating that the first node has released the memory region.

[0008] In the above scheme, a "closed" state is added to the existing state system of the memory region (including valid and invalid states). When the first node returns the memory region, it first changes the state of the memory region to "closed" and then notifies the second node to return the memory region. This means that the first node does not perform the invalidation of cached data before returning the memory, and the time for the first node to return the memory region is independent of the time spent on invalidating cached data, thus shortening the memory return time. In contrast, in related technologies, invalidating cached data needs to be performed before notifying the second node to return the memory region, resulting in a longer memory return time. Therefore, compared with related technologies, the above scheme can significantly reduce the memory return time.

[0009] In one possible implementation, the CPU cache includes first data, the memory address of which is located in the aforementioned memory region. After the CPU sends a notification message to the second node, the method further includes: if the CPU determines that the first data is valid, marking the first data as invalid; and modifying the state of the memory region to an invalid state.

[0010] In the above scheme, after notifying the second node to return the memory area, the data in the cache whose memory address is located in that memory area can be marked as invalid data, which can prevent data from occupying cache resources for a long time.

[0011] In one possible implementation, before the CPU marks the first data as invalid data, the method further includes: if the CPU determines that the first data is dirty data, sending a write-back request to the first connector, the write-back request including the first data and the memory address of the first data; the first connector receiving the write-back request, obtaining the state of the memory region according to the memory address in the write-back request, and if it determines that the state of the memory region is the closed state, sending a success response to the CPU and discarding the first data; the CPU receiving the success response, determining to mark the first data as invalid data.

[0012] In the above scheme, when the data in the cache is dirty, it needs to be written back to the memory of the second node first. Since the second node has been notified to return the memory before invalidating the cached data, the first connector discards the requested write-back data after successfully responding to the CPU's write-back request, without sending a write-back request message to the second node. In other words, the write operation for dirty data is not performed, thus the above scheme can also reduce the communication resources between the two nodes.

[0013] In one possible implementation, the first connector stores a status identifier of the memory region, with different status identifiers representing different states. The CPU determines that the state of the memory region is a valid state by: obtaining the status identifier of the memory region from the first connector; and determining that the state of the memory region is the valid state based on the status identifier of the memory region.

[0014] In the above scheme, after determining the memory region to be returned, the CPU can learn the status of the memory region from the first connector.

[0015] In one possible implementation, the CPU modifying the state of the memory region to a closed state includes: the CPU sending a first modification instruction to the first connector; the first connector receiving the first modification instruction and modifying the state of the memory region to the closed state according to the first modification instruction.

[0016] In one possible implementation, the CPU modifying the state of the memory region to an invalid state includes: the CPU sending a second modification instruction to the first connector; the first connector receiving the second modification instruction and modifying the state of the memory region to the invalid state according to the second modification instruction.

[0017] In one possible implementation, the first connector includes a state machine, which includes a state register and logic circuitry. The state register stores a state identifier of the memory region, and the logic circuitry modifies the state identifier stored in the state register according to a modification instruction sent by the CPU.

[0018] In one possible implementation, the CPU further includes a core and a cache controller, wherein marking the first data as invalid data by the CPU includes: the core instructing the cache controller to mark the first data as invalid data.

[0019] Secondly, this application also provides a memory management device. The device includes a processing module and a notification module.

[0020] The processing module is used to determine when the first node releases the memory area of ​​the second node. The first node includes a CPU and a first connector. The first connector is communicatively connected to a second connector in the second node. The CPU is used to occupy the memory area to store data through the first connector and the second connector.

[0021] The processing module is further configured to change the state of the memory region to a closed state when the state of the memory region is in a valid state, and the first connector is configured to discard the data requested by the CPU to be written to the memory region when the state of the memory region is in the closed state.

[0022] The notification module is used to send a notification message to the second node, the notification message indicating that the first node is releasing the memory region.

[0023] In one possible implementation, the CPU cache includes first data, the memory address of which is located in the memory region. After sending a notification message to the second node, the processing module is further configured to: mark the first data as invalid data if it is determined that the first data is valid; and modify the state of the memory region to an invalid state.

[0024] In one possible implementation, before the CPU marks the first data as invalid data, the processing module is further configured to, if it is determined that the first data is dirty data, send a write-back request to the first connector, the write-back request including the first data and the memory address of the first data, wherein the first connector receives the write-back request, obtains the status of the memory region according to the memory address in the write-back request, and, if it is determined that the status of the memory region is the closed state, sends a success response to the CPU and discards the first data. The processing module is further configured to receive the success response and determine to mark the first data as invalid data.

[0025] In one possible implementation, the first connector stores the status identifier of the memory region, with different status identifiers used to represent different states. The processing module is further configured to: obtain the status identifier of the memory region from the first connector; and determine the state of the memory region as the valid state based on the status identifier of the memory region.

[0026] In one possible implementation, the processing module is further configured to: send a first modification instruction to the first connector, the first connector being configured to receive the first modification instruction, and modify the state of the memory region to the closed state according to the first modification instruction.

[0027] In one possible implementation, the processing module is further configured to: send a second modification instruction to the first connector, the first connector being configured to receive the second modification instruction, and modify the state of the memory region to the invalid state according to the second modification instruction.

[0028] In one possible implementation, the first connector includes a state machine, which includes a state register and logic circuitry. The state register stores a state identifier of the memory region, and the logic circuitry modifies the state identifier stored in the state register according to a modification instruction sent by the CPU.

[0029] In one possible implementation, the CPU further includes a cache controller, and the processing module is further configured to: instruct the cache controller to mark the first data as invalid data.

[0030] Thirdly, this application also provides a chip. The chip includes a CPU and a first connector, the CPU and the first connector being used to implement the memory management method provided in any possible embodiment of the first aspect or in combination with the first aspect.

[0031] Fourthly, this application also provides a computing device. The computing device includes the chip and memory described in the third aspect, the chip being configured to execute instructions stored in the memory to cause the computing device to implement the memory management method provided in the first aspect or any possible implementation of the first aspect.

[0032] Fifthly, this application also provides a computing device cluster. The computing device cluster includes at least one computing device, each computing device including the chip and memory described in the third aspect; the chip of the at least one computing device is used to execute instructions stored in the memory of the at least one computing device, so that the computing device cluster implements the memory management method provided in the first aspect or any possible implementation in combination with the first aspect.

[0033] Sixthly, this application also provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to implement the memory management method provided in the first aspect or any possible implementation in conjunction with the first aspect.

[0034] In a seventh aspect, this application also provides a computer program product containing instructions that, when run on a computer, cause the computer to implement the memory management method provided in the first aspect or any possible implementation in conjunction with the first aspect.

[0035] Any of the devices, computer storage media, or computer program products provided above are used to execute the methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the corresponding solutions in the corresponding methods provided above, and will not be repeated here. Attached Figure Description

[0036] Figure 1 is a schematic diagram of a memory borrowing scenario provided in an embodiment of this application;

[0037] Figure 2 is a schematic diagram of the data mapping relationship of cache in a memory borrowing scenario provided in an embodiment of this application;

[0038] Figure 3 is a flowchart of a memory management method provided in an embodiment of this application;

[0039] Figures 4a and 4b are schematic diagrams illustrating a memory return method shown in Figure 3 provided in an embodiment of this application;

[0040] Figure 5 is a schematic diagram of the state transition of a state machine provided in an embodiment of this application;

[0041] Figure 6 is a flowchart of a data processing method applied to the method shown in Figure 3, provided by an embodiment of this application;

[0042] Figure 7 is a schematic diagram of the structure of a connector provided in an embodiment of this application;

[0043] Figures 8a to 8c are schematic diagrams of the connector shown in Figure 7 processing read / write / write-back requests according to an embodiment of this application;

[0044] Figure 9 is a schematic diagram of a memory management device based on the method shown in Figure 3 provided in an embodiment of this application;

[0045] Figure 10 is a schematic diagram of a data processing device based on the method shown in Figure 6 provided in an embodiment of this application;

[0046] Figure 11 is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0047] Figure 12 is a schematic diagram of the structure of a computing device cluster based on the computing device shown in Figure 11 provided in an embodiment of this application;

[0048] Figure 13 is a schematic diagram of a structure in which the memory management device shown in Figure 10 and the data processing device shown in Figure 11 are deployed in a computing device cluster shown in Figure 12, according to an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0050] In the description of the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0051] In the description of the embodiments in this application, the term "and / or" is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0053] A connector is a device located on the input / output die (IO die) integrated on the system-on-chip (SOC) of a computing device. Connectors can be used to enable communication between CPUs. For example, two computing devices (Computing Device A and B) each have a connector. The connector of Computing Device A can send data (and / or instructions) from the CPU of Computing Device A to the connector of Computing Device B, and / or send data (and / or instructions) from the CPU of Computing Device B sent by the connector of Computing Device B to the CPU of Computing Device A. As another example, a computing device includes two SOCs (SOC1 and SOC2), each with a connector. The connector of SOC1 can send data (and / or instructions) from the CPU of SOC1 to the connector of SOC2, and / or send data (and / or instructions) from the CPU of SOC2 sent by the connector of SOC2 to the CPU of SOC1.

[0054] A cache is a device located in a computing device that stores data read from the device's memory. Caches can include Level 1 cache, Level 2 cache, and Level 3 cache. Each cache contains multiple cache lines, and each cache line can include data bits, tag bits, valid bits, and dirty bits.

[0055] The data bits are used to store data read from memory. This data can be modified according to the user's actual needs.

[0056] The flag bit can be used to store the memory address of data or partial information about the memory address. When the core of the computing device needs to read data from memory, it compares the partial information of the memory address (usually the high-order bits) with the flag bit of the cache line to determine whether the required data is already in the cache.

[0057] The valid bit indicates whether the data in the cache line is valid. If the valid bit is set (usually 1), the data bits of the cache line contain valid data. If the valid bit is not set (usually 0), the data bits of the cache line do not contain valid data, i.e., the data bits are invalid data. Valid data refers to the data at the corresponding location in memory stored in the cache line, or the latest data after the data at the corresponding location in memory has been updated. Invalid data refers to outdated data or data that is inconsistent with the data at the corresponding location in memory. The CPU core can obtain valid data by accessing the cache through the cache controller without accessing memory.

[0058] The dirty bit (also known as the modified bit or modification flag) indicates whether data in a cache line has been modified but not yet written back to memory. If the dirty bit is set (usually 1), it indicates that the data in the cache line is different from the data in memory, meaning the data has been modified and is considered dirty data. If the dirty bit is not set (usually 0), it indicates that the data in the cache line is the same as the data in memory, meaning the data has not been modified.

[0059] A state machine consists of a state register and logic circuits. The state register stores state identifiers. The logic circuits determine the next state based on the input control signals and the current state, following pre-defined state transition logic, and modify the state identifiers stored in the state register, thereby achieving state transitions.

[0060] The states of a memory region include valid, invalid, and closed states.

[0061] When the memory region is in a valid state, a request to access the memory region can be successfully responded to, and data can be read from the memory region and / or written to the memory region.

[0062] In the case of an invalid memory region, requests to access the memory region cannot be successfully responded to (fail response), and it is impossible to read data from or write data to the memory region.

[0063] In the case of an invalid memory region, a request to access the memory region can be successfully responded to, but data cannot be read from or written to the memory region.

[0064] Figure 1 is a schematic diagram of a memory borrowing scenario provided in an embodiment of this application.

[0065] As shown in Figure 1, this scenario includes a first node 100 and a second node 200. The first node 100 and the second node 200 can be any two servers in a server cluster, or any virtual instance of two servers. This server cluster can be used to run a database system or a data center.

[0066] The first node 100's system-on-a-chip (SoC) integrates an input / output die (IO die) 1, a central processing unit (CPU) 101 as shown in Figure 1, and memory 102. The input / output die 1 integrates a connector 103 as shown in Figure 1.

[0067] The second node 100's system-on-a-chip integrates a read / write chip (input / output die, IO die) 2, a CPU 201 as shown in Figure 1, and a memory 202. Among them, the read / write chip 2 integrates a connector 203 as shown in Figure 1.

[0068] Connector 103 and connector 203 are communicatively connected. That is, connector 103 and connector 203 can communicate with each other through the communication components in their respective devices.

[0069] In the scenario shown in Figure 1, the first node 100 can borrow one or more memory regions from the second node 200 to store data, wherein the one or more memory regions are located in the memory 202 of the second node 200. By borrowing memory, the utilization rate of the memory resources of the second node 200 can be improved.

[0070] Generally, connector 103 can be used to store the status of one or more of the aforementioned memory regions. The status of a memory region can include a valid status and an invalid status. A valid status indicates that CPU 101 can read or write data to that memory region. An invalid status indicates that CPU 101 cannot read or write data to that memory region. In other words, connector 103 can only successfully respond to CPU 101's read / write requests for that memory region when the memory region is in a valid status.

[0071] For example, as shown in Figure 1, CPU 101 can send a read / write request to connector 103. The read / write request includes the memory address of first data, which is located in one of the aforementioned memory regions. Connector 103 receives the read / write request, determines the memory region based on the memory address in the read / write request, and if the memory region is determined to be in a valid state, sends a read / write operation to connector 203. Connector 203 receives the read / write operation and reads / writes data to memory 202 based on the read / write operation.

[0072] Figure 2 is a schematic diagram of the structure of the CPU 101 of the first node 100 provided in the embodiment of this application.

[0073] As shown in Figure 2, the CPU 101 may include a core 1011, a cache controller 1012, and a cache 1013. An application can run on the core 1011. After the application runs on the core 1011, it can generate read / write requests for the memory region of memory 202, thereby reading / writing data to memory 202.

[0074] During the process of reading / writing data to memory 202, as shown in Figure 2, the cache 1013 of CPU 101 can store first data and second data. As shown in Figure 2, the first data is mapped to memory 202, and the second data is mapped to memory 102. Furthermore, the cache 1013 stores identifiers for each piece of first data and identifiers for each piece of second data, including the aforementioned valid bit and dirty bit. It should be noted that the cache 1013 can include multiple pieces of first data and / or multiple pieces of second data.

[0075] In cases where the memory area of ​​memory 202 needs to be returned, it indicates that the first data stored in cache 1013 is no longer in use. The first data needs to be marked as invalid before the memory area of ​​memory 202 can be returned. However, the process of invalidating cached data usually takes a considerable amount of time, increasing the time required to return the memory. For example, the first data might be dirty data, requiring a write-back operation to be performed first, i.e., writing the first data back to the corresponding memory area in memory 202.

[0076] Therefore, this application provides a memory management method that can solve the above problems.

[0077] In the memory management method provided in this application embodiment, when the CPU 101 of the first node 100 determines that the memory region of the second node needs to be released, if the state of the memory region is determined to be valid, the CPU 101 first changes the state of the memory region to closed, and then notifies the second node 200 to release the memory region, thereby returning the memory region to the second node and releasing it from occupation.

[0078] The above scheme adds a "closed" state to the existing memory region state system (including valid and invalid states). When a memory region needs to be returned, its state is first changed from valid to closed, and then the second node 200 is notified to return the memory. Since the invalidation of cached data is not performed before notifying the second node 200 to return the memory, this scheme can shorten the memory return time.

[0079] The memory management method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0080] Figure 3 is a flowchart of a memory management method provided in an embodiment of this application. As shown in Figure 3, the method is applied to the first node 100, and the method may include the following steps S301 to S306.

[0081] S301, CPU101 determines to release a memory region located in memory 202 of the second node 200.

[0082] This step can be executed by CPU101 core 1011, which can determine the memory area to be returned based on user needs.

[0083] Specifically, the memory 102 of the first node 100 can store a memory management program. The user can launch this memory management program through the display interface of the first node 100, causing it to run on the core 1011 of the CPU 101. After the memory management program runs on the core 1011, the user can trigger memory return within the program, generating a memory return instruction. The memory return instruction can include identification information of the memory region. Thus, the core 1011 can determine the memory region to be returned based on the identification information in the memory return instruction; this address information can indicate the address range within memory 202.

[0084] S302, CPU101 determines that the memory region is in a valid state.

[0085] The states of a memory region include valid, invalid, and closed states. Different states are represented by different status identifiers. In other words, valid, invalid, and closed states each correspond to a different status identifier. For example, when the status identifiers are represented in binary, the status identifier for the valid state can be represented as 11, the status identifier for the invalid state can be represented as 00, and the status identifier for the closed state can be represented as 10.

[0086] After determining the memory region to be returned, core 1011 can obtain the status identifier of the memory region from connector 103 and determine the status of the memory region as valid based on the status identifier.

[0087] Specifically, connector 103 may include one or more state machines. A state machine may include a state register and logic circuitry. The state register stores state identifiers for different memory regions. The logic circuitry can modify the state identifiers in the state register according to instructions, thereby modifying the state of different memory regions and completing the state transitions shown in Figure 5. In Figure 5, the state of a memory region can transition from a valid state to a closed state, or from an invalid state to a valid state, or from a closed state to an invalid state.

[0088] Specifically, core 1011 can send a status read instruction to linker 103, which may include the address information of a memory region. Linker 103 receives the status read instruction, determines the memory region based on the address information, reads the status flag of the memory region from the status register in the state machine corresponding to that memory region, and returns it to core 1011. Core 1011 receives the status flag of the memory region and determines whether the memory region is in a valid state based on the status flag.

[0089] In some embodiments, CPU 101 may include one or more status registers for storing status identifiers of one or more memory regions. Thus, after determining that a memory region is to be returned, core 10111 can obtain the status identifier of the memory region from the status registers on CPU 101, and then determine that the memory region is in a valid state based on the status identifier.

[0090] S303, CPU101 changes the state of the memory region to the off state.

[0091] Taking the memory region status identifier stored in connector 103 as an example, as shown in Figure 4a, core 1011 can send a first status modification instruction to connector 103. The first status modification instruction may include the address information of the memory region and the status identifier corresponding to the closed state.

[0092] Connector 103 receives the first state modification instruction, determines the state machine storing the state of the memory region based on the address information of the memory region, and generates a control signal based on the state flag corresponding to the off state. The control signal is then input into the logic circuit of the state machine. The logic circuit can modify the state flag in the state register to the state flag corresponding to the off state based on the control signal and the state flag in the current state register, as shown in Figure 4a, thereby completing the transition from the active state to the off state as shown in Figure 5.

[0093] In some other embodiments, before modifying the state of the memory region to the off state, the CPU 101 can determine whether first data exists in the cache 1013, wherein the memory address of the first data is located in the memory region, and the first data is valid data. Specifically, the core 1011 can obtain the identifier bits of each cache line in the cache 1013 through the cache controller 1012, and determine one or more first cache lines based on the identifier bits of each cache line and the address range of the memory region. Taking the storage of the high-order part of the memory address in the flag bit of the first cache line as an example, the identifier bits of the cache line can be compared with the high-order part of each memory address in the address range of the memory region. If the identifier bit of the cache is the same as the high-order part of a memory address, the cache line is a first cache line. The core 1011 can determine whether the first data stored in the data bit of the first cache line is valid data based on the valid bit of the first cache line. For example, if the valid bit of the first cache line is 1, the first data is valid data; otherwise, it is invalid data. If the core 1011 determines that the first data does not exist in the cache, the core 1011 can execute S303 to modify the state of the memory region to the invalid state.

[0094] S304, CPU101 notifies the second node 200 to return the memory area.

[0095] Core 1011 can send a notification message to second node 200 via the communication component in first node 100, as shown in Figure 4a, to notify the second node to return the memory region. The communication component may include, but is not limited to, a wired communication module and / or a wireless communication module. Notifying the second node 200 to return the memory region indicates that the memory region has been returned.

[0096] S305, CPU101 marks the first data as invalid data.

[0097] As shown in Figure 4a, the core 1011 can send an invalidation instruction to the cache controller 1012 to mark one or more first data items as invalid data. The specific execution process of the cache controller will be described in detail later with reference to Figure 6, and will not be repeated here.

[0098] S306, CPU101 instructs connector103 to modify the state of the memory region to an invalid state.

[0099] As shown in Figure 4b, the core 1011 can send a second state modification instruction to the linker 103 to modify the state of the memory region to an invalid state. The second state modification instruction may include the address information of the memory region and the state identifier corresponding to the invalid state.

[0100] Connector 103 receives the second state modification instruction, determines the state machine storing the state of the memory region based on the address information of the memory region, and generates a control signal based on the state flag corresponding to the invalid state. The control signal is then input into the logic circuit of the state machine. The logic circuit can modify the state flag in the state register to the state flag corresponding to the invalid state based on the control signal and the state flag in the current state register, as shown in Figure 4b, thereby completing the transition from the off state to the invalid state as shown in Figure 5.

[0101] In the case where the state of the memory region is invalid, the connector 103 can use the state machine to represent the state of other memory regions and control the state transitions of other memory regions.

[0102] In the method embodiment shown in Figure 3 above, a "closed" state is added to the memory region's state system. When a memory region needs to be returned, and it is determined that valid data mapping that memory region exists in the cache, the memory region's state is first changed from a valid state to a closed state. Furthermore, while in the closed state, the first node notifies the second node 200 to return the memory region. This avoids the process of entering invalid cache data before returning the memory region, thus saving time.

[0103] Based on the method embodiment shown in Figure 3, this application embodiment also provides a data processing method.

[0104] Figure 6 is a flowchart of a data processing method provided in an embodiment of this application. As shown in Figure 6, the method may include steps S601-S605.

[0105] S601, after notifying the second node to return the memory region, as shown in Figure 4a, the core 1011 can send an invalidation instruction to the cache controller 1012 to mark the data mapping the memory region as invalid data. The invalidation instruction may include tag bits of one or more first cache lines in the cache 1013.

[0106] S602, the cache controller 1012 receives an invalid instruction and determines whether the first data is dirty data.

[0107] After receiving an invalid instruction, the cache controller 1012 can obtain the dirty bit of the first cache line based on the tag bit in the invalid instruction. Furthermore, it determines whether the first data stored in the data bit of the first cache line is dirty data based on the dirty bit.

[0108] In step S603, if the first data is determined to be dirty data, as shown in FIG4a, the cache controller 1012 sends a write-back request to the connector 103. This write-back request may include the first data and its memory address. The memory address of the first data is located in the specified memory region.

[0109] S604, connector 103 receives the write-back request, returns a success response, and discards the first data.

[0110] After receiving a write-back request, connector 103 determines the memory region based on the memory address in the write-back request and obtains the status of that memory region. If the status of the memory region is determined to be closed, a success response is sent to cache controller 1012, and then the first data is discarded. Since core 1011 has already instructed connector 103 to change the status of the memory region to closed, indicating that the memory region has been returned to second node 200, connector 103 cannot send a message requesting the writing of the first data to second node 200. By discarding the first data, connector 103 saves communication resources between first node 100 and second node 200.

[0111] S605, the cache controller 1012 receives a success response and marks the first data as invalid data.

[0112] Specifically, after receiving a successful response, the cache controller 1012 can modify the valid bit in the first cache line to indicate invalidity.

[0113] In this embodiment, if it is determined in S602 that the first data is not dirty data, as shown in FIG6, the cache controller 1012 can directly modify the valid bit in the first cache line to an invalid identifier.

[0114] In the embodiment shown in Figure 6 above, when invalid cached data occurs, if a write-back operation happens, the connector 103 responds successfully, thus avoiding affecting the invalidation process of the cache controller 1012. Since the core 1011 has already instructed the connector 103 to change the state of the memory region to a close instruction and notified the second node 200 to return the memory region, the connector 103 can discard the data requested for write-back. Simultaneously, this saves communication resources between the two nodes.

[0115] Based on the method embodiment shown in FIG3, this application embodiment also provides a connector.

[0116] Figure 7 is a schematic diagram of a connector provided in an embodiment of this application. As shown in Figure 7, the connector may include a receiving module and a transmitting module. This connector can be applied to the first node 100 and / or the second node 200 described above to enable communication between the two nodes.

[0117] Taking the application of the connector to the first node 100 as an example, the functions of the receiving module and the transmitting module are as follows.

[0118] The receiving module can be used to receive messages from the second node 100 and send the messages to the core 1011 and / or the cache controller 1012.

[0119] The sending module can be used to receive status modification instructions from the core 1011, as well as read / write requests and write-back requests from the cache controller 1012.

[0120] When a state modification instruction is received, the sending module modifies the state of the memory region according to the instruction. The sending module may include one or more state machines. Each state machine includes a state register and logic circuitry. The state register of the state machine stores the state flag of the memory region. The logic circuitry of the state machine controls the state transitions of the memory region according to the state modification instructions from the receiving module, such as the first and second state modification instructions mentioned above. A schematic diagram of the state transitions of each memory region is shown in Figure 5.

[0121] Upon receiving a read / write request or write-back request, the sending module determines whether to send the request to the connector of the second node 200 based on the status flag of the memory region stored in the state machine's status register. This read / write request or write-back request is used to access the memory region.

[0122] When the memory area stored in the status register is in a valid state, as shown in Figure 8a, after receiving the request from the cache controller 1012, the sending module 702 sends a success response to the cache controller 1012, and then sends a read or write message to the connector 203 of the second node so that the second node 200 can perform a read or write operation.

[0123] When the memory area stored in the status register is in the closed state, as shown in Figure 8b, after receiving a request from the cache controller 1012, the sending module 702 sends a success response to the cache controller 1012, but does not send read or write messages to the connector 203 of the second node. Specifically, when the request is a write request or a write-back request, the sending module 702 discards the requested data.

[0124] If the memory region stored in the status register is in an invalid state, the connector 103 cannot respond to the request from the cache controller 1012 because the memory has been returned. As shown in Figure 8c, after receiving the request from the cache controller 1012, the sending module 702 sends a failure response to the cache controller 1012.

[0125] Based on the method embodiment shown in FIG3, this application provides a memory management device.

[0126] Figure 9 is a schematic diagram of a memory management device 900 provided in an embodiment of this application. As shown in Figure 9, the memory management device 900 may include a processing module 901 and a notification module 902.

[0127] The processing module 901 is used to determine if the memory region returned by the first node to the second node is valid. If the CPU's cache contains first data, the module instructs the first connector to change the state of the memory region to a closed state. The first node includes a CPU and a first connector, which is communicatively connected to a second connector in the second node. The CPU borrows the memory region to store data through the first and second connectors. The first connector stores the state of the memory region. Furthermore, if the memory address of the first data is located in the memory region and the first data is valid, the first connector discards the data requested by the CPU to be written to the memory region when the memory region is in the closed state.

[0128] The notification module 902 is used to notify the second node to return the memory region.

[0129] It should be noted that the memory management device 900 provided in the embodiment shown in Figure 9 is only illustrated by the division of the above-mentioned functional modules when executing the memory management method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the memory management device provided in the above embodiment and the memory management method embodiment shown in Figure 3 belong to the same concept, and the specific implementation process can be found in the method embodiment, which will not be repeated here.

[0130] Based on the method embodiment shown in FIG6, this application provides a data processing apparatus.

[0131] Figure 10 is a schematic diagram of a data processing apparatus 1000 provided in an embodiment of this application. As shown in Figure 10, the data processing apparatus 1000 may include an invalidation module 1001, a write-back module 1002, and a marking module 1003.

[0132] The invalidation module 1001 is used to send invalidation instructions to the cache controller 1012.

[0133] The write-back module 1002 is used to send a write-back request to the connector 103 when the cache controller 1012 determines that the first data is dirty data. The connector 103 receives the write-back request, returns a success response, and discards the first data.

[0134] The marking module 1003 is used to mark the first data as invalid data.

[0135] It should be noted that the data processing device 1000 provided in the embodiment shown in Figure 10 is only illustrated by the division of the above-mentioned functional modules when executing the data processing method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the data processing device provided in the above embodiment and the data processing method embodiment shown in Figure 6 belong to the same concept, and the specific implementation process can be found in the method embodiment, which will not be repeated here.

[0136] Figure 11 is a schematic diagram of the hardware structure of a computing device 1100 provided in an embodiment of this application.

[0137] The computing device 1100 can be either the first node 100 or the second node 200 described above. Referring to Figure 11, the computing device 1100 includes a chip 1101, a memory 1102, a communication interface 1103, and a bus 1104. The chip 1101, memory 1102, and communication interface 1103 are interconnected via the bus 1104. The chip 1101, memory 1102, and communication interface 1103 can also be connected using other connection methods besides the bus 1104.

[0138] The memory 1102 can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical storage, hard disk, etc.

[0139] Chip 1101 may be a System-on-a-Chip (SOC) as described above, which may include a processor and a connector. The processor may be a general-purpose processor. A general-purpose processor may be a processor that performs specific steps and / or operations by reading and executing contents stored in memory (e.g., memory 1102). For example, a general-purpose processor may be a central processing unit (CPU). Chip 1101 may include at least one circuit to perform all or part of the steps of the methods provided in the embodiments shown in FIG3 or FIG6.

[0140] The communication interface 1103 includes input / output (I / O) interfaces, physical interfaces, and logical interfaces for interconnecting devices within the computing device 1100, as well as interfaces for interconnecting the computing device 1100 with other devices (such as other computing devices or user equipment). The physical interface can be an Ethernet interface, a fiber optic interface, an ATM interface, etc.

[0141] The bus 1104 can be any type of communication bus used to interconnect the chip 1101, memory 1102 and communication interface 1103, such as a system bus.

[0142] The aforementioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. Whether to dispose of the devices independently on different chips or integrate them on one or more chips often depends on the needs of the product design. This application does not limit the specific implementation of the aforementioned devices.

[0143] The computing device 1100 shown in Figure 11 is merely an example. In the implementation process, the computing device 1100 may also include other components, which will not be listed one by one in this article.

[0144] Based on the methods shown in Figures 3 and 6, embodiments of this application also provide a computing device cluster.

[0145] Figure 12 illustrates a computing device cluster 1200 according to an embodiment of this application. As shown in Figure 12, the computing device cluster includes at least one computing device 1100. The memory 1102 of one or more computing devices 1100 in the computing device cluster may store the same instructions for executing the methods shown in Figure 3 or Figure 6. A memory management device 900 and / or a data processing device 1000 may be deployed on one computing device 1100 or distributed across multiple computing devices 1100. In the distributed deployment scenario, the memory management device 900 may be deployed on one computing device or distributed across multiple computing devices 1100; similarly, the data processing device 1000 may be deployed on one computing device 1100 or distributed across multiple computing devices 1100.

[0146] The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smartphone.

[0147] In some possible implementations, the memory 1102 of one or more computing devices 1100 in the computing device cluster may also store partial instructions for executing the methods shown in FIG3 or FIG6. In other words, a combination of one or more computing devices 1100 may jointly store instructions for executing the methods shown in FIG3 or FIG6.

[0148] It should be noted that the memory 1102 in different computing devices 1100 within the computing device cluster can store different instructions, which are used to execute some functions of the devices shown in FIG9 and / or FIG10. That is, the instructions stored in the memory 1102 in different computing devices 1100 can implement the functions of one or more modules in the devices shown in FIG9 and / or FIG10.

[0149] In some possible implementations, one or more computing devices in a computing device cluster can be connected via a network. This network can be a wide area network (WAN) or a local area network (LAN), etc. Figure 13 illustrates one possible implementation. As shown in Figure 13, two computing devices 1100A and 1100B are connected via a network. Specifically, they are connected to the network through communication interfaces in each computing device. In this type of possible implementation, the memory 1102 in computing device 1100A stores instructions for implementing the functions of the memory management device 900. Simultaneously, the memory 1102 in computing device 1100B stores instructions for implementing the functions of the data processing device 1000.

[0150] It should be understood that the functions of computing device 1100A shown in Figure 13 can also be performed by multiple computing devices 1100. Similarly, the functions of computing device 1100B can also be performed by multiple computing devices 1100.

[0151] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0152] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. It should be understood that in the embodiments of this application, the order of the process numbers does not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0153] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A memory management method, characterized in that, Applied to a first node, the first node including a central processing unit (CPU) and a first connector, the first connector being communicatively connected to a second connector in a second node, the CPU being used to occupy a memory region of the second node to store data via the first connector and the second connector, the method comprising: The CPU determines to release the memory region. If the memory region is in an active state, the CPU changes the state of the memory region to a closed state. The first connector is used to discard the data that the CPU requests to write to the memory region when the memory region is in the closed state. The CPU sends a notification message to the second node, the notification message indicating that the first node is releasing the memory region.

2. The method according to claim 1, characterized in that, The CPU cache includes first data, the memory address of which is located in the memory region. After the CPU sends a notification message to the second node, the method further includes: If the CPU determines that the first data is valid, it will mark the first data as invalid. The CPU modifies the state of the memory region to an invalid state.

3. The method according to claim 2, characterized in that, Before the CPU marks the first data as invalid data, the method further includes: When the CPU determines that the first data is dirty data, it sends a write-back request to the first connector. The write-back request includes the first data and the memory address of the first data. The first connector receives the write-back request, obtains the status of the memory region based on the memory address in the write-back request, and if the status of the memory region is determined to be the closed state, sends a success response to the CPU and discards the first data. The CPU receives the success response and determines that the first data should be marked as invalid data.

4. The method according to claim 2 or 3, characterized in that, The first connector stores the status identifiers of the memory region. Different status identifiers are used to represent different states. The CPU determines that the state of the memory region is valid by: Obtain the status identifier of the memory region from the first connector; The state of the memory region is determined to be the valid state based on the state identifier of the memory region.

5. The method according to claim 4, characterized in that, The CPU modifies the state of the memory region to a closed state by: The CPU sends a first modification instruction to the first connector; The first connector receives the first modification instruction and modifies the state of the memory region to the closed state according to the first modification instruction.

6. The method according to claim 4 or 5, characterized in that, The CPU modifies the state of the memory region to an invalid state by: The CPU sends a second modification instruction to the first connector; The first connector receives the second modification instruction and modifies the state of the memory region to the invalid state according to the second modification instruction.

7. The method according to any one of claims 1-6, characterized in that, The first connector includes a state machine, which includes a state register and logic circuitry. The state register is used to store the state identifier of the memory region, and the logic circuitry is used to modify the state identifier stored in the state register according to the modification instruction sent by the CPU.

8. The method according to any one of claims 2-7, characterized in that, The CPU also includes a core and a cache controller, and the CPU marks the first data as invalid data by: The core instructs the cache controller to mark the first data as invalid data.

9. A memory management device, characterized in that, The device includes: A processing module is configured to determine when a first node releases a memory region of a second node, and, if the memory region is in a valid state, modify the state of the memory region to a closed state. The first node includes a CPU and a first connector, the first connector being communicatively connected to a second connector in the second node. The CPU is configured to occupy the memory region to store data via the first and second connectors. The first connector is configured to discard data requested by the CPU to be written to the memory region if the memory region is in the closed state. The notification module is used to send a notification message to the second node, the notification message indicating that the first node has released the memory region.

10. The apparatus according to claim 9, characterized in that, The CPU cache includes first data, the memory address of which is located in the memory region. After sending a notification message to the second node, the processing module is further configured to: If the first data is determined to be valid, the first data is marked as invalid data; Change the state of the memory region to invalid.

11. The apparatus according to claim 10, characterized in that, Before the CPU marks the first data as invalid data, The processing module is further configured to send a write-back request to the first connector when it is determined that the first data is dirty data. The write-back request includes the first data and the memory address of the first data. The first connector is configured to receive the write-back request, obtain the status of the memory region according to the memory address in the write-back request, and send a success response to the CPU and discard the first data when it is determined that the status of the memory region is the closed state. The CPU receives the success response and determines that the first data should be marked as invalid data.

12. The apparatus according to any one of claims 9 or 10, characterized in that, The first connector stores the status identifiers of the memory region, with different status identifiers representing different states. The processing module is further configured to: Obtain the status identifier of the memory region from the first connector; The state of the memory region is determined to be the valid state based on the state identifier of the memory region.

13. The apparatus according to claim 12, characterized in that, The processing module is also used for: A first modification instruction is sent to the first connector, which is used to receive the first modification instruction and modify the state of the memory region to the closed state according to the first modification instruction.

14. The apparatus according to claim 12 or 13, characterized in that, The processing module is also used for: A second modification instruction is sent to the first connector, which receives the second modification instruction and modifies the state of the memory region to the invalid state according to the second modification instruction.

15. The apparatus according to any one of claims 9-14, characterized in that, The first connector includes a state machine, which includes a state register and logic circuitry. The state register is used to store the state identifier of the memory region, and the logic circuitry is used to modify the state identifier stored in the state register according to the modification instruction sent by the CPU.

16. The apparatus according to any one of claims 10-15, characterized in that, The CPU also includes a cache controller, and the processing module is further configured to: instruct the cache controller to mark the first data as invalid data.

17. A chip, characterized in that, The chip includes a CPU and a first connector, the CPU and the first connector being used to implement the method according to any one of claims 1 to 8.

18. A computing device, characterized in that, The computing device includes the chip and memory as described in claim 17, the chip being configured to execute instructions stored in the memory to cause the computing device to implement the method of any one of claims 1 to 6.

19. A computing device cluster, characterized in that, The system includes at least one computing device, each computing device including the chip and memory as described in claim 17, wherein the chip of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device to cause the cluster of computing devices to implement the method of any one of claims 1 to 8.

20. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 8.

21. A computer program product, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 8.

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