Surge protection circuit having high response speed and voltage clamping function

Abstract

Provided is a surge protection circuit. A protected circuit is connected between a power supply terminal avdd and a ground terminal avss. The surge protection circuit comprises a fast start-up circuit, a bleeder circuit, and a voltage clamping circuit. The fast start-up circuit comprises a first resistor R1, a second PNP triode Q2, a first forward diode D1, a second forward diode D2, and a first high-voltage PMOS transistor PM1. The bleeder circuit comprises a first high-voltage NMOS transistor NM1, a first high-voltage NPN transistor Q1, a second resistor R2, a second high-voltage PMOS transistor PM2, a third high-voltage PMOS transistor PM3, a third resistor R3, a seventh diode D7, a second high-voltage NMOS transistor NM2, a fourth resistor R4, and a third high-voltage NMOS transistor NM3. The voltage clamping circuit comprises a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6.

Description

A surge protection circuit with high response speed and voltage clamping function Technical Field

[0001] This invention relates to the field of active protection circuits, and more specifically, to a surge protection circuit with high response speed and voltage clamping function. Background Technology

[0002] With the development of electronic information technology, the application of various electronic devices and systems is becoming increasingly widespread. However, as the complexity of electrical and electronic systems continues to increase, circuits also face various electrical interference and overvoltage problems. The protection requirements for surge and other EOS / ESD electrical overstress events in circuits are also becoming increasingly stringent. Common EOS / ESD electrical overstress protection uses passive single devices to achieve protection functions, or uses RC circuits for current discharge without voltage clamping functions. These protection devices / circuits have slow response speeds and relatively simple functions, which cannot meet the increasingly demanding circuit protection requirements. Currently, there is little research on active circuits specifically for EOS protection. Most studies focus on designing TVS devices with good EOS protection performance. The commonly used positive differential negative resistance TVS devices in the industry are mainly diodes, Schottky diodes, and Zener diodes. Although these devices have good voltage clamping functions, their EOS electrical overstress protection robustness is poor, and they cannot be actively controlled, lacking controllability. Summary of the Invention

[0003] This invention provides a surge protection circuit with high response speed and voltage clamping function to solve the technical problems existing in the prior art.

[0004] To achieve the above objectives, the present invention provides a surge protection circuit with high response speed and voltage clamping function. The protected circuit is connected between the power supply terminal avdd and the ground terminal avss, and includes a fast start-up circuit, a discharge circuit, and a voltage clamping circuit, wherein:

[0005] The fast-start circuit includes a first resistor R1, a second PNP transistor Q2, a first forward diode D1, a second forward diode D2, and a first high-voltage PMOS transistor PM1.

[0006] The discharge circuit includes a first high-voltage NMOS transistor NM1, a first high-voltage NPN transistor Q1, a second resistor R2, a second high-voltage PMOS transistor PM2, a third high-voltage PMOS transistor PM3, a third resistor R3, a seventh diode D7, a second high-voltage NMOS transistor NM2, a fourth resistor R4, and a third high-voltage NMOS transistor NM3.

[0007] The voltage clamping circuit includes a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6.

[0008] The PLUS terminal of the first resistor R1 is connected to the power supply voltage terminal avdd. The MINUX terminal of the first resistor R1 is connected to the emitter of the second PNP transistor Q2. The base of the second PNP transistor Q2 is connected to the PLUS terminal of the first forward diode D1. The PLUS terminal of the second forward diode D2 is connected to the MINUX terminal of the first forward diode D1 and the gate of the first high-voltage PMOS transistor PM1, forming node A, which is used to quickly turn on the first high-voltage PMOS transistor PM1. The drain of the first high-voltage PMOS transistor PM1 is connected to the gate of the second high-voltage NMOS transistor NM2, the PLUS terminal of the third resistor R3, and the drain of the third high-voltage PMOS transistor PM3, forming node C.

[0009] The PLUS terminal of the third diode D3 is connected to the MINUX terminal of the second forward diode D2. The MINUX terminal of the third diode D3 is connected to the PLUS terminal of the fourth diode D4. The MINUX terminal of the fourth diode D4 is connected to the PLUS terminal of the fifth diode D5. The MINUX terminal of the fifth diode D5 is connected to the PLUS terminal of the sixth diode D6 and the gate of the first high-voltage NMOS transistor NM1. The MINUX terminal of the sixth diode D6 is connected to the base of the first high-voltage NPN transistor Q1.

[0010] The gate of the first high-voltage NMOS transistor NM1 is connected to the MINUX terminal of the fifth diode D5 and the PLUS terminal of the sixth diode D6. The source of the first high-voltage NMOS transistor NM1 is connected to the collector of the first high-voltage NPN transistor Q1. The base of the first high-voltage NPN transistor Q1 is connected to the MINUX terminal of the sixth diode D6. The emitter of the first high-voltage NPN transistor Q1 is connected to the PLUS terminal of the second resistor R2. The MINUX terminal of the second resistor R2 is connected to the ground terminal avss. The drain of the second high-voltage PMOS transistor PM2 is connected to the drain of the first high-voltage NMOS transistor NM1 and the gate of the second high-voltage PMOS transistor PM2. The source of the second high-voltage PMOS transistor PM2 is connected to the power supply terminal avdd. The gate of the third high-voltage PMOS transistor PM3 is connected to the gate of the second high-voltage PMOS transistor PM2 as a current mirror. The source of the third high-voltage PMOS transistor PM3... Connect the power supply terminal avdd. The drain of the third high-voltage PMOS transistor PM3 is connected to the PLUS terminal of the third resistor R3, the gate of the second high-voltage NMOS transistor NM2, the PLUS terminal of the seventh diode D7, and the drain of the first high-voltage PMOS transistor PM1, forming node C. The MINUX terminal of the third resistor R3 is connected to the ground terminal avss. The MINUX terminal of the seventh diode D7 is connected to the ground terminal avss. The drain of the second high-voltage NMOS transistor NM2 is connected to the power supply terminal avdd. The source of the second high-voltage NMOS transistor NM2 is connected to the PLUS terminal of the fourth resistor R4 and the gate of the third high-voltage NMOS transistor NM3, forming node D. The MINUX terminal of the fourth resistor R4 is connected to the ground terminal avss. The drain of the third high-voltage NMOS transistor NM3 is connected to the power supply terminal avdd. The source of the third high-voltage NMOS transistor NM3 is connected to the ground terminal avss.

[0011] In one embodiment of the present invention, the first forward diode D1 and the second forward diode D2 are Schottky diodes.

[0012] In one embodiment of the present invention, the third diode D3 to the seventh diode D7 are Zener diodes.

[0013] In the event of a surge, the surge protection circuit provided by this invention, featuring high response speed and voltage clamping function, can automatically activate and release current to maintain voltage stability in subsequent circuits. This invention uses high-voltage MOSFETs to control the current switching of each branch, thereby avoiding leakage and reducing static power consumption. By ensuring that the current flowing through the diode series branch is small, the size of the diodes can be effectively reduced, saving layout area and decreasing diode capacitance, which helps improve the response speed of the voltage regulation function and achieve more reliable protection. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 is a structural block diagram of the surge protection circuit with high response speed and voltage clamping function provided by the present invention;

[0016] Figure 2 is a circuit diagram of a surge protection circuit with high response speed and voltage clamping function according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Figure 1 is a structural block diagram of the surge protection circuit with high response speed and voltage clamping function provided by the present invention, and Figure 2 is a circuit diagram of the surge protection circuit with high response speed and voltage clamping function according to an embodiment of the present invention. As shown in Figures 1 and 2, the present invention provides a surge protection circuit with high response speed and voltage clamping function. The protected circuit is connected between the power supply terminal avdd and the ground terminal avss, and includes a fast start-up circuit, a discharge circuit, and a voltage clamping circuit, wherein:

[0019] The fast-start circuit is used to quickly start the bleed tube in the early stage of an electrical overstress event (surge event) to achieve current discharge;

[0020] The discharge circuit includes circuit structures such as transistors, current mirrors, and high-voltage discharge tubes, and is used to discharge current during electrical overstress events to prevent damage to subsequent circuits.

[0021] Voltage clamping circuits are used to provide voltage clamping protection for downstream circuits during electrical overstress events, preventing overvoltage damage.

[0022] As shown in Figure 1, the fast-start circuit includes a first resistor R1, a second PNP transistor Q2, a first forward diode D1, a second forward diode D2, and a first high-voltage PMOS transistor PM1.

[0023] The discharge circuit includes a first high-voltage NMOS transistor NM1, a first high-voltage NPN transistor Q1, a second resistor R2, a second high-voltage PMOS transistor PM2, a third high-voltage PMOS transistor PM3, a third resistor R3, a seventh diode D7, a second high-voltage NMOS transistor NM2, a fourth resistor R4, and a third high-voltage NMOS transistor NM3.

[0024] The voltage clamping circuit includes a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6.

[0025] The PLUS terminal of the first resistor R1 is connected to the power supply voltage terminal avdd. The MINUX terminal of the first resistor R1 is connected to the emitter of the second PNP transistor Q2. The base of the second PNP transistor Q2 is connected to the PLUS terminal of the first forward diode D1. The PLUS terminal of the second forward diode D2 is connected to the MINUX terminal of the first forward diode D1 and the gate of the first high-voltage PMOS transistor PM1, forming node A, which is used to quickly turn on the first high-voltage PMOS transistor PM1. The drain of the first high-voltage PMOS transistor PM1 is connected to the gate of the second high-voltage NMOS transistor NM2, the PLUS terminal of the third resistor R3, and the drain of the third high-voltage PMOS transistor PM3, forming node C.

[0026] The PLUS terminal of the third diode D3 is connected to the MINUX terminal of the second forward diode D2. The MINUX terminal of the third diode D3 is connected to the PLUS terminal of the fourth diode D4. The MINUX terminal of the fourth diode D4 is connected to the PLUS terminal of the fifth diode D5. The MINUX terminal of the fifth diode D5 is connected to the PLUS terminal of the sixth diode D6 and the gate of the first high-voltage NMOS transistor NM1. The MINUX terminal of the sixth diode D6 is connected to the base of the first high-voltage NPN transistor Q1.

[0027] The gate of the first high-voltage NMOS transistor NM1 is connected to the MINUX terminal of the fifth diode D5 and the PLUS terminal of the sixth diode D6. The source of the first high-voltage NMOS transistor NM1 is connected to the collector of the first high-voltage NPN transistor Q1. The base of the first high-voltage NPN transistor Q1 is connected to the MINUX terminal of the sixth diode D6. The emitter of the first high-voltage NPN transistor Q1 is connected to the PLUS terminal of the second resistor R2. The MINUX terminal of the second resistor R2 is connected to the ground terminal avss. The drain of the second high-voltage PMOS transistor PM2 is connected to the drain of the first high-voltage NMOS transistor NM1 and the gate of the second high-voltage PMOS transistor PM2. The source of the second high-voltage PMOS transistor PM2 is connected to the power supply terminal avdd. The gate of the third high-voltage PMOS transistor PM3 is connected to the gate of the second high-voltage PMOS transistor PM2 as a current mirror. The source of the third high-voltage PMOS transistor PM3... Connect the power supply terminal avdd. The drain of the third high-voltage PMOS transistor PM3 is connected to the PLUS terminal of the third resistor R3, the gate of the second high-voltage NMOS transistor NM2, the PLUS terminal of the seventh diode D7, and the drain of the first high-voltage PMOS transistor PM1, forming node C. The MINUX terminal of the third resistor R3 is connected to the ground terminal avss. The MINUX terminal of the seventh diode D7 is connected to the ground terminal avss. The drain of the second high-voltage NMOS transistor NM2 is connected to the power supply terminal avdd. The source of the second high-voltage NMOS transistor NM2 is connected to the PLUS terminal of the fourth resistor R4 and the gate of the third high-voltage NMOS transistor NM3, forming node D. The MINUX terminal of the fourth resistor R4 is connected to the ground terminal avss. The drain of the third high-voltage NMOS transistor NM3 is connected to the power supply terminal avdd. The source of the third high-voltage NMOS transistor NM3 is connected to the ground terminal avss.

[0028] In this embodiment, the first forward diode D1 and the second forward diode D2 are Schottky diodes.

[0029] In this embodiment, the third diode D3 to the seventh diode D7 are Zener diodes.

[0030] The surge protection circuit with high response speed and voltage clamping function provided by the present invention is connected in parallel with the protected circuit between the power supply terminal avdd and the ground terminal avss. When a surge event occurs, the surge protection circuit with high response speed and voltage clamping function provided by the present invention starts to work, discharges current and maintains the voltage stability at both ends of the subsequent circuit.

[0031] When a surge event occurs in the circuit, the fast-start circuit starts working first. First, the voltage at the power supply terminal avdd is rapidly increased. In the early stage of the surge, the PN junction of Q2 is turned on, which increases the potential at the PLUS terminal of D1. Then D1 and D2 are turned on. The forward conduction voltage drop of D1 and D2 creates a potential difference between the gate potential and the source potential of PM1. That is, the potential difference between point A and point B is the voltage drop when the two forward diodes are turned on, which turns on PM1. The drain potential of PM1, i.e., node C, is rapidly pulled up, the gate voltage of NM2 is pulled up, and NM2 is turned on. The source current of NM2 through resistor R4 increases the voltage at node D, i.e., the gate voltage of NM3, and NM3 is turned on, completing the fast response function.

[0032] In the bleeder circuit, PM2 and PM3 form current mirrors of the same size to reduce gain, increase bandwidth, and improve circuit response speed. The current mirror copy ratio of the second high-voltage PMOS transistor PM2 and the third high-voltage PMOS transistor PM3 is 1:1. After NM1 and Q1 are turned on, the PM2 branch generates current, which is copied to the PM3 branch. The drain current of PM3 flows through resistor R3, generating a voltage drop that increases the node voltage C, i.e., the gate voltage of NM2 increases, and NM2 turns on. Zener diode D7 is used to protect the gate of NM2 and prevent gate-source breakdown. The source current of NM2 flows through resistor R4, generating a voltage drop that increases the node voltage D, i.e., the gate voltage of NM3 increases, and NM3 turns on to discharge surge current.

[0033] In a voltage clamping circuit, when a surge event causes the power supply terminal voltage avdd to rise continuously, when the difference between the base voltage of Q2 and the base voltage of Q1 reaches the turn-on voltage of the forward diode string (D1~D2) and the Zener diode string (D3~D6), the diode string (D1~D2, D3~D6) conducts, and V Diode This is the forward voltage of the diode string, and it is related to the voltage drop across resistor R1 and the voltage across transistor Q2 in the circuit. BE2 V of transistor Q1 BE1 Together with the voltage drop across resistor R2, they form the voltage clamping value V. clamp This enables the circuit to regulate voltage.

[0034] When Q1, Q2, and the diode string are fully turned on, the clamping voltage value V clamp =V R1 +V BE2 +V Diode +V BE1 +V R2 V R1 The voltage drop across the first resistor R1 when the circuit is fully conducting, V BE2 The absolute value of the base-emitter voltage difference of the second PNP transistor Q2, V. DiodeThis refers to the sum of the voltage drops of the forward diode string and the Zener diode string, V. BE1 This refers to the absolute value of the base-emitter voltage difference of the first high-voltage NPN transistor Q1, V. R2 This refers to the voltage drop across the first resistor R2 when the circuit is fully conducting.

[0035] The sum of the voltage drops of the forward diode string and the Zener diode string, V clamp The voltage regulation value of the circuit can be actively adjusted by modifying the connection method and number of diodes in the diode string.

[0036] This invention employs a BJT, a current mirror, and a source follower (NM2 and R4 constitute the source follower) to achieve a fast circuit response. A high-voltage power MOSFET is used to discharge surge current. During a surge event, the current characteristics of the transistor and the working principle of the source follower are utilized to rapidly increase the gate voltage of the high-voltage power MOSFET, enabling it to conduct quickly. Schottky diodes and Zener diodes are used, leveraging the forward voltage drop of the Schottky diode and the Zener diode's voltage regulation value. By combining different forward and reverse diode connections, different voltage clamping and regulation values ​​are set for the protection circuit, achieving voltage regulation during surges.

[0037] In the event of a surge, the surge protection circuit provided by this invention, featuring high response speed and voltage clamping function, can automatically activate and release current to maintain voltage stability in subsequent circuits. This invention uses high-voltage MOSFETs to control the current switching of each branch, thereby avoiding leakage and reducing static power consumption. By ensuring that the current flowing through the diode series branch is small, the size of the diodes can be effectively reduced, saving layout area and decreasing diode capacitance, which helps improve the response speed of the voltage regulation function and achieve more reliable protection.

[0038] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention.

[0039] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A surge protection circuit having high response speed and voltage clamping function, a protected circuit being connected between a power supply terminal avdd and a ground terminal avss, characterized by, The application relates to a fast starting circuit, a bleeder circuit and a voltage clamping circuit, wherein: The fast starting circuit comprises a first resistor R1, a second PNP transistor Q2, a first forward diode D1, a second forward diode D2 and a first high-voltage PMOS tube PM1, The bleeder circuit comprises a first high-voltage NMOS tube NM1, a first high-voltage NPN tube Q1, a second resistor R2, a second high-voltage PMOS tube PM2, a third high-voltage PMOS tube PM3, a third resistor R3, a seventh diode D7, a second high-voltage NMOS tube NM2, a fourth resistor R4 and a third high-voltage NMOS tube NM3, The voltage clamping circuit comprises a third diode D3, a fourth diode D4, a fifth diode D5 and a sixth diode D6, The PLUS end of the first resistor R1 is connected with a power supply voltage terminal avdd, the MINUX end of the first resistor R1 is connected with the emitter of the second PNP transistor Q2, the base of the second PNP transistor Q2 is connected with the PLUS end of the first forward diode D1, the PLUS end of the second forward diode D2 is connected with the MINUX end of the first forward diode D1 and the gate of the first high-voltage PMOS tube PM1, thereby forming a node A, which is used for making the first high-voltage PMOS tube PM1 quickly conductive, the drain of the first high-voltage PMOS tube PM1 is connected with the gate of the second high-voltage NMOS tube NM2, the PLUS end of the third resistor R3 and the drain of the third high-voltage PMOS tube PM3, thereby forming a node C, The PLUS end of the third diode D3 is connected with the MINUX end of the second forward diode D2, the MINUX end of the third diode D3 is connected with the PLUS end of the fourth diode D4, the MINUX end of the fourth diode D4 is connected with the PLUS end of the fifth diode D5, the MINUX end of the fifth diode D5 is connected with the PLUS end of the sixth diode D6 and the gate of the first high-voltage NMOS tube NM1, the MINUX end of the sixth diode D6 is connected with the base of the first high-voltage NPN tube Q1, The gate of the first high-voltage NMOS transistor NM1 is connected to the MINUX end of the fifth diode D5 and the PLUS end of the sixth diode D6, the source of the first high-voltage NMOS transistor NM1 is connected to the collector of the first high-voltage NPN transistor Q1, the base of the first high-voltage NPN transistor Q1 is connected to the MINUX end of the sixth diode D6, the emitter of the first high-voltage NPN transistor Q1 is connected to the PLUS end of the second resistor R2, the MINUX end of the second resistor R2 is connected to the ground terminal avss, the drain of the second high-voltage PMOS transistor PM2 is connected to the drain of the first high-voltage NMOS transistor NM1 and the gate of the second high-voltage PMOS transistor PM2, the source of the second high-voltage PMOS transistor PM2 is connected to the power supply terminal avdd, the gate of the third high-voltage PMOS transistor PM3 is connected to the gate of the second high-voltage PMOS transistor PM2 and used as a mirror current, the source of the third high-voltage PMOS transistor PM3 is connected to the power supply terminal avdd, the drain of the third high-voltage PMOS transistor PM3 is connected to the PLUS end of the third resistor R3, the gate of the second high-voltage NMOS transistor NM2, the PLUS end of the seventh diode D7 and the drain of the first high-voltage PMOS transistor PM1, to form a node C, the MINUX end of the third resistor R3 is connected to the ground terminal avss, the MINUX end of the seventh diode D7 is connected to the ground terminal avss, the drain of the second high-voltage NMOS transistor NM2 is connected to the power supply terminal avdd, the source of the second high-voltage NMOS transistor NM2 is connected to the PLUS end of the fourth resistor R4 and the gate of the third high-voltage NMOS transistor NM3 to form a node D, the MINUX end of the fourth resistor R4 is connected to the ground terminal avss, the drain of the third high-voltage NMOS transistor NM3 is connected to the power supply terminal avdd, and the source of the third high-voltage NMOS transistor NM3 is connected to the ground terminal avss.

2. The surge protection circuit having a high response speed and a voltage clamping function according to claim 1, characterized by, The first forward diode D1 and the second forward diode D2 are Schottky diodes.

3. The surge protection circuit having high response speed and voltage clamping function according to claim 1, characterized in that, The third diode D3 to the seventh diode D7 are Zener diodes.

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