Data processing method and apparatus, and system

Abstract

Embodiments of the present application disclose a data processing method and apparatus, and a system. The method specifically comprises: performing PCS processing on a first bit set in a plurality of bits to obtain a second bit set; performing first interleaving on the second bit set and a third bit set other than the first bit set in the plurality of bits so as to obtain two fourth bit sets; respectively performing forward error correction (FEC) encoding on the two fourth bit sets to obtain two fifth bit sets; respectively performing second interleaving on the two fifth bit sets to obtain two sixth bit sets; and performing third interleaving on the two sixth bit sets to obtain a seventh bit set. It should be noted that 4×Z+4 consecutive bits in the seventh bit set are used for mapping to obtain a dual-polarization symbol, the dual-polarization symbol comprises a first polarization symbol and a second polarization symbol, and Z is an integer greater than or equal to 3.

Description

A data processing method, apparatus and system

[0001] This application claims priority to Chinese Patent Application No. 202410706091.4, filed with the State Intellectual Property Office of China on May 31, 2024, entitled “A Data Processing Method, Apparatus and System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards high capacity, packetization, and intelligence. Coherent optical communication systems utilize the amplitude, phase, polarization, and frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and to maintain long-distance transmission, coherent optical communication systems typically employ efficient forward error correction (FEC) codes to combat optical impairments during optical transmission, ensuring a sufficiently low bit error rate over long distances. For example, the OpenFEC code (OFEC code) adopted by the current 400ZR+ and 800ZR has an overhead (OH) of 15.3%, and when using soft-decision decoding, its performance is approximately 2.0E-2 before correction.

[0004] To improve spectral efficiency, multi-level quadrature amplitude modulation (QAM), such as 16QAM, 32QAM, 64QAM, or even higher QAM, is commonly used. In traditional QAM modulation, each constellation point on the signal constellation diagram appears with the same probability. Probabilistic Constellation Shaping (PCS) technology changes the probability of constellation points while keeping their positions constant, making them non-uniformly distributed, thereby improving system transmission performance. As a modulation format optimization technique, PCS has advantages such as approaching the Shannon limit and flexibility, and has been widely researched and applied. Current data processing and transmission methods using OFEC coding mainly employ traditional QAM modulation, which is unsuitable for future scenarios using PCS technology, representing a pressing issue that needs to be addressed. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system that can employ modulation schemes with higher performance than DP-64QAM, such as DP-256QAM. By combining DP-256QAM and other modulation schemes with FEC coding, interleaving, and PCS technology, the overall data processing operation is kept simple, with low complexity and low power consumption. At the same time, it improves spectrum utilization and enhances system transmission performance, meeting the needs of future metropolitan area telecommunications transmission and metropolitan area DCI interconnection scenarios.

[0006] In a first aspect, embodiments of this application provide a data processing method. Specifically, a first set of bits from a plurality of bits undergoes PCS processing to obtain a second set of bits. The second set of bits and a third set of bits from the plurality of bits (excluding the first set of bits) undergo a first interleaving to obtain two fourth set of bits. The two fourth set of bits undergo forward error correction (FEC) coding to obtain two fifth set of bits. The two fifth set of bits undergo a second interleaving to obtain two sixth set of bits. The two sixth set of bits undergo a third interleaving to obtain a seventh set of bits. It should be noted that the consecutive 4×Z+4 bits in the seventh set of bits are used for mapping to obtain one dual-polarization symbol, which includes a first polarization symbol and a second polarization symbol, where Z is an integer greater than or equal to 3. The first polarization symbol can also be denoted as an X-polarization symbol, and the second polarization symbol can also be denoted as a Y-polarization symbol.

[0007] Of the 4×Z+4 bits used to map to the first polarization symbol, 2×Z bits come from the second bit set, and the other 2 bits come from the third bit set or FEC-encoded parity bits. Similarly, of the 4×Z+4 bits used to map to the second polarization symbol, 2×Z bits come from the second bit set, and the other 2 bits come from the third bit set or FEC-encoded parity bits. It should be understood that "2 bits from the third bit set or FEC-encoded parity bits" means that the 2 bits come from at least one of the third bit set and FEC-encoded parity bits. For example, both bits may come from the third bit set; or both bits may come from FEC-encoded parity bits; or one bit may come from the third bit set and the other bit may come from FEC-encoded parity bits.

[0008] In this implementation, for future metropolitan area telecommunications transmission and metropolitan area DCI interconnection scenarios, modulation schemes with higher probabilities than DP-64QAM, such as DP-256QAM, may be adopted. DP-256QAM and similar modulation schemes are combined with FEC coding and PCS processing technology to meet the requirements of longer transmission distances. The introduction of PCS processing requires that, during symbol mapping operations, the symbol bits mapped to a modulation symbol are equally probable (0 or 1), and the amplitude bits mapped to a modulation symbol are not equally probable (0 or 1). The probabilities are closer to the distribution corresponding to the theoretically optimal probability constellation shaping, further improving overall performance. Taking OFEC coding as an example, to minimize the impact on existing OFEC coding and OFEC interleavers, a new interleaver needs to be introduced after OFEC coding and before the symbol mapping operation. This allows the bits with unequal probabilities of 0 and 1 obtained after PCS processing to be mapped to the amplitude bits of the modulation symbols. This achieves a change in the probability of constellation point occurrence while keeping the constellation point position unchanged, making it non-uniformly distributed, thus improving overall performance to meet the requirements of longer transmission distances in the future.

[0009] In some possible implementations, the second bit set includes Z-type bits, where every two bits in the 2×Z bits used to map to the first polarization symbol come from the corresponding Class 1 bits in the Z-type bits, and every two bits in the 2×Z bits used to map to the second polarization symbol come from the corresponding Class 1 bits in the Z-type bits. Taking DP-256QAM with Z=3 as an example, the second bit set includes first-type bits, second-type bits, and third-type bits. Two out of the six bits used to map to the first polarization symbol come from the first-type bits, two out of the six bits used to map to the first polarization symbol come from the second-type bits, and two out of the six bits used to map to the first polarization symbol come from the third-type bits; two out of the six bits used to map to the second polarization symbol come from the first-type bits, two out of the six bits used to map to the second polarization symbol come from the second-type bits, and two out of the six bits used to map to the second polarization symbol come from the third-type bits.

[0010] In this implementation, the amplitude bits mapped to a modulation symbol correspond to eight amplitude values. Taking the eight amplitude values ​​1, 3, 5, 7, 9, 11, 13, and 15 as an example, the probabilities of 1, 3, 5, 7, 9, 11, 13, and 15 are not exactly the same. The probability of 1, 3, 5, 7, 9, 11, 13, and 15 occurring is jointly determined by the corresponding three amplitude bits, all of which come from the second bit set. If these three amplitude bits are not distinguished during processing, the probabilities of 0 and 1 appearing in the three amplitude bits will definitely be the same, resulting in the same probability of 1, 9, and 13 occurring, and the same probability of 3, 7, and 11 occurring. Therefore, the probability of the eight amplitude values ​​occurring deviates from the distribution corresponding to the theoretically optimal probability constellation shaping. If these three amplitude bits are processed separately, it is permissible for the probabilities of 0 and 1 appearing in the three amplitude bits to be different, resulting in different probabilities of 1, 9, and 13 occurring, and different probabilities of 3, 7, and 11 occurring. This makes the probability of the eight amplitude values ​​appear closer to the distribution corresponding to the theoretically optimal probability constellation shaping, further improving the overall performance.

[0011] In some possible implementations, the Z-type bits are arranged in target order, and the error bit rate of the Z-type bits is increasing. Taking DP-256QAM with Z=3 as an example, the second bit set includes the first, second, and third types of bits. The error bit rate of the first type of bits is less than that of the second type of bits, and the error bit rate of the second type of bits is less than that of the third type of bits. It should be understood that the distance between different constellation points of the first type of bits on the constellation diagram is greater than the distance between different constellation points of the second type of bits, and the distance between different constellation points of the second type of bits is greater than the distance between different constellation points of the third type of bits.

[0012] More specifically, when the first type of bit is 0, the amplitude value can only be 15, 13, 11, or 9. In this case, if the second type of bit is 0, the amplitude value can only be 15 or 13. Then, when the third type of bit is 0, the amplitude value is 15, and when the third type of bit is 1, the amplitude value is 13. If the second type of bit is 1, the amplitude value can only be 11 or 9. Then, when the third type of bit is 0, the amplitude value is 9, and when the third type of bit is 1, the amplitude value is 11.

[0013] Similarly, when the first type of bit is 1, the amplitude value can only be 7, 5, 3, or 1. In this case, if the second type of bit is 0, the amplitude value can only be 3 or 1. Then, when the third type of bit is 0, the amplitude value is 3, and when the third type of bit is 1, the amplitude value is 1. If the second type of bit is 1, the amplitude value can only be 7 or 5. Then, when the third type of bit is 0, the amplitude value is 7, and when the third type of bit is 1, the amplitude value is 5. Therefore, the first type of bit is more tolerant of noise than the second type of bit, and the second type of bit is more tolerant of noise than the third type of bit. Thus, the first type of bit has a lower error probability than the second type of bit, and the second type of bit has a lower error probability than the third type of bit.

[0014] In some possible implementations, the Z-class bits include the V1-class bits and the V2-class bits arranged in the target order, where 1 ≤ V1 < Z, 1 < V2 ≤ Z, and V1 < V2. The probability that a bit in the V1-class bits is 1 is P. V1-1 The probability that a bit in the V1 class is 0 is P. V1-0 The probability that a bit in the V2 class is 1 is P. V2-1 The probability that a bit in the V2 class is 0 is P. V2-0 P V1-1 -P V1-0 The absolute value is greater than or equal to P V2-1 -P V2-0 The absolute value of.

[0015] Taking DP-256QAM with Z=3 as an example, the second bit set includes first-class bits, second-class bits, and third-class bits. The probability of a bit in the first-class set being 1 is P. 0-1 The probability that a bit in the first type of bit is 0 is P. 0-0 The probability that a bit in the second type of bit is 1 is P. 1-1 The probability that a bit in the second type of bit is 0 is P. 1-0 The probability that a bit in the third type of bit is 1 is P. 2-1 The probability that a bit in the third type of bit is 0 is P. 2-0 P 0-1 -P 0-0 The absolute value is greater than or equal to P 1-1 -P 1-0 The absolute value of P 1-1 -P 1-0 The absolute value is greater than or equal to P 2-1 -P 2-0 The absolute value of . It should be understood that the difference between the sum of the probabilities of amplitude values ​​1, 3, 5, and 7 and the sum of the probabilities of amplitude values ​​9, 11, 13, and 15 is |P. 0-1 -P 0-0The difference between the sum of probabilities of amplitude values ​​11, 9, 7, and 5 and the sum of probabilities of amplitude values ​​15, 13, 3, and 1 is |P|. 1-1 -P 1-0 The difference between the sum of probabilities of amplitude values ​​13, 11, 5, and 3 and the sum of probabilities of amplitude values ​​15, 9, 7, and 1 is |P|. 2-1 -P 2-0 |。 Where, when |P 0-1 -P 0-0 |≥|P 1-1 -P 1-0 |≥|P 2-1 -P 2-0 At that time, according to the theoretically optimal distribution, the probability of amplitude values ​​1, 3, 5, 7, 9, 11, 13 and 15 appearing decreases in sequence, thus reaching the lowest average symbol energy.

[0016] In some possible implementations, Z = 3, that is, 16 consecutive bits in the seven-bit set are used for mapping to obtain one DP-256QAM symbol.

[0017] In some possible implementations, the second bit set includes a first type of bit, a second type of bit, and a third type of bit, and the first bit set includes L PCS A first bit subset, and performing PCS processing on the first bit set to obtain a second bit set, including: for each first bit subset, where k pcs_0 The first PCS subprocess is performed on each bit to obtain n. pcs_0 k first bits; for each subset of the first bits, k pcs_1 Each bit is processed by the second PCS subprocess to obtain n. pcs_1 k first bits; for each subset of the first bits, k pcs_2 Each bit is processed by the third PCS subprocess to obtain n. pcs_2 The first bit; for n pcs_0 The first bit, n pcs_1 The first bit and n pcs_2 Perform bit mapping on the first bit to obtain n pcs_0 The second bit, n pcs_1 The second bit and n pcs_2 The second bit. Where, n pcs_0 The second bit includes the first type of bit, n pcs_1 The second bit includes the second type of bit, n pcs_2 The second bit includes a third type of bit, k pcs_0 k pcs_1 and k pcs_2 All are integers greater than or equal to 1, n pcs_0 >k pcs_0 n pcs_1>k pcs_1 n pcs_2 >k pcs_2 n pcs_0 =n pcs_1 =n pcs_2 It should be understood that the probabilities of 0 and 1 appearing in the first, second, and third types of bits may be different. Therefore, it is advisable to process them separately using first, second, and third PCS sub-processes to facilitate the differentiation of the first, second, and third types of bits. By designing bit mappings, the number of erroneous bits can be reduced under the same symbol error rate. Furthermore, PCS processing can be implemented through multiple PCS sub-processes, which helps reduce the complexity of PCS processing, and the implementation of a single PCS sub-process is simpler.

[0018] In some possible implementations, for n pcs_0 The first bit, n pcs_1 The first bit and n pcs_2 Perform bit mapping on the first bit to obtain n pcs_0 The second bit, n pcs_1 The second bit and n pcs_2 The second bit includes: obtaining n pcs_0 Bits a and n in the first bit pcs_1 Bits b and n in the first bit pcs_2 Bit c from the first bit is used to perform bit mapping on bits a, bit b, and bit c to obtain bits a, bit a∧b, and bit b∧c. pcs_0 The second bit includes bits a, n pcs_1 The second bit includes bits a∧b, n pcs_2 The second bit includes bits b∧c, where ∧ represents the XOR operation. It should be understood that this bit mapping rule ensures that the constellation diagram satisfies the Gray mapping, where the Hamming distance between the bit values ​​corresponding to adjacent constellation points is 1, i.e., the minimum Hamming distance, which is beneficial for performance improvement. Furthermore, the XOR operation is a relatively simple way to satisfy this relationship.

[0019] In some possible implementations, n pcs_0 The probability P that the first bit is 1 cs0-1 The probability P of a bit being 0 cs0-0 P cs0-0 +P cs0-1 =1; n pcs_1 The probability P that the first bit is 1 cs1-1 The probability P of a bit being 0 cs1-0 P cs1-0 +P cs1-1 =1; n pcs_2The probability P that the first bit is 1 cs2-1 The probability P of a bit being 0 cs2-0 P cs2-0 +P cs2-1 =1. It should be understood that a bit value of 1 corresponds to a smaller average amplitude value, for example, amplitude values ​​1, 3, 5, and 7 in the first type of bits; for example, amplitude values ​​1 and 3, or amplitude values ​​9 and 11 in the second type of bits; and for example, amplitude values ​​1, 5, 9, or 13 in the third type of bits. A bit value of 0 corresponds to a larger average amplitude value, for example, amplitude values ​​9, 11, 13, and 15 in the first type of bits; for example, amplitude values ​​5 and 7, or amplitude values ​​13 and 15 in the second type of bits; and for example, amplitude values ​​3, 7, 11, or 15 in the third type of bits. It should be understood that low amplitude values ​​occur more frequently in high-performance PCS processing; therefore, the probability of a bit value of 1 is higher than the probability of a bit value of 0, which is beneficial for achieving the lowest average symbol energy, thereby improving performance.

[0020] In some possible implementations, k pcs_0 <k pcs_1 <k pcs_2 P cs0-1 >P cs1-1 >P cs2-1 P cs0-0 <P cs1-0 <P cs2-0 Or, k pcs_0 =k pcs_1 =k pcs_2 P cs0-1 =P cs1-1 =P cs2-1 P cs0-0 =P cs1-0 =P cs2-0 This helps achieve the lowest average symbol energy, thereby improving performance.

[0021] In some possible implementations, 2×Z+2 bits in the even-numbered positions of the 4×Z+4 bits are used to map to the first polarization symbol, and 2×Z+2 bits in the odd-numbered positions of the 4×Z+4 bits are used to map to the second polarization symbol.

[0022] In some possible implementations, taking DP-256QAM with Z=3 as an example, the 0th, 2nd, 4th, and 6th bits of the 16 bits are used to map to the first component of the first polarization symbol; the 8th, 10th, 12th, and 14th bits of the 16 bits are used to map to the second component of the first polarization symbol; the 1st, 3rd, 5th, and 7th bits of the 16 bits are used to map to the first component of the second polarization symbol; and the 9th, 11th, 13th, and 15th bits of the 16 bits are used to map to the second component of the second polarization symbol.

[0023] In some possible implementations, taking DP-256QAM with Z=3 as an example, the second bit set includes first-class bits, second-class bits, and third-class bits. The 2nd, 3rd, 10th, and 11th bits come from the first-class bits, the 4th, 5th, 12th, and 13th bits come from the second-class bits, and the 6th, 7th, 14th, and 15th bits come from the third-class bits.

[0024] In some possible implementations, the first half of the 4×Z+4 bits (2×Z+2 bits) is used to map to the first polarization symbol, and the second half of the 4×Z+4 bits (2×Z+2 bits) is used to map to the second polarization symbol.

[0025] In some possible implementations, taking DP-256QAM with Z=3 as an example, the 0th, 1st, 2nd, and 3rd bits of the 16 bits are used to map to the first component of the first polarization symbol; the 4th, 5th, 6th, and 7th bits of the 16 bits are used to map to the second component of the first polarization symbol; the 8th, 9th, 10th, and 11th bits of the 16 bits are used to map to the first component of the second polarization symbol; and the 12th, 13th, 14th, and 15th bits of the 16 bits are used to map to the second component of the second polarization symbol.

[0026] In some possible implementations, taking DP-256QAM with Z=3 as an example, the second bit set includes first-class bits, second-class bits, and third-class bits. The 1st, 5th, 9th, and 13th bits come from the first-class bits, the 2nd, 6th, 10th, and 14th bits come from the second-class bits, and the 3rd, 7th, 11th, and 15th bits come from the third-class bits.

[0027] In some possible implementations, the polarization direction of the first polarization symbol is orthogonal to the deflection direction of the second polarization symbol. The first component is an I-path component, and the second component is a Q-path component; or, the first component is a Q-path component, and the second component is an I-path component.

[0028] In some possible implementations, the 8 even-numbered bits of the 16 bits are mapped to the first polarization symbol, and the 8 odd-numbered bits of the 16 bits are mapped to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits. The sixth bit set includes 16 subsets of the second bit set in 2 rows and 8 columns. Each subset of the second bit set includes 256 bits in 16 rows and 16 columns. The bit distribution pattern of each subset of the second bit set is shown below:

[0029] In the bit distribution pattern of the second bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0030] In some possible implementations, the first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes first-class bits, second-class bits, and third-class bits. The sixth bit set includes 16 subsets of the second bit set (2 rows, 8 columns). Each subset of the second bit set includes 256 bits (16 rows, 16 columns). The bit distribution pattern of each subset of the second bit set is shown below:

[0031] In the bit distribution pattern of the second bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0032] In some possible implementations, performing a second interleaving on the two fifth bit sets to obtain two sixth bit sets includes: performing a fourth interleaving on the two fifth bit sets to obtain two eighth bit sets, wherein each eighth bit set 2 includes 2 rows and 8 columns of 16 third bit subsets, and each third bit subset includes 16 rows and 16 columns of 256 bits. Performing a fifth interleaving on the two eighth bit sets to obtain two sixth bit sets, wherein the fifth interleaving is used to interleave the 16 bits in each row of each third bit subset in the eighth bit set. That is, the second interleaving operation can be implemented in two steps, namely the fourth interleaving and the fifth interleaving. The fifth interleaving can be understood as a way to perform intra-row interleaving of the bits in each row of the second bit subset. This design improves the flexibility of the implementation of this scheme.

[0033] In some possible implementations, the 8 even-numbered bits of the 16 bits are used to map to the first polarization symbol, and the 8 odd-numbered bits of the 16 bits are used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits, and the bit distribution pattern of each third bit subset is shown below:

[0034] In the bit distribution pattern of the third bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0035] In some possible implementations, the first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits, and the bit distribution pattern of each third bit subset is shown below:

[0036] In the bit distribution pattern of the third bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0037] In some possible implementations, each fifth bit set comprises 16 fourth bit subsets arranged in 2 rows and 8 columns, with each fourth bit subset comprising 256 bits arranged in 16 rows and 16 columns. Within these 16 fourth bit subsets, bits in columns 0 through 3 originate from the second and third bit sets; bits in columns 4, 5, and 6 (including columns 0 through 14) originate from the second bit set; and bits in columns 15 and 7 of the fourth bit subset in column 6 are FEC-encoded check bits.

[0038] In some possible implementations, the 8 even-numbered bits of the 16 bits are used to map to the first polarization symbol, and the 8 odd-numbered bits of the 16 bits are used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits. The bit distribution pattern of the fourth bit subset from column 0 to column 2 in each fifth bit set is shown below:

[0039] In the bit distribution pattern of the fourth bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0040] In some possible implementations, the first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits. The bit distribution pattern of the fourth bit subset from column 0 to column 2 in each fifth bit set is shown below:

[0041] In the bit distribution pattern of the fourth bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0042] In some possible implementations, the third interleaving of the two sixth-bit sets to obtain the seventh-bit set includes: performing intra-matrix interleaving on the two sixth-bit sets to obtain two ninth-bit sets, each ninth-bit set comprising 16 subsets of fifth bits (2 rows, 8 columns), with each subset comprising 256 bits (16 rows, 16 columns). Inter-matrix interleaving is then performed on the two ninth-bit sets to obtain the seventh-bit set, which comprises 672 subsets of fifth bits (84 rows, 8 columns). A specific implementation of the third interleaving is provided here, which includes both intra-matrix and inter-matrix interleaving, improving the practicality of this scheme.

[0043] In some possible implementations, the first bit set includes a first bit set 1 and a first bit set 2. Performing PCS processing on the first bit set among multiple bits to obtain the second bit set includes: performing PCS processing on the first bit set 1 to obtain the second bit set 1, and performing PCS processing on the first bit set 2 to obtain the second bit set 2, wherein the second bit set includes the second bit set 1 and the second bit set 2. It should be understood that implementing this in two PCS processes helps reduce the complexity of a single PCS process, and the hardware implementation of a single PCS process is simpler.

[0044] In some possible implementations, the third bit set includes third bit set 1 and third bit set 2. Performing a first interleaving of the second bit set and the third bit set (excluding the first bit set) to obtain two fourth bit sets includes: performing a first interleaving of second bit set 1, second bit set 2, third bit set 1, and third bit set 2 to obtain two fourth bit sets.

[0045] In some possible implementations, the third bit set includes third bit set 1 and third bit set 2. Performing a first interleaving of the second bit set and the third bit set (excluding the first bit set) to obtain two fourth bit sets includes: performing a first interleaving of second bit set 1 and third bit set 1 to obtain one of the fourth bit sets, and performing a first interleaving of second bit set 2 and third bit set 2 to obtain the other fourth bit set. It should be understood that implementing this in two separate first interleavings helps reduce the complexity of a single first interleaving, and the hardware implementation of a single first interleaving is simpler.

[0046] In some possible implementations, performing a first interleaving of the second bit set and a third bit set other than the first bit set to obtain two fourth bit sets includes performing a first interleaving of the second bit set 1, the second bit set 2 and the third bit set to obtain two fourth bit sets.

[0047] In some possible implementations, the amplitude bits mapped to the dual-polarization symbol come from a second set of bits, and the symbol bits mapped to the dual-polarization symbol come from a third set of bits or FEC-encoded parity bits.

[0048] In some possible implementations, the data processing method is applied in scenarios including Ethernet, optical transport networks, and space optical communications.

[0049] Secondly, embodiments of this application provide a data processing apparatus. This data processing apparatus includes: a PCS unit, a first interleaving unit, an FEC encoding unit, a second interleaving unit, and a third interleaving unit. The PCS unit is used to: perform PCS processing on a first set of bits from a plurality of bits to obtain a second set of bits. The first interleaving unit is used to: perform a first interleaving on the second set of bits and a third set of bits from the plurality of bits excluding the first set of bits to obtain two fourth set of bits. The FEC encoding unit is used to: perform FEC encoding on the two fourth set of bits respectively to obtain two fifth set of bits. The second interleaving unit is used to: perform a second interleaving on the two fifth set of bits respectively to obtain two sixth set of bits. The third interleaving unit is used to: perform a third interleaving on the two sixth set of bits to obtain a seventh set of bits, wherein 4×Z+4 consecutive bits in the seventh set of bits are used for mapping to obtain one double-polarization symbol, the double-polarization symbol including a first polarization symbol and a second polarization symbol, where Z is an integer greater than or equal to 3. Of the 4×Z+4 bits used to map to the first polarization symbol, 2×Z bits come from the second bit set, and the other 2 bits used to map to the first polarization symbol come from the third bit set or FEC-encoded check bits. Of the 4×Z+4 bits used to map to the second polarization symbol, 2×Z bits come from the second bit set, and the other 2 bits used to map to the second polarization symbol come from the third bit set or FEC-encoded check bits.

[0050] In some possible implementations, the second bit set includes Z-type bits, where every two bits in the 2×Z bits used to map to the first polarization symbol come from the corresponding Class 1 bits in the Z-type bits, and every two bits in the 2×Z bits used to map to the second polarization symbol come from the corresponding Class 1 bits in the Z-type bits. Taking DP-256QAM with Z=3 as an example, the second bit set includes first-type bits, second-type bits, and third-type bits. Two out of the six bits used to map to the first polarization symbol come from the first-type bits, two out of the six bits used to map to the first polarization symbol come from the second-type bits, and two out of the six bits used to map to the first polarization symbol come from the third-type bits; two out of the six bits used to map to the second polarization symbol come from the first-type bits, two out of the six bits used to map to the second polarization symbol come from the second-type bits, and two out of the six bits used to map to the second polarization symbol come from the third-type bits.

[0051] In some possible implementations, the Z-type bits are arranged in the target order, and the error bit rate of the Z-type bits is increasing. Taking DP-256QAM with Z=3 as an example, the second bit set includes the first, second, and third types of bits. The error bit rate of the first type of bits is less than that of the second type of bits, and the error bit rate of the second type of bits is less than that of the third type of bits.

[0052] In some possible implementations, the Z-class bits include the V1-class bits and the V2-class bits arranged in the target order, where 1 ≤ V1 < Z, 1 < V2 ≤ Z, and V1 < V2. The probability that a bit in the V1-class bits is 1 is P. V1-1 The probability that a bit in the V1 class is 0 is P. V1-0 The probability that a bit in the V2 class is 1 is P. V2-1 The probability that a bit in the V2 class is 0 is P. V2-0 P V1-1 -P V1-0 The absolute value is greater than or equal to P V2-1 -P V2-0 The absolute value of . Taking DP-256QAM with Z=3 as an example, the second bit set includes the first type of bits, the second type of bits, and the third type of bits. The probability that a bit in the first type of bits is 1 is P. 0-1 The probability that a bit in the first type of bit is 0 is P. 0-0 The probability that a bit in the second type of bit is 1 is P. 1-1 The probability that a bit in the second type of bit is 0 is P. 1-0 The probability that a bit in the third type of bit is 1 is P. 2-1 The probability that a bit in the third type of bit is 0 is P.2-0 P 0-1 -P 0-0 The absolute value is greater than or equal to P 1-1 -P 1-0 The absolute value of P 1-1 -P 1-0 The absolute value is greater than or equal to P 2-1 -P 2-0 The absolute value of.

[0053] In some possible implementations, Z = 3, that is, 16 consecutive bits in the seven-bit set are used for mapping to obtain one DP-256QAM symbol.

[0054] In some possible implementations, the second bit set includes a first type of bit, a second type of bit, and a third type of bit, and the first bit set includes L PCS The first bit subset. The PCS unit is specifically used for: for each first bit subset, k of which pcs_0 The first PCS subprocess is performed on each bit to obtain n. pcs_0 k first bits; for each subset of the first bits, k pcs_1 Each bit is processed by the second PCS subprocess to obtain n. pcs_1 k first bits; for each subset of the first bits, k pcs_2 Each bit is processed by the third PCS subprocess to obtain n. pcs_2 The first bit; for n pcs_0 The first bit, n pcs_1 The first bit and n pcs_2 Perform bit mapping on the first bit to obtain n pcs_0 The second bit, n pcs_1 The second bit and n pcs_2 The second bit. Where, n pcs_0 The second bit includes the first type of bit, n pcs_1 The second bit includes the second type of bit, n pcs_2 The second bit includes a third type of bit, k pcs_0 k pcs_1 and k pcs_2 All are integers greater than or equal to 1, n pcs_0 >k pcs_0 n pcs_1 >k pcs_1 n pcs_2 >k pcs_2 n pcs_0 =n pcs_1 =n pcs_2 .

[0055] In some possible implementations, the PCS unit is specifically used to: obtain n pcs_0Bits a and n in the first bit pcs_1 Bits b and n in the first bit pcs_2 Bit c from the first bit is used to perform bit mapping on bits a, bit b, and bit c to obtain bits a, bit a∧b, and bit b∧c. pcs_0 The second bit includes bits a, n pcs_1 The second bit includes bits a∧b, n pcs_2 The second bit includes the bit b∧c, where ∧ represents the XOR operation.

[0056] In some possible implementations, n pcs_0 The probability P that the first bit is 1 cs0-1 The probability P of a bit being 0 cs0-0 P cs0-0 +P cs0-1 =1; n pcs_1 The probability P that the first bit is 1 cs1-1 The probability P of a bit being 0 cs1-0 P cs1-0 +P cs1-1 =1; n pcs_2 The probability P that the first bit is 1 cs2-1 The probability P of a bit being 0 cs2-0 P cs2-0 +P cs2-1 =1.

[0057] In some possible implementations, k pcs_0 <k pcs_1 <k pcs_2 P cs0-1 >P cs1-1 >P cs2-1 P cs0-0 <P cs1-0 <P cs2-0 Or, k pcs_0 =k pcs_1 =k pcs_2 P cs0-1 =P cs1-1 =P cs2-1 P cs0-0 =P cs1-0 =P cs2-0 .

[0058] In some possible implementations, 2×Z+2 bits in the even-numbered positions of the 4×Z+4 bits are used to map to the first polarization symbol, and 2×Z+2 bits in the odd-numbered positions of the 4×Z+4 bits are used to map to the second polarization symbol.

[0059] In some possible implementations, taking DP-256QAM with Z=3 as an example, the 0th, 2nd, 4th, and 6th bits of the 16 bits are used to map to the first component of the first polarization symbol; the 8th, 10th, 12th, and 14th bits of the 16 bits are used to map to the second component of the first polarization symbol; the 1st, 3rd, 5th, and 7th bits of the 16 bits are used to map to the first component of the second polarization symbol; and the 9th, 11th, 13th, and 15th bits of the 16 bits are used to map to the second component of the second polarization symbol.

[0060] In some possible implementations, taking DP-256QAM with Z=3 as an example, the second bit set includes first-class bits, second-class bits, and third-class bits. The 2nd, 3rd, 10th, and 11th bits come from the first-class bits, the 4th, 5th, 12th, and 13th bits come from the second-class bits, and the 6th, 7th, 14th, and 15th bits come from the third-class bits.

[0061] In some possible implementations, the first half of the 4×Z+4 bits (2×Z+2 bits) is used to map to the first polarization symbol, and the second half of the 4×Z+4 bits (2×Z+2 bits) is used to map to the second polarization symbol.

[0062] In some possible implementations, taking DP-256QAM with Z=3 as an example, the 0th, 1st, 2nd, and 3rd bits of the 16 bits are used to map to the first component of the first polarization symbol; the 4th, 5th, 6th, and 7th bits of the 16 bits are used to map to the second component of the first polarization symbol; the 8th, 9th, 10th, and 11th bits of the 16 bits are used to map to the first component of the second polarization symbol; and the 12th, 13th, 14th, and 15th bits of the 16 bits are used to map to the second component of the second polarization symbol.

[0063] In some possible implementations, taking DP-256QAM with Z=3 as an example, the second bit set includes first-class bits, second-class bits, and third-class bits. The 1st, 5th, 9th, and 13th bits come from the first-class bits, the 2nd, 6th, 10th, and 14th bits come from the second-class bits, and the 3rd, 7th, 11th, and 15th bits come from the third-class bits.

[0064] In some possible implementations, the polarization direction of the first polarization symbol is orthogonal to the deflection direction of the second polarization symbol. The first component is an I-path component, and the second component is a Q-path component; or, the first component is a Q-path component, and the second component is an I-path component.

[0065] In some possible implementations, the 8 even-numbered bits of the 16 bits are mapped to the first polarization symbol, and the 8 odd-numbered bits of the 16 bits are mapped to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits. The sixth bit set includes 16 subsets of the second bit set in 2 rows and 8 columns. Each subset of the second bit set includes 256 bits in 16 rows and 16 columns. The bit distribution pattern of each subset of the second bit set is shown below:

[0066] In the bit distribution pattern of the second bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0067] In some possible implementations, the first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes first-class bits, second-class bits, and third-class bits. The sixth bit set includes 16 subsets of the second bit set (2 rows, 8 columns). Each subset of the second bit set includes 256 bits (16 rows, 16 columns). The bit distribution pattern of each subset of the second bit set is shown below:

[0068] In the bit distribution pattern of the second bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0069] In some possible implementations, the second interleaving unit is specifically used for: performing a second interleaving on the two fifth bit sets to obtain two sixth bit sets, including: performing a fourth interleaving on the two fifth bit sets to obtain two eighth bit sets, wherein each eighth bit set 2 includes 2 rows and 8 columns of 16 third bit subsets, and the third bit subsets include 16 rows and 16 columns of 256 bits. Performing a fifth interleaving on the two eighth bit sets to obtain two sixth bit sets, wherein the fifth interleaving is used to interleave the 16 bits in each row of each third bit subset in the eighth bit set.

[0070] In some possible implementations, the 8 even-numbered bits of the 16 bits are used to map to the first polarization symbol, and the 8 odd-numbered bits of the 16 bits are used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits, and the bit distribution pattern of each third bit subset is shown below:

[0071] In the bit distribution pattern of the third bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0072] In some possible implementations, the first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits, and the bit distribution pattern of each third bit subset is shown below:

[0073] In the bit distribution pattern of the third bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0074] In some possible implementations, each fifth bit set comprises 16 fourth bit subsets arranged in 2 rows and 8 columns, with each fourth bit subset comprising 256 bits arranged in 16 rows and 16 columns. Within these 16 fourth bit subsets, bits in columns 0 through 3 originate from the second and third bit sets; bits in columns 4, 5, and 6 (including columns 0 through 14) originate from the second bit set; and bits in columns 15 and 7 of the fourth bit subset in column 6 are FEC-encoded check bits.

[0075] In some possible implementations, the 8 even-numbered bits of the 16 bits are used to map to the first polarization symbol, and the 8 odd-numbered bits of the 16 bits are used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits. The bit distribution pattern of the fourth bit subset from column 0 to column 2 in each fifth bit set is shown below:

[0076] In the bit distribution pattern of the fourth bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0077] In some possible implementations, the first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes the first type of bits, the second type of bits, and the third type of bits. The bit distribution pattern of the fourth bit subset from column 0 to column 2 in each fifth bit set is shown below:

[0078] In the bit distribution pattern of the fourth bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

[0079] In some possible implementations, the third interleaving unit is specifically used to: perform intra-matrix interleaving on the two sets of sixth bits to obtain two sets of ninth bits, each set of ninth bits comprising 16 subsets of fifth bits in 2 rows and 8 columns, each subset comprising 256 bits in 16 rows and 16 columns. Inter-matrix interleaving is then performed on the two sets of ninth bits to obtain a set of seventh bits, which comprises 672 subsets of fifth bits in 84 rows and 8 columns.

[0080] In some possible implementations, the first bit set includes a first bit set 1 and a first bit set 2. The PCS unit is specifically used to: perform PCS processing on the first bit set 1 to obtain a second bit set 1, and perform PCS processing on the first bit set 2 to obtain a second bit set 2, wherein the second bit set includes a second bit set 1 and a second bit set 2.

[0081] In some possible implementations, the third bit set includes third bit set 1 and third bit set 2. The first interleaving unit is specifically used to: perform a first interleaving on second bit set 1, second bit set 2, third bit set 1, and third bit set 2 to obtain two fourth bit sets.

[0082] In some possible implementations, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving unit is specifically used to: perform a first interleaving on the second bit set 1 and the third bit set 1 to obtain one of the fourth bit sets, and perform a first interleaving on the second bit set 2 and the third bit set 2 to obtain another fourth bit set.

[0083] In some possible implementations, the first interleaving unit is specifically used to: perform a first interleaving on the second bit set 1, the second bit set 2, and the third bit set to obtain two fourth bit sets.

[0084] In some possible implementations, the amplitude bits mapped to the dual-polarization symbol come from a second set of bits, and the symbol bits mapped to the dual-polarization symbol come from a third set of bits or FEC-encoded parity bits.

[0085] In some possible implementations, the data processing method is applied in scenarios including Ethernet, optical transport networks, and space optical communications.

[0086] Thirdly, embodiments of this application provide a chip for performing the method as described in any of the embodiments of the first aspect.

[0087] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0088] In some possible implementations, the interface is specifically an electrical interface through which the processor transmits electrical signals. For example, the processor executes the method described in any embodiment of the first aspect and performs data processing on the eighth bit set to obtain a dual-polarization symbol sequence, and transmits the dual-polarization symbol sequence through the interface. The data processing here includes symbol mapping, polarization partitioning, and framing. In this embodiment, "framing" can also be referred to as "DSP framing," and "dual-polarization symbol sequence" can also be referred to as "superframe" or "DSP superframe."

[0089] In some possible implementations, the interface is specifically an optical interface, and the optical module further includes a modulator. For example, the processor executes the method described in any embodiment of the first aspect and performs data processing on the eighth bit set to obtain a dual-polarization symbol sequence. The modulator then performs signal processing such as electro-optic conversion based on the dual-polarization symbol sequence to obtain an optical signal, which is then transmitted through the interface. The data processing here includes symbol mapping, polarization division, and framing.

[0090] Fifthly, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in any embodiment of the fourth aspect. The optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

[0091] Sixthly, embodiments of this application provide an apparatus. The apparatus includes a processor and an interface. The processor is used to perform the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The apparatus may be a router, switch, server, or optical transport network equipment, etc.

[0092] In a seventh aspect, embodiments of this application provide a communication system, which includes the transmitting device and receiving device described in the fifth aspect, wherein the transmitting device is used to transmit optical signals to the receiving device.

[0093] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any embodiment of the first aspect to be implemented.

[0094] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first aspect. Attached Figure Description

[0095] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0096] Figure 2 is a schematic diagram of a data frame structure;

[0097] Figure 3 is a schematic diagram of an embodiment of the first data processing in this application;

[0098] Figure 4(a) is a schematic diagram of an embodiment of the second data processing in this application;

[0099] Figure 4(b) is a schematic diagram of an embodiment of the second data subprocessing in this application;

[0100] Figure 5(a) is a schematic diagram of an embodiment of the third data processing in this application;

[0101] Figure 5(b) is a schematic diagram of another embodiment of the third data processing in this application;

[0102] Figure 5(c) is a schematic diagram of yet another embodiment of the third data processing in this application;

[0103] Figure 6(a) is a schematic diagram of an embodiment of PCS processing and first interleaving in this application;

[0104] Figure 6(b) is a schematic diagram of another embodiment of PCS processing and first interleaving in this application;

[0105] Figure 6(c) is a schematic diagram of another embodiment of PCS processing and first interleaving in this application;

[0106] Figure 6(d) is a schematic diagram of another embodiment of PCS processing and first interleaving in the present application;

[0107] Figure 6(e) is a schematic diagram of an embodiment of the PCS processing in this application, which includes multiple PCS sub-processes;

[0108] Figure 6(f) is a schematic diagram of another embodiment of the PCS processing in this application, which includes multiple PCS sub-processes;

[0109] Figure 7 is a schematic diagram of a 7-column bit block in each row in an embodiment of this application;

[0110] Figure 8 is a schematic diagram of a fourth bit set in an embodiment of this application;

[0111] Figure 9 is a schematic diagram of a 16×16 bit block in an embodiment of this application;

[0112] Figure 10 is a schematic diagram of a 16×15 bit block in an embodiment of this application;

[0113] Figure 11 is a schematic diagram of a first bit pattern in an embodiment of this application;

[0114] Figure 12(a) is a schematic diagram of a second bit pattern in an embodiment of this application;

[0115] Figure 12(b) is a schematic diagram of another second bit pattern in an embodiment of this application;

[0116] Figure 13 is a schematic diagram of a third bit pattern and a fourth bit pattern in an embodiment of this application;

[0117] Figure 14 is a schematic diagram of a fifth bit pattern in an embodiment of this application;

[0118] Figure 15 is a schematic diagram of one embodiment of data processing of two first bit streams in this application;

[0119] Figure 16 is a schematic diagram of a bit block with 8 columns per row in an embodiment of this application;

[0120] Figure 17 shows a schematic diagram of a fifth bit set in an embodiment of this application;

[0121] Figure 18(a) is a schematic diagram of a sixth bit pattern in an embodiment of this application;

[0122] Figure 18(b) is a schematic diagram of a seventh bit pattern in an embodiment of this application;

[0123] Figure 19 is a schematic diagram of an eighth bit set in an embodiment of this application;

[0124] Figure 20 is a schematic diagram of a sixth bit set in an embodiment of this application;

[0125] Figure 21 is a schematic diagram of one embodiment of the fifth interlacing in this application;

[0126] Figure 22 is a schematic diagram of an eighth bit pattern in an embodiment of this application;

[0127] Figure 23 is a schematic diagram of one embodiment of interlacing within a square matrix in this application;

[0128] Figure 24 is a schematic diagram of a ninth bit pattern in an embodiment of this application;

[0129] Figure 25 is a schematic diagram of an embodiment of inter-array interleaving in this application;

[0130] Figure 26 is a schematic diagram of the bit set after interleaving between square matrices in an embodiment of this application;

[0131] Figure 27 is a schematic diagram of another first bit pattern in an embodiment of this application;

[0132] Figure 28(a) is a schematic diagram of another second bit pattern in an embodiment of this application;

[0133] Figure 28(b) is a schematic diagram of another second bit pattern in an embodiment of this application;

[0134] Figure 29 is a schematic diagram of another third bit pattern in an embodiment of this application;

[0135] Figure 30 is a schematic diagram of another fourth bit pattern in an embodiment of this application;

[0136] Figure 31 is a schematic diagram of another fifth bit pattern in an embodiment of this application;

[0137] Figure 32 is a schematic diagram of another sixth bit pattern in an embodiment of this application;

[0138] Figure 33 is a schematic diagram of another eighth-bit pattern in an embodiment of this application;

[0139] Figure 34 is a schematic diagram of another ninth bit pattern in an embodiment of this application;

[0140] Figure 35 is a schematic diagram of another first bit pattern in an embodiment of this application;

[0141] Figure 36 is a schematic diagram of another second bit pattern in an embodiment of this application;

[0142] Figure 37 is a schematic diagram of another eighth-bit pattern in an embodiment of this application;

[0143] Figure 38 is a schematic diagram of another ninth bit pattern in an embodiment of this application;

[0144] Figure 39 is a schematic diagram of another first bit pattern in an embodiment of this application;

[0145] Figure 40(a) is a schematic diagram of another second bit pattern in an embodiment of this application;

[0146] Figure 40(b) is a schematic diagram of another second bit pattern in an embodiment of this application;

[0147] Figure 41 is a schematic diagram of another third bit pattern in an embodiment of this application;

[0148] Figure 42 is a schematic diagram of another fourth bit pattern in an embodiment of this application;

[0149] Figure 43 is a schematic diagram of another fifth bit pattern in an embodiment of this application;

[0150] Figure 44 is a schematic diagram of another sixth bit pattern in an embodiment of this application;

[0151] Figure 45 is a schematic diagram of another eighth bit pattern in an embodiment of this application;

[0152] Figure 46 is a schematic diagram of another ninth bit pattern in an embodiment of this application;

[0153] Figure 47 is a schematic diagram of an application scenario of the second data processing in the embodiments of this application;

[0154] Figure 48(a) is a schematic diagram of a bit distribution of the last 71 bits in the fifth bit set in an embodiment of this application;

[0155] Figure 48(b) is a schematic diagram of a bit distribution in the last 71 bits of the eighth bit set in an embodiment of this application;

[0156] Figure 49 shows the third bit of data d. scr Mapping distribution to N PCS+FEC A schematic diagram showing the details of the "PCS+FEC" module;

[0157] Figure 50 is a schematic diagram of another embodiment of inter-array interleaving in this application;

[0158] Figure 51 is a schematic diagram of an application scenario of the second data processing in the embodiments of this application;

[0159] Figure 52 is a schematic diagram of a constellation diagram according to an embodiment of this application;

[0160] Figure 53 is a schematic diagram of a data processing device in an embodiment of this application;

[0161] Figure 54 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0162] Figure 55 is a schematic diagram of a transmitting device in an embodiment of this application. Detailed Implementation

[0163] This application provides a data processing method, apparatus, and system that can employ modulation schemes with higher performance than DP-64QAM, such as DP-256QAM. By combining DP-256QAM and other modulation schemes with FEC coding, interleaving, and PCS technology, the overall data processing operation is kept simple, with low complexity and low power consumption. At the same time, it improves spectrum utilization and enhances system transmission performance, meeting the needs of future metropolitan area telecommunications transmission and metropolitan area DCI interconnection scenarios.

[0164] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0165] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, at the transmitting end, the source provides a data stream to be transmitted, and the transmitting end data processor receives the data stream. The transmitting end data processor first performs data processing including PCS processing, encoding, interleaving, modulation, and digital signal processing (DSP) framing to obtain a symbol data stream, which is then sent to the transmitting end signal processor for signal processing, and then transmitted through the channel to the receiving device. After receiving the distorted signal caused by noise or other impairments in the channel, the receiving device sends it to the receiving end signal processor for dispersion compensation, synchronization, phase recovery, and other operations, and then sends it to the receiving end data processor for demodulation, deinterleaving, decoding, and other operations to recover the original data, and then sends the recovered data to the destination.

[0166] It should be noted that the terms "bit set" and "bit subset" in this application specification and claims are concepts introduced for ease of description only. In practical applications, the data stream is a whole and does not involve division; each bit set or bit subset can be considered as one or more bits in the data stream. It should be understood that bit sets and bit subsets can also be presented in the form of matrices, arrays, sequences, etc., and no specific limitation is made here.

[0167] It should be noted that the data processing method provided in this application can be divided into three parts, referred to as "first data processing," "second data processing," and "third data processing," respectively. The "first data processing," "second data processing," and "third data processing" are described in detail below. Figure 2 is a schematic diagram of a data frame structure. As shown in Figure 2, the data frame includes multiple rows of bits, and each row includes q bits. It should be understood that this application does not limit the specific type of data frame. In some specific applications, the integer q is an integer multiple of 257; typically, q is 10280, 8224, 4112, or 2056, etc. In other specific applications, the integer q is an integer multiple of 128, for example, q is 128. Figure 3 is a schematic diagram of an embodiment of the first data processing in this application. As shown in Figure 3, the first data processing includes Cyclic Redundancy Check (CRC), padding, and scrambling. In practical applications, at least one of the CRC and padding operations can be performed. For example, the first data processing performs CRC check on the first bit of data and inserts padding bits to obtain the second bit of data, and then scrambles it to obtain the third bit of data. As another example, the first data processing performs CRC check on the first bit of data and then scrambles it to obtain the third bit of data. Yet another example, the first data processing inserts padding bits into the first bit of data to obtain the second bit of data, and then scrambles it to obtain the third bit of data.

[0168] Figure 4(a) is a schematic diagram of an embodiment of the second data processing in this application. As shown in Figure 4(a), multiple bits of data are obtained from the third bit data output after the first data processing, and are then sent to L second data subprocesses (i.e., second data subprocess 0, second data subprocess 1, ..., second data subprocess L-1) in a round-robin fashion. For example, each second data subprocess inputs e bits. After L second data subprocesses, L data streams can be obtained. Then, the L data streams are merged to obtain the output of the second data processing, i.e., the fourth bit of data in Figure 4(a), where L is an integer greater than 0.

[0169] Figure 4(b) is a schematic diagram of an embodiment of the second data subprocessing in this application. As shown in Figure 4(b), the operations of the second data subprocessing i (i = 0, 1, ..., L-1) include PCS processing and first interleaving (i.e., "PCS processing and first interleaving i" in Figure 4(b)), FEC encoding (i.e., "FEC encoding 2i" and "FEC encoding 2i+1" in Figure 4(b)), second interleaving (i.e., "second interleaving 2i" and "second interleaving 2i+1" in Figure 4(b)) and third interleaving (i.e., "third interleaving i" in Figure 4(b)). The third interleaving includes intra-matrix interleaving (i.e., "intra-matrix interleaving 2i" and "intra-matrix interleaving 2i+1" in Figure 4(b)) and inter-matrix interleaving (i.e., "inter-matrix interleaving i" in Figure 4(b)). The third interleaving is also called block interleaving. It should be understood that the various interleaving operations mentioned in the embodiments of this application may have other names in different scenarios. For example, interleaving may also be called permutation or reordering.

[0170] Specifically, the second data subprocess acquires multiple bits and performs PCS processing and first interleaving to obtain two first bit streams. The two first bit streams are then FEC encoded to obtain two second bit streams. The two second bit streams are then second interleaved to obtain two third bit streams. Finally, the two third bit streams are third interleaved to obtain a fourth bit stream, which is one output data stream of the second data subprocess. It should be understood that in some possible scenarios, the second interleaving can be a single operation, or it can be divided into two operations: a fourth interleaving and a fifth interleaving, which will be described in detail below.

[0171] The L second data sub-processing output bitstreams, resulting from L sub-processing steps, are merged to obtain a single second data processing output bitstream. Each second data processing output bitstream contains multiple fourth bits. Typically, the merging operation extracts S bits from each second data sub-processing output bitstream to obtain a total of S×L bits, which are then used as the S×L consecutive bits in the second data processing output bitstream. This merging operation can be called block merging or multiplexing (MUX). It should be noted that when L=1, i.e., there is only one second data sub-processing output bitstream, merging is not required to obtain the second data processing output bitstream. As an example, L can be 2, 4, or 8, etc., and is not limited here.

[0172] Figure 5(a) is a schematic diagram of an embodiment of the third data processing in this application. As shown in Figure 5(a), the fourth bit data undergoes symbol mapping and polarization distribution to obtain a dual-polarization symbol sequence. Symbol mapping and polarization distribution map every 12 bits of the fourth bit data to one dual-polarization symbol. Then, the dual-polarization symbol sequence is subjected to DSP framing. Specifically, a frame alignment word sequence (FAW sequence) and a training sequence are inserted in the X-polarization and Y-polarization directions, respectively. At least one sequence from reserved fields and pilot sequences is retained to obtain the dual-polarization symbol sequence to be transmitted. The dual-polarization symbol sequence can also be called a super-frame, multi-frame, DSP frame, frame, or DSP super-frame.

[0173] It should be noted that frame synchronization symbols are used for frame synchronization alignment, training symbols are used for link training, pilot symbols are used for carrier phase recovery, and reserved symbols are reserved for future use and innovation. The values ​​of reserved symbols can be known and unchanging, or they can be randomized; the values ​​of reserved symbols can also be called patterns. In some specific embodiments, reserved symbols can also be called fixed stuff (FS), and frame synchronization symbols can also be called multi-frame alignment signals (MFAS).

[0174] It should be noted that the DSP framing operation shown in Figure 5(a) is performed on symbols. DSP framing operations can also be performed on bits, as shown in Figures 5(b) and 5(c). Figure 5(b) is a schematic diagram of another embodiment of the third data processing in this application. As shown in Figure 5(b), the DSP framing operation can also insert the bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence into the fourth bit data before symbol mapping. After symbol mapping and polarization division, a dual-polarized symbol sequence identical to that in Figure 5(a) can be obtained. Figure 5(c) is a schematic diagram of yet another embodiment of the third data processing in this application. As shown in Figure 5(c), the DSP framing operation can also insert the bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence into the fourth bit data before symbol mapping. After polarization division and symbol mapping, a dual-polarized symbol sequence identical to that in Figure 5(a) can also be obtained. It should be understood that other framing operations are not excluded, and will not be described further in this application.

[0175] As shown in Figures 4(a) and 4(b), the bit stream output from the third interleaving is merged to obtain the fourth bit data. Symbol mapping and polarization partitioning are then performed on the fourth bit data to obtain a dual-polarized symbol. In this embodiment, symbol mapping and polarization partitioning map each 4×Z+4 bits to obtain one dual-polarized symbol. The 4×Z+4 bits include sign bits and Z-type amplitude bits, where Z is an integer greater than or equal to 3. For example, for DP-256QAM modulation, Z=3, so each 16 bits map to obtain one DP-256QAM symbol, which includes sign bits and three types of amplitude bits (i.e., first-type amplitude bits, second-type amplitude bits, and third-type amplitude bits). As another example, for DP-1024QAM modulation, Z=4, so each 20 bits map to obtain one DP-1024QAM symbol, which includes sign bits and four types of amplitude bits (i.e., first-type amplitude bits, second-type amplitude bits, third-type amplitude bits, and fourth-type amplitude bits). A dual-polarization symbol comprises an X-polarization symbol and a Y-polarization symbol, wherein the X-polarization and Y-polarization are orthogonal to each other. The X-polarization symbol includes the I-direction component (in-phase component) and the Q-direction component (quadrature-phase component) of the X-polarization, and the Y-polarization symbol includes the I-direction component and the Q-direction component of the Y-polarization, which can be denoted as Xi, Xj, ... I X, Y I Y Q .

[0176] It should be understood that the bits mapped to a dual-polarization symbol include 4×Z + 4 bits, and the 4×Z + 4 bits include symbol bits and Z classes of amplitude bits. Among them, the number of bits included in the symbol bits is 4 each, that is, the 4 symbol bits are respectively mapped to X I 、X Q 、Y I 、Y Q These 4 components; the number of bits included in the z-th class of amplitude bits is also 4 each, that is, the 4 z-th class of amplitude bits are also respectively mapped to X I 、X Q 、Y I 、Y Q These 4 components, where 0 < z ≤ Z.

[0177] It should be understood that when considering DP-2 T QAM modulation, where T is an even number greater than or equal to 8 (that is, when considering DP-256QAM modulation and higher modulations), 2×T bits are mapped to obtain a dual-polarization symbol, then 2×T = 4×Z + 4. Among them, Z = (T - 2) / 2 bits determine an amplitude, and these Z bits can be divided into Z classes of amplitude bits. The Z classes of amplitude bits all come from the second bit set after PCS processing of the first bit set. Therefore, the bits in the second bit set can also be divided into Z classes of bits, where the z-th class of amplitude bits comes from the corresponding z-th class of bits in the second bit set, 0 < z ≤ Z. Specifically, the Z classes of bits can include the first class of bits, the second class of bits, the third class of bits,..., the Z-th class of bits.

[0178] It should be noted that the distance between constellation points of different types of bits in the constellation diagram is greater than the distance between constellation points of different types of bits in the second type, the distance between constellation points of different types of bits in the second type is greater than the distance between constellation points of different types of bits in the third type, and so on, until the distance between constellation points of different types of bits in the (Z-1)th type is greater than the distance between constellation points of different types of bits in the Zth type. Therefore, the first type of bits, the second type of bits, the third type of bits, ..., the Zth type of bits are arranged in the target order, and the error bit rate of these Z types of bits increases progressively. Figure 52 is a schematic diagram of a constellation diagram according to an embodiment of this application. As shown in Figure 52, taking Z-type bits, including first-type bits, second-type bits, and third-type bits, as an example, consider a constellation point G1 in a polarization direction. Assume that the first-type bits, second-type bits, and third-type bits corresponding to this constellation point in the I component are 0, 0, and 0 respectively, and the first-type bits, second-type bits, and third-type bits corresponding to these bits in the Q component are also 0, 0, and 0 respectively. Then, the amplitude value in the I component and the amplitude value in the Q component in this polarization direction are both 15. Consider another constellation point G2, whose first-type bits are different from those of constellation point G1. Then, the first-type bits, second-type bits, and third-type bits corresponding to this constellation point in the I component are 1, 0, and 0 respectively, and the first-type bits, second-type bits, and third-type bits corresponding to these bits in the Q component are also 1, 0, and 0 respectively. Then, the amplitude value in the I component in this polarization direction is... The value is 1, and the amplitude value in the Q component is 1; Consider another constellation point G3, which is different from the second type of bit of constellation point G1. When the first type of bit, the second type of bit, and the third type of bit of constellation point G3 are 0, 1, and 0 respectively in the I component, and the first type of bit, the second type of bit, and the third type of bit of constellation point G3 are 0, 1, and 0 respectively in the Q component, the amplitude value in the I component in this polarization direction is 9, and the amplitude value in the Q component is 9; Consider another constellation point G4, which is different from the third type of bit of constellation point G1. When the first type of bit, the second type of bit, and the third type of bit of constellation point G4 are 0, 0, and 1 respectively in the I component, and the first type of bit, the second type of bit, and the third type of bit of constellation point G4 are 0, 0, and 1 respectively in the I component, and the first type of bit, the second type of bit, and the third type of bit of constellation point G4 are 0, 0, and 1 respectively in the Q component, the amplitude value in the I component in this polarization direction is 13, and the amplitude value in the Q component is 13. On a constellation diagram, the distance between constellation points G1 and G2, which are different in the first type of bits, is greater than the distance between constellation points G1 and G3, which are different in the second type of bits, and is greater than the distance between constellation points G1 and G4, which are different in the third type of bits.

[0179] For ease of explanation, the following description uses T=8, i.e., Z=3, i.e., one DP-256QAM symbol is obtained by mapping every 16 bits. Implementations based on higher modulation can be adapted on this basis, which will not be elaborated in this application.

[0180] Specifically, the L bit streams output from the third interleaving are grouped into S = 16 bits each, and then polled and merged. Symbol mapping is then performed (i.e., the 16 bits output from third interleaving 0 are mapped to a dual-polarization modulation symbol, the next 16 bits output from third interleaving 1 are mapped to a dual-polarization modulation symbol, and so on, up to the 16 bits output from third interleaving L-1 are mapped to a dual-polarization modulation symbol). For the case of dual-polarization 256QAM modulation (DP-256QAM), the symbol mapping and polarization division are performed in groups of 16 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b...). 10 ,b 11 ,b 12 ,b 13 ,b 14 ,b 15 The mapping yields one DP-256QAM symbol. For each signaling dimension X... I / X Q / Y I / Y Q The four bits are mapped to the corresponding symbol amplitudes as follows: (0,0,0,0)→-15, (0,0,0,1)→-13, (0,0,1,1)→-11, (0,0,1,0)→-9, (0,1,1,0)→-7, (0,1,1,1)→-5, (0,1,0,1)→-3, (0,1,0,0)→-1, (1,1,0,0)→+1, (1,1,0,1)→+3, (1,1,1,1)→+5, (1,1,1,0)→+7, (1,0,1,0)→+9, (1,0,1,1)→+11, (1,0,0,1)→+13, (1,0,0,0)→+15

[0181] It should be noted that the real part X I And the imaginary part X Q The complex number formed is used to represent the modulation symbol in the X-polarization direction, with the real part Y. I And the imaginary part Y Q The complex number formed is used to represent the modulation symbol in the Y-polarization direction. The dual-polarization symbol can be transmitted by transmitting the I-direction component X in the X-polarization direction. I X-polarization Q-direction component X Q Y-polarization component in the I direction I The Q-direction component Y in Y polarization Q Perform digital-to-analog conversion (DAC) to obtain the corresponding four analog signals.

[0182] Sixteen bits are mapped to a DP-256QAM symbol, of which 12 bits are amplitude bits and the other 4 bits are symbol bits. These amplitude bits can be further divided into three types: Type I amplitude bits, Type II amplitude bits, and Type III amplitude bits, with the same number of each type. Typically, the error bit rates of Type I, Type II, and Type III amplitude bits increase sequentially. The amplitude bits originate from the second bit set after PCS processing of the first bit set. Therefore, the bits in the second bit set can be divided into Type I, Type II, and Type III bits, with Type I amplitude bits originating from Type I bits, Type II amplitude bits from Type II bits, and Type III amplitude bits from Type III bits.

[0183] In some possible implementations, the probability that a bit in the first type of bit is 1 is P. 0-1 The probability that a bit in the first type of bit is 0 is P. 0-0 The probability that a bit in the second type of bit is 1 is P. 1-1 The probability that a bit in the second type of bit is 0 is P. 1-0 The probability that a bit in the third type of bit is 1 is P. 2-1 The probability that a bit in the third type of bit is 0 is P. 2-0 Among them, P 0-1 -P 0-0 The absolute value is greater than or equal to P 1-1 -P 1-0 The absolute value of P 1-1 -P 1-0 The absolute value is greater than or equal to P 2-1 -P 2-0 The absolute value of.

[0184] As an example, for DP-256QAM, consider the following first symbol mapping scheme: (b0,b2,b4,b6) is mapped to the I-direction component of the DP-256QAM symbol in X polarization, denoted as X. I ;(b8,b 10 ,b 12 ,b 14 The mapping is to the Q-direction component of the DP-256QAM symbol in X polarization, denoted as X. Q (b1,b3,b5,b7) is mapped to the I-direction component of the DP-256QAM symbol in Y polarization, denoted as Y. I ;(b9,b 11 ,b 13 ,b 15 The mapping is to the Q-direction component of the DP-256QAM symbol in Y polarization, denoted as Y. QAt this point, 16 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b) are... 10 ,b 11 ,b 12 ,b 13 ,b 14 ,b 15 In the original text, b0 and b8 are two symbol bits in 256QAM in the X-polarization direction, and b2, b4, b6, and b... 10 b 12 and b 14 These are six amplitude bits in a 256QAM array in the X-polarization direction, where b2 and b... 10 These are called type I amplitude bits, b4 and b 12 These are called type II amplitude bits, b6 and b 14 These are called the third type of amplitude bits; b1 and b9 are two symbol bits in the 256QAM in the Y-polarization direction, and b3, b5, b7, b... 11 b 13 and b 15 These are six amplitude bits in a 256QAM array in the Y-polarization direction, where b3 and b... 11 These are called Class I amplitude bits, b5 and b 13 These are called type II amplitude bits, b7 and b 15 This is called the second type of amplitude bit.

[0185] As another example, for DP-64QAM, consider the following second symbol mapping scheme: (b0,b1,b2,b3) is mapped to the I-direction component of the DP-256QAM symbol in X polarization, denoted as X. I (b4,b5,b6,b7) is mapped to the Q-direction component of the DP-256QAM symbol in X polarization, denoted as X. Q ;(b8,b9,b 10 ,b 11 The mapping is to the I-direction component of the DP-256QAM symbol in Y polarization, denoted as Y. I ;(b 12 ,b 13 ,b 14 ,b 15 The mapping is to the Q-direction component of the DP-256QAM symbol in Y polarization, denoted as Y. Q At this point, 16 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b) are... 10 ,b 11 ,b 12 ,b 13 ,b 14 ,b 15In the above, b0 and b4 are two symbol bits in the 256QAM along the X-polarization direction, and b1, b2, b3, b5, b6, and b7 are six amplitude bits in the 256QAM along the X-polarization direction. Among them, b1 and b5 are called first-type amplitude bits, b2 and b6 are called second-type amplitude bits, and b3 and b7 are called third-type amplitude bits; b8 and b 12 These are two symbol bits in 256QAM along the Y-polarization direction, b9 and b 10 b 11 b 13 b 14 and b 15 These are six amplitude bits in a 256QAM array in the Y-polarization direction, where b9 and b... 13 This is called the first type of amplitude bit, b 10 and b 14 This is called the second type amplitude bit, b 11 and b 15 This is called the third type of amplitude bit.

[0186] It should be noted that, for the first symbol mapping scheme, b0, b2, b4, b6, b8, b... of the 16 bits... 10 b 12 and b 14 Used for mapping to the X-polarization symbol, bits b1, b3, b5, b7, b9, b1, b2, b3, b4, b5, b6, b7, b8, b9, b1, b1, b1, b1, b2, b3, b4, b5, b7, b9, b1 ... 11 b 13 and b 15 Used for mapping to the Y-polarization symbol; for the second symbol mapping scheme, bits b0, b1, b2, b3, b4, b5, b6, and b7 of the 16 bits are used for mapping to the X-polarization symbol, and bits b8, b9, b1, b2, b3, b4, b5, b6, and b7 of the 16 bits are used for mapping to the X-polarization symbol. 10 b 11 b 12 b 13 b 14 and b 15Used for mapping to the Y-polarization symbol. Of the 16 bits used for mapping to the X-polarization symbol, 6 bits come from the second bit set, and the other 2 bits come from the third bit set or FEC-encoded parity bits; similarly, of the 16 bits used for mapping to the Y-polarization symbol, 6 bits come from the second bit set, and the other 2 bits come from the third bit set or FEC-encoded parity bits. It should be understood that "2 bits from the third bit set or FEC-encoded parity bits" means that the 2 bits come from at least one of the third bit set and FEC-encoded parity bits. For example, both bits can come from the third bit set; or both bits can come from FEC-encoded parity bits; or one bit comes from the third bit set and the other bit comes from FEC-encoded parity bits.

[0187] The following section takes the modulation using the first symbol mapping scheme as an example to describe in detail the operations of the second data subprocessing i (i = 0, 1, ..., L-1), where L is an integer greater than 0.

[0188] (1) PCS processing and first interleaving:

[0189] Figure 6(a) is a schematic diagram of an embodiment of PCS processing and first interleaving in this application. As shown in Figure 6(a), "PCS processing and first interleaving i" specifically includes one PCS processing operation and one first interleaving operation.

[0190] Specifically, firstly, e bits are obtained, where e is an integer greater than 0. The first set of bits from the e bits is sent to "PCS processing" to obtain the second set of bits. The second set of bits, combined with the third set of bits remaining after removing the first set from the e bits, is sent to the first interleaving to shuffle the order, resulting in two sets of fourth bits. It should be understood that the e bits are composed of the first set of bits and the third set of bits. It should be understood that, as shown in Figure 6(a), the first bit stream 2i and the first bit stream 2i+1 output by "PCS processing and first interleaving i" can include multiple sets of fourth bits.

[0191] Typically, each fourth bit set contains 1776×k0 bits, the second bit set contains 3072×k0 bits, the third bit set contains 480×k0 bits, and the first bit set contains e-(480×k0) bits, where k0 is an integer greater than 0.

[0192] As an example, when k0 = 2, the first bit set contains e-960 bits, the second bit set contains 6144 bits, of which 2048 bits are used to generate first-type amplitude bits, another 2048 bits are used to generate second-type amplitude bits, and the remaining 2048 bits are used to generate third-type amplitude bits. The third bit set contains 960 bits, and each fourth bit set contains 3552 bits.

[0193] Figure 6(b) is a schematic diagram of another embodiment of PCS processing and first interleaving in this application. As shown in Figure 6(b), "PCS processing and first interleaving i" specifically includes two PCS processing operations and one first interleaving operation. It should be understood that, compared with the implementation of Figure 6(a), the implementation in Figure 6(b) is divided into two PCS processing operations, which helps to reduce the complexity of a single PCS processing operation and makes the hardware implementation of a single PCS processing operation simpler.

[0194] Specifically, firstly, e bits are obtained, where e is an integer greater than 1. These e bits comprise two first bit sets, each of which is processed by PCS to obtain one second bit set. Typically, e is an even number greater than 0, and each first bit set contains the same number of bits. The e bits also comprise two third bit sets; it should be understood that the e bits are composed of two first bit sets and two third bit sets. Both the two second bit sets and the two third bit sets are fed into the first interleaving process to shuffle their order, resulting in two fourth bit sets. It should be understood that, as shown in Figure 6(b), the first bit stream 2i and the first bit stream 2i+1 output from "PCS processing and first interleaving i" can include multiple fourth bit sets.

[0195] Typically, each fourth bit set contains 1776×k0 bits, each second bit set contains 1536×k0 bits, each third bit set contains 240×k0 bits, and each first bit set contains e / 2-240×k0 bits, where k0 is a positive integer.

[0196] As an example, consider e as an even number greater than 0. When k0 = 6, each first bit set contains e / 2 - 1440 bits, and each second bit set contains 9216 bits. Of these 9216 bits, 3072 bits are used to generate first-type amplitude bits, another 3072 bits are used to generate second-type amplitude bits, and the remaining 3072 bits are used to generate third-type amplitude bits. Each third bit set contains 1440 bits, and each fourth bit set contains 10656 bits. It should be understood that in the above example, one first bit set and one third bit set together contain e / 2 bits. That is, the input e bits are first split into two paths, each containing e / 2 bits, before further processing. In some other possible scenarios, the input e bits can also be split into two paths in other proportions, meaning that the number of bits in one first bit set and one third bit set is different from the number of bits in another first bit set and another third bit set.

[0197] Figure 6(c) is a schematic diagram of another embodiment of PCS processing and first interleaving in this application. As shown in Figure 6(c), "PCS processing and first interleaving i" specifically includes two PCS processing operations and two first interleaving operations. It should be understood that, compared with the implementations of Figures 6(a) and 6(b), Figure 6(c) is implemented by dividing the first interleaving into two operations, which helps to reduce the complexity of a single first interleaving and makes the hardware implementation of a single first interleaving simpler.

[0198] Specifically, firstly, e bits are obtained, where e is an integer greater than 0. These e bits comprise two first bit sets, each of which is processed by PCS to obtain one second bit set. Typically, e is an even number greater than 0, and each first bit set contains the same number of bits. It should be understood that the e bits consist of two first bit sets and two third bit sets. One third bit set and one second bit set are fed into the first interleaving process to shuffle their order, resulting in one fourth bit set. It should be understood that, as shown in Figure 6(c), the first bit stream 2i and the fourth bit set 2i+1 output from "PCS processing and first interleaving i" can include multiple fourth bit sets.

[0199] Typically, each fourth bit set contains 1776×k0 bits, each second bit set contains 1536×k0 bits, each third bit set contains 240×k0 bits, and each first bit set contains e / 2-240×k0 bits, where k0 is a positive integer.

[0200] As an example, consider e as an even number greater than 0. When k0 = 42, each first bit set contains e / 2 - 10080 bits, and each second bit set contains 64512 bits. Of these 64512 bits, 21504 bits are used to generate first-type amplitude bits, another 21504 bits are used to generate second-type amplitude bits, and the remaining 21504 bits are used to generate third-type amplitude bits. Each third bit set contains 10080 bits, and each fourth bit set contains 74592 bits. It should be understood that in the above example, one first bit set and one third bit set together contain e / 2 bits. That is, the input e bits are first split into two paths, each containing e / 2 bits, before further processing. In some other possible scenarios, the input e bits can also be split into two paths in other proportions, meaning that the number of bits included in one first bit set and one third bit set is different from the number of bits included in another first bit set and another third bit set.

[0201] Figure 6(d) is a schematic diagram of another embodiment of PCS processing and first interleaving in this application. As shown in Figure 6(d), "PCS processing and first interleaving i" includes 2 PCS processes and 1 first interleaving. It should be understood that, compared with the implementation of Figure 6(a), Figure 6(d) is implemented by dividing it into 2 PCS processes, which helps to reduce the complexity of a single PCS process and makes the hardware implementation of a single PCS process simpler.

[0202] Specifically, firstly, e bits are obtained, where e is an integer greater than 0. These e bits comprise two first bit sets, each of which is processed by PCS to obtain one second bit set. Typically, e is an even number greater than 0, and each first bit set contains the same number of bits. It should be understood that the e bits consist of two first bit sets and one third bit set. The one third bit set and two second bit sets are then fed into the first interleaving process to shuffle their order, resulting in two fourth bit sets. It should be understood that, as shown in Figure 6(d), the first bit stream 2i and the fourth bit set 2i+1 output from "PCS processing and first interleaving i" can include multiple fourth bit sets.

[0203] Typically, each fourth bit set contains 1776×k0 bits, each second bit set contains 1536×k0 bits, each third bit set contains 480×k0 bits, and each first bit set contains e / 2-240×k0 bits, where k0 is an integer greater than 0.

[0204] As an example, considering e as an even number greater than 0, when k0 = 2, each first bit set contains e / 2 - 480 bits, each second bit set contains 3072 bits, of which 1024 bits are used to generate first-type amplitude bits, another 1024 bits are used to generate second-type amplitude bits, and the remaining 1024 bits are used to generate third-type amplitude bits. The third bit set contains 960 bits, and each fourth bit set contains 3552 bits.

[0205] In some possible implementations, the PCS process shown in Figures 6(a), 6(b), 6(c), and 6(d) may further include multiple PCS sub-processes. Figure 6(e) is a schematic diagram of an embodiment of the PCS process including multiple PCS sub-processes in this application. As shown in Figure 6(e), the PCS process includes L PCS Each PCS subprocess is divided into three groups: PCS subprocess 0, PCS subprocess 1, and PCS subprocess 2. L PCS The input k is a positive integer. The PCS subprocesses the input k pairs. pcs_0 Each bit is processed to obtain n, which has an uneven distribution of values ​​0 and 1. pcs_0 One output bit, processed by the PCS subprocessing of one pair of input k pcs_1 Each bit is processed to obtain n, which has an uneven distribution of values ​​0 and 1. pcs_1 One output bit, processed by the PCS subprocessing of 2 pairs of input k pcs_2 Each bit is processed to obtain n, which has an uneven distribution of values ​​0 and 1. pcs_2 n output bits. pcs_0 >k pcs_0 n pcs_1 >k pcs_1 n pcs_2 >k pcs_2 And n pcs_0 =n pcs_1 =n pcs_2 Typically, the n pcs_0 The probability P of each output bit being 1 cs0-1 The probability P that is greater than 0 cs0-0 And P cs0-0 +P cs0-1 =1; the n pcs_1 The probability P of each output bit being 1 cs1-1 The probability P that is greater than 0 cs1-0 And P cs1-0 +P cs1-1 =1; the n pcs_2 The probability P of each output bit being 1 cs2-1The probability P that is greater than 0 cs2-0 And P cs2-0 +P cs2-1 =1. Without loss of generality, assume k pcs_0 ≤k pcs_1 ≤k pcs_2 There is P cs0-1 ≥P cs1-1 ≥P cs2-1 P cs0-0 ≤P cs1-0 ≤P cs2-0 .

[0206] Consider using Gray mapping in symbol mapping (i.e., modulation). For example, 3 bits (0,0,0) are mapped to the maximum amplitude 15 with probability P. 15 The three bits (0,0,1) map to the second largest amplitude 13, with a probability of P. 13 The probability that 3 bits (0, 1, 1) map to the third largest amplitude 11 is P. 11 Three bits (0,1,0) map to the fourth largest amplitude 9 with probability P9; three bits (1,1,0) map to the fifth largest amplitude 7 with probability P7; three bits (1,1,1) map to the sixth largest amplitude 5 with probability P5; three bits (1,0,1) map to the seventh largest amplitude 3 with probability P3; three bits (1,0,0) map to the smallest amplitude 1 with probability P1. To ensure that P1≥P3≥P5≥P7≥P9≥P 11 ≥P 13 ≥P 15 n pcs_0 One output bit, n pcs_1 One output bit and n pcs_2Each output bit is also bit-mapped. This bit mapping transforms the three input bits (a, b, c) into three output bits (a, a∧b, b∧c), where ∧ represents the XOR operation. That is, one bit after bit mapping becomes a first-type bit in the second bit set, used to map to the first-type amplitude bits of the double-polarization symbol; another bit after bit mapping becomes a second-type bit in the second bit set, used to map to the second-type amplitude bits of the double-polarization symbol; and yet another bit after bit mapping becomes a third-type bit in the second bit set, used to map to the third-type amplitude bits of the double-polarization symbol. More specifically, three bits (0,0,0) are mapped to (0,0,0), three bits (0,0,1) are mapped to (0,0,1), three bits (0,1,0) are mapped to (0,1,1), three bits (0,1,1) are mapped to (0,1,0), three bits (1,0,0) are mapped to (1,1,0), three bits (1,0,1) are mapped to (1,1,1), three bits (1,1,0) are mapped to (1,0,1), and three bits (1,1,1) are mapped to (1,0,0).

[0207] As an example, bit a comes from the n pcs_0 One output bit, bit b comes from the n pcs_1 There are n output bits, and bit c comes from the n pcs_2 There are one output bit. At this time, P1 = P cs0-1 ×P cs1-1 ×P cs2-1 P3 = P cs0-1 ×P cs1-1 ×P cs2-0 P5 = P cs0-1 ×P cs1-0 ×P cs2-1 P7 = P cs0-1 ×P cs1-0 ×P cs2-0 P9 = P cs0-0 ×P cs1-1 ×P cs2-1 P 11 =P cs0-0 ×P cs1-1 ×P cs2-0 P 13 =P cs0-0 ×P cs1-0 ×P cs2-1 P 15 =P cs0-0 ×P cs1-0 ×P cs2-0 And P1≥P3≥P5≥P7≥P9≥P 11 ≥P 13 ≥P 15In some specific applications, k pcs_0 <k pcs_1 <k pcs_2 There is P cs0-1 >P cs1-1 >P cs2-1 P cs0-0 <P cs1-0 <P cs2-0 P1>P3>P5>P7>P9>P 11 >P 13 >P 15 In other specific applications, k pcs_0 =k pcs_1 =k pcs_2 There is P cs0-1 =P cs1-1 =P cs2-1 P cs0-0 =P cs1-0 =P cs2-0 P1>P3=P5=P9>P7=P 11 =P 13 >P 15 .

[0208] Figure 6(f) is a schematic diagram of another embodiment of the PCS processing in this application, which includes multiple PCS sub-processes. In some specific applications, the PCS processing includes L PCS =4 sets of PCS subprocesses and 4 bit mappings corresponding to the 4 sets of PCS subprocesses, as shown in Figure 6(f). Of the 12 data streams output by the 4 bit mappings, the bits in one data stream (data stream 0 in Figure 6(f)) are used to generate the signal dimension (also called the component) X. I The first type of amplitude bits, all bits in one data stream (as shown in Figure 6(f) of the mapped output data stream 1) are used to generate X. I The second type of amplitude bits, all bits in one data stream (as shown in Figure 6(f) mapped output data stream 2) are used to generate X. I The third type of amplitude bits; all bits in one data stream (as shown in Figure 6(f) mapped output data stream 3) are used to generate X. Q The first type of amplitude bits, and the bits in one data stream (as shown in Figure 6(f) map output data stream 4) are all used to generate X. Q The second type of amplitude bits, all bits in one data stream (as shown in Figure 6(f) of the mapped output data stream 5) are used to generate X. Q The third type of amplitude bits; all bits in one data stream (as shown in Figure 6(f) mapped output data stream 6) are used to generate Y. I The first type of amplitude bits, and the bits in one data stream (as shown in Figure 6(f) mapped output data stream 7) are all used to generate Y.I The second type of amplitude bits, all bits in one data stream (as shown in Figure 6(f) mapped output data stream 8) are used to generate Y. I The third type of amplitude bits; all bits in one data stream (as shown in Figure 6(f) map output data stream 9) are used to generate Y. Q The first type of amplitude bits, all bits in one data stream (as shown in Figure 6(f) of the mapped output data stream 10) are used to generate Y. Q The second type of amplitude bits, all bits in one data stream (as shown in Figure 6(f) mapped output data stream 11) are used to generate Y. Q The third type of amplitude bit.

[0209] In some applications, PCS subprocesses 0, 1, and 2 can be implemented using lookup tables (LUTs). In some specific applications, LUT processing can also be implemented using multiple sub-lookup tables, where the input and output bit counts of the sub-lookup tables can differ. In this case, the PCS processing is also called PCS LUT processing. It should be noted that PCS processing can also be called a distribution matcher (DM). In some specific applications, the first interleaving can be called a block map, pre-FEC interleaver, or pre-FEC permutation.

[0210] It should be noted that, as shown in Figures 6(a), 6(b), 6(c), and 6(d), the first bit stream contains multiple fourth bit sets. Each fourth bit set can be distributed as a multi-row bit block, where each row contains 7 columns of bit blocks. The bits in each bit block are consecutive. It should be understood that in some possible scenarios, a bit block can also be called a bit subset, and a bit block is a specific implementation of a row-column distribution of bit subsets. Furthermore, if the number of rows and columns of a bit block is the same, the bit block can also be called a bit square block, matrix, or cube. For example, a bit block with 16 rows and 16 columns mentioned in this document can also be called a bit square block, matrix, or cube. It should be understood that in the embodiments of this application, all bit sets, bit subsets, bit blocks, etc., involving row-column distribution are counted starting from row 0 and column 0. It should also be understood that in the embodiments of this application, whenever a row or column is mentioned in a bit set, it refers to a subset or block of bits that are distributed in rows and columns. In the embodiments of this application, whenever a row or column is mentioned in a subset or block of bits, it refers to bits that are distributed in rows and columns. The row and column in a subset or block of bits can also be called a bit row and a bit column.

[0211] Figure 7 is a schematic diagram of a 7-column bit block in an embodiment of this application. As shown in Figure 7, the 0th, 1st, 2nd, 3rd, 4th, and 5th bit blocks each contain 256 bits (16 rows and 16 columns), and the 6th bit block contains 240 bits (16 rows and 15 columns). That is, each 7-column bit block contains a total of 1776 bits. It should be noted that a bit block containing 256 bits (16 rows and 16 columns) can be called a square block or a cube.

[0212] It should be noted that in some specific applications, the first interleaving operation in "PCS processing and first interleaving" is performed with a granularity of 7104 or 3552 bits. In other specific applications, the first interleaving operation in "PCS processing and first interleaving" is performed with a granularity of 21312 or 10656 bits; and in still other specific applications, the first interleaving operation in "PCS processing and first interleaving" is performed with a granularity of 149184 or 74592 bits.

[0213] It should be noted that the first bit stream contains multiple fourth bit sets. As an example, each fourth bit set has a bit distribution of 2 rows and 7 columns, totaling 14 bit blocks. Each bit block in the first 6 columns contains 16 bit rows and 16 bit columns, and each bit block in the last column contains 16 bit rows and 15 bit columns. Each row contains 7 bit blocks, for a total of 1776 bits, as shown in Figure 7. The bits in each bit block are consecutive. It should be understood that other forms of bit distribution in fourth bit sets are possible, but will not be elaborated upon here. The following description uses the above-described 2 rows and 7 columns of 14 bit blocks as an example.

[0214] Figure 8 is a schematic diagram of a fourth bit set according to an embodiment of this application. As shown in Figure 8, the aforementioned fourth bit set can specifically be presented in the form of a rectangular bit block. The bit block in the i0th row and j0th column of the fourth bit set is denoted as... Where 0 ≤ i0 < 2 and 0 ≤ j0 < 7.

[0215] As shown in Figure 8, each bit block in the first 6 columns (i.e., columns 0 to 5) of the fourth bit set contains 16-bit rows and 16-bit columns, i.e. (0≤i0<2 and 0≤j0<6) is a square matrix containing 256 bits. In some specific applications, bit blocks... (0≤i0<2 and 0≤j0<6) A total of 256 bits, comprising 16 rows and 16 columns, are consecutive in the first bitstream. Figure 9 is a schematic diagram of a 16×16 bit block according to an embodiment of this application. As shown in Figure 9, each bit block... In a block of bits (0 ≤ i0 < 2 and 0 ≤ j0 < 6), the bit in row r0 and column c0 (0 ≤ r0 < 16 and 0 ≤ c0 < 16) corresponds to the 16 × r0 + c0 bit out of 256 consecutive bits. For example, the bit in row r0 = 1 and column c0 = 0 in a bit block corresponds to the 16th bit out of 256 bits. As another example, the bit in row r0 = 2 and column c0 = 3 in a bit block corresponds to the 35th bit out of 256 bits.

[0216] As shown in Figure 8, each bit block in the last column (i.e., the 6th column) of the fourth bit set contains 16 bits in a row and 15 bits in a column. (0 ≤ i0 < 2 and j0 = 6) is a bit block containing 240 bits. In some specific applications, bit blocks... (0≤i0<2 and j0=6) A total of 240 bits, comprising 16 rows and 15 columns, are consecutive in the first bitstream. Figure 10 is a schematic diagram of a 16×15 bit block according to an embodiment of this application. As shown in Figure 10, each bit block... In a block of bits (0 ≤ i0 < 2 and j0 = 6), the bit in row r1, column c1 (0 ≤ r1 < 16 and 0 ≤ c1 < 15) corresponds to the 15 × r1 + c1 bit out of 240 consecutive bits. For example, the bit in row r1 = 1, column c1 = 0 corresponds to the 15th bit out of 240 bits. As another example, the bit in row r1 = 2, column c1 = 3 corresponds to the 33rd bit out of 240 bits.

[0217] It should be noted that in some specific applications, the 3552 bits (2 rows and 7 columns) in the fourth bit set are consecutive on the first bit stream. Furthermore, in some specific applications, the 14 bit blocks (2 rows and 7 columns) in the fourth bit set can be distributed as consecutive 1776 bits (1 row) in the first bit stream. For example, in the fourth bit set... The 7 bit blocks, totaling 1776 bits, are consecutive in the first bitstream, where 0 ≤ i0 < 2. In other specific applications, the 14 bit blocks (2 rows, 7 columns) in the fourth bit set can be distributed as 2 rows of 3552 consecutive bits in the first bitstream. For example, in the fourth bit set A... 0,0 A 1,0 A 0,1 A 1,1 A 0,2 A 1,2 A 0,3 A 1,3 A 0,4 A 1,4 A 0,5 A 1,5 A 0,6 A 1,6 The 14 bit blocks, totaling 3552 bits, are consecutive in the first bit stream.

[0218] As shown in Figure 8, the bits in the fourth bit set are distributed in 2 rows and 7 columns, totaling 14 bit blocks. (0≤i0<2 and 0≤j0<7). The bits in the leftmost 4 columns of the fourth bit set, i.e., the bit blocks filled with the shaded background shown in Figure 8. (0≤i0<2 and 0≤j0<4), bits from the second bit set processed by PCS and bits from the third bit set not processed by PCS. The rightmost three columns of bits in the fourth bit set, i.e., the bit blocks filled with the non-shaded (white) background as shown in Figure 8. (0≤i0<2 and 4≤j0<7), bits from the remaining portion of the second bit set after PCS processing (i.e., bits not from the third bit set).

[0219] It should be noted that the bit pattern (also called bit distribution pattern) in the embodiments of this application is used to describe the source and purpose of each specific bit in the bit block. The bit pattern distribution is r rows and c columns, where r rows and c columns can be 16 rows and 16 columns, or 16 rows and 15 columns. Bits with different sources or purposes in the bit pattern can be labeled with different numbers. As an example, some bits in the bit pattern come from the third bit set that has not been processed by PCS or from the parity bits of FEC encoding, and are used as symbol bits in the symbol mapping (also called modulation), and are labeled with the number "0" in each bit pattern. As another example, some bits in the bit pattern come from the second bit set that has been processed by PCS, and are used as amplitude bits in the symbol mapping (also called modulation), for example, they are labeled with the number "1" in some bit patterns below; or, for example, the bits from the second bit set are divided into 3 types of bits, and these 3 types of bits are labeled with the numbers "1", "2", and "3" respectively in some other bit patterns below. In other words, the specific position of each bit in the bit pattern can be seen from the numbers marked in the bit pattern below. For example, the number "0" marked in the bit pattern indicates the specific positions of the symbol bit in the symbol mapping. Several bit patterns are given below, combining different symbol mapping schemes and different number marking methods.

[0220] More specifically, taking the first symbol mapping as an example, the portion of the bit block in the bit pattern marked with the number "0" in the r-th row and c-th column indicates that the bit in the r-th row and c-th column of the bit block comes from the third bit set without PCS processing or from the parity bit of FEC encoding, and serves as the symbol bit in the symbol mapping (also known as modulation). The portion of the bit block in the bit pattern marked with the number "1" in the r-th row and c-th column indicates that the bit in the r-th row and c-th column of the bit block comes from the second bit set after PCS processing, and serves as the amplitude bit in the symbol mapping (also known as modulation).

[0221] Referring to the 2-row, 7-column bit block diagram shown in Figure 8, the bit block in the fourth bit set of the first bit stream is described below. (0≤i0<2 and 0≤j0<7) pattern. Specifically, Figure 11 is a schematic diagram of a first bit pattern in an embodiment of this application; Figure 12(a) is a schematic diagram of a second bit pattern in an embodiment of this application; Figure 12(b) is a schematic diagram of another second bit pattern in an embodiment of this application; Figure 13 is a schematic diagram of a third bit pattern and a fourth bit pattern in an embodiment of this application; Figure 14 is a schematic diagram of a fifth bit pattern in an embodiment of this application.

[0222] 1) For the case where 0≤i0<2 and 0≤j0<3: the corresponding 6 bit blocks The bit pattern uses the first bit pattern. As an example, the first bit pattern is shown in Figure 11, which contains a 16-row, 16-column bit block. Each row contains 4 bits marked with the number "0" (i.e., bits from the third bit set that has not been processed by PCS, and which serve as sign bits in the symbol map) and 12 bits marked with the number "1" (i.e., bits from the second bit set that has been processed by PCS, and which serve as amplitude bits in the symbol map).

[0223] 2) For 0 ≤ i0 < 2 and j0 = 3: the corresponding two bit blocks The bit pattern uses the second bit pattern. It contains a 16-row, 16-column bit block, which includes 48 bits marked with the number "0" (i.e., bits from the third bit set that has not been processed by PCS, and which serve as sign bits in the symbol mapping) and 208 bits marked with the number "1" (i.e., bits from the second bit set that has been processed by PCS, and which serve as amplitude bits in the symbol mapping).

[0224] In one specific implementation, the second bit pattern is shown in Figure 12(a); in another specific implementation, the second bit pattern is shown in Figure 12(b).

[0225] 3) For 0≤i0<2 and j0=4: the corresponding 2 bit blocks The bit pattern uses a third bit pattern. As an example, the third bit pattern is shown in Figure 13, which contains 256 bits marked with the number "1" in a 16-row, 16-column bit block (i.e., bits from the second bit set processed by the PCS, and serving as amplitude bits in the symbol mapping). The bits marked with the number "1" are bits from the second bit set processed by the PCS.

[0226] 4) For 0 ≤ i0 < 2 and j0 = 5: the corresponding 2 bit blocks The bit pattern uses the fourth bit pattern. As an example, the fourth bit pattern is shown in Figure 13.

[0227] 5) For 0 ≤ i0 < 2 and j0 = 6: the corresponding 2 bit blocks The bit pattern uses the fifth bit pattern. As an example, the fourth bit pattern is shown in Figure 14, which contains 240 bits marked with the number "1" in a 16-row, 15-column bit block (i.e., bits from the second bit set processed by the PCS, and serving as amplitude bits in the symbol mapping). The bits marked with the number "1" come from the second bit set processed by the PCS.

[0228] It should be noted that for the case where 0 ≤ i0 < 2 and j0 = 4, the corresponding two bit blocks In this example, each bit block consists of 16 rows and 16 columns, containing 208 bits from the second bit set and 48 bits from the third bit set. As an example, The corresponding second bit pattern is shown in Figure 12(a) and Figure 12(b). The corresponding second bit pattern may also differ from the examples shown in Figures 12(a) and 12(b), which will not be elaborated further in this application. It should also be noted that bit blocks... The distribution patterns of (0≤i0<2 and 0≤j0<4) are different, meaning the distribution positions of amplitude bits and symbol bits in the bit block are different. It should be understood that the first bit stream 2i and the first bit stream 2i+1 after "PCS processing and first interleaving" can include multiple sets of fourth bits.

[0229] (2) FEC coding:

[0230] Figure 15 is a schematic diagram of one implementation method for data processing of two first bit streams in this application. As shown in Figure 15, "FEC encoding" encodes the fourth bit set in the first bit stream and adds parity bits to obtain the fifth bit set. It should be understood that the second bit stream output by FEC encoding may include multiple fifth bit sets. It should be noted that the input processing granularity of FEC encoding is K, and the corresponding output granularity is N. Considering K / N = 111 / 128, the encoding redundancy of FEC encoding is N / K-1 = 15.3%. As an example, K = 3552, N = 4096, and FEC encoding uses extended BCH(256,239). FEC encoding encodes every two bit rows in the fourth bit set, totaling 1776 × 2 = 3552 bits, and adds parity bits to obtain a total of 4096 encoded bits, which is the fifth bit set. FEC encoding encodes every bit row in the fourth bit set, totaling 111 bits, and adds 17 parity bits to obtain one row of 128 bits in the fifth bit set. More specifically, a bit row in the fourth bit set (which can be considered the current bit row) contains 111 bits. Combined with the 128 bits from the previous multiple bit rows in the fourth bit set (which can be considered previous bit rows), the total is 111 + 128 = 239 bits. This is then extended (256, 239) with 17 parity bits to obtain a 256-bit codeword. It should be understood that the FEC encoding is a convolutional algebraic code, also known as a spatially coupled code.

[0231] It should be noted that the second bit stream contains multiple fifth bit sets, each fifth bit set having a bit distribution of 2 rows and 8 columns, totaling 16 bit blocks, where each bit block is a square matrix containing 16 bit rows and 16 bit columns. Typically, 256 bits in each of these square matrices are consecutive in the second data stream. Figure 16 is a schematic diagram of a bit block with 8 columns per row in an embodiment of this application. As shown in Figure 16, each row of bit blocks contains 8 bit blocks, for a total of 2048 bits. It should be understood that from FEC encoding until the completion of the third interleaving, the operations of the fourth interleaving, fifth interleaving, intra-matrix interleaving, and inter-matrix interleaving are all performed with a granularity of 2 rows and 8 columns, totaling 16 bit blocks. It should be noted that in some specific applications, the fourth interleaving may be performed with a granularity of 3 rows and 8 columns, totaling 24 bit blocks; in other specific applications, the fourth interleaving may be performed with a granularity of 6 rows and 8 columns, totaling 48 bit blocks. For simplicity, the operations of the fourth interleaving, fifth interleaving, intra-array interleaving, and inter-array interleaving in this application are performed in granularity of 16 bit blocks (2 rows, 8 columns).

[0232] Figure 17 shows a schematic diagram of a fifth bit set according to an embodiment of this application. As shown in Figure 17, the fifth bit set is presented in the form of a rectangular bit block. The square matrix of the i1th row and j1st column of the fifth bit set is denoted as... Where 0 ≤ i0 < 2 and 0 ≤ j1 < 8.

[0233] In some specific applications, bit blocks (0≤i0<2 and 0≤j1<8) Containing 16 rows and 16 columns, totaling 256 bits, is continuous in the second bitstream. More specifically, Figure 9 shows a specific distribution where each bit block In a bit block (0 ≤ i0 < 2 and 0 ≤ j1 < 8), the bit in row r0 and column c0 (0 ≤ r0 < 16 and 0 ≤ c0 < 16) corresponds to the 16 × r0 + c0 bit out of 256 bits. For example, the bit in row r0 = 1 and column c0 = 0 in the bit block corresponds to the 16th bit out of 256 bits. As another example, the bit in row r0 = 2 and column c0 = 3 in the bit block corresponds to the 35th bit out of 256 bits.

[0234] It should be noted that in some specific applications, the 16-bit block (2 rows, 8 columns) in the fifth bit set can be distributed as a continuous 2048-bit block (1 row), for example, in the fifth bit set... The 8 bit blocks, totaling 2048 bits, are consecutive in the second bitstream, where 0 ≤ i0 < 2. In other specific applications, the 42 rows and 8 columns of the fifth bit set, totaling 336 bits, can be distributed consecutively in the second bitstream as 2 rows of bit blocks, totaling 4096 bits. For example, in the fifth bit set, B... 0,0 B 1,0 B 0,1 B 1,1 B 0,2 B 1,2 B 0,3 B 1,3 B 0,4 B 1,4 B 0,5 B 1,5 B 0,6 B 1,6 B 0,7 B 1,7 The 16 bit blocks, totaling 4096 bits, are consecutive on the second bit stream.

[0235] As shown in Figure 17, the fifth bit set is distributed in 2 rows and 8 columns, totaling 16 bit blocks. (0≤i0<2 and 0≤j1<8). The bits in the leftmost 4 columns (i.e., columns 0-3) of the fifth bit set, i.e., the bit blocks filled with the shaded background shown in Figure 17. (0≤i0<2 and 0≤j1<4), bits from the second bit set processed by PCS and bits from the third bit set not processed by PCS, the fourth column of the fifth bit set. (0≤i0<2), 5th column bit block (0≤i0<2) and the 6th column bit block The leftmost 15-bit column (0≤i0<2) contains bits from a total of 16+16+15=47 bits, which come from the remaining bits in the second bit set processed by PCS (i.e., excluding bits from the third bit set). The 6th bit block in the fifth bit set... The rightmost bit column and the 7th bit block in (0≤i0<2) (0≤i0<2)), and the bits in the 1+16=17 bit column are the check bits obtained from FEC encoding.

[0236] The bit block (matrix) pattern in the fifth bit set is described below. Figure 18(a) is a schematic diagram of a sixth bit pattern in an embodiment of this application; Figure 18(b) is a schematic diagram of a seventh bit pattern in an embodiment of this application.

[0237] For 0 ≤ i0 < 2 and 0 ≤ j1 < 6, the bit block (matrix) in the fifth bit set The bit pattern and the corresponding bit block (matrix) in the fourth bit set before encoding. (0≤i0<2 and 0≤j0<6) are consistent.

[0238] For 0 ≤ i0 < 2 and j1 = 6, the bit block (matrix) B in the fifth bit set is... 0,6 The bit pattern uses the sixth bit pattern. As an example, the fifth bit pattern is shown in Figure 18(a), which contains a 16-row, 16-column bit block with a total of 240 bits marked with the number "1" and 16 bits marked with the number "0". The bits marked with the number "1" come from the bits in the second bit set processed by PCS, and the bits marked with the number "0" come from the FEC-encoded parity bits.

[0239] For the case where 0 ≤ i0 < 2 and j1 = 7, the bit block (matrix) in the fifth bit set The bit pattern uses the seventh bit pattern. As an example, the seventh bit pattern is shown in Figure 18(b), which contains 256 bits marked with the number "1" in a 16-row, 16-column bit block. The bits marked with the number "1" come from the FEC-encoded parity bits.

[0240] In some specific applications, a fifth bit set in the second bitstream is obtained by directly adding parity bits to a fourth bit set before encoding. More specifically, the bit data in columns 0-111 of a fifth bit set in the second bitstream is equal to the bit data in columns 0-111 of the fourth bit set before encoding. It should be understood that the second bitstream after "FEC encoding" can include multiple fifth bit sets.

[0241] (3) Second interweaving:

[0242] As shown in Figure 15, the second interleaving can involve two steps: a fourth interleaving and a fifth interleaving. A fifth bit set distributed as a 2x8 bit block from the second bit stream is fed into the fourth interleaving to obtain an eighth bit set. This eighth bit set, also distributed as a 2x8 bit block, is then fed into the fifth interleaving to obtain a sixth bit set. It should be understood that, as shown in Figure 15, the fifth bit stream output from the fourth interleaving can include multiple eighth bit sets, and the third bit stream output from the fifth interleaving can include multiple sixth bit sets.

[0243] The fourth and fifth interlacings are described below.

[0244] In some specific application scenarios, the 10 bit blocks from j1=3 to j1=7 in the fifth bit set of the fourth interleaving pair The bits in (0≤i0<2 and 0≤j1<8) are interleaved and shuffled to obtain the eighth bit set, that is, the 6 bit blocks from j1=0 to j1=2 in the fifth bit set are not changed. (0≤i0<2 and 0≤j1<3). Furthermore, in some specific application scenarios, the fourth interleaving does not change the j1=3th column in the fifth bit set. The bit positions of certain bit columns in (0≤i0<2); for example, without changing The bit positions of the first few (i.e., the leftmost) bit columns in (0≤i0<2), that is... In the sequence (0≤i0<2), the first few (i.e., leftmost) bit columns do not participate in the fourth interleaving. For example, The first 9 bits (i.e., the leftmost bits) in the (0≤i0<2) sequence do not participate in the fourth interleaving operation. Columns 9, 10, 11, 12, 13, 14, and 15, combined with... The 71-bit column of bits is subjected to the fourth interleaving.

[0245] Figure 19 is a schematic diagram of an eighth bit set according to an embodiment of this application. As shown in Figure 19, the bit distribution in the eighth bit set obtained after the fourth interleaving is 2 rows and 8 columns, totaling 16 bit blocks. (0≤i0<2 and 0≤j1<8). It should be noted that in the above 2 rows and 8 columns of 16 bit blocks C, all bit blocks... The size of each (0≤i0<2 and 0≤j1<8) is 16 rows and 16 columns of bits (i.e., 16×16=256 bits), as shown in Figure 9. For simplicity, (r0,c0) represents the bit block located in the i0th row and j1st column. A bit in the r0th bit row and c0th bit column of a block of bits. In some specific applications, a bit block... The 256 bits, consisting of 16 rows and 16 columns, are consecutive in the fifth bitstream.

[0246] The bit block (matrix) patterns in the eighth bit set are described below. Referring to the 2x8 bit block diagram shown in Figure 19, for the case where 0≤i0<2 and 0≤j1<8, the corresponding 16 bit blocks are... The bit pattern uses the first bit pattern. As an example, the first bit pattern is shown in Figure 11, where bits marked with the number "0" come from bits in the third bit set that have not been processed by PCS or from parity bits encoded by FEC, and bits marked with the number "1" come from bits in the second bit set that have been processed by PCS.

[0247] It should be noted that the bit patterns of the 8-bit blocks in each row of the fifth bit set obtained after FEC encoding are not completely identical. The fourth interleaving ensures that the bit patterns of the 8-bit blocks in each row of the eighth bit set are identical. In some specific applications, the fourth interleaving can also be called Post-FEC Permutation.

[0248] Each bit block in the fifth interleaving pair of the eighth bit set (0≤i0<2 and 0≤j1<8) are interleaved and shuffled to obtain the sixth bit set. As shown in Figure 20, the sixth bit set is distributed as 2 rows and 8 columns, totaling 16 bit blocks. (0≤i0<2 and 0≤j1<8). Each bit block The size of each (0≤i0<2 and 0≤j1<8) is 16 rows and 16 columns of bits (i.e., 16×16=256 bits), as shown in Figure 9. For simplicity, (r2,c2) represents the bit block located in the j1st square of the i0th square matrix. A bit in the r2-th bit row and c2-th bit column of a given block, where 0 ≤ r2 < 16 and 0 ≤ c2 < 16. In some specific applications, a bit block... The 256 bits, consisting of 16 rows and 16 columns, are continuous on the third bit stream.

[0249] In some specific applications, the fifth interleaving pair is used for each bit block in the eighth bit set. Each bit row in the set (0≤i0<2 and 0≤j1<8) consists of 16 bits. These bits are permuted to obtain the corresponding bit block in the sixth bit set. The fifth interleaving involves interleaving and shuffling the order of 16 bits per row in each bit block, also known as row permutation, row interleaving, or "^r" row permutation.

[0250] More specifically, the bit block in the sixth bit set The bit in the r2-th row and c2-th column (r2, c2) are bit blocks from the eighth bit set. The bit in the r0th bit row and c0th bit column (r0,c0), where r2 = r0 and c2 = c0^r0. Here, a^b represents a bitwise exclusive OR operation on two positive integers a and b. Figure 21 is a schematic diagram of one implementation of the fifth interleaving in this application. As shown in Figure 21, the specific interleaving method can be understood with reference to Figure 21.

[0251] The bit block pattern in the sixth bit set is described below. Figure 20 is a schematic diagram of a sixth bit set according to an embodiment of this application. As shown in Figure 20, referring to the 2-row, 8-column bit block schematic diagram shown in Figure 20, Figure 22 is a schematic diagram of an eighth bit pattern according to an embodiment of this application.

[0252] For the case where 0 ≤ i0 < 2 and 0 ≤ j1 < 8: the corresponding 16 bit blocks The bit pattern uses the eighth bit pattern. As an example, the eighth bit pattern is shown in Figure 22, where the bits marked with the number "0" come from the bits in the third bit set that have not been processed by PCS or the parity bits of FEC encoding, and serve as the symbol bits in the symbol map; the bits marked with the number "1" come from the bits in the second bit set that have been processed by PCS, and serve as the amplitude bits in the symbol map.

[0253] (4) The third interweaving:

[0254] As shown in Figure 15, the third interleaving can also be called block interleaving. The third interleaving includes intra-block interleaving and inter-block interleaving.

[0255] A set of sixth bits arranged in 2 rows and 8 columns from the third bit stream is fed into a square matrix for interleaving to obtain a set of ninth bits arranged in 2 rows and 8 columns. It should be understood that the sixth bit stream output by interleaving in the square matrix may include multiple sets of ninth bits.

[0256] Inter-matrix interleaving involves interleaving and shuffling the 21 sets of ninth bits in the sixth bitstream 2i and the 21 sets of ninth bits in the sixth bitstream 2i+1, resulting in a seventh bit set distributed in 84 rows and 8 columns. It should be noted that in some specific applications, inter-matrix interleaving is also called OFEC interleaving.

[0257] The following sections describe the interweaving within and between squares.

[0258] Figure 23 is a schematic diagram of one implementation of interleaving within a square array in this application. As shown in Figure 23, interleaving within a square array first involves processing the bit blocks of each received sixth bit set. After interleaving (0≤i0<2 and 0≤j1<8) within the matrix, the resulting bit block is the ninth bit set, which has a bit distribution of 2 rows and 8 columns, totaling 16 bits. (0≤i0<2 and 0≤j1<8). That is, each 16x16 input matrix is ​​interleaved and shuffled according to the interleaving rules shown in Figure 23 to obtain a 16x16 output matrix. In Figure 23, the element in the m-th row and n-th column (0≤m<16 and 0≤n<16) of the 16x16 matrix is ​​(a,b), indicating that the bit in the m-th row and n-th column of the output matrix after interleaving comes from the bit in the a-th row and b-th column of the input matrix. For example, if the element in the 1-th row and 0-th column of Figure 23 is (14,15), then the bit in the 1-th row and 0-th column of the output matrix after interleaving comes from the bit in the 14-th row and 15-th column of the input matrix. More specifically, the bit block after interleaving... The bit in row 1, column 0 comes from the bit block. The bits in the 14th row and 15th column. In some specific applications, square matrices... The bit stream, consisting of 256 bits in 16 rows and 16 columns, is continuous in the interleaved output bit stream within the square matrix.

[0259] The bit block pattern in the ninth bit set is described below. Figure 24 is a schematic diagram of a ninth bit pattern in an embodiment of this application.

[0260] For the case where 0 ≤ i0 < 2 and 0 ≤ j1 < 8: the corresponding 16 bit blocks The bit pattern uses the ninth bit pattern. As an example, the ninth bit pattern is shown in Figure 24, where the bits marked with the number "0" come from the bits in the third bit set that have not been processed by PCS or from the parity bits of FEC encoding, and serve as the symbol bits in the symbol map; the bits marked with the number "1" come from the bits in the second bit set that have been processed by PCS, and serve as the amplitude bits in the symbol map.

[0261] Bits that have undergone intra-matrix interleaving are then interleaved between matrices to improve overall burst resistance. The inter-matrix interleaving operation is described below.

[0262] Figure 25 is a schematic diagram of an embodiment of interleaving between square matrices in this application. As shown in Figure 25, the interleaving between square matrices includes an 84-row, 8-column interleaving buffer M, with each row containing 8 square matrices, and each square matrice containing 16 rows and 16 columns, totaling 256 bits. That is, the interleaving buffer M contains a total of 84 × 16 = 1344 bits in rows and 8 × 16 = 128 bits in columns. Figure 26 is a schematic diagram of the bit set after interleaving between square matrices in this application. As shown in Figure 26, the 84-row, 8-column bit block in the interleaving buffer M. A schematic diagram of (0≤i1<84 and 0≤j1<8).

[0263] The interleaving buffer size for inter-matrix interleaving is 84×8×256=172032 bits. Among them, the output packets of inter-matrix interleaving from the sixth bit stream 2i are located in the even rows of the interleaving buffer M, and the output packets of inter-matrix interleaving from the sixth bit stream 2i+1 are located in the odd rows of the interleaving buffer M.

[0264] The following introduces bit blocks. The pattern. For 0≤i1<84 and 0≤j1<8: the corresponding 672 bit blocks. The bit pattern uses the ninth bit pattern. As an example, the ninth bit pattern is shown in Figure 24, where the bits marked with the number "0" come from the bits in the third bit set that have not been processed by PCS or from the parity bits of FEC encoding, and serve as the symbol bits in the symbol map; the bits marked with the number "1" come from the bits in the second bit set that have been processed by PCS, and serve as the amplitude bits in the symbol map.

[0265] The interleaving buffer M, which is interleaved between square matrices, can be divided into 4 sets, as shown in Figure 25. Set 0 contains a total of 21 × 16 × 128 = 43008 bits of square matrices in rows 0, 2, 4, ..., 40 of interleaving buffer M. Set 1 contains a total of 43008 bits of square matrices in rows 1, 3, 5, ..., 41 of interleaving buffer M. Set 2 contains a total of 43008 bits of square matrices in rows 42, 44, 46, ..., 82 of interleaving buffer M. Set 3 contains a total of 43008 bits of square matrices in rows 43, 45, 47, ..., 83 of interleaving buffer M.

[0266] Bits in each column are read from the interleaved buffer M in 8-bit granularity, polling each set in turn. After reading all bits in each column, the next column is read. First, the first group of 8 bits is read from set 0 from top to bottom. Then, the first 8 bits are read from sets 1, 2, and 3 respectively from top to bottom, for a total of 32 bits per cycle. Next, the next cycle reads the next group of 8 bits from sets 0, 1, 2, and 3 respectively from top to bottom, for a total of 32 bits. After a total of 42 cycles, the current column of 1344 bits is read. The specific operation for reading bits from each column from each set is as follows:

[0267] First, read 8 bits sequentially from top to bottom from the 0th row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0268] Read 8 bits sequentially from top to bottom from the first row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0269] Read 8 bits sequentially from top to bottom from the 42nd row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0270] Read 8 bits sequentially from top to bottom from the 43rd row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0271] Then, read 8 bits sequentially from top to bottom from the 0th row of the interleaved buffer M (the 8th to 15th bit row of the matrix).

[0272] Read 8 bits sequentially from top to bottom from the first row of the interleaved buffer M (row 8-15 of the matrix).

[0273] Read 8 bits sequentially from top to bottom from the 42nd row of the interleaved buffer M (row 8-15 in the matrix).

[0274] Read 8 bits sequentially from top to bottom from the 43rd row of the interleaved buffer M (row 8-15 in the matrix).

[0275] Then, read 8 bits sequentially from top to bottom from the second row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0276] …, until all 1344 bits in the current bit column of the interleaved buffer M have been completely read out.

[0277] Next, similarly, the same operation is performed to completely read out all 1344 bits in the next column of bit arrays in interleaving buffer M, until all 1344 bits in the last column of bit arrays in interleaving buffer M are completely read out. At this point, all 172032 bits in interleaving buffer M have been read out. The 172032 bits read out from interleaving buffer M are the output of the third interleaving, i.e., the seventh bit set. It should be understood that interleaving buffer M has a total of 128 column bits.

[0278] It should be noted that the bit stream output from the third interleaving (including intra-array and inter-array interleaving) is merged to obtain the fourth bit data. This fourth bit data is then subjected to symbol mapping and polarization partitioning to obtain dual-polarization symbols. Specifically, a total of L bit streams output from the third interleaving are grouped into S = 16 bits each, and then merged in a round-robin fashion. Symbol mapping is then performed: the 16 bits output from third interleaving 0 are mapped to one dual-polarization modulation symbol, followed by the 16 bits output from third interleaving 1, and so on, up to the 16 bits output from third interleaving L-1. The interleaving buffer used in the inter-array interleaving of the third interleaving contains 172032 bits, meaning the interleaving granularity is 172032 bits. These 172032 bits are mapped to 172032 / 16 = 10752 DP-256QAM symbols. In other words, the output of the third interleaving is the seventh bit set, and a total of 172,032 bits are mapped to 172,032 / 16 = 10,752 DP-256QAM symbols.

[0279] It should be noted that the above description of the first to ninth bit patterns only distinguishes between two types of bits: sign bits and amplitude bits, labeled with the numbers "0" and "1" respectively. Furthermore, the description of a specific bit pattern needs to distinguish between four types of bits: the first type of amplitude bits, the second type of amplitude bits, and the third type of amplitude bits within the sign bits and amplitude bits. This means it requires describing the 16 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b...) mapped to a DP-256QAM symbol. 10 ,b 11 ,b 12 ,b 13 ,b 14 ,b 15 The symbol bits, first type amplitude bits, second type amplitude bits, and third type amplitude bits in the () are distinguished.

[0280] More specifically, the number "0" is used to label the symbol bits in the DP-256QAM symbol; the number "1" is used to label the first type of amplitude bits in the DP-256QAM symbol; the number "2" is used to label the second type of amplitude bits in the DP-256QAM symbol; and the number "3" is used to label the third type of amplitude bits in the DP-256QAM symbol. Further, for the first symbol mapping scheme, the number "0" is used to label bits b0, b1, b8, and b9; and the number "1" is used to label bits b2, b3, b4, b5, b6, b7, b8, b9, b9, b1 ... 10 and b 11 Labeling; using the number "2" to pair bits b4, b5, b 12 and b 13 Label; use the number "3" to pair bits b6, b7, b 14 and b 15 The bits are labeled. Bits labeled with the number "0" come from the third bit set that has not been processed by PCS or from the parity bits encoded by FEC. Bits labeled with the numbers "1", "2" and "3" come from the second bit set that has been processed by PCS.

[0281] The following description, based on the inter-matrix interleaving implementation shown in Figure 25, takes the differentiation of symbol bits, first type amplitude bits, second type amplitude bits, and third type amplitude bits mapped to a DP-256QAM symbol as an example to introduce the first to ninth bit patterns. Figure 27 is a schematic diagram of another first bit pattern in an embodiment of this application; Figure 28(a) is a schematic diagram of another second bit pattern in an embodiment of this application; Figure 28(b) is a schematic diagram of another second bit pattern in an embodiment of this application; Figure 29 is a schematic diagram of another third bit pattern in an embodiment of this application; Figure 30 is a schematic diagram of another fourth bit pattern in an embodiment of this application; Figure 31 is a schematic diagram of another fifth bit pattern in an embodiment of this application; Figure 32 is a schematic diagram of another sixth bit pattern in an embodiment of this application; Figure 33 is a schematic diagram of another eighth bit pattern in an embodiment of this application; and Figure 34 is a schematic diagram of another ninth bit pattern in an embodiment of this application.

[0282] The first bit pattern adopts the bit distribution pattern shown in Figure 27, which contains a 16-row, 16-column bit block containing a total of 64 bits labeled with the number "0", 64 bits labeled with the number "1", 64 bits labeled with the number "2", and 64 bits labeled with the number "3".

[0283] In some specific embodiments, the second bit pattern adopts the bit distribution pattern shown in Figure 28(a), which contains a 16-row, 16-column bit block containing 48 bits labeled with the number "0", 68 bits labeled with the number "1", 64 bits labeled with the number "2", and 76 bits labeled with the number "3". In other specific embodiments, the second bit pattern adopts the bit distribution pattern shown in Figure 28(b), which contains a 16-row, 16-column bit block containing 48 bits labeled with the number "0", 68 bits labeled with the number "1", 64 bits labeled with the number "2", and 76 bits labeled with the number "3".

[0284] The third bit pattern adopts the bit distribution pattern shown in Figure 29. It contains a 16-row, 16-column bit block, which contains 0 bits labeled with the number "0", 84 bits labeled with the number "1", 92 bits labeled with the number "2", and 80 bits labeled with the number "3".

[0285] The fourth bit pattern adopts the bit distribution pattern shown in Figure 30. It contains a 16-row, 16-column bit block, which contains 0 bits labeled with the number "0", 84 bits labeled with the number "1", 84 bits labeled with the number "2", and 80 bits labeled with the number "3".

[0286] The fifth bit pattern adopts the bit distribution pattern shown in Figure 31. It contains a 16-row, 15-column bit block, which includes 0 bits labeled with the number "0", 84 bits labeled with the number "1", 80 bits labeled with the number "2", and 76 bits labeled with the number "3".

[0287] The sixth bit pattern adopts the bit distribution pattern shown in Figure 32. It contains a 16-row, 16-column bit block, which includes 16 bits labeled with the number "0", 84 bits labeled with the number "1", 80 bits labeled with the number "2", and 76 bits labeled with the number "3".

[0288] The seventh bit pattern adopts the bit distribution pattern shown in Figure 18(b), which contains a 16-row, 16-column bit block containing a total of 256 bits labeled with the number "0", 0 bits labeled with the number "1", 0 bits labeled with the number "2", and 0 bits labeled with the number "3".

[0289] The eighth bit pattern adopts the bit distribution pattern shown in Figure 33. It contains a 16-row, 16-column bit block, which contains 64 bits labeled with the number "0", 64 bits labeled with the number "1", 64 bits labeled with the number "2", and 64 bits labeled with the number "3".

[0290] The ninth bit pattern adopts the bit distribution pattern shown in Figure 34. It contains a 16-row, 16-column bit block, which includes 64 bits labeled with the number "0", 64 bits labeled with the number "1", 64 bits labeled with the number "2", and 64 bits labeled with the number "3".

[0291] It should be noted that the above descriptions of the operations for the second data subprocessing i (i = 0, 1, ..., L-1) are based on the first symbol mapping scheme. The following descriptions of the first to twenty-fourth bit patterns when using the second symbol mapping scheme will be presented separately.

[0292] 1) When distinguishing between two types of bits (sign bits and amplitude bits):

[0293] The bit pattern is distributed in r rows and c columns, where r rows and c columns can be 16 rows and 16 columns, or 16 rows and 15 columns. The part in the bit pattern marked with the number "0" at the r-th row and c-th column indicates that the bit at the r-th row and c-th column in the corresponding bit block is used as b0, b4, b8, or b in the symbol mapping (also called modulation). 12 The bit, which comes from the third bit set without PCS processing or from the parity bit of FEC encoding; the part in the bit pattern marked with the number "1" in the r-th row and c-th column indicates that the bit in the r-th row and c-th column of the corresponding bit block is used as b1, b2, b3, b5, b6, b7, b9, b in the symbol mapping (also known as modulation). 10 b 11 b 13 b 14 or b 15 The bit comes from the second set of bits processed by PCS.

[0294] Figure 35 is a schematic diagram of another first bit pattern in an embodiment of this application; Figure 36 is a schematic diagram of another second bit pattern in an embodiment of this application; Figure 37 is a schematic diagram of another eighth bit pattern in an embodiment of this application; Figure 38 is a schematic diagram of another ninth bit pattern in an embodiment of this application.

[0295] The first bit pattern adopts the bit distribution pattern shown in Figure 35, which contains a 16-row, 16-column bit block containing 64 bits marked with the number "0" and 192 bits marked with the number "1".

[0296] In some specific embodiments, the second bit pattern adopts the bit distribution pattern shown in Figure 36, which contains a 16-row, 16-column bit block containing 48 bits labeled with the number "0" and 208 bits labeled with the number "1". In other specific embodiments, the second bit pattern adopts the bit distribution pattern shown in Figure 12(b).

[0297] The third bit pattern adopts the bit distribution pattern shown in Figure 13, the fourth bit pattern adopts the bit distribution pattern shown in Figure 13, the fifth bit pattern adopts the bit distribution pattern shown in Figure 14, the sixth bit pattern adopts the bit distribution pattern shown in Figure 18(a), and the seventh bit pattern adopts the bit distribution pattern shown in Figure 18(b).

[0298] The eighth bit pattern adopts the bit distribution pattern shown in Figure 37, which contains a 16-row, 16-column bit block containing 64 bits marked with the number "0" and 192 bits marked with the number "1".

[0299] The ninth bit pattern adopts the bit distribution pattern shown in Figure 38, which contains a 16-row, 16-column bit block containing 64 bits marked with the number "0" and 192 bits marked with the number "1".

[0300] 2) When distinguishing between four types of bits (sign bit, first type amplitude bit, second type amplitude bit, and third type amplitude bit):

[0301] The symbol bits in the DP-256QAM symbol are labeled with the number "0"; the first type of amplitude bits in the DP-256QAM symbol are labeled with the number "1"; the second type of amplitude bits in the DP-256QAM symbol are labeled with the number "2"; and the third type of amplitude bits in the DP-256QAM symbol are labeled with the number "3". Furthermore, for the second symbol mapping scheme, the number "0" is used to label bits b0, b4, b8, and b... 12 Label; use the number "1" to pair bits b1, b5, b9, and b 13 Labeling; using the number "2" to pair bits b2, b6, b 10 and b 14 Label; use the number "3" to pair bits b3, b7, b 11 and b 15 The bits are labeled. Bits labeled with the number "0" come from the third bit set that has not been processed by PCS or from the parity bits encoded by FEC. Bits labeled with the numbers "1", "2" and "3" come from the second bit set that has been processed by PCS.

[0302] Figure 39 is a schematic diagram of another first bit pattern in an embodiment of this application; Figure 40(a) is a schematic diagram of another second bit pattern in an embodiment of this application; Figure 40(b) is a schematic diagram of another second bit pattern in an embodiment of this application; Figure 41 is a schematic diagram of another third bit pattern in an embodiment of this application; Figure 42 is a schematic diagram of another fourth bit pattern in an embodiment of this application; Figure 43 is a schematic diagram of another fifth bit pattern in an embodiment of this application; Figure 44 is a schematic diagram of another sixth bit pattern in an embodiment of this application; Figure 45 is a schematic diagram of another eighth bit pattern in an embodiment of this application; Figure 46 is a schematic diagram of another ninth bit pattern in an embodiment of this application.

[0303] The first bit pattern adopts the bit distribution pattern shown in Figure 39, which contains a 16-row, 16-column bit block containing a total of 64 bits labeled with the number "0", 64 bits labeled with the number "1", 64 bits labeled with the number "2", and 64 bits labeled with the number "3".

[0304] In some specific embodiments, the second bit pattern adopts the bit distribution pattern shown in Figure 40(a), which includes a 16-row, 16-column bit block containing 48 bits labeled with the number "0", 72 bits labeled with the number "1", 64 bits labeled with the number "2", and 72 bits labeled with the number "3". In other specific embodiments, the second bit pattern adopts the bit distribution pattern shown in Figure 40(b), which includes a 16-row, 16-column bit block containing 48 bits labeled with the number "0", 72 bits labeled with the number "1", 64 bits labeled with the number "2", and 72 bits labeled with the number "3".

[0305] The third bit pattern adopts the bit distribution pattern shown in Figure 41. It contains a 16-row, 16-column bit block, which includes 0 bits labeled with the number "0", 80 bits labeled with the number "1", 96 bits labeled with the number "2", and 80 bits labeled with the number "3".

[0306] The fourth bit pattern adopts the bit distribution pattern shown in Figure 42. It contains a 16-row, 16-column bit block, which contains 0 bits labeled with the number "0", 88 bits labeled with the number "1", 80 bits labeled with the number "2", and 88 bits labeled with the number "3".

[0307] The fifth bit pattern adopts the bit distribution pattern shown in Figure 43. It contains a 16-row, 15-column bit block, which contains 0 bits labeled with the number "0", 80 bits labeled with the number "1", 80 bits labeled with the number "2", and 80 bits labeled with the number "3".

[0308] The sixth bit pattern adopts the bit distribution pattern shown in Figure 44. It contains a 16-row, 16-column bit block, which includes 16 bits labeled with the number "0", 80 bits labeled with the number "1", 80 bits labeled with the number "2", and 80 bits labeled with the number "3".

[0309] The seventh bit pattern adopts the bit distribution pattern shown in Figure 18(b), which contains a 16-row, 16-column bit block containing a total of 256 bits labeled with the number "0", 0 bits labeled with the number "1", 0 bits labeled with the number "2", and 0 bits labeled with the number "3".

[0310] The eighth bit pattern adopts the bit distribution pattern shown in Figure 45. It contains a 16-row, 16-column bit block, which contains 64 bits labeled with the number "0", 64 bits labeled with the number "1", 64 bits labeled with the number "2", and 64 bits labeled with the number "3".

[0311] The ninth bit pattern adopts the bit distribution pattern shown in Figure 46, which contains a 16-row, 16-column bit block containing 64 bits labeled with the number "0", 64 bits labeled with the number "1", 64 bits labeled with the number "2", and 64 bits labeled with the number "3".

[0312] The following are some specific implementation examples based on the above introduction to the second data processing.

[0313] Example 1:

[0314] Figure 47 is a schematic diagram of an application scenario of the second data processing in the embodiments of this application. As shown in Figure 47, considering the second data processing L=2, it includes 2 PCS processing and the first interleaving, namely "PCS processing and first interleaving 0" and "PCS processing and first interleaving 1", and the PCS processing and the first interleaving are specifically adopted in the manner shown in Figure 6(c).

[0315] In some applications, PCS processing, the first interleaving, and the fourth interleaving can be combined to form a Probabilistic Constellation Shaper, as shown in the shaded area of ​​the grid in Figure 37. In some applications, the input processing granularity of FEC coding is K = 3552 bits, and the corresponding output granularity is N = 4096 bits. Using an extended BCH (256, 239) with 15.3% coding redundancy, the FEC coding and the fifth interleaving can be combined to form OFEC coding, as shown in the shaded area of ​​the diagonal line in Figure 47.

[0316] Example 2:

[0317] Considering k0=2, the fifth bit set, which is distributed as a 2-row, 8-column bit block in the second bit stream, is sent to the fourth interleaving to obtain the eighth bit set.

[0318] Figure 48(a) is a schematic diagram of a bit distribution in the last 71 bits of the fifth bit set in an embodiment of this application. As an example, for 0 ≤ i0 < 2, the bit block in the i0th row and j1th column of the fifth bit set... The pattern of the last 7 bits in the set is shown in Figure 48(a), where these bits are all amplitude bits; the bit block in row i0 and column j1 = 4, 5, 6 and 7 of the fifth bit set. and The pattern of bits in the diagram is shown in Figure 48(a), i.e. and All bits in the data are amplitude bits. The first 15 bits in the sequence are all amplitude bits and The last column of bits in the table all come from the FEC check bits (i.e., all are sign bits). All the bits in the data come from the FEC check bits (i.e., all are sign bits).

[0319] Figure 48(b) is a schematic diagram of the bit distribution of the last 71 bits in the eighth bit set in an embodiment of this application. The bits of the last 71 bits in the fifth bit set are fed into the fourth interleaving to obtain the bits of the last 71 bits in the eighth bit set as shown in Figure 48(b).

[0320] In the eighth bit set, for 0 ≤ i0 < 2 and j1 = 3, the bit block The distribution pattern of the last 7 bit columns, i.e., the bit columns r0 = 9, 10, 11, 12, 13, 14, and 15, is shown in the 9th, 10th, 11th, 12th, 13th, 14th, and 15th bit columns in Figure 11; when j1 = 4, 5, 6, and 7, the bit block... and The distribution patterns are shown in Figure 11.

[0321] Example 3:

[0322] Figure 49 shows the third bit of data d. scr Mapping distribution to N PCS+FEC A schematic diagram illustrating the details of a "PCS+FEC" module. As an example, consider k0 = 2. As shown in Figure 49, the third bit data d... scr It contains 168 "PCS+FEC" modules, each containing 8384 bits, i.e., d scr =168 × 8384 = 1408512. Considering the second data processing L = 2, each "PCS+FEC" module contains 4 "PCS sub-processing + FEC" modules, and each "PCS sub-processing + FEC" module contains 2096 bits, then the third bit data d scr It contains a total of 4 × 168 = 672 "PCS subprocessing + FEC" modules. (The last part, "d", appears to be a typo and can be omitted.) scr The 0th of the 8384 bits is distributed in a round-robin fashion to each "PCS subprocessing + FEC" module within the 0th "PCS+FEC" module, with a granularity of 1 bit. scr The first 8384 bits of the total number of bits are distributed in a round-robin fashion to each "PCS subprocessing + FEC" module within the first "PCS+FEC" module, with a granularity of 1 bit, ..., until d is distributed. scr The 167th of the 8384 bits is distributed in a round-robin fashion to each "PCS subprocessing + FEC" module in the 167th "PCS+FEC" module with a granularity of 1 bit.

[0323] In the 672 "PCS sub-processing + FEC" modules, a portion of the bits in each "PCS sub-processing + FEC" module, after PCS sub-processing, together with the remaining unprocessed bits, constitute a "Pre-FEC module," resulting in a total of 672 "Pre-FEC modules." More specifically, each "PCS sub-processing + FEC" module contains 2 × 808 PCS-processed bits and 480 unprocessed bits. The PCS sub-processing is performed as shown in Figure 6(f), where every 808 bits undergoes PCS sub-processing to obtain 1536 bits, meaning each "Pre-FEC module" contains a total of 2 × 1536 + 480 = 3552 bits.

[0324] It should be noted that, as shown in Figure 25, the inter-matrix interleaving in the second data sub-processing i (i = 0, 1, ..., L-1) is performed with an 8-bit granularity from the interleaving buffer M, using a round-robin approach to read bits from each column of each set. In other application scenarios, the inter-matrix interleaving in the second data sub-processing i is performed with a 16-bit granularity from the interleaving buffer M, using a round-robin approach to read bits from each column of each set. The following description uses the 16-bit granularity approach of round-robin reading of bits from each column of each set from the interleaving buffer M as an example.

[0325] Figure 50 is a schematic diagram of another embodiment of interleaving between square matrices in this application. As shown in Figure 50, the first group of 16 bits is read from top to bottom from set 0. Then, the first 16 bits are read from top to bottom from sets 1, 2, and 3 respectively, for a total of 64 bits read in one loop. Next, the next loop reads the next group of 16 bits from top to bottom from sets 0, 1, 2, and 3 respectively, for a total of 64 bits read. After a total of 21 loops, the current column of 1344 bits is read out. The specific operation for reading bits from each column from each set is as follows:

[0326] First, read 16 bits sequentially from top to bottom from the 0th row of the interleaved buffer M (the 0th to 15th bit row of the matrix).

[0327] Read 16 bits sequentially from top to bottom from the first row of the interleaved buffer M (the row containing bits 0-15 in the matrix).

[0328] Read 16 bits sequentially from top to bottom from the 42nd row of the interleaved buffer M (row 0-15 of the matrix).

[0329] Read 16 bits sequentially from top to bottom from the 43rd row of the interleaved buffer M (row 0-15 of the matrix).

[0330] Then, 16 bits are read sequentially from top to bottom from the second row of the interleaved buffer M (the 0th to 15th bit row of the matrix).

[0331] Read 16 bits sequentially from top to bottom from the third row of the interleaved buffer M (row 0-15 of the matrix).

[0332] Read 16 bits sequentially from top to bottom from the 44th row of the interleaved buffer M (row 0-15 of the matrix).

[0333] Read 16 bits sequentially from top to bottom from the 45th row of the interleaved buffer M (the 0th to 15th bit row in the matrix).

[0334] Then, read 16 bits sequentially from top to bottom from the 4th row of the interleaved buffer M (the 0th to 15th bit row of the matrix).

[0335] …, until all 1344 bits in the current bit column of the interleaved buffer M have been completely read out.

[0336] Next, similarly, the same operation is performed to completely read out all 1344 bits in the next column of bit arrays in interleaving buffer M, until all 1344 bits in the last column of bit arrays in interleaving buffer M are completely read out. At this point, all 172032 bits in interleaving buffer M have been read out. The 172032 bits read out from interleaving buffer M are the output of the third interleaving, i.e., the seventh bit set. It should be understood that interleaving buffer M has a total of 128 column bits.

[0337] The following describes the implementation of inter-matrix interleaving based on Figure 50. Taking the second data subprocessing i (i = 0, 1, ..., L-1, where L is an integer greater than 0) as an example, it uses inter-matrix interleaving to read bits from each column of each set in 16-bit granularity from the interleaving buffer M, and iteratively reads bits from each set. The first to ninth bit patterns are described below. It should be noted that the pattern obtained by using inter-matrix interleaving to read bits from each column of each set in 16-bit granularity from the interleaving buffer M is the same as the pattern obtained by using inter-matrix interleaving to read bits from each column of each set in 8-bit granularity from the interleaving buffer M.

[0338] More specifically, taking the first symbol mapping as an example, when considering the distinction between the symbol bit, the first amplitude bit, the second amplitude bit, and the third amplitude bit, the first bit pattern adopts the bit distribution pattern shown in Figure 27, the second bit pattern adopts the bit distribution pattern shown in Figure 28(a) or Figure 28(b), the third bit pattern adopts the bit distribution pattern shown in Figure 29, the fourth bit pattern adopts the bit distribution pattern shown in Figure 30, the fifth bit pattern adopts the bit distribution pattern shown in Figure 31, the sixth bit pattern adopts the bit distribution pattern shown in Figure 32, the seventh bit pattern adopts the bit distribution pattern shown in Figure 18(b), the eighth bit pattern adopts the bit distribution pattern shown in Figure 33, and the ninth bit pattern adopts the bit distribution pattern shown in Figure 34.

[0339] Taking the second symbol mapping as an example, when considering the distinction between the symbol bit, the first amplitude bit, the second amplitude bit, and the third amplitude bit, the first bit pattern adopts the bit distribution pattern shown in Figure 39, the second bit pattern adopts the bit distribution pattern shown in Figure 40(a) or Figure 40(b), the third bit pattern adopts the bit distribution pattern shown in Figure 41, the fourth bit pattern adopts the bit distribution pattern shown in Figure 42, the fifth bit pattern adopts the bit distribution pattern shown in Figure 43, the sixth bit pattern adopts the bit distribution pattern shown in Figure 44, the seventh bit pattern adopts the bit distribution pattern shown in Figure 18(b), the eighth bit pattern adopts the bit distribution pattern shown in Figure 45, and the ninth bit pattern adopts the bit distribution pattern shown in Figure 46.

[0340] The following are some specific implementation examples based on the above introduction to the second data processing.

[0341] Example 4:

[0342] Figure 51 is a schematic diagram of an application scenario of the second data processing in the embodiments of this application. As shown in Figure 51, considering the second data processing L=4, it includes a total of 4 PCS processing and first interleaving, namely "PCS processing and first interleaving 0", "PCS processing and first interleaving 1", "PCS processing and first interleaving 2" and "PCS processing and first interleaving 3", and the PCS processing and first interleaving are specifically adopted in the manner shown in Figure 6(c).

[0343] In some applications, PCS processing, the first interleaving, and the fourth interleaving can be combined to form a Probabilistic Constellation Shaper, as shown in the shaded area of ​​the grid in Figure 51. In some applications, the input processing granularity of FEC coding is K = 3552 bits, and the corresponding output granularity is N = 4096 bits. Using an extended BCH (256, 239) with a coding redundancy of 15.3%, the FEC coding and the fifth interleaving can be combined to form OFEC coding, as shown in the shaded area of ​​the diagonal line in Figure 51.

[0344] Figure 53 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 53, the data processing device includes: a PCS unit 101, a first interleaving unit 102, an FEC encoding unit 103, a second interleaving unit 104, and a third interleaving unit 105. The PCS unit 101 is specifically used to perform the PCS processing operation in the above embodiment. The first interleaving unit 102 is specifically used to perform the first interleaving operation in the above embodiment. The FEC encoding unit 103 is specifically used to perform the FEC encoding operation in the above embodiment. The second interleaving unit 104 is specifically used to perform the second interleaving operation in the above embodiment. The third interleaving unit 105 is specifically used to perform the third interleaving operation in the above embodiment. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The integrated units described above can be implemented in either hardware or software functional units.

[0345] Figure 54 is a schematic diagram of an optical module structure in an embodiment of this application. As shown in Figure 54, the optical module includes a processor 201 and an interface 202. The processor 201 is used to perform the first data processing, second data processing, and third data processing operations described in the above embodiments. In one possible implementation, the processor 201 includes the PCS unit 101, first interleaving unit 102, FEC encoding unit 103, second interleaving unit 104, and third interleaving unit 105 shown in Figure 53. The interface 202 can be a transceiver or an input / output interface. The interface 202 is used to receive signals from other devices and transmit them to the processor 201 or to send signals from the processor 201 to other devices. As an example, after performing the first, second, and third data processing described above, the processor 201 obtains a dual-polarization symbol sequence and sends the dual-polarization symbol sequence through the interface 202. In this example, the interface 202 can specifically refer to an electrical interface. As another example, after the processor 201 performs the first, second, and third data processing steps described above to obtain a dual-polarization symbol sequence, the modulator in the optical module performs electro-optic conversion and other signal processing based on the dual-polarization symbol sequence to obtain an optical signal, which is then transmitted through interface 202. In this example, interface 202 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 203, which is used to store program instructions and data.

[0346] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0347] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0348] Figure 55 is a schematic diagram of a transmitting device in an embodiment of this application. As shown in Figure 55, the transmitting device includes a host-side device 301 and an optical module 302. The host-side device 301 is used to send data to the optical module 302, and the optical module 302 generates an optical signal based on the data sent by the host-side device 301 and transmits the optical signal through a channel. For example, the host-side device may specifically be a switch, router, or server. The transmitting device can be a communication device including the host-side device 301 and the optical module 302. It should also be understood that the transmitting device in the embodiments of this application is named based on the data flow direction and does not limit the function of the device. For example, the transmitting device may also have a receiving function.

[0349] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor performs the first data processing, second data processing, and third data processing operations described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0350] This application also provides a chip. The chip integrates circuitry for implementing the functions of the processor 201 described above, and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0351] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0352] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0353] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0354] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0355] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0356] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0357] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0358] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0359] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: The first set of bits from a plurality of bits is subjected to probabilistic constellation shaping (PCS) to obtain the second set of bits. The second bit set and the third bit set (excluding the first bit set) of the plurality of bits are first interleaved to obtain two fourth bit sets; The two sets of fourth bits are respectively subjected to forward error correction (FEC) encoding to obtain two sets of fifth bits; The two sets of fifth bits are interleaved a second time to obtain two sets of sixth bits; The two sets of sixth bits are interleaved a third time to obtain a set of seventh bits, wherein 4 × Z + 4 consecutive bits in the set of seventh bits are used for mapping to obtain a double polarization symbol, wherein the double polarization symbol includes a first polarization symbol and a second polarization symbol, and Z is an integer greater than or equal to 3; Of the 4×Z+4 bits, 2×Z bits used to map to the first polarization symbol come from the second bit set, and the other 2 bits used to map to the first polarization symbol come from the third bit set or the FEC-encoded check bits.

2. The method according to claim 1, characterized in that, The second bit set includes Z-type bits, wherein each pair of bits in the 2×Z bits of the first polarization symbol is derived from the corresponding class 1 bits in the Z-type bits, and each pair of bits in the 2×Z bits of the second polarization symbol is derived from the corresponding class 1 bits in the Z-type bits.

3. The method according to claim 2, characterized in that, The Z-type bits are arranged in the target order, and the error bit rate of the Z-type bits is increasing.

4. The method according to claim 3, characterized in that, The Z-class bits include the V1-class bits and the V2-class bits arranged in the target order, where 1 ≤ V1 < Z, 1 < V2 ≤ Z, and V1 < V2. The probability of the bit value of the first V1 type bit being 1 is P V1-1 The probability of the bit value of the first V1 type bit being 0 is P V1-0 The probability of the bit value of the first V2 type bit being 1 is P V2-1 The probability of the bit value of the first V2 type bit being 0 is P V2-0 The absolute value of P V1-1 The absolute value of P V1-0 is greater than or equal to P V2-1 The absolute value of P V2-0 .

5. The method according to any one of claims 1 to 4, characterized in that, Z＝3。 6. The method according to any one of claims 2 to 4, characterized in that, The second set of bits includes first type bits, second type bits and third type bits, and the first set of bits includes L PCS first bit subsets, and performing the PCS processing on the first set of bits to obtain the second set of bits includes: For each of the first subset of bits, where k pcs_0 The first PCS subprocess is performed on each bit to obtain n. pcs_0 The first bit; performing a second PCS sub-process on k pcs_1 bits of each of the first subsets of bits to obtain n pcs_1 first bits; For each of the first subset of bits, where k pcs_2 Each bit is processed by the third PCS subprocess to obtain n. pcs_2 The first bit; For the n pcs_0 The first bit, the n pcs_1 The first bit and the n pcs_2 Perform bit mapping on the first bit to obtain n pcs_0 The second bit, n pcs_1 The second bit and n pcs_2 The second bit; Wherein, n pcs_0 The second bit includes the first type of bit, the n pcs_1 The second bit includes the second type of bit, the n pcs_2 The second bit includes the third type of bit, k pcs_0 k pcs_1 and k pcs_2 All are integers greater than or equal to 1, n pcs_0 >k pcs_0 n pcs_1 >k pcs_1 n pcs_2 >k pcs_2 n pcs_0 =n pcs_1 =n pcs_2 .

7. The method according to claim 6, characterized in that, For the n pcs_0 The first bit, the n pcs_1 The first bit and the n pcs_2 Perform bit mapping on the first bit to obtain n pcs_0 The second bit, n pcs_1 The second bit and n pcs_2 The second bit includes: Obtain the n pcs_0 Bit a in the first bit, the n pcs_1 Bit b in the first bit and n pcs_2 Bit c from the first bit, bit a, bit b, and bit c are bit mapped to obtain bit a, bit a∧b, and bit b∧c, and n pcs_0 The second bit includes bit a, and the n pcs_1 The second bit includes the bit a∧b, and the n pcs_2 The second bit includes the bit b∧c, where ∧ represents the XOR operation.

8. The method according to claim 6 or 7, characterized in that, The n pcs_0 The probability P that the first bit is 1 cs0-1 The probability P of a bit being 0 cs0-0 P cs0-0 +P cs0-1 =1; the n pcs_1 The probability P that the first bit is 1 cs1-1 The probability P of a bit being 0 cs1-0 P cs1-0 +P cs1-1 =1; the n pcs_2 The probability P that the first bit is 1 cs2-1 The probability P of a bit being 0 cs2-0 P cs2-0 +P cs2-1 =1.

9. The method according to claim 8, characterized in that, k pcs_0 <k pcs_1 <k pcs_2 P cs0-1 >P cs1-1 >P cs2-1 P cs0-0 <P cs1-0 <P cs2-0 Or, k pcs_0 =k pcs_1 =k pcs_2 P cs0-1 =P cs1-1 =P cs2-1 P cs0-0 =P cs1-0 =P cs2-0 .

10. The method according to any one of claims 1 to 9, characterized in that, Of the 4×Z+4 bits, the 2×Z+2 bits in even positions are used to map to the first polarization symbol, and the 2×Z+2 bits in odd positions are used to map to the second polarization symbol.

11. The method according to claim 5, characterized in that, Bits 0, 2, 4, and 6 of the 16 bits are used to map to the first component of the first polarization symbol; bits 8, 10, 12, and 14 of the 16 bits are used to map to the second component of the first polarization symbol; bits 1, 3, 5, and 7 of the 16 bits are used to map to the first component of the second polarization symbol; and bits 9, 11, 13, and 15 of the 16 bits are used to map to the second component of the second polarization symbol.

12. The method according to claim 11, characterized in that, The second set of bits includes a first type of bit, a second type of bit, and a third type of bit. The 2nd, 3rd, 10th, and 11th bits are from the first type of bit, the 4th, 5th, 12th, and 13th bits are from the second type of bit, and the 6th, 7th, 14th, and 15th bits are from the third type of bit.

13. The method according to any one of claims 1 to 9, characterized in that, Of the 4×Z+4 bits, the first half (2×Z+2 bits) is used to map to the first polarization symbol, and the second half (2×Z+2 bits) is used to map to the second polarization symbol.

14. The method according to claim 5, characterized in that, Bits 0, 1, 2, and 3 of the 16 bits are used to map to the first component of the first polarization symbol; bits 4, 5, 6, and 7 of the 16 bits are used to map to the second component of the first polarization symbol; bits 8, 9, 10, and 11 of the 16 bits are used to map to the first component of the second polarization symbol; and bits 12, 13, 14, and 15 of the 16 bits are used to map to the second component of the second polarization symbol.

15. The method according to claim 14, characterized in that, The second set of bits includes a first type of bit, a second type of bit, and a third type of bit, wherein the 1st bit, the 5th bit, the 9th bit, and the 13th bit are from the first type of bit, the 2nd bit, the 6th bit, the 10th bit, and the 14th bit are from the second type of bit, and the 3rd bit, the 7th bit, the 11th bit, and the 15th bit are from the third type of bit.

16. The method according to claim 11 or 14, characterized in that, The polarization direction of the first polarization symbol is orthogonal to the deflection direction of the second polarization symbol; The first component is an I-channel component, and the second component is a Q-channel component; or, the first component is a Q-channel component, and the second component is an I-channel component.

17. The method according to any one of claims 1 to 16, characterized in that, Of the 16 bits, the 8 even-numbered bits are mapped to the first polarization symbol, and the 8 odd-numbered bits are mapped to the second polarization symbol, Z=3. The second bit set includes first-class bits, second-class bits, and third-class bits. The sixth bit set includes 16 subsets of the second bit set (2 rows, 8 columns). Each subset of the second bit set includes 256 bits (16 rows, 16 columns). The bit distribution pattern of each subset of the second bit set is shown below: In the bit distribution pattern of the second bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

18. The method according to any one of claims 1 to 16, characterized in that, The first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes first-class bits, second-class bits, and third-class bits. The sixth bit set includes 16 subsets of the second bit set (2 rows, 8 columns). Each subset of the second bit set includes 256 bits (16 rows, 16 columns). The bit distribution pattern of each subset of the second bit set is shown below: In the bit distribution pattern of the second bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

19. The method according to any one of claims 1 to 18, characterized in that, Performing a second interleaving on the two sets of fifth bits to obtain two sets of sixth bits includes: The two fifth bit sets are respectively subjected to a fourth interleaving to obtain two eighth bit sets, wherein each eighth bit set 2 includes 16 third bit subsets in 2 rows and 8 columns, and the third bit subsets include 256 bits in 16 rows and 16 columns; The two sets of eighth bits are interleaved a fifth time to obtain the two sets of sixth bits, wherein the fifth interleaving is used to interleave 16 bits in each row of each of the third bit subsets in the sets of eighth bits.

20. The method according to claim 19, characterized in that, Of the 16 bits, the 8 even-numbered bits are mapped to the first polarization symbol, and the 8 odd-numbered bits are mapped to the second polarization symbol, Z=3. The second bit set includes a first type of bit, a second type of bit, and a third type of bit. The bit distribution pattern of each subset of the third bit is shown below: In the bit distribution pattern of the third bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

21. The method according to claim 19, characterized in that, The first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z=3. The second bit set includes first-class bits, second-class bits, and third-class bits, and the bit distribution pattern of each third bit subset is shown below: In the bit distribution pattern of the third bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

22. The method according to any one of claims 1 to 21, characterized in that, Each of the fifth bit sets comprises 16 fourth bit subsets in 2 rows and 8 columns, and each fourth bit subset comprises 256 bits in 16 rows and 16 columns. In the 16 fourth bit subsets in the 2 rows and 8 columns, the bits in the fourth bit subsets from column 0 to column 3 come from the second bit set and the third bit set. The bits in the fourth bit subsets of column 4, column 5, and column 0 to column 14 of the fourth bit subset of column 6 come from the second bit set. The bits in column 15 and column 7 of the fourth bit subset of column 6 are the check bits of the FEC encoding.

23. The method according to claim 22, characterized in that, Of the 16 bits, the 8 even-numbered bits are mapped to the first polarization symbol, and the 8 odd-numbered bits are mapped to the second polarization symbol, Z = 3. The second bit set includes first-class bits, second-class bits, and third-class bits. The bit distribution pattern of the fourth bit subset from column 0 to column 2 in each of the fifth bit sets is shown below: In the bit distribution pattern of the fourth bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

24. The method according to claim 22, characterized in that, The first half of the 16 bits (8 bits) is used to map to the first polarization symbol, and the second half of the 16 bits (8 bits) is used to map to the second polarization symbol, Z = 3. The second bit set includes first-class bits, second-class bits, and third-class bits. The bit distribution pattern of the fourth bit subset from column 0 to column 2 in each of the fifth bit sets is shown below: In the bit distribution pattern of the fourth bit subset, "0" represents a bit from the third bit set or the check bit of the FEC encoding; "1" represents a bit from the first type of bit; "2" represents a bit from the second type of bit; and "3" represents a bit from the third type of bit.

25. The method according to any one of claims 1 to 24, characterized in that, The third interleaving of the two sixth bit sets to obtain the seventh bit set includes: The two sets of sixth bits are interleaved within a square matrix to obtain two sets of ninth bits. Each set of ninth bits includes 16 subsets of fifth bits in 2 rows and 8 columns, and each subset of fifth bits includes 256 bits in 16 rows and 16 columns. The two sets of ninth bits are interleaved to obtain the set of seventh bits, which includes 672 subsets of the fifth bits in 84 rows and 8 columns.

26. The method according to any one of claims 1 to 25, characterized in that, The first bit set includes a first bit set 1 and a first bit set 2. The second bit set is obtained by performing PCS processing on the first bit set from multiple bits, including: The first bit set 1 is subjected to PCS processing to obtain the second bit set 1, and the first bit set 2 is subjected to PCS processing to obtain the second bit set 2, wherein the second bit set includes the second bit set 1 and the second bit set 2.

27. The method according to any one of claims 1 to 26, characterized in that, The amplitude bits mapped to the dual-polarization symbol come from the second bit set, and the symbol bits mapped to the dual-polarization symbol come from the third bit set or the FEC-encoded parity bits.

28. A data processing apparatus, characterized in that, The data processing device includes: a probabilistic constellation shaping (PCS) unit, a first interleaving unit, a forward error correction (FEC) coding unit, a second interleaving unit, and a third interleaving unit; The PCS unit is used to: perform PCS processing on a first set of bits from a plurality of bits to obtain a second set of bits; The first interleaving unit is used to: perform a first interleaving on the second bit set and the third bit set other than the first bit set in the plurality of bits to obtain two fourth bit sets; The FEC encoding unit is used to: perform FEC encoding on the two fourth bit sets respectively to obtain two fifth bit sets; The second interleaving unit is used to: perform a second interleaving on the two sets of fifth bits respectively to obtain two sets of sixth bits; The third interleaving unit is used to: perform a third interleaving on the two sets of sixth bits to obtain a set of seventh bits, wherein 4×Z+4 consecutive bits in the set of seventh bits are used for mapping to obtain a double polarization symbol, the double polarization symbol including a first polarization symbol and a second polarization symbol, and Z is an integer greater than or equal to 3; Of the 4×Z+4 bits, 2×Z bits used to map to the first polarization symbol come from the second bit set, and the other 2 bits used to map to the first polarization symbol come from the third bit set or the FEC-encoded check bits.

29. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 27.

30. An optical module, characterized in that, The optical module includes a processor and an interface, the processor being configured to perform the method as described in any one of claims 1 to 27 and to transmit signals through the interface.

31. The optical module according to claim 30, characterized in that, The processor is used to process the seventh bit set to obtain a dual-polarization symbol sequence, and to send the dual-polarization symbol sequence through the interface.

32. The optical module according to claim 30, characterized in that, The optical module further includes a modulator. The processor is used to process the seventh bit set to obtain a dual-polarization symbol sequence. The modulator is used to perform electro-optic conversion based on the dual-polarization symbol sequence to obtain an optical signal and to send the optical signal through the interface.

33. A transmitting device, characterized in that, The transmitting device includes a host-side device and an optical module as described in any one of claims 30 to 32, wherein the optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

34. A communication system, characterized in that, include: The transmitting device and the receiving device as described in claim 33, wherein the transmitting device is configured to transmit an optical signal to the receiving device.

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