Method for use in a boolean logic computing system for aggregating logic signals

Abstract

A Boolean logic computing system (100, 300, 400, 500, 600) for aggregating input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) is provided. The Boolean logic computing system includes a controller (102). The controller is configured to receive two or more input signals (IN_SIGNAL_1, IN_SIGNAL_n). The two or more input signals being logic signals. A logic signal can take one out of a first value (V1) and a second value (V2). The controller is configured to aggregate the two or more input signals into an output signal (106, 312, 414, 508, 616). The controller is further configured to perform the aggregation by providing the output signal based on the number of input signals taking the first value (V1) and minus the number of input signals taking the second value (V2).

Description

[0001] METHOD FOR USE IN A BOOLEAN LOGIC COMPUTING SYSTEM FOR AGGREGATING LOGIC SIGNALS

[0002] TECHNICAL FIELD

[0003] The disclosure relates to signal processing and more particularly, the disclosure relates to a method for use in a Boolean logic computing system for aggregating logic signals. The disclosure relates to a Boolean logic circuitry for aggregating logic signals. The disclosure also relates to a Boolean logic computing system including a controller configured to aggregate logic signals.

[0004] BACKGROUND

[0005] In computing systems, signal aggregation is a process of combining received signals into a single representative signal. In computing systems, logic signals are physical signals that convey logical information rather than continuous real-valued data. Unlike analog signals, which represent a range of values, the logic signals in the computing systems convey binary information using Boolean logic values of TRUE and FALSE. For example, an existing logic signal aggregation method combines input logic signals into a single output logic signal using the majority logic gate. Each input logic signal represents a binary logic value, which can be either TRUE or FALSE. The majority logic gate is a hardware device that executes the existing logic signal aggregation method. The majority logic gate evaluates the input logic signals to determine whether most of the input logic signals are TRUE or FALSE. If most input logic signals are TRUE, the computing systems set the output logic signal to TRUE. If most input logic signals are FALSE, the computing systems set the output signal to FALSE. The existing logic signal aggregation method is performed through the majority logic gate, leading to unstable and low learning performance in deep learning systems that require a high level of detailed information.

[0006] Existing method for aggregating real-valued signals using arithmetic summation. In computing systems dealing with real- valued signals, an aggregation process is straightforward and may be unnoticeable. This is because adding numbers together is a basic mathematical operation that doesn't involve complex decision-making like in the existing logic signal aggregation method. In hardware circuits, the arithmetic summation for signal aggregation can be implemented using an ADDER gate.

[0007] Therefore, there arises a need to address the aforementioned technical problem / drawbacks of aggregating logic signals.

[0008] SUMMARY

[0009] It is an object of the disclosure to provide a method for use in a Boolean logic computing system for aggregating logic signals. The disclosure relates to Boolean logic circuitry for aggregating logic signals. The disclosure also relates to a Boolean logic computing system including a controller configured to aggregate logic signals while avoiding one or more disadvantages of prior art approaches.

[0010] This object is achieved by the features of the independent claims. Further, implementation forms are apparent from the dependent claims, the description, and the figures.

[0011] According to a first aspect, a method for use in a Boolean logic computing system is provided. The method includes receiving two or more input signals (IN_SIGNAL_1 , IN_SIGNAL_n). The two or more input signals being logic signals. A logic signal can take one out of a first value (VI) and a second value (V2). The method includes aggregating the two or more input signals into an output signal. The aggregation is performed by providing the output signal based on the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

[0012] This method for use in the Boolean logic system can efficiently manage input signals in deep neural networks, especially those designed for logic or deep learning systems. This reduces computational complexity due to the processing of deep neural systems, thereby reducing energy consumption, processing latency, and silicon area of computing chips compared to existing systems. This method of the Boolean logic system is suitable for computing systems that handle logic signals and can adapt to both parallel and serial input signal settings.

[0013] Optionally, the method further includes performing the aggregation by providing the output signal as equalling the number of input signals taking the first value (VI ) minus the number of input signals taking the second value (V2).

[0014] Optionally, the method further includes performing the aggregation by performing a POPCOUNT operation on the two or more input signals and performing a COUNT operation on the two or more input signals. The output signal is provided as equalling the sum of two times the result of the POPCOUNT operation minus the result of the COUNT operation. The POPCOUNT operation counts the number of input signals taking the first value in a time period and the COUNT operation counts the number of input signals in the time period.

[0015] Optionally, the method further includes determining the sum of two times the result of the POPCOUNT operation minus the result of the COUNT operation by multiplying the result of the COUNT operation by -1 and adding the result to two times the POPCOUNT operation.

[0016] Optionally, the method further includes performing the aggregation by performing a first POPCOUNT operation on the two or more input signals, and performing a second POPCOUNT operation on the inverses of the two or more input signals. The output signal is provided as equalling the sum of the result of the first POPCOUNT operation minus the result of the second POPCOUNT operation. The second POPCOUNT operation counts the number of input signals taking the first value in a time period.

[0017] Optionally, the method further includes performing the aggregation by performing a first adding operation on the two or more input signals. The first adding operation adds a 1 for each signal taking the first value (VI), resulting in a first count. The method further includes performing a second adding operation on the inverse of the two or more input signals. The second adding operation adds a 1 for each inverted signal taking the first value (VI), resulting in a second count. The output signal is provided as equalling the sum of the first count minus the result of the second count.

[0018] Optionally, the method further includes weighting each of the two or more input signals with weights (W) prior to performing the first adding operation and weighting each of the inverted two or more input signals with the same weights (W) prior to performing the second adding operation.

[0019] Optionally, the weights are real- valued and the output signal is thus also real- valued.

[0020] Optionally, the method further includes performing the adding operations utilizing an indicator logic gate (1). The indicator logic gate (1 ) applied to a signal output a ‘ 1’ if the input signal takes on the first value (VI ). The weighting of the two or more input signals is performed by multiplying the result of the indicator logic gate with the corresponding weight.

[0021] Optionally, the method is for use in a Deep Learning system.

[0022] According to a second aspect, there is Boolean logic circuitry is provided. The Boolean logic circuitry includes circuitry for receiving two or more input signals (IN_SIGNAL_1 , IN_SIGNAL_n), the two or more input signals being logic signals. A logic signal can take one out of a first value (VI) and a second value (V2). The Boolean logic circuitry includes circuitry for aggregating the two or more input signals into an output signal. The circuitry for aggregation includes circuitry for providing the output signal based on the number of input signals taking the first value (VI ) minus the number of input signals taking the second value (V2). This Boolean logic circuitry can efficiently manage input signals in deep neural networks, especially those designed for logic or deep learning systems. This reduces computational complexity due to the processing of deep neural systems, thereby reducing energy consumption, processing latency, and silicon area of computing chips compared to existing systems. This Boolean logic circuitry is suitable for computing systems that handle logic signals and can adapt to both parallel and serial input signal settings.

[0023] Optionally, the circuitry for performing the aggregation further includes circuitry for performing a POPCOUNT operation on the two or more input signals, and circuitry for performing a COUNT operation on the two or more input signals. The circuitry for providing output signal includes circuitry for summarizing two times the result of the POPCOUNT operation minus the result of the COUNT operation. The POPCOUNT operation counts the number of input signals taking the first value in a time period and the COUNT operation counts the number of input signals in the time period.

[0024] Optionally, the circuitry for performing the aggregation further includes circuitry for performing a first POPCOUNT operation on the two or more input signals, and circuitry for performing a second POPCOUNT operation on the inverses of the two or more input signals. The circuitry for providing output signal includes circuitry for summarizing the result of the first POPCOUNT operation minus the result of the second POPCOUNT operation. The second POPCOUNT operation counts the number of input signals taking the first value in a time period.

[0025] Optionally, the method further comprises the circuitry for performing the aggregation further includes circuitry for performing a first adding operation on the two or more input signals. The first adding operation adds a 1 for each signal taking the first value (VI), resulting in a first count. The method further includes circuitry for performing a second adding operation on the inverse of the two or more input signals. The circuitry for providing the output signal further includes circuitry for summarizing the first count minus the result of the second count. The circuitry for adding operations includes circuitry for an indicator logic gate (1 ). The indicator logic gate (1 ) applied to a signal output a ‘ 1’ if the input signal takes on the first value (VI ), and circuitry for weighting the two or more input signals by multiplying the result of the indicator logic gate with the corresponding weight.

[0026] According to a third aspect, a Boolean logic computing system is provided. The Boolean logic computing system includes a controller. The controller is configured to receive two or more input signals (IN_SIGNAL_1 , IN_SIGNAL_n), the two or more input signals being logic signals. A logic signal can take one out of a first value (VI) and a second value (V2). The controller is configured to aggregate the two or more input signals into an output signal. The controller is further configured to perform the aggregation by providing the output signal based on the number of input signals taking the first value (VI) and minus the number of input signals taking the second value (V2).

[0027] This Boolean computing system can efficiently manage input signals in deep neural networks, especially those designed for logic or deep learning systems. This reduces computational complexity due to the processing of deep neural systems, thereby reducing energy consumption, processing latency, and silicon area of computing chips compared to existing systems. This computing system is suitable for computing systems that handle logic signals and can adapt to both parallel and serial input signal settings.

[0028] Optionally, the controller is further configured to apply a forward logic circuit to a main input signal (X) to provide a first intermediate result. The controller is further configured to perform a first aggregation of the first intermediate result into a main output signal (Y). The first intermediate result includes the two or more input signals for the first aggregation. The controller is further configured to receive a backpropagation signal (Z). The controller is further configured to apply a backpropagation logic to the backpropagation signal (Z) to provide a second intermediate result. The controller is further configured to perform a second aggregation of the second intermediate result into a main feedback signal (U). The second intermediate result includes the two or more input signals for the second aggregation. The controller is further configured to apply an optimization logic to the backpropagation signal (Z) to provide a third intermediate result. The controller is further configured to perform a third aggregation of the third intermediate result into a main optimization signal (Q). The third intermediate includes the two or more input signals for the third aggregation.

[0029] According to a fourth aspect, a computer program product includes program instructions for performing all the steps of the method when executed by one or more processors in a Boolean logic computing system.

[0030] Therefore, in contradistinction to the existing solutions, the Boolean logic computing system includes a controller configured to aggregate the input signals. The Boolean logic computing can be applied to a deep learning system to manage the input signals efficiently with less computational power as described above.

[0031] These and other aspects of the disclosure will be apparent from the implementation s) described below.

[0032] BRIEF DESCRIPTION OF DRAWINGS

[0033] Implementations of the disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0034] FIG. 1 illustrates a block diagram of a Boolean logic computing system for aggregating logic signals in accordance with an implementation of the disclosure;

[0035] FIG. 2 illustrates a block diagram of layers / stages of a deep learning system that utilizes a Boolean logic computing system for aggregating input signals during a training process in accordance with an implementation of the disclosure;

[0036] FIG. 3 illustrates a block diagram of a Boolean logic circuitry for aggregating input signals in accordance with an implementation of the disclosure;

[0037] FIG. 4 illustrates a block diagram of a Boolean logic circuitry that utilizes two POPCOUNT logic gates for aggregating input signals in accordance with an implementation of the disclosure;

[0038] FIG. 5 illustrates a block diagram of a Boolean logic circuitry that manages both logic signals and weighting / multiplexed signals in accordance with an implementation of the disclosure;

[0039] FIG. 6 illustrates a block diagram of a Boolean logic circuitry that utilizes three ADD logic gates for aggregating input signals in accordance with an implementation of the disclosure;

[0040] FIG. 7 illustrates a flow diagram of a method for use in a Boolean logic computing system for aggregating input signals in accordance with an implementation of the disclosure; and

[0041] FIG. 8 is an illustration of a computer system (e.g., a Boolean logic computing system) in which the various architectures and functionalities of the various previous implementations may be implemented.

[0042] DETAILED DESCRIPTION OF THE DRAWINGS

[0043] This disclosure describes implementations that provide a method for use in a Boolean logic computing system for aggregating logic signals. The disclosure relates to Boolean logic circuitry for aggregating logic signals. The disclosure also relates to a Boolean logic computing system including a controller configured to aggregate logic signals. To make solutions of the disclosure more comprehensible for a person skilled in the art, the following implementations of the disclosure are described with reference to the accompanying drawings.

[0044] Terms such as “a first”, “a second”, “a third”, and “a fourth” (if any) in the summary, claims, and foregoing accompanying drawings of the disclosure are used to distinguish between similar objects and are not necessarily used to describe a specific sequence or order. It should be understood that the terms so used are interchangeable under appropriate circumstances, so that the implementations of the disclosure described herein are, for example, capable of being implemented in sequences other than the sequences illustrated or described herein. Furthermore, the terms “include” and “have” and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, a method, a system, a product, or a device that includes a series of steps or units, is not necessarily limited to expressly listed steps or units but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or device.

[0045] Definitions:

[0046] A logic signal is also referred to as a binary-valued signal where each time slot can take on one out of two values, for example [0,1], [-1,1], [TRUE, FALSE], and so on.

[0047] FIG. 1 illustrates a block diagram of a Boolean logic computing system 100 for aggregating logic signals in accordance with an implementation of the disclosure. The Boolean logic computing system 100 includes a controller 102. The controller 102 is configured to receive two or more input signals (IN_SIGNAL_1, IN_SIGNAL_n) 104A-N. The two or more input signals 104A-N are logic signals. A logic signal can take one out of a first value, VI, and a second value, V2. The logic signals are a type of binary- valued signal which means the logic signals include two possible values {VI, VALUE1, V2, VALUE2}. For example, the logic signals include logic data {TRUE, FALSE} , signed binary data {- 1 , + 1 } , and unsigned binary data {0, 1 } .

[0048] The controller 102 is configured to aggregate the two or more input signals 104A-N into an output signal 106. The controller 102 is further configured to perform the aggregation by providing the output signal 106 based on the number of input signals taking the first value, VI {COUNTER OF IN_LOGIC_SIGNALs TAKING VALUE1} minus the number of input signals taking the second value, V2 {COUNTER OF IN_LOGIC_SIGNALs TAKING VALUE2}.

[0049] This Boolean computing system 100 can efficiently manage input signals, e.g., the two or more input signals 104A-N in deep neural networks, especially those designed for logic or deep learning systems. This reduces computational complexity due to the processing of deep neural systems, thereby reducing energy consumption, processing latency, and silicon area of computing chips compared to existing systems. This Boolean computing system 100 is suitable for computing systems that handle logic signals and can adapt to both parallel and serial input signal settings.

[0050] The Boolean logic circuitry 100 performs the aggregation by providing the output signal 106 as equalling the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

[0051] FIG. 2 illustrates a block diagram of layers / stages of a deep learning system 200 that utilizes a Boolean logic computing system for aggregating input signals during a training process in accordance with an implementation of the disclosure. The deep learning system 200 includes a forward processing layer 226, a backpropagation layer 228, and an optimizer 230. The forward processing layer 226 receives an input signal, represented as X at 214 along with a weight of the deep learning system 200, represented as W at 224 A. The input signal 214 is a data signal. The forward processing layer 226 processes the input signal 214 from left to right.

[0052] The forward processing layer 226 applies a forward logic circuit at 202 to the input signal 214 to generate a first intermediate result. Based on an implementation-specific rule, the forward logic circuit 202 calculates the first intermediate result using the X 214 and the W 224A. The first intermediate result is a new signal or computed signal. Optionally, the implementationspecific rule is generated by the optimizer 230 by adjusting weights of the deep learning system 200. The implementationspecific rule is I = {i | INVERT_COND = TRUE} .

[0053] For example, the forward logic circuit 202 applies an exclusive OR, XOR logic to each pair (X[i], W[i]) to generate the first intermediate result, where [i] is a symbolic index representing elements of the X 214 and the W 224 A. The first intermediate result includes two or more input signals (X[i], W[i]) for the first aggregation 204. Subsequently, the forward processing layer 226 performs the first aggregation 204 on the first intermediate result to generate a main output signal, Y depicted at 216, which means aggregates the computed signals from the forward logic circuit 202 to generate the main output signal 216.

[0054] The backpropagation layer 228 includes a backpropagation logic 208, an optimization logic 212, a second aggregation block 206, and a third aggregation block 210. The backpropagation logic 208, and the optimization logic 212 are implementationspecific processing components. The backpropagation layer 228 receives a backpropagation signal, represented as Z at 220 along with the weight 224A of the data learning system 200. The backpropagation layer 228 processes the input signal 220 from right to left. The backpropagation layer 228 applies the backpropagation logic 208 to the backpropagation signal 220 to generate a second intermediate result. The second intermediate result includes the two or more input signals for the second aggregation 206. The backpropagation layer 228 performs the second aggregation 206 on the second intermediate result to generate a main feedback signal (U) depicted at 218.

[0055] The backpropagation layer 228 applies the optimization logic 212 to the backpropagation signal 220 to provide a third intermediate result. The third intermediate includes two or more input signals for the third aggregation 210. The backpropagation layer 228 performs or computes a third aggregation 210 on the third intermediate result to generate a main optimization signal (Q) along with weight depicted at 222 and 224B. The main optimization signal 222 and the main feedback signal 218 are utilized for the training ofthe deep learning system 200. The X, Y, Z, Q, U, and W are multi-dimensional tensors. The Boolean logic computing system is applied to blocks of the first aggregation 204, the second aggregation 206, and the third aggregation 210 to aggregate the generate the main output signal 216, the main feedback signal 218, and the main optimization signal along with weight 222 and 224B.

[0056] FIG. 3 illustrates a block diagram of a Boolean logic circuitry 300 for aggregating input signals 302A-N in accordance with an implementation of the disclosure. The Boolean logic circuitry 300 includes a POPCOUNT logic gate 304, a COUNT logic gate 306, and an ADD logic gate 310. The Boolean logic circuitry 300 receives two or more input signals 302A-N. The Boolean logic circuitry 300 performs a POPCOUNT operation on the two or more input signals 302A-N using the POPCOUNT logic gate 304. The POPCOUNT operation counts a number of input signals taking the first value in a period, i.e., counts a number of TRUE signals or counts the number of TRUE events within a specified time window. The Boolean logic circuitry 300 performs a COUNT operation on the two or more input signals 302A-N using the count logic gate 306. The COUNT operation counts the number of input signals in a period, i.e., counts the total number of events within a specified time window.

[0057] The ADD logic gate 310 calculates an output signal 312 by summing two times the result of the POPCOUNT operation using a first multiplier 308A and subtracting the result ofthe COUNT operation by -1 using a second multiplier 308B, i.e., subtracting the total COUNT of the TRUE signals from twice the POPCOUNT of the two or more input signals which compute the difference between a number of TRUE signals and the number of FALSE signals.

[0058] The Boolean logic circuitry 300 determines the sum of two times the result of the POPCOUNT operation minus the result of the COUNT operation by multiplying the result of the COUNT operation by -1 and adding the result to two times the POPCOUNT operation.

[0059] OUTPUT_SIGNAL = 2 x POPCOUNT - COUNT = NUMBER OF TRUEs - NUMBER OF FALSEs FIG. 4 illustrates a block diagram of a Boolean logic circuitry 400 that utilizes two POPCOUNT logic gates for aggregating input signals in accordance with an implementation of the disclosure. The Boolean logic circuitry 400 includes a first POPCOUNT logic gate 404, a second POPCOUNT logic gate 406, a first inverter logic gate 408A, a second inverter logic gate 408B, and an ADD logic gate 412. The first POPCOUNT logic gate 404 receives two or more input signals 402A-N. The first POPCOUNT logic gate 404 performs a first POPCOUNT operation on two or more input signals 402A-N.

[0060] The first inverter logic gate 408A and the second inverter logic gate 408B receive the two or more input signals 402A-N. The first inverter logic gate 408A and the second inverter logic gate 408B invert the received two or more input signals 402A-N. The second POPCOUNT logic gate 406 receives the two or more inverted input signals. The second POPCOUNT logic gate 406 performs a second POPCOUNT operation on the two or more inverted input signals.

[0061] The ADD logic gate 412 provides an output signal 414 by summing the result of the first POPCOUNT operation minus the result of the second POPCOUNT operation using a multiplier at 410. The first POPCOUNT logic gate 404 counts the number of input signals taking the first value in a time period operation, i.e., counts the number of TRUE signals among the two or more input signals 402 A-N. The second POPCOUNT logic gate 406 counts the number of FALSE signals among the two or more inverted input signals.

[0062] FIG. 5 illustrates a block diagram of a Boolean logic circuitry 500 that manages both logic signals 502A-N and weighting / multiplexed signals 504A-N in accordance with an implementation of the disclosure. The Boolean logic circuitry 500 includes an AGGR 506. The AGGR gate 506 receives two sets of input signals in two possible cases. The two sets of input signals include a first set of input signals that may be logic signal (XI to Xn) 502 A-N and a second set of signal includes weighting or multiplexed signals (W1 to Wn) 504A-N. In a first case, the AGGR gate 506 receives the input signal X which may be a logic signal, and the input signal W which may be a weighting signal. In a second case, the AGGR gate 506 receives the input signal X which may be a weighting signal, and the input signal W which may be a logic signal. The AGGR gate 506 aggregates the logic signal and the weighting signal to generate the output signal that has a specific property.

[0063] FIG. 6 illustrates a block diagram of a Boolean logic circuitry 600 that utilizes three ADD logic gates for aggregating input signals in accordance with an implementation of the disclosure. The Boolean logic circuitry 600 includes a first inverter gate 606A, a second inverter gate 606B, a first ADD logic gate 608, a second ADD logic gate 610, and a third ADD logic gate 614. The first ADD logic gate 608 receives two or more input signals (X_l , X_n) at 602A-N along with weights that are depicted as W1 and Wn at 612 A-N. The first ADD logic gate 608 receives X_1 and W1 through a first multiplier 604 A. The first multiplier 604A multiplies the X_1 signal and W 1 before being fed into the first ADD logic gate 608.

[0064] The first ADD logic gate 608 receives X_n and Wn through a second multiplier 604B. The second multiplier 604B multiplies the X_n signal and Wn before being fed into the first ADD logic gate 608. The first ADD logic gate 608 performs a first adding operation on the two or more input signals 602A-N along with weight 612A-N. The first adding operation adds a 1 for each input signal taking the first value (VI), resulting in a first count.

[0065] The first inverter gate 606A receives the X_1 signal. The first inverter gate 606A inverts the X_1 signal. The second inverter gate 606B receives the X_n signal. The second inverter gate 606B inverts the X_n signal. The second ADD logic gate 610 receives the inverse of two or more input signals 602 A-N along with the weight 612 A-N from the first inverter 606 A and the second inverter 606B. The second ADD logic gate 610 receives the inverted X_1 signal and W1 through a third multiplier 604C. The third multiplier 604C multiplies the inverted X_1 signal and W1 before being fed into the second ADD logic gate 610. The second ADD logic gate 610 receives the inverted X_n signal and Wn through a fourth multiplier 604D. The fourth multiplier 604D multiplies the inverted X_n signal and Wn before being fed into the second ADD logic gate 610. The second ADD logic gate 610 performs a second adding operation on the inverse of the two or more input signals 602A-N along with the weight 612A-N. The Boolean logic circuitry 600 weighs each input signal with weights (W) before performing the first adding operation. The Boolean logic circuitry 600 weighs each input signal with the same weights (W) before performing the second adding operation. The Boolean logic circuitry 600 weighs the two or more input signals by multiplying the result of the indicator logic gate with the corresponding weight.

[0066] The third ADD logic gate 614 provides an output signal 616 by summing a first count minus the result of the second count using a fifth multiplier 604E. The weights are real-valued, consequently, the output signal 616 is also real-valued. i.e., OUTJSIGNAL = COUNTER_1 - COUNTER_2

[0067] The adding operations include circuitry for an indicator logic gate (1 ). The indicator logic gate (1 ) is applied to the two or more input signals 602 A-N. The indicator logic gate (1) outputs a ‘1’ if the input signal takes on the first value (VI). The indicator logic gate (1) outputs a ‘0’ if the input signal takes on the second value (V2). i.e.,

[0068] COUNTER_1 = 1 (X_l = TRUE) x W_1 + ... + l(X_n = TRUE) x W_n, COUNTER_2 = 1 (X_l = FALSE) x W_1 + ... + l(X_n = FALSE) x W_n,

[0069] Where l(X_i = V) is the indicator logic gate. The indicator logic gate outputs (i) 1 if X_i is V, and (ii) 0 if X_i is not V.

[0070] FIG. 7 illustrates a flow diagram of a method for use in a Boolean logic computing system for aggregating input signals in accordance with an implementation of the disclosure. At a step 702, the method includes receiving two or more input signals (IN_SIGNAL_1, IN_SIGNAL_n). The two or more input signals being logic signals A logic signal can take one out of a first value (VI ) and a second value (V2). At a step 704, the method includes aggregating the two or more input signals into an output signal. The aggregation is performed by providing the output signal based on the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

[0071] This method for use in the Boolean logic system can efficiently manage input signals in deep neural networks, especially those designed for logic or deep learning systems. This reduces computational complexity due to the processing of deep neural systems, thereby reducing energy consumption, processing latency, and silicon area of computing chips compared to existing systems. This method of the Boolean logic system is suitable for computing systems that handle logic signals and can adapt to both parallel and serial input signal settings.

[0072] FIG. 8 is an illustration of a computer system (e.g., a Boolean logic computing system) 800 in which the various architectures and functionalities of the various previous implementations may be implemented. As shown, the computer system 800 includes at least one processor 803 that is connected to a bus 802, wherein the computer system 800 may be implemented using any suitable protocol, such as Peripheral Component Interconnect, PCI, Express, Accelerated Graphics Port, AGP, Hyper Transport, or any other bus or point-to-point communication protocol. The computer system 800 also includes a memory 806.

[0073] Control logic (software) and data are stored in the memory 806 which may take a form of random-access memory, RAM. In the disclosure, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional central processing unit, CPU, and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. The computer system 800 may also include a secondary storage 810. The secondary storage 810 includes, for example, a hard disk drive and a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, a digital versatile disk, a DVD drive, a recording device, a universal serial bus, a USB flash memory. The removable storage drives at least one of reads from and writes to a removable storage unit in a well-known manner.

[0074] Computer programs, or computer control logic algorithms, may be stored in at least one of the memory 806 and the secondary storage 810. Such computer programs, when executed, enable the computer system 800 to perform various functions as described in the foregoing. The memory 806, the secondary storage 810, and any other storage are possible examples of computer-readable media.

[0075] In an implementation, the architectures and functionalities depicted in the various previous figures may be implemented in the context of the processor 804, a graphics processor coupled to a communication interface 812, an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the processor 804 and a graphics processor, a chipset (namely, a group of integrated circuits designed to work and sold as a unit for performing related functions, and so forth).

[0076] Furthermore, the architectures and functionalities depicted in the various previous-described figures may be implemented in a context of a general computer system, a circuit board system, a game console system dedicated to entertainment purposes, an application- specific system. For example, the computer system 800 may take the form of a desktop computer, a laptop computer, a server, a workstation, a game console, or an embedded system.

[0077] Furthermore, the computer system 800 may take the form of various other devices including, but not limited to a personal digital assistant, PDA, device, a mobile phone device, a smart phone, a television, and so forth. Additionally, although not shown, the computer system 800 may be coupled to a network (for example, a telecommunications network, a local area network, LAN, a wireless network, a wide area network, WAN, such as the Internet, a peer-to-peer network, a cable network, or the like) for communication purposes through an I / O interface 808.

[0078] It should be understood that the arrangement of components illustrated in the figures described is exemplary and that other arrangement may be possible. It should also be understood that the various system components (and means), defined by the claims, described below, and illustrated in the various block diagrams, represent components in some systems configured according to the subject matter disclosed herein. For example, one or more of these system components (and means) may be realized, in whole or in part, by at least some of the components illustrated in the arrangements illustrated in the described figures.

[0079] In addition, while at least one of these components is implemented at least partially as an electronic hardware component, and therefore constitutes a machine, the other components may be implemented in software that when included in an execution environment constitutes a machine, hardware, or a combination of software and hardware.

[0080] Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

CLAIMS1. A method for use in a Boolean logic computing system (100, 300, 400, 500, 600), wherein the method comprises receiving two or more input signals (IN_SIGNAL_1 , IN_SIGNAL_n) (104A-N, 302A-N, 402A-N, 502A-N, 504A- N, 602A-N), the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) being logic signals, wherein a logic signal can take one out of a first value (VI ) and a second value (V2); and aggregating the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) into an output signal (106, 312, 414, 508, 616), wherein the method is characterized in that the aggregation is performed by providing the output signal (106, 312, 414, 508, 616) based on the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

2. The method according to claim 1, wherein the method further comprises performing the aggregation by providing the output signal (106, 312, 414, 508, 616) as equalling the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

3. The method according to claim 1 or 2, wherein the method further comprises performing the aggregation by performing a POPCOUNT operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A- N, 602A-N), and performing a COUNT operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), wherein the output signal (106, 312, 414, 508, 616) is provided as equalling the sum of two times the result of the POPCOUNT operation minus the result of the COUNT operation, wherein the POPCOUNT operation counts the number of input signals taking the first value in a time period and the COUNT operation counts the number of input signals in the time period.

4. The method according to claim 3, wherein the method further comprises determining the sum of two times the result of the POPCOUNT operation minus the result of the COUNT operation by multiplying the result of the COUNT operation by -1 and adding the result to two times the POPCOUNT operation.

5. The method according to claim 1 or 2, wherein the method further comprises performing the aggregation by performing a first POPCOUNT operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), and performing a second POPCOUNT operation on the inverses of the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), wherein the output signal (106, 312, 414, 508, 616) is provided as equalling the sum of the result of the first POPCOUNT operation minus the result of the second POPCOUNT operation, wherein the second POPCOUNT operation counts the number of input signals taking the first value in a time period.

6. The method according to claim 1 or 2, wherein the method further comprises performing the aggregation by performing a first adding operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), wherein the first adding operation adds a 1 for each signal taking the first value (VI), resulting in a first count, performing a second adding operation on the inverse of the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), wherein the second adding operation adds a 1 for each inverted signal taking the first value (VI), resulting in a second count, wherein the output signal (106, 312, 414, 508, 616) is provided as equalling the sum of the first count minus the result of the second count.

7. The method according to claim 6, wherein the method further comprisesweighting each of the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) with weights (W) prior to performing the first adding operation, and weighting each of the inverted two or more input signals ( 104A- N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) with the same weights (W) prior to performing the second adding operation.

8. The method according to claim 7, wherein the weights are real- valued and the output signal (106, 312, 414, 508, 616) is thus also real- valued.

9. The method according to claim 6, 7, or 8, wherein the method further comprises performing the adding operations utilizing an indicator logic gate ( 1 ), wherein the indicator logic gate ( 1 ) applied to a signal output a ‘ 1’ if the input signal takes on the first value (VI), and wherein the weighting of the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) is performed by multiplying the result of the indicator logic gate with the corresponding weight.

10. The method according to any preceding claim, wherein the method is for use in a Deep Learning system (200).

11. Boolean logic circuitry (100, 300, 400, 500, 600) comprising circuitry for receiving two or more input signals (IN_SIGNAL_1 , IN_SIGNAL_n) (104A-N, 214, 220, 224A, 302A- N, 402A-N, 502A-N, 504A-N, 602A-N), the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A- N))being logic signals , wherein a logic signal can take one out of a first value (VI) and a second value (V2); and circuitry for aggregating the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) into an output signal (106, 312, 414, 508, 616), wherein the method is characterized in that the circuitry for aggregation comprises circuitry for providing the output signal (106, 312, 414, 508, 616) based on the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

12. The Boolean logic circuitry (100, 300, 400, 500, 600) according to claim 11, wherein the Boolean logic circuitry (100, 300, 400, 500, 600) for performing the aggregation further comprises circuitry for performing a POPCOUNT operation on the two or more input signals 104A-N, 302A-N, 402A-N, 502A- N, 504A-N, 602A-N ), and circuitry for performing a COUNT operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N ), wherein the Boolean logic circuitry (100, 300, 400, 500, 600) for providing output signal (312, 414,508, 616) comprises circuitry for summarizing two times the result of the POPCOUNT operation minus the result of the COUNT operation, wherein the POPCOUNT operation counts the number of input signals taking the first value in a time period and the COUNT operation counts the number of input signals in the time period.

13. The Boolean logic circuitry (100, 300, 400, 500, 600) according to claim 11, wherein the Boolean logic circuitry (100, 300, 400, 500, 600) for performing the aggregation further comprises circuitry for performing a first POPCOUNT operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) and circuitry for performing a second POPCOUNT operation on the inverses of the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), wherein the circuitry for providing output signal (106, 312, 414, 508, 616) comprises circuitry for summarizing the result of the first POPCOUNT operation minus the result of the second POPCOUNT operation,wherein the second POPCOUNT operation counts the number of input signals taking the first value in a time period.

14. The Boolean logic circuitry (100,300, 400, 500, 600) according to claim 11 , wherein the Boolean logic circuitry (100, 300, 400, 500, 600) for performing the aggregation further comprises circuitry for performing a first adding operation on the two or more input signals (104A-N, 302A-N, 402A-N, 502A- N, 504A-N, 602A-N), wherein the first adding operation adds a 1 for each signal taking the first value (VI), resulting in a first count; and circuitry for performing a second adding operation on the inverse of the two or more input signals (104A-N, 302A- N, 402A-N, 502A-N, 504A-N, 602A-N), wherein the circuitry for providing the output signal (106, 312, 414, 508, 616) further comprises circuitry for summarizing the first count minus the result of the second count, and wherein the circuitry for adding operations comprises circuitry for an indicator logic gate (1 ), wherein the indicator logic gate (1 ) applied to a signal output a ‘ 1’ if the input signal ) takes on the first value (VI ); and circuitry for weighting the two or more input signals (106, 312, 414, 508, 616) by multiplying the result of the indicator logic gate with the corresponding weight.

15. A Boolean logic computing system (100, 300, 400, 500, 600) comprising a controller (102) configured to receive two ormore input signals (IN_SIGNAL_1, IN_SIGNAL_n) (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N), the two ormore input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) being logic signals, wherein a logic signal can take one out of a first value (VI ) and a second value (V2); and aggregate the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) into an output signal (106, 312, 414, 508, 616), wherein the Boolean logic computing system (100) is characterized in that the controller (102) is further configured to perform the aggregation by providing the output signal (106, 224B, 312, 414, 508, 616) based on the number of input signals taking the first value (VI) minus the number of input signals taking the second value (V2).

16. The Boolean logic computing system (100, 300, 400, 500, 600) according to claim 15, wherein the controller (102) is further configured to apply a forward logic circuit (202) to a main input signal (X) (214) to provide a first intermediate result; perform a first aggregation (204) as per claim 15 of the first intermediate result into a main output signal (Y) (216), wherein the first intermediate result comprises the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) for the first aggregation (204); receive a backpropagation signal (Z) (220); apply a backpropagation logic (208) to the backpropagation signal (Z) (220) to provide a second intermediate result; perform a second aggregation (206) as per claim 15 of the second intermediate result into a main feedback signal (U) (218), wherein the second intermediate result comprises the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) for the second aggregation (206); and apply an optimization logic (212) to the backpropagation signal (Z) to provide a third intermediate result, perform a third aggregation (210) as per claim 15 of the third intermediate result into a main optimization signal (Q) (222), wherein the third intermediate comprises the two or more input signals (104A-N, 302A-N, 402A-N, 502A-N, 504A-N, 602A-N) for the third aggregation (210).

17. A computer program product comprising program instructions for performing the method according to any of claims 1 to 10, when executed by one or more processors in a Boolean logic computing system (100, 300, 400, 500, 600).

Images