Storage device and method for driving storage device

Abstract

Provided is a novel method for driving a storage device. The storage device includes: a plurality of transistors which are arranged in a matrix of m rows and n columns (where m and n are each an integer equal to or greater than 2) and which function as memory cells; m lines WL; m lines SL; n lines BL; and n lines PL. Each transistor has a paraelectric gate insulation layer and a ferroelectric back gate insulation layer. In each transistor, the gate is connected to the i-th line WL (where i is an integer between 1 and m inclusive), one of either the source or the drain is electrically connected to the j-th line BL (where j is an integer between 1 and m inclusive), the other of either the source or the drain is electrically connected to the i-th line SL, and the back gate is electrically connected to the j-th line PL. The potential difference between the i-th line WL and the j-th line PL is made larger than the potential difference between the lines WL other than the i-th and the j-th line PL, and data is written to the transistor located in the i-th row and j-th column.

Description

Storage device and method for driving storage device

[0001] One embodiment of the present invention relates to a memory device and a method for driving the memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Therefore, examples of technical fields related to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, testing methods thereof, and methods of using thereof.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics is being actively carried out. For next-generation ferroelectric memories, ferroelectric HfO ２ Research on ferroelectric hafnium oxide thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２Research into hafnium oxide is also being actively conducted, including the demonstration of FeRAM and CMOS integration using hafnium oxide (Non-Patent Document 5).

[0006] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al. , “Ferroelectric HfO▲2▼-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016Jun Okuno, et al. , "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf 0.5 Zr 0.5 O 2 ", VLSI 2020. Akira Toriumi, "Ferroelectricity of HfO 2 thin film", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. T. Francois, et al. , "Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications," IEDM 2019. Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology (AIST) Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] A field effect transistor (FeFET) using a ferroelectric material for the gate insulating layer is known. The FeFET has the function of controlling the polarization direction of the gate insulating layer, which is made of a ferroelectric material, by the gate voltage, thereby changing the threshold voltage of the transistor. One FeFET can function as one memory element. Therefore, it is easy to realize a memory element with a small occupancy area.

[0008] On the other hand, when reading data stored in the FeFET, the FeFET is switched between on and off states. Because the switching between on and off states is performed by the gate voltage, repeated on and off states can change the polarization direction of the gate insulating layer, which is a ferroelectric material, raising concerns about reduced reliability.

[0009] An object of one embodiment of the present invention is to provide a storage device with a small occupation area. Another object is to provide a storage device with high reliability. Another object is to provide a storage device with low power consumption. Another object is to provide a storage device with a large storage capacity. Another object is to provide a novel storage device. Another object is to provide a novel driving method for a storage device.

[0010] It should be noted that the problems associated with one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. It should be noted that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.

[0011] (1) One embodiment of the present invention is a memory device including a plurality of transistors arranged in a matrix of m rows and n columns (m and n are each an integer of 2 or greater), m wirings WL, m wirings SL, n wirings BL, and n wirings PL, in which a gate of a transistor arranged in an i-th row and a j-th column (i is an integer of 1 to m, j is an integer of 1 to n) is electrically connected to the i-th wiring WL, one of a source or a drain of a transistor arranged in the i-th row and the j-th column is electrically connected to the j-th wiring BL, the other of a source or a drain of a transistor arranged in the i-th row and the j-th column is electrically connected to the i-th wiring SL, and a back gate of a transistor arranged in the i-th row and the j-th column is electrically connected to the j-th wiring PL, and each of the plurality of transistors has a paraelectric gate insulating layer and a ferroelectric back-gate insulating layer.

[0012] Each of the plurality of transistors preferably contains indium and oxygen in a semiconductor layer in which a channel is formed, the gate insulating layer preferably contains silicon and oxygen, and the back gate insulating layer preferably contains oxygen and one or both of hafnium and zirconium.

[0013] (2) Another aspect of the present invention is a method for driving a memory device including a plurality of transistors arranged in a matrix of m rows and n columns, m wirings WL, m wirings SL, n wirings BL, and n wirings PL, wherein a gate of the transistor arranged in the i-th row and j-th column is electrically connected to the i-th wiring WL, one of a source or a drain of the transistor arranged in the i-th row and j-th column is electrically connected to the j-th wiring BL, the other of the source or the drain of the transistor arranged in the i-th row and j-th column is electrically connected to the i-th wiring SL, and a back gate of the transistor arranged in the i-th row and j-th column is electrically connected to the j-th wiring PL, and each of the plurality of transistors has a paraelectric gate insulating layer and a ferroelectric back gate insulating layer, in which a first potential difference that is a potential difference between the i-th wiring WL and the j-th wiring PL is made larger than a second potential difference that is a potential difference between a wiring WL other than the i-th wiring and the j-th wiring PL, and data is written to the transistor arranged in the i-th row and j-th column. The second potential difference is preferably 30% to 70% of the first potential difference.

[0014] Another embodiment of the present invention is a method for driving a memory device described in (2), in which a potential V0 is supplied to the i-th wiring SL, a potential VBL that is higher than the potential V0 is supplied to the j-th wiring BL, and then a potential VR is supplied to the i-th wiring WL, a current value flowing through the j-th wiring BL is measured, and data held in a transistor arranged in the i-th row and j-th column is read.

[0015] According to one embodiment of the present invention, a storage device with a small occupation area can be provided. Alternatively, a storage device with high reliability can be provided. Alternatively, a storage device with low power consumption can be provided. Alternatively, a storage device with a large storage capacity can be provided. Alternatively, a novel storage device can be provided. Alternatively, a novel driving method for a storage device can be provided.

[0016] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. Note that the other effects are effects not mentioned in this section, which will be described below. Those skilled in the art can derive the other effects from the description in the specification or drawings, and can extract them as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.

[0017] 1A to 1C are diagrams illustrating an example of a configuration of a transistor according to an embodiment of the present invention. FIG. 1D is an equivalent circuit diagram of a transistor according to an embodiment of the present invention. FIG. 2A is a diagram illustrating an example of hysteresis characteristics of a ferroelectric. FIGS. 2B and 2C are diagrams illustrating remanent polarization of a ferroelectric capacitor. FIGS. 3A and 3B are diagrams illustrating remanent polarization of a transistor according to an embodiment of the present invention. FIG. 3C is a diagram illustrating the Id-Vg characteristics of a transistor. FIGS. 4A to 4C are diagrams illustrating an example of a configuration of a transistor according to an embodiment of the present invention. FIG. 4D is an equivalent circuit diagram of a transistor according to an embodiment of the present invention. FIGS. 5A to 5C are diagrams illustrating an example of a configuration of a transistor according to an embodiment of the present invention. FIG. 5D is an equivalent circuit diagram of a transistor according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an example of a memory cell array. FIG. 7 is a timing chart illustrating an example of operation of the memory cell array. FIGS. 8A and 8B are circuit diagrams illustrating an example of operation of the memory cell array. FIGS. 9A and 9B are circuit diagrams illustrating an example of operation of the memory cell array. 10A1 to 10A7 and 10B1 to 10B6 are diagrams illustrating electrical connections. FIGS. 11A and 11B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 11C is a cross-sectional view illustrating an indium oxide film. FIG. 12A is a block diagram illustrating a configuration example of a memory device. FIGS. 12B and 12C are perspective views illustrating a configuration example of a memory device. FIG. 13 is a cross-sectional view illustrating a configuration example of a memory device. FIG. 14 is a block diagram illustrating a CPU. FIGS. 15A and 15B are perspective views of a semiconductor device. FIGS. 16A and 16B are perspective views of a semiconductor device. FIG. 17 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 18A and 18B are configuration examples of electronic components. FIGS. 19A to 19C are configuration examples of a mainframe computer. FIG. 20A is a configuration example of space equipment. FIG. 20B is a configuration example of a storage system.

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0019] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Therefore, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element, a device having such a circuit, etc. Transistors and diodes are also examples of semiconductor devices. For example, integrated circuits, chips equipped with integrated circuits, and electronic components in which a chip is housed in a package are also examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] Furthermore, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in the actual manufacturing process, layers and resist masks may be unintentionally eroded by processes such as etching, but this may be omitted from the description to facilitate understanding of the invention.

[0021] In addition, in order to facilitate understanding of the invention, some components may be omitted from plan views, perspective views, etc. Also, some hidden lines may be omitted.

[0022] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0023] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, ordinal numbers may be used in the claims to avoid confusion between components. Furthermore, the ordinal numbers used in this specification may differ from those used in the claims. Furthermore, even if a term has an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0024] Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification do not limit the functionality of these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" and "wiring" are integrated together. Furthermore, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wiring," "terminals," etc. are integrated together. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0025] Furthermore, in this specification and the like, supplying a signal refers to supplying a predetermined potential to a wiring or the like. Therefore, the term "signal" may be replaced with a term such as "potential." Furthermore, the term "potential" may be replaced with "signal." Furthermore, the "signal" may be a variable potential or a fixed potential.

[0026] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0027] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductive layers sandwiching the insulator. Therefore, the term "pair of conductive layers" in a "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The term "one of the pair of terminals" can sometimes be referred to as "one terminal" or "first terminal." The term "the other of the pair of terminals" can sometimes be referred to as "the other terminal" or "second terminal." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it can be set to 1 pF or more and 10 μF or less.

[0028] In this specification and elsewhere, the term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate wiring refers to a wiring for connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0029] In this specification and elsewhere, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The source region refers to one of two regions of a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region. The source wiring refers to a wiring that connects the source electrode of at least one transistor to another electrode or another wiring.

[0030] In this specification and elsewhere, the term "drain" refers to a part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region. The drain wiring refers to a wiring that connects the drain electrode of at least one transistor to another electrode or another wiring.

[0031] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) field-effect transistors. Furthermore, if the transistors described in this specification and the like are n-channel transistors, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0 V unless otherwise specified. Furthermore, if the transistors described in this specification and the like are p-channel transistors, the Vth of the transistors is less than or equal to 0 V unless otherwise specified. Furthermore, unless otherwise specified, the Vth of multiple transistors of the same conductivity type is the same.

[0032] In this specification and the like, a current flowing between a source and a drain is also referred to as a "drain current" or "Id." Unless otherwise specified, the off-state current refers to Id when a transistor is in an off state (also referred to as a "non-conducting state" or "cut-off state"). Unless otherwise specified, the off-state refers to a state in which the potential difference between the gate and the source (also referred to as a "gate voltage" or "Vg") with respect to the source is lower than the threshold voltage in an n-channel transistor, and a state in which Vg is higher than the threshold voltage in a p-channel transistor. For example, the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.

[0033] In general, "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Furthermore, "potential" is relative, and the potential applied to wiring, etc., may change depending on the reference potential. Therefore, "voltage" and "potential" can sometimes be used interchangeably.

[0034] In this specification, terms indicating position, such as "above," "below," "upward," or "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components may change as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "an insulating layer located above a conductive layer" can be rephrased as "an insulating layer located below the conductive layer" by rotating the orientation of the drawing 180 degrees. For example, the expression "an insulating layer located above an opening" may include "an insulating layer located on the side of the opening."

[0035] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0037] In this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0040] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0041] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0042] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0043] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 10A1 and 10A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 10A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0044] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 10A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 10A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0045] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 10A6 and 10A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 10A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 10A6 and 10A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0046] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0047] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 10B1, 10B2, and 10B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 10B4 and 10B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 10B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0048] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0049] Embodiment 1 In this embodiment, a memory device according to one embodiment of the present invention will be described.

[0050] <Configuration Example> FIG. 1A is a plan view of a transistor 10A that can be used for a memory device according to one embodiment of the present invention. FIG. 1B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG. 1A. FIG. 1C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in FIG. 1A. Note that FIG. 1B is a cross-sectional view of the transistor 10A in the channel length direction, and FIG. 1C is a cross-sectional view of the transistor 10A in the channel width direction. FIG. 1D is a circuit symbol for the transistor 10A.

[0051] Transistor 10A has an insulating layer 202 arranged on substrate 201, an insulating layer 514 arranged on insulating layer 202, an insulating layer 516 arranged on insulating layer 514, a conductive layer 505 arranged so as to be embedded in insulating layer 516, an insulating layer 522 arranged on insulating layer 516 and conductive layer 505, and an insulating layer 524 arranged on insulating layer 522.

[0052] The transistor 10A also has a semiconductor layer 520a arranged on the insulating layer 524, a semiconductor layer 520b arranged on the semiconductor layer 520a, and a conductive layer 542a and a conductive layer 542b arranged spaced apart from each other on the semiconductor layer 520b.

[0053] The transistor 10A also includes an insulating layer 554 disposed on the conductive layers 542a and 542b, and an insulating layer 580 disposed on the insulating layer 554. The insulating layer 554 and the insulating layer 580 have a region overlapping with the conductive layer 542a when viewed from the Z direction and a region overlapping with the conductive layer 542b when viewed from the Y direction. The insulating layer 554 and the insulating layer 580 also have an opening between the conductive layers 542a and 542b when viewed from the Y direction. The transistor 10A also includes an insulating layer 550 and a conductive layer 560 disposed to cover the side surfaces and bottom of the opening.

[0054] The insulating layer 554 also has a region in contact with the top surface and side surface of the conductive layer 542a, a region in contact with the top surface and side surface of the conductive layer 542b, a region in contact with the side surface of the semiconductor layer 520a, a region in contact with the side surface of the semiconductor layer 520b, and a region in contact with the top surface of the insulating layer 522.

[0055] 1B and 1C , the upper surface of the conductive layer 560 coincides with or substantially coincides with the upper surface of the insulating layer 550 (the surface in contact with the insulating layer 574 described later) and the upper surface of the insulating layer 580. Note that in this specification and the like, the semiconductor layer 520a and the semiconductor layer 520b may be collectively referred to as the semiconductor layer 520.

[0056] The conductive layer 542a functions as one of a source electrode and a drain electrode of the transistor 10A. The conductive layer 542b functions as the other of the source electrode and the drain electrode of the transistor 10A. In this specification, the conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0057] The channel of the transistor 10A is formed in a region of the semiconductor layer 520 that overlaps with the conductive layer 560. Therefore, the channel length L of the transistor 10A can be expressed as the length in the X direction of the conductive layer 560 in the region that overlaps with the semiconductor layer 520. Furthermore, the channel of the transistor 10A is formed between a region that functions as a source and a region that functions as a drain of the semiconductor layer 520. Therefore, the channel length L of the transistor 10A can be expressed as the distance from the end of the conductive layer 542a to the end of the conductive layer 542b that face each other.

[0058] The channel width W of the transistor 10A can be expressed as the length of the semiconductor layer 520 in the Y direction in the region where the semiconductor layer 520 overlaps with the conductive layer 560 .

[0059] Although the transistor 10A has a structure in which two layers, the semiconductor layer 520a and the semiconductor layer 520b, are stacked as the semiconductor layer 520, the present invention is not limited to this. For example, the semiconductor layer 520 may be a single layer or may have a stacked structure of three or more layers.

[0060] For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 520, and a first metal oxide is used for the semiconductor layer 520a and a second metal oxide is used for the semiconductor layer 520b, it is preferable that the first metal oxide and the second metal oxide have a common metal element. When the semiconductor layers 520a and 520b have a common metal element (as a main component), a mixed layer with a low defect level density can be formed at the interface between the semiconductor layers 520a and 520b. For example, when the semiconductor layer 520b is an In oxide, an In—Ga—Zn oxide or the like can be used for the semiconductor layer 520a. The semiconductor layer 520a can also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide or a stacked structure of In—Ga—Zn oxide and gallium oxide can be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In can be used for the semiconductor layer 520a.

[0061] 1A to 1C, the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided inside the conductive layer 560a to fill the opening. Although the conductive layer 560 in the transistor 10A has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 can have a single-layer structure or a stacked structure of three or more layers.

[0062] The conductive layer 560a is made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0063] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0064] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560b also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure. For example, the conductive layer 560b may have a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0065] 1C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the conductive layer 560 is arranged to cover the top surface and side surfaces of the semiconductor layer 520. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 10A, to act not only on the top surface but also on the side surfaces of the semiconductor layer 520. This increases the on-state current of the transistor 10A and improves its frequency characteristics.

[0066] The conductive layer 560 functions as a gate electrode of the transistor, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. The conductive layer 560 is provided so as to fill the opening of the insulating layer 554, the opening of the insulating layer 580, and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 10A, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 10A. This allows for an increased integration density of the memory device.

[0067] When an oxide semiconductor is used for the semiconductor layer 520, a conductive material that is not easily oxidized or a conductive material that maintains conductivity even when absorbing oxygen is preferably used for the conductive layer 542. A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 10A.

[0068] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 10A. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, and the insulating layer 580.

[0069] When an oxide semiconductor is used for the semiconductor layer 520, an insulating layer having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0070] Furthermore, an insulating layer having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) is preferably used for the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522 and the insulating layer 554. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0071] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are sandwiched between the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from diffusing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0072] 1B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) is provided, which is connected to the transistor 10A and functions as a plug. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 that functions as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 1B, a first conductive layer of the conductive layer 545 is provided inside the opening in contact with the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside the first conductive layer.

[0073] Here, the height of the top surface of the conductive layer 545 can be made approximately the same as the height of the top surface of the insulating layer 581. Note that although the transistor 10A has a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can also have a single layer structure or a stacked structure of three or more layers.

[0074] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This occurs because part of the top surface of the semiconductor layer 520b is removed when the conductive layers 542a and 542b are formed. Furthermore, when a conductive film that becomes the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b located between the conductive layers 542a and 542b in a plan view, it is possible to prevent unintended current from flowing between the conductive layers 542a and 542b.

[0075] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0076] The conductive layer 505 includes a conductive layer 505a and a conductive layer 505b. The conductive layer 505a is provided in contact with the bottom and sidewalls of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to be embedded in a recess formed in the conductive layer 505a. The height of the top surface of the conductive layer 505b is the same as or approximately the same as the height of the upper end portion (the surface in contact with the insulating layer 522) of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0077] When an oxide semiconductor is used for the semiconductor layer 520, the conductive layers 505a and 505b are preferably formed using a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like).

[0078] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 505a, it is possible to prevent impurities such as hydrogen contained in the insulating layer 516 from diffusing into the conductive layer 505b. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 505a, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0079] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. For example, when the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a backgate electrode.

[0080] 1C , the conductive layer 505 preferably extends to a region outside an end portion of the semiconductor layer 520 that intersects with the channel width direction. That is, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0081] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0082] The conductive layer 505 can be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, without being limited thereto, a conductive layer that functions as a wiring can also be provided under the conductive layer 505.

[0083] The insulating layer 514 may be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from diffusing from the substrate side to the transistor 10A. Therefore, the insulating layer 514 may be formed using an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., the impurities are less likely to permeate through the insulating layer). Alternatively, the insulating layer 514 may be formed using an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate through the insulating layer).

[0084] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 10A side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0085] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0086] When the conductive layer 505 is used as a back gate electrode, the insulating layers 522 and 524 function as back gate insulating layers. When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, the insulating layer 524 is preferably made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 10A is improved.

[0087] The transistor 10A according to one embodiment of the present invention uses a material that can have ferroelectricity (also referred to as a "ferroelectric") as the insulating layer 522 that functions as a back-gate insulating layer. A paraelectric material has the property that when a voltage is applied, the random polarization direction aligns in a certain direction and returns to the random state when the voltage application is stopped. A ferroelectric material has the property that when a voltage is applied, the polarization aligns in a certain direction and remains aligned even after the voltage application is stopped. Furthermore, when the voltage is reversed, the polarization is reversed. The transistor 10A according to one embodiment of the present invention can control the threshold voltage by utilizing the properties of the ferroelectric material.

[0088] Furthermore, depending on the composition of the ferroelectric, the leakage current may be larger than that of a paraelectric. For this reason, the insulating layer 524 provided between the insulating layer 522 and the semiconductor layer 520 is preferably made of a paraelectric material. By providing the insulating layer 524, which is a paraelectric, between the insulating layer 522 and the semiconductor layer 520, the leakage current between the insulating layer 522, which is a ferroelectric layer, and the semiconductor layer 520 is reduced, and the power consumption of the transistor 10A can be reduced.

[0089] [Regarding hysteresis characteristics of ferroelectrics] Ferroelectrics have hysteresis characteristics. FIG. 2A is a diagram showing an example of the hysteresis characteristics of a ferroelectric. The hysteresis characteristics of a ferroelectric can be measured using a ferroelectric capacitor that uses a ferroelectric as the dielectric. In FIG. 2A, the horizontal axis represents the voltage (electric field) applied to the ferroelectric. This voltage is the potential difference between one electrode and the other electrode of the ferroelectric capacitor. The electric field strength can be found by dividing this potential difference by the thickness of the ferroelectric.

[0090] In Figure 2A, the vertical axis represents the polarization of the ferroelectric. When the polarization is positive, it indicates that the positive charge in the ferroelectric is biased toward one electrode of the capacitance element, and the negative charge is biased toward the other electrode of the capacitance element. On the other hand, when the polarization is negative, it indicates that the negative charge in the ferroelectric is biased toward one electrode of the capacitance element, and the positive charge is biased toward the other electrode of the capacitance element.

[0091] In addition, the polarization shown on the vertical axis of the graph in Figure 2A can be positive when negative charges are biased toward one electrode of the capacitance element and positive charges are biased toward the other electrode of the capacitance element, and can be negative when positive charges are biased toward one electrode of the capacitance element and negative charges are biased toward the other electrode of the capacitance element.

[0092] 2A, the hysteresis characteristics of a ferroelectric material can be expressed by a curve 51 and a curve 52. The voltages at the intersections of the curves 51 and 52 are referred to as the saturated polarization voltage +VSP (also referred to as "+VSP") and the saturated polarization voltage -VSP (also referred to as "-VSP"). It can be said that +VSP and -VSP have opposite polarities.

[0093] When a voltage equal to or less than -VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is increased, the polarization of the ferroelectric changes according to curve 51. On the other hand, when a voltage equal to or greater than +VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is decreased, the polarization of the ferroelectric changes according to curve 52. Note that +VSP may be referred to as a "positive saturation polarization voltage" or a "first saturation polarization voltage." Furthermore, -VSP may be referred to as a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0094] When the polarization of a ferroelectric changes according to curve 51, the voltage at which the polarization becomes 0 is referred to as coercive voltage +Vc. Also, when the polarization of a ferroelectric changes according to curve 52, the voltage at which the polarization becomes 0 is referred to as coercive voltage -Vc. The values ​​of +Vc and -Vc are between +VSP and -VSP. Note that +Vc may be referred to as a "positive coercive voltage" or "first coercive voltage," and -Vc may be referred to as a "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0095] Furthermore, when no voltage is applied to the ferroelectric (when the voltage is 0 V), the maximum value of polarization is referred to as "residual polarization +Pr" or "residual polarization Pr1," and the minimum value is referred to as "residual polarization -Pr" or "residual polarization Pr2."

[0096] The absolute value of the difference between the remanent polarization +Pr and the remanent polarization -Pr is referred to as the "remanent polarization 2Pr." The larger the remanent polarization 2Pr, the larger the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. Furthermore, when a ferroelectric is used for the insulating layer 522 that functions as a back gate insulating layer, the larger the remanent polarization 2Pr, the larger the fluctuation range of the threshold voltage. Therefore, the larger the remanent polarization 2Pr, the more preferable it is.

[0097] Fig. 2B is a schematic diagram of the capacitance element 30, which is a ferroelectric capacitor, when 0 V is applied to terminal A, +VSP is applied to terminal B, and the remnant polarization is +Pr (remnant polarization Pr1). Fig. 2C is a schematic diagram of the capacitance element 30, which is a ferroelectric capacitor, when -VSP is applied to terminal A, 0 V is applied to terminal B, and the remnant polarization is -Pr (remnant polarization Pr2). Figs. 2B and 2C schematically show the polarization of the dielectric of the capacitance element 30.

[0098] Examples of ferroelectrics include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of ferroelectrics include materials obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close thereto. Examples of ferroelectrics include materials obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of element J2 atoms can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or close thereto. Furthermore, as the ferroelectric, piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiOx (X is a real number greater than 0)), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate can also be used.

[0099] As a ferroelectric material, aluminum scandium nitride (Al １−ａ Sc ａ N ｂ(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1. Hereinafter, this may be referred to simply as "AlScN"), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used. Ferroelectrics include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Ferroelectrics include materials obtained by adding element M3 to the above-mentioned metal nitrides. The element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately. Since the above metal nitride contains at least a Group 13 element and nitrogen, which is a Group 15 element, the metal nitride may be referred to as a Group 13-15 ferroelectric, a Group 13 nitride ferroelectric, etc.

[0100] As a ferroelectric material, SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0101] Although the above description has been given with reference to metal oxides and metal nitrides, the present invention is not limited to these. For example, it is also possible to use metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides.

[0102] Furthermore, the ferroelectric may be, for example, a mixture or compound of multiple materials selected from the materials listed above. For example, the ferroelectric may have a layered structure of multiple materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. For this reason, in this specification, the term ferroelectric is used to refer not only to materials that exhibit ferroelectricity, but also to materials that may have ferroelectricity.

[0103] Metal oxides containing hafnium and / or zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing hafnium and / or zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and / or zirconium, transistors can be miniaturized. A typical example of a metal oxide containing hafnium and zirconium is HfZrOx. Furthermore, a metal oxide obtained by adding Y (yttrium) to HfZrOx can also be used. Adding Y to HfZrOx can enhance ferroelectricity.

[0104] In this specification and the like, a ferroelectric may be referred to as a "ferroelectric material." A ferroelectric material formed into a film may be referred to as a "ferroelectric layer." A device having a ferroelectric layer may be referred to as a "ferroelectric device."

[0105] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. It is also believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. It is particularly preferable for an insulating layer to contain crystals having an orthorhombic crystal structure, as this will manifest ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0106] Furthermore, adding a Group 3 element in the periodic table to an oxide containing either or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing either or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0107] As described above, a metal oxide containing either or both of hafnium and zirconium can have ferroelectricity even when it is a thin film of a few nanometers, and is therefore preferable for the insulating layer 522. The film thickness of the insulating layer 522 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).

[0108] Furthermore, a metal oxide containing either or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 522. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the temperature is lower than this, the material may still have ferroelectricity.

[0109] [Relationship Between Polarization of Ferroelectric and Id-Vg Characteristics] Next, the relationship between the polarization of the insulating layer 522, which is a ferroelectric layer, and the Id-Vg characteristics of the transistor 10A will be described.

[0110] 3A and 3B show the circuit symbol of the transistor 10A. Note that, in FIGS. 3A and 3B, the polarization of the insulating layer 522 (see FIGS. 1B and 1C), which is a ferroelectric layer, is schematically shown. For example, the back gate of the transistor 10A corresponds to terminal B of the capacitive element 30.

[0111] 3C is a graph illustrating the Id-Vg characteristics of the transistor 10A when the voltage between the source and drain (also referred to as the "drain voltage" or "Vd") of the transistor 10A is constant. The horizontal axis of FIG. 3C represents the voltage between the source and gate (Vg), and the vertical axis represents the current (Id) flowing between the source and drain.

[0112] In FIG. 3C, characteristic 290 indicates the Id-Vg characteristics of transistor 10A when no remanent polarization occurs in insulating layer 522.

[0113] 3C, a characteristic 291 indicates the Id-Vg characteristic when the remanent polarization of the insulating layer 522 is Pr1. Also, FIG. 3A is a schematic diagram showing the remanent polarization of the insulating layer 522 in the characteristic 291.

[0114] Because the remanent polarization Pr1 is positive, a positive voltage is generated on the semiconductor layer 520 side of the insulating layer 522. As a result, the Id-Vg characteristic of characteristic 290 shifts in the negative direction of Vg to become characteristic 291. That is, the threshold voltage of the transistor 10A shifts in the negative direction of Vg.

[0115] 3C, a characteristic 292 indicates the Id-Vg characteristic when the remanent polarization of the insulating layer 522 is Pr2. FIG. 3B is a schematic diagram showing the remanent polarization of the insulating layer 522 in the characteristic 292.

[0116] Because the remanent polarization Pr2 is negative, a negative voltage is generated on the semiconductor layer 520 side of the insulating layer 522. As a result, the Id-Vg characteristic of characteristic 290 shifts in the positive direction of Vg to become characteristic 292. That is, the threshold voltage of the transistor 10A shifts in the positive direction of Vg.

[0117] 3A to 3C, the Id-Vg characteristics of the transistor 10A can be changed depending on the remanent polarization of the insulating layer 522, which is a ferroelectric layer. In other words, the threshold voltage of the transistor 10A can be controlled by controlling the polarization of the insulating layer 522. Therefore, the transistor 10A can function as a memory cell.

[0118] For example, when binary data of data "0" or "1" is written to the transistor 10A functioning as a memory cell, the remanent polarization of the insulating layer 522 is set to Pr1 when data "1" is written, and the remanent polarization of the insulating layer 522 is set to Pr2 when data "0" is written. The Id-Vg characteristics of the transistor 10A in which data "1" is written become characteristic 291. The Id-Vg characteristics of the transistor 10A in which data "0" is written become characteristic 292.

[0119] [Variation 1] FIGS. 4A to 4D show a transistor 10B, which is a variation of the transistor 10A. FIG. 4A is a plan view of the transistor 10B that can be used for a memory device according to one embodiment of the present invention. FIG. 4B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG. 4A. FIG. 4C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in FIG. 4A. FIG. 4B is a cross-sectional view of the transistor 10B in the channel length direction, and FIG. 4C is a cross-sectional view of the transistor 10B in the channel width direction. FIG. 4D is a circuit symbol for the transistor 10B.

[0120] The transistor 10B has a configuration in which the insulating layer 524 is removed from the transistor 10A. If the leakage current of the insulating layer 522, which is a ferroelectric layer, is small, it is possible not to form the insulating layer 524. By not forming the insulating layer 524, the productivity of the transistor 10B can be improved. Furthermore, the productivity of a memory device including the transistor 10B can be improved.

[0121] [Variation 2] Figures 5A to 5D show a transistor 10C, which is a variation of the transistor 10A. Figure 5A is a plan view of the transistor 10C that can be used for a memory device of one embodiment of the present invention. Figure 5B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Figure 5A. Figure 5C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Figure 5A. Note that Figure 5B is a cross-sectional view of the transistor 10C in the channel length direction, and Figure 5C is a cross-sectional view of the transistor 10C in the channel width direction. Figure 5D is a circuit symbol for the transistor 10C.

[0122] The transistor 10C differs from the transistor 10A in that an insulating layer 523 is provided between the insulating layer 522 and the conductive layer 505. Note that the insulating layer 523 is provided to cover the conductive layer 505 and the insulating layer 516. For example, the insulating layer 523 can be formed using a material containing silicon and at least one of oxygen and nitrogen. Alternatively, for example, the insulating layer 523 can be formed using a material containing zirconium, yttrium, and oxygen. The insulating layer 523 can also have a stacked structure of multiple layers. For example, the insulating layer 523 can be formed using a stack of an insulating layer containing silicon nitride and an insulating layer containing zirconium oxide and yttrium oxide.

[0123] The insulating layer 523 is preferably a paraelectric material. By providing the insulating layer 523, which is a paraelectric layer, between the insulating layer 522, which is a ferroelectric layer, and the conductive layer 505, leakage current between the insulating layer 522 and the conductive layer 505 is reduced, thereby reducing the power consumption of the transistor 10C. Furthermore, the power consumption of a memory device including the transistor 10C can be reduced. Note that the transistor 10C is also a modified example of the transistor 10B.

[0124] In this specification, the transistors 10A, 10B, and 10C may be collectively referred to as the transistors 10.

[0125] <Constituent Materials of Semiconductor Device> Examples of materials that can be used for a semiconductor device (for example, the transistor 10) according to one embodiment of the present invention will be described.

[0126] [Substrate] When a semiconductor device is provided on a substrate, there are no significant limitations on the material used for the substrate. The material can be determined depending on the purpose, taking into consideration factors such as whether the substrate is light-transmitting or not and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Also usable are semiconductor substrates, flexible substrates, and resin substrates.

[0127] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0128] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are also substrates in which a conductor or a semiconductor is provided on an insulator substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate.

[0129] Examples of materials that can be used for flexible substrates or resin substrates include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofiber.

[0130] By using the above materials for the substrate, it is possible to provide a lightweight semiconductor device including the transistor 10. Furthermore, by using the above materials for the substrate, it is possible to provide a semiconductor device that is resistant to shocks. Furthermore, by using the above materials for the substrate, it is possible to provide a semiconductor device that is less likely to break.

[0131] Alternatively, a substrate provided with elements can be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0132] [Insulating Layer] For the insulating layer, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used. For example, the insulating layer can be formed using a single layer or a stack of insulating materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like. Alternatively, a single insulating layer can be formed using a plurality of materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials.

[0133] In this specification and elsewhere, a nitride oxide refers to a material containing more nitrogen than oxygen. An oxynitride refers to a material containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0134] As transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. By using high-k materials (high dielectric constant materials, materials with a high relative dielectric constant) for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, lead zirconate titanate, strontium titanate (SrTiO ３ ), barium strontium titanate ((Ba,Sr)TiO ３In some cases, a material with a high dielectric constant, such as SiO2, can be used. On the other hand, for the insulating layer that functions as an interlayer film, a material with a low dielectric constant can be used to reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select a material depending on the function required for the insulating layer.

[0135] Furthermore, examples of materials with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0136] Furthermore, materials with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin.

[0137] The method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and spin coating can be used.

[0138] For example, in the above-described transistor 10, the insulating layer 514 and the insulating layer 574 are preferably formed using an insulating material that is impermeable to impurities. For example, an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Examples of insulating materials that are impermeable to impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0139] By using an insulating material that is impervious to impurities for the insulating layer 514, it is possible to suppress the diffusion of impurities from below the insulating layer 514 and improve the reliability of the transistor 10. That is, it is possible to improve the reliability of a semiconductor device including the transistor 10. By using an insulating material that is impervious to impurities for the insulating layer 574, it is possible to suppress the diffusion of impurities from above the insulating layer 574 and improve the reliability of the transistor 10. That is, it is possible to improve the reliability of a semiconductor device including the transistor 10.

[0140] It is also preferable to use an insulating layer that can function as a planarizing layer as the insulating layer. Examples of materials that function as a planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimideamide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof. In addition to the above organic materials, low-k materials (low dielectric constant materials, materials with a small relative dielectric constant), siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), and the like can also be used. It is also possible to stack multiple insulating layers made of these materials.

[0141] The siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane resin may have an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

[0142] [Conductive Layer] Examples of conductive materials that can be used for conductive layers such as various wirings and electrodes that constitute a semiconductor device include metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and ruthenium (Ru), alloys containing the above-mentioned metal elements as components, and alloys combining the above-mentioned metal elements.

[0143] For example, conductive materials such as tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are also preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used. The method for forming the conductive material is not particularly limited, and various formation methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0144] Furthermore, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used as the conductive material. A layer formed of a Cu-X alloy can be processed by a wet etching process, which reduces manufacturing costs. Furthermore, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can be used as the conductive material.

[0145] In addition, conductive materials that can be used for the conductive layer include conductive materials containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon oxide has been added. Furthermore, conductive materials containing nitrogen, such as titanium nitride, tantalum nitride, and tungsten nitride, can also be used. The conductive layer can also have a stacked structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0146] For example, the conductive layer can have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, or a three-layer structure in which a titanium layer, an aluminum layer is stacked on the titanium layer, and a titanium layer is further stacked on top of that.

[0147] In addition, a plurality of conductive layers formed from the above-mentioned conductive materials can be stacked and used. For example, the conductive layer can have a stacked structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. In addition, the conductive layer can have a stacked structure in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. In addition, the conductive layer can have a stacked structure in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0148] For example, the conductive layer may have a three-layer structure in which a conductive layer containing at least one of indium or zinc and oxygen is stacked on a conductive layer containing copper, and a conductive layer containing at least one of indium or zinc and oxygen is further stacked on top of that. In this case, it is preferable that the side surface of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium or zinc and oxygen. Furthermore, for example, a plurality of conductive layers containing at least one of indium or zinc and oxygen may be stacked as the conductive layer.

[0149] [Semiconductor Layer] As the semiconductor layer 520, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Examples of compound semiconductors that can be used include organic materials having semiconductor properties and metal oxides having semiconductor properties (also referred to as "oxide semiconductors"). Note that these semiconductor materials may contain impurities as dopants.

[0150] For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be used for the semiconductor layer 520. For example, low temperature polysilicon (LTPS) can be used for the polycrystalline silicon.

[0151] A transistor using amorphous silicon for the semiconductor layer 520 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 520 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 520 has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed.

[0152] The semiconductor layer 520 can have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0153] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0154] [Metal Oxide Layer] The transistor 10 is preferably a transistor including an oxide semiconductor, which is a type of metal oxide, in the semiconductor layer 520 including a channel formation region (also referred to as an "OS transistor").

[0155] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide layer contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide layer. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide layer is reduced and the channel formation region in the metal oxide layer is made i-type (intrinsic) or substantially i-type.

[0156] On the other hand, the source and drain regions in the metal oxide layer functioning as a semiconductor of the OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, and have a high carrier concentration and low resistance due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0157] The band gap of the metal oxide layer functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide functioning as a semiconductor with a wide band gap for the semiconductor layer 520, the off-state current of the transistor 10 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has good frequency characteristics, the semiconductor device can operate at high speed.

[0158] A metal oxide that can be used for a semiconductor layer of an OS transistor preferably contains at least indium (In). The metal oxide preferably contains at least one of indium and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0159] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0160] For example, examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide (In oxide or indium oxide). Examples of the metal oxide include zinc oxide (Zn oxide or zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”), and indium. Examples of the usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0161] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0162] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0163] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0164] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0165] <Memory Cell Array> As described above, for example, a memory cell capable of storing 1-bit (binary) data can be realized using one transistor 10. This allows for a memory cell with a small area to be realized. By configuring a memory cell array by arranging multiple transistors 10 in m rows and n columns (m and n are each an integer of 2 or greater), a memory device with a high memory density can be realized. Furthermore, a memory device with a large memory capacity can be realized.

[0166] 6 shows an example of a memory cell array 100. The memory cell array 100 shown in Fig. 6 includes a plurality of transistors 10 arranged in a matrix of m rows and n columns, m wirings WL, m wirings SL, n wirings BL, and n wirings PL.

[0167] 6 and other figures, the transistor 10 arranged in the first row and first column is indicated as transistor 10[1,1], the transistor 10 arranged in the mth row and first column is indicated as transistor 10[m,1], the transistor 10 arranged in the first row and nth column is indicated as transistor 10[1,n], the transistor 10 arranged in the mth row and nth column is indicated as transistor 10[m,n], and the transistor 10 arranged in the ith row and jth column (i is an integer from 1 to m, and j is an integer from 1 to n) is indicated as transistor 10[i,j].

[0168] In addition, in FIG. 6 and other figures, when indicating the first wiring, [1] is added to the end of the symbol indicating that wiring. When indicating the mth wiring, [m] is added to the end of the symbol indicating that wiring. When indicating the nth wiring, [n] is added to the end of the symbol indicating that wiring. When indicating the ith wiring, [i] is added to the end of the symbol indicating that wiring. When indicating the jth wiring, [j] is added to the end of the symbol indicating that wiring.

[0169] The transistor 10[i,j] is connected to the wiring WL[i], the wiring SL[i], the wiring BL[j], and the wiring PL[j]. More specifically, the gate of the transistor 10[i,j] is connected to the wiring WL[i], and the back gate is connected to the wiring PL[j]. One of the source and the drain of the transistor 10[i,j] is connected to the wiring BL[j], and the other of the source and the drain is connected to the wiring SL[i].

[0170] <Operation Example> Next, a write operation, an erase operation, and a read operation of the transistor 10 in the memory cell array 100 will be described. In this embodiment, the description will be given using the memory cell array 100 in which m and n are each 2. In this embodiment and the like, the transistor 10 is always a normally-off type regardless of the data stored therein. Also, immediately before each operation, a potential V0 is supplied to the wiring BL, the wiring SL, the wiring PL, and the wiring WL.

[0171] The potential V0 is, for example, a reference potential (0 V). By supplying the potential V0 to the gate of the transistor 10, the transistor 10 is turned off regardless of the data stored therein. Note that in this embodiment and the like, a potential higher than the potential V0 may be marked with a "+" sign. A potential lower than the potential V0 may be marked with a "-" sign. A potential higher than the potential V0 may be referred to as a "positive potential." A potential lower than the potential V0 may be referred to as a "negative potential."

[0172] FIG. 7 is a timing chart for explaining the write operation, erase operation, and read operation.

[0173] <Write Operation> By making the potential difference between the gate and back gate of the transistor 10 to which data is not to be written smaller than the potential difference between the gate and back gate of the transistor 10 to which data is to be written, it is possible to prevent corruption of data held in the transistor 10 to which data is not to be written. The data write operation described in this embodiment can achieve highly reliable data write operation.

[0174] First, the operation of writing data "1" to transistor 10[1,1] functioning as a memory cell will be described. Period T11 shown in FIG. 7 is the period during which data "1" is written to transistor 10[1,1]. FIG. 8A is a circuit diagram showing the state of memory cell array 100 during period T11. Note that in circuit diagrams and the like, in order to clearly show the potential of wiring and the like, symbols indicating the potential of the wiring may be written adjacent to the wiring. Furthermore, symbols indicating the potential may be enclosed in text around wiring in which a potential change has occurred.

[0175] In the period T11, a potential +VW is supplied to the wiring PL[1], and a potential +V1 is supplied to the wiring WL[2] (see FIGS. 7 and 8A). For example, +VSP is supplied to the wiring PL[1] as the potential +VW. Then, the potential +VW (here, +VSP) is supplied to the back gate of the transistor 10[1,1]. In addition, a potential V0, which is a reference potential, is supplied to the gate of the transistor 10[1,1]. Therefore, the remnant polarization of the insulating layer 522 becomes Pr1, and the Id-Vg characteristics of the transistor 10[1,1] become the characteristics 291 (see FIGS. 3A and 3C).

[0176] The wiring PL[1] is also connected to the transistor 10[2,1]. When the data "0" is stored in the transistor 10[2,1], if the potential of the wiring WL[2] remains at the potential V0, the data stored in the transistor 10[2,1] may be rewritten to the data "1." Therefore, by supplying a potential +V1 to the wiring WL[2], it is possible to prevent the data in the transistor 10[2,1] from being rewritten.

[0177] In addition, by supplying a potential +V1 to the wiring WL[2], the potential +V1 is set to be higher than the potential V0 and lower than the potential +VW in order to prevent data held in the transistor 10[2,2] connected to the wiring WL[2] from being rewritten.

[0178] For this reason, the potential +V1 is preferably an intermediate potential between the potential V0 and the potential +VW. Specifically, the potential +V1 is preferably a potential that is ±20% of the average value of the potential V0 and the potential +VW, more preferably a potential that is ±10% of the average value, and even more preferably a potential that is the average value.

[0179] By supplying the potential +V1, which is an intermediate potential between the potential V0 and the potential +VW, to the gate of the transistor 10 to which data is not to be written, the potential difference between the gate and back gate of the transistor 10 to which data is not to be written is reduced, thereby preventing unintended polarization inversion of the insulating layer 522.

[0180] Next, an operation of writing data "0" to transistor 10[1,1] functioning as a memory cell will be described. A period T12 shown in FIG. 7 is a period during which data "0" is written to transistor 10[1,1]. FIG. 8B is a circuit diagram showing the state of memory cell array 100 during period T12.

[0181] In the period T12, a potential -VW is supplied to the wiring PL[1], and a potential -V1 is supplied to the wiring WL[2] (see FIGS. 7 and 8B). For example, -VSP is supplied to the wiring PL[1] as the potential -VW. Then, the potential -VW (here, -VSP) is supplied to the back gate of the transistor 10[1,1]. In addition, a potential V0, which is a reference potential, is supplied to the gate of the transistor 10[1,1]. Therefore, the remnant polarization of the insulating layer 522 becomes Pr2, and the Id-Vg characteristics of the transistor 10[1,1] become the characteristics 292 (see FIGS. 3A and 3C).

[0182] The wiring PL[1] is also connected to the transistor 10[2,1]. When the data "1" is stored in the transistor 10[2,1], if the potential of the wiring WL[2] remains at the potential V0, the data stored in the transistor 10[2,1] may be rewritten to the data "0." Therefore, by supplying a potential -V1 to the wiring WL[2], it is possible to prevent the data in the transistor 10[2,1] from being rewritten.

[0183] In addition, by supplying a potential -V1 to the wiring WL[2], the potential -V1 is set to be lower than the potential V0 and higher than the potential -VW in order to prevent data held in the transistor 10[2,2] connected to the wiring WL[2] from being rewritten.

[0184] For this reason, the potential −V1 is preferably an intermediate potential between the potentials V0 and −VW. Specifically, the potential −V1 is preferably a potential that is ±20% of the average value of the potentials V0 and −VW, more preferably a potential that is ±10% of the average value, and even more preferably a potential that is the average value.

[0185] By supplying the potential −V1, which is an intermediate potential between the potential V0 and the potential −VW, to the gate of the transistor 10 to which data is not to be written, the potential difference between the gate and back gate of the transistor 10 to which data is not to be written is reduced, thereby preventing unintended polarization inversion of the insulating layer 522.

[0186] Here, if the absolute value of the potentials +VW and -VW is "potential VW" and the absolute value of the potentials +V1 and -V1 is "potential V1," then the potential difference between potential V1 and potential V0 is preferably about half the potential difference between potential VW and potential V0. Therefore, the potential difference between potential V1 and potential V0 is preferably ±20% of half the potential difference between potential VW and potential V0, more preferably ±10% of half the potential difference between potential VW and potential V0, and even more preferably ±5% of half the potential difference between potential VW and potential V0.

[0187] That is, the potential difference between potential V1 and potential V0 is preferably 30% or more and 70% or less of the potential difference between potential VW and potential V0, more preferably 40% or more and 60% or less of the potential difference between potential VW and potential V0, and even more preferably 45% or more and 55% or less of the potential difference between potential VW and potential V0.

[0188] A similar write operation can also be realized in a memory cell array 100 in which m and n are each 3 or greater. Specifically, when data "1" is written to the transistor 10[i,j], a potential +VW is supplied to the j-th wiring PL (wiring PL[j]), a potential V0 is supplied to the i-th wiring WL (wiring WL[i]), and a potential +V1 is supplied to the wirings WL other than the i-th wiring. When data "0" is written to the transistor 10[i,j], a potential -VW is supplied to the wiring PL[j], a potential V0 is supplied to the wiring WL[i], and a potential -V1 is supplied to the wirings WL other than the i-th wiring.

[0189] In other words, when data is written to the transistor 10[i,j], a potential VW is supplied to the wiring PL[j], a potential V0 is supplied to the wiring WL[i], and a potential V1 is supplied to the wiring WL other than the i-th wiring. By making the potential difference between the wiring WL other than the wiring WL[i] and the wiring PL[j] smaller than the potential difference between the wiring WL[i] and the wiring PL[j], it is possible to prevent data stored in the transistor 10 that is not the target of data writing (the transistor 10 other than the transistor 10[i,j]) from being destroyed. The data write operation described in this embodiment enables highly reliable data write operation.

[0190] If the potential difference between wiring WL[i] and wiring PL[j] is the first potential difference, and the potential difference between wiring WL other than the i-th wiring and wiring PL[j] is the second potential difference, the second potential difference is preferably 30% to 70% of the first potential difference, more preferably 40% to 60%, and even more preferably 45% to 55%.

[0191] After the data is written, a potential V0 is supplied to the wiring BL, the wiring SL, the wiring PL, and the wiring WL, thereby retaining the written data. The transistor 10 according to one embodiment of the present invention has a function of storing written data depending on the direction of remanent polarization of the insulating layer 522, which is a ferroelectric layer. Therefore, the written data can be stored even when power supply to the transistor 10 is stopped. Therefore, the transistor 10 according to one embodiment of the present invention can function as a nonvolatile memory element. A memory device including the transistor 10 according to one embodiment of the present invention can function as a nonvolatile memory device.

[0192] <Erase Operation> In this embodiment, data erasure is achieved by, for example, writing data "0" to the transistor 10. In this case, the erase operation is the same as the operation of writing data "0" to the transistor 10. That is, the erase operation can be achieved by setting the polarization of the insulating layer 522 to the remanent polarization Pr2.

[0193] For example, by supplying a potential V0 to all m wirings WL and a potential −VW to the j-th wiring PL, data of the transistors 10 arranged in the j-th column can be erased all at once. For example, by supplying a potential V0 to all m wirings WL and a potential −VW to all n wirings PL, data of all transistors 10 included in the memory cell array 100 can be erased all at once.

[0194] Although the above example shows that data is erased by writing data "0" to the transistor 10, the present invention can also be applied to a case where data is erased by writing data "1" to the transistor 10. In this case, the potential supplied to the wiring PL for data erasure is set to the potential +VW.

[0195] The simultaneous erase operation can also be called a simultaneous write operation of data "0" or data "1".

[0196] <Read Operation> Next, an operation of reading data stored in the transistor 10[1,1] functioning as a memory cell will be described. Periods T13 and T14 shown in FIG. 7 are periods during which data stored in the transistor 10[1,1] is read. FIG. 9A is a circuit diagram showing the state of the memory cell array 100 during period T13. FIG. 9B is a circuit diagram showing the state of the memory cell array 100 during period T14.

[0197] In the period T13, the potential VBL is supplied to the wiring BL[1] (see FIGS. 7 and 9A). The potential V0 is supplied to the wiring BL connected to the transistor 10 arranged in a column that is not a target for data reading. However, the wiring BL can be in an electrically floating state.

[0198] Next, in period T14, potential VR is supplied to wiring WL[1] (see FIGS. 7 and 9B). Potential VR is a potential that turns on transistor 10 when transistor 10 holds data "1." Potential VR is a potential that keeps transistor 10 off when transistor 10 holds data "0." That is, potential VR is a potential that is higher than the threshold voltage when the remanent polarization of insulating layer 522 of transistor 10 is Pr1 and lower than the threshold voltage when the remanent polarization of insulating layer 522 is Pr2. For example, potential VR is preferably 1 / 5 to 1 / 2, more preferably 1 / 4 to 1 / 3, of potential +VW (+VSP) when potential VO is used as a reference.

[0199] If the potential difference between the potential VR and the potential VO is defined as a third potential difference, and the potential difference between the potential +VW and the potential VO is defined as a fourth potential difference, the third potential difference is preferably 20% to 50% of the fourth potential difference, and more preferably 25% to 30%. That is, the third potential difference is preferably 20% to 50% of +VSP, and more preferably 25% to 30%.

[0200] Furthermore, during a data read operation, by minimizing the potential difference between the gate and back gate of the transistor 10 that is not a data read target, corruption of data held in the transistor 10 that is not a data read target can be prevented. In other words, when reading data held in the transistor 10[i, j], by minimizing the potential difference between the wiring WL other than the i-th wiring and the j-th wiring PL, corruption of data held in the transistor 10 that is not a data read target (transistor 10 other than the transistor 10[i, j]) can be prevented. The data read operation described in this embodiment can achieve highly reliable data read operation.

[0201] During a data read operation, the potential difference between the wiring WL other than the i-th wiring and the j-th wiring PL is preferably 0 V or more and 1 / 6 or less of the potential +VW (+VSP), more preferably 0 V or more and 1 / 10 or less of the potential +VW.

[0202] When the transistor 10[1,1], which is the data read target, holds data "1," the transistor 10[1,1] is turned on when the potential VR is supplied to the wiring WL[1]. When the transistor 10[1,1] is turned on, a current Id1 flows between the wiring BL[1] and the wiring SL[1] through the channel formation region of the transistor 10[1,1] (see FIG. 3C).

[0203] When the transistor 10[1,1] from which data is to be read holds data "0," the transistor 10[1,1] is not turned on but remains off even when the potential VR is supplied to the wiring WL[1]. In other words, the data held in the transistor 10[1,1] can be read by measuring the value of the current flowing through the wiring BL[1] or the wiring SL[1].

[0204] Furthermore, after supplying a potential VBL to the wiring BL[1] in the period T13, the wiring BL[1] is set in a floating state, and the change in the potential of the wiring BL[1] is measured in the period T14, so that the data stored in the transistor 10[1,1] can be read.

[0205] In the period T13, the potential of the wiring SL connected to the transistor 10 arranged in a row that is not a target for data reading is the potential V0. However, as shown in the period T23 in FIG. 7, the potential VBL can be supplied to the wiring (the potential of the wiring SL[2] in FIG. 7). By supplying the potential VBL to the wiring, an unintended current can be prevented from flowing between the wiring BL[1] and the wiring, thereby reducing noise components and improving the accuracy of data reading.

[0206] In other words, when data held in the transistor 10[i,j] is read, in the period T13, a potential VBL is supplied to the j-th wiring BL (wiring BL[j]) and a potential V0 is supplied to the i-th wiring SL (wiring SL[i]) to generate a potential difference between the wiring BL[j] and the wiring SL[i]. Subsequently, in the period T14, a potential VR is supplied to the wiring WL[i] and the current value flowing through the wiring BL[j] or the wiring SL[i] is measured, thereby enabling the data held in the transistor 10[i,j] to be read. Alternatively, after the potential VBL is supplied to the wiring BL[j] in the period T13, the wiring BL[j] is brought into a floating state, and a change in the potential of the wiring BL[j] is measured in the period T14, thereby enabling the data held in the transistor 10[i,j] to be read.

[0207] In this embodiment, since the transistor 10 is an n-channel transistor, a positive potential is used as the potential VBL. The potential difference between the wiring BL and the wiring SL may invert the remanent polarization of the insulating layer 522, which is a ferroelectric layer, and may destroy data stored in the transistor 10. To prevent data destruction during a read operation, the potential difference between the potential VBL and the potential V0 is preferably ½ or less, more preferably ⅓ or less, of the potential difference between the potential +VW and the potential V0. On the other hand, if the potential difference between the potential VBL and the potential V0 is too small, the accuracy of data reading decreases. Therefore, the potential difference between the potential VBL and the potential V0 is preferably ½ or more, more preferably ⅕ or more, and less than ⅓ of the potential difference between the potential +VW and the potential V0. That is, the potential difference between the potential VBL and the potential V0 is preferably ½ or more, more preferably ⅕ or more, and less than ⅓ of the saturation polarization voltage +VSP.

[0208] The transistor 10 according to one embodiment of the present invention functions as a memory cell. Furthermore, the transistor 10 according to one embodiment of the present invention does not require a refresh operation that is required in, for example, a DRAM. Therefore, a memory device with low power consumption can be realized.

[0209] Furthermore, the transistor 10 according to one embodiment of the present invention uses a paraelectric material for the insulating layer 550 functioning as a gate insulating layer and a ferroelectric material for the insulating layer 522 functioning as a back-gate insulating layer. Generally, data is read more frequently than data is written. Therefore, the insulating layer 550 is exposed to more voltage stress than the insulating layer 522. Repeated application of voltage stress to the ferroelectric layer makes the remanent polarization of the ferroelectric layer more likely to change, resulting in a decrease in reliability of data retention. Therefore, by using a paraelectric material for the insulating layer 550 functioning as a gate insulating layer and a ferroelectric material for the insulating layer 522 functioning as a back-gate insulating layer, the reliability of the transistor 10 can be improved. Furthermore, the reliability of a memory device including the transistor 10 can be improved.

[0210] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0211] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of the transistor 10 according to one embodiment of the present invention will be described.

[0212] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0213] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0214] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be described below. Fig. 11A is a schematic diagram showing the carrier concentration dependence of the Hall mobility for silicon (Si) and indium oxide (InOx), and Fig. 11B is a schematic diagram showing the carrier concentration dependence of the Hall mobility for IGZO.

[0215] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 11B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 11A (see Non-Patent Document 6). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 11A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 11A.

[0216] 11A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0217] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0218] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0219] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0220] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 11A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0221] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0222] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 11B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 11A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0223] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0224] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0225] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0226] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0227] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0228] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0229] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0230] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0231] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0232] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0233] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0234] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0235] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 11C, oxygen (O) diffusing into an indium oxide film (denoted as InOx) passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0236] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0237] 11C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0238] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0239] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0240]

[0241] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0242] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0243] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0244] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0245] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0246] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0247] Embodiment 3 In this embodiment, a memory device 900, which is one type of semiconductor device according to one embodiment of the present invention, will be described. The memory device 900 includes a plurality of transistors 10 according to one embodiment of the present invention.

[0248] Fig. 12A shows a block diagram illustrating a configuration example of a memory device 900. Figs. 12B and 12C are schematic perspective views of the memory device 900. The memory device 900 shown in Fig. 12A includes a driver circuit 910 and a memory cell array 100. The memory cell array 100 includes a plurality of transistors 10 that function as memory cells. Fig. 12A shows an example in which the memory cell array 100 includes a plurality of transistors 10 arranged in a matrix.

[0249] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0250] In the storage device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0251] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0252] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the memory device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0253] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0254] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell array 100. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0255] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell array 100, the function of reading data from the memory cell array 100, the function of holding the read data, etc.

[0256] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell array 100. The data (Dout) read from the memory cell array 100 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. The output circuit 926 also has a function of outputting Dout to the outside of the memory device 900. The data output from the output circuit 926 is a signal RDA.

[0257] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply potential of the memory device 900 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 12A, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0258] 12B , the memory device 900 may be configured such that a driver circuit 910 is provided in the element layer 70, a memory cell array 100 is provided in the element layer 80, and the element layer 80 is stacked on the element layer 70. For example, a single-crystal silicon substrate may be used as the element layer 70, and the driver circuit 910 may be formed on the silicon substrate. By forming the channel formation region of the Si transistor included in the driver circuit 910 on the silicon substrate, a Si transistor having a single-crystal semiconductor in the channel formation region and having a high operating speed may be formed.

[0259] By stacking the element layer 70 including the driver circuit 910 and the element layer 80 including the memory cell array 100, the signal propagation distance between the driver circuit 910 and the memory cell array 100 can be shortened. Therefore, the parasitic resistance and parasitic capacitance between the driver circuit 910 and the memory cell array 100 are reduced, and power consumption and signal delay can be reduced. Furthermore, the memory device 900 can be made smaller. Furthermore, the memory capacity per unit area can be increased.

[0260] For example, an SOI substrate or the like can be used as the element layer 70. Examples of SOI substrates that can be used include a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that occur in the surface layer, a Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, and an ELTRAN method (registered trademark: Epitaxial Layer Transfer). Si transistors fabricated using an SOI substrate have reduced parasitic capacitance and can achieve high-speed operation.

[0261] Furthermore, it is preferable to use an OS transistor as the transistor 10 included in the memory cell array 100. Because an OS transistor is a thin film transistor, it is easy to provide the element layer 80 overlapping the element layer 70. In addition, as described above, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, even if the memory cell array 100 including an OS transistor is provided overlapping the driver circuit 910 including a Si transistor, it is less susceptible to heat generated by the driver circuit 910. Therefore, the reliability of the memory device 900 can be improved.

[0262] 12C , it is possible to provide a plurality of element layers 80 including a memory cell array 100 stacked on an element layer 70 including a driver circuit 910. FIG. 12C shows an example in which k (k is an integer of 2 or more) element layers 80 are stacked on the element layer 70. In FIG. 12C , the first element layer 80 provided on the element layer 70 is shown as element layer 80[1], and the kth element layer 80 is shown as element layer 80[k]. Furthermore, the memory cell array 100 provided in the element layer 80[k] is shown as memory cell array 100[k].

[0263] By stacking the element layer 70 including the driver circuit 910 and the element layer 80 including the memory cell array 100, the signal propagation distance between the driver circuit 910 and the memory cell array 100 can be shortened. Therefore, the parasitic resistance and parasitic capacitance between the driver circuit 910 and the memory cell array 100 are reduced, and power consumption and signal delay can be reduced. Furthermore, the memory device 900 can be made smaller. Furthermore, the memory capacity per unit area can be increased.

[0264] 13 shows an example of a cross-sectional structure of a portion of the memory device 900 shown in FIG. 13 illustrates one transistor 400 as an example of the plurality of transistors included in the element layer 70. Also, in FIG. 13, one transistor 10 is illustrated as an example of the plurality of transistors included in each of the element layers 80[1] and 80[2].

[0265] The transistor 400 is provided over a substrate 371 and includes a conductive layer 376 that functions as a gate electrode, an insulating layer 375 that functions as a gate insulating layer, a semiconductor region 373 that is part of the substrate 371, and low-resistance regions 374a and 374b that are part of the substrate 371 and function as source and drain regions. The transistor 400 may be either a p-channel transistor or an n-channel transistor. The substrate 371 may be, for example, a single crystal silicon substrate.

[0266] In the transistor 400, a semiconductor region 373 (a part of the substrate 371) where a channel is formed has a convex shape. A conductive layer 376 is provided to cover the side and top surfaces of the semiconductor region 373 with an insulating layer 375 interposed therebetween. Note that the conductive layer 376 may be made of a material that adjusts the work function. Such a transistor is also called a Fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that functions as a mask for forming the convex portion may be provided in contact with the top of the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0267] The driver circuit 910 includes a plurality of transistors 400. Note that the transistor 400 can be used not only as a transistor included in the driver circuit 910 but also as a transistor included in another circuit (not shown) formed in the element layer 70. Note that the transistor 400 shown in FIG. 13 is an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0268] The element layer 70 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0269] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 392 and the like are embedded in the insulating layer 390 and the insulating layer 391. A conductive layer 395, a conductive layer 397, and the like are embedded in the insulating layer 393 and the insulating layer 394. The conductive layer 392 and the conductive layer 395 function as contact plugs or wirings.

[0270] The insulating layer functioning as an interlayer film may also function as a planarizing film that covers the uneven shape below it. For example, the top surface of the insulating layer 391 may be subjected to CMP treatment or the like to improve the planarity.

[0271] 13, an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 385, a conductive layer 386, and a conductive layer 397 are formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 385, the conductive layer 386, and the conductive layer 397 function as contact plugs or wirings.

[0272] 13, an insulating layer 202 of the element layer 80[1] is provided over the insulating layer 384. In the element layer 80[1] shown in FIG. 13, a conductive layer 583 and an insulating layer 582 are provided over the insulating layer 581. The conductive layer 583 is formed so as to be embedded in the insulating layer 581. The conductive layer 583 is connected to the conductive layer 545a. An insulating layer 584 is provided over the conductive layer 583 and the insulating layer 582, and an insulating layer 585 is provided over the insulating layer 584. The insulating layer 202 of the element layer 80[2] is provided over the insulating layer 585 of the element layer 80[1].

[0273] The element layer 80[1] and the element layer 80[2] each include a plurality of transistors 10 functioning as memory cells. By providing a plurality of element layers 80 overlapping the element layer 70, the memory capacity per unit area of ​​the memory device 900 can be further increased.

[0274] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0275] Embodiment 4 In this embodiment, an example of a processing device that can include a memory device according to one embodiment of the present invention will be described.

[0276] 14 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 14 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0277] The arithmetic device 960 shown in FIG. 14 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0278] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0279] As will be described later, a memory cell array 100 can be provided by stacking it on an arithmetic unit 960. The memory cell array 100 can also be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory cell array 100 to the cache 999. In this case, it is preferable that a drive circuit 910 is provided as part of the cache interface 989.

[0280] It is also possible to use only the memory cell array 100 as a cache without providing the cache 999 .

[0281] The arithmetic device 960 shown in FIG. 14 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 14 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0282] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0283] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0284] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0285] 14, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 996 can be stopped.

[0286] The memory cell array 100 and the arithmetic device 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 15A and 15B. The semiconductor device 970A has a layer 930 on which memory cell arrays are provided, on an arithmetic device 960. The layer 930 is provided with a memory cell array 100L1, a memory cell array 100L2, and a memory cell array 100L3. The arithmetic device 960 and each memory cell array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in FIG. 15B.

[0287] By overlapping the layer 930 having the memory cell array and the arithmetic device 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, the short connection distance can reduce power consumption.

[0288] As a method for stacking the layer 930 having the memory cell array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having the memory cell array is stacked directly on the arithmetic device 960 can be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and connection is made using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) can be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0289] Here, the arithmetic device 960 does not have a cache 999, and the memory cell array 100L1, memory cell array 100L2, and memory cell array 100L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory cell array 100L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory cell array 100L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory cell array 100L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory cell arrays, the memory cell array 100L3 has the largest capacity and the lowest access frequency. Furthermore, the memory cell array 100L1 has the smallest capacity and the highest access frequency.

[0290] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory cell array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0291] 15B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory cell array 100L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory cell array 100L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory cell array 100L3 via a connection electrode 940L3.

[0292] Although the number of memory cell arrays functioning as caches is three in this example, the number of memory cell arrays functioning as caches is not limited to three. The number of memory cell arrays functioning as caches can be one, two, or four or more.

[0293] When the memory cell array 100L1 is used as a cache, the drive circuit 910L1 can be configured to function as part of the cache interface 989, or the drive circuit 910L1 can be configured to be connected to the cache interface 989. Similarly, the drive circuits 910L2 and 910L3 can also be configured to function as part of the cache interface 989, or the drive circuits 910L3 can be configured to be connected to the cache interface 989.

[0294] Whether the memory cell array 100 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the multiple transistors 10 included in the memory device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0295] The memory device 900 can cause the plurality of transistors 10 functioning as memory cells or some of the plurality of transistors 10 to function as a cache, and the remaining part to function as a main memory. That is, the memory device 900 can function as both a cache and a main memory. The memory device 900 according to one aspect of the present invention can function as, for example, a universal memory.

[0296] It is also possible to provide a layer 930 having one memory cell array 100 overlapping the arithmetic device 960. Fig. 16A shows a perspective view of a semiconductor device 970B.

[0297] In the semiconductor device 970B, one memory cell array 100 can be divided into multiple areas, each of which can be used for a different function. Fig. 16A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0298] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0299] It is also possible to stack a plurality of memory cell arrays. Figure 16B shows a perspective view of a semiconductor device 970C.

[0300] The semiconductor device 970C includes a layer 930L1 having a memory cell array 100L1, a layer 930L2 having a memory cell array 100L2 on top of that, and a layer 930L3 having a memory cell array 100L3 on top of that. The memory cell array 100L1, which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory cell array 100L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory cell array to be increased, thereby further improving processing power.

[0301] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0302] Embodiment 5 In this embodiment, an example of the applicability of a storage device according to one embodiment of the present invention will be described with reference to FIGS.

[0303] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 17 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 17, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0304] In FIG. 17 , from the top layer of the triangle, memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs, and storage memories such as 3D NANDs and hard disks (also called HDDs: hard disk drives) are shown.

[0305] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0306] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0307] The memory device according to one embodiment of the present invention can also function as a DRAM.

[0308] 17 illustrates only up to the L3 cache, but the cache memory is not limited to this. For example, a storage device according to one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0309] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0310] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0311] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0312] By using an OS transistor in the memory device according to one embodiment of the present invention, it can be monolithically integrated with the peripheral circuitry. Furthermore, the use of an OS transistor allows monolithic stacking with the peripheral circuitry. This provides advantages in terms of data access to the peripheral circuitry. Furthermore, the memory device according to one embodiment of the present invention can be stacked with the peripheral circuitry, thereby increasing the degree of integration. Furthermore, the memory device according to one embodiment of the present invention can retain data for a long period of time. Therefore, when the memory device according to one embodiment of the present invention is used as a DRAM, the frequency of refresh can be reduced.

[0313] Furthermore, in the memory device according to one embodiment of the present invention, leakage current can be reduced by using an OS transistor, and power saving can be achieved. Furthermore, in the memory device according to one embodiment of the present invention, a ferroelectric layer is included in the back-gate insulating layer, and thus data can be retained for a long time.

[0314] A storage device according to one embodiment of the present invention can be used for the Target2 area and the Target1 area of ​​the storage device illustrated in FIG.

[0315] 17, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC mentioned above.

[0316] By replacing a DRAM with a memory device according to one embodiment of the present invention, power consumption can be reduced. This configuration can reduce power consumption to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, of that of a configuration using a DRAM. Therefore, the memory device according to one embodiment of the present invention is suitable for Target 1.

[0317] Furthermore, a storage device according to one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, a storage device according to one embodiment of the present invention is particularly suitable for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying a storage device according to one embodiment of the present invention to Target1_1, the reliability of the semiconductor device can be improved. Furthermore, the degree of integration of the semiconductor device functioning as a storage device can be increased. Furthermore, the power consumption of the semiconductor device functioning as a storage device can be reduced.

[0318] Furthermore, the memory device according to one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and is therefore suitable for Target1_2, which is rewritten more frequently than Target1. By applying the memory device according to one embodiment of the present invention to Target1_2, the computational efficiency of the semiconductor device can be improved and power consumption can be reduced.

[0319] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM (including a storage device according to one embodiment of the present invention) is stacked on a processing device such as a CPU, GPU, or NPU. A configuration in which a processing device and a storage device are stacked is called a monolithic stack. By configuring the processing device and the storage device as a monolithic stack, for example, it is possible to significantly reduce the power consumption required for data access between the processing device and the storage device. Therefore, by deploying information processing devices including supercomputers (also called HPCs (High Performance Computers)), computers, servers, etc. that employ such a configuration throughout the world, it is possible to mitigate global warming.

[0320] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0321] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0322] Embodiment 6 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the memory device according to one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0323] [Electronic Component] FIG. 18A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 18A has memory device 710 in mold 711. Memory device 900 described in the above embodiment can be used as memory device 710. FIG. 18A omits some details in order to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to memory device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0324] The memory device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0325] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0326] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0327] The memory device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0328] 18B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 710 provided on the interposer 731.

[0329] The electronic component 730 shows an example in which the memory device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, an NPU, or an FPGA (Field Programmable Gate Array).

[0330] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0331] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, a TSV can also be used as the through electrode.

[0332] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0333] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0334] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space corresponding to the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure can be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0335] It is also preferable to provide a heat sink (heat dissipation plate) overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 710 and the height of the semiconductor device 735.

[0336] In order to mount the electronic component 730 on another substrate, it is preferable to provide electrodes 733 on the bottom of the package substrate 732. Fig. 18B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 can also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0337] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0338] 19A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0339] 19B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0340] Fig. 19C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629, etc., which are mounted on the board 5622. Note that Fig. 19C illustrates components other than electronic components 5626, 5627, and 5628.

[0341] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0342] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0343] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0344] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0345] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0346] [Space Equipment] A semiconductor device according to one aspect of the present invention is suitable for space equipment.

[0347] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0348] Fig. 20A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 20A shows a planet 6804 in space as an example.

[0349] 20A, a battery management system (also referred to as a BMS) or a battery control circuit is preferably provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0350] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0351] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0352] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0353] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has higher reliability than a Si transistor in an environment where radiation may be incident.

[0354] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0355] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0356] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0357] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0358] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0359] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0360] Fig. 20B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 20B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0361] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 can be connected to each other via a network.

[0362] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0363] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0364] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0365] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0366] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0367] 10: transistor, 30: capacitor, 51: curve, 52: curve, 70: element layer, 80: element layer, 100: memory cell array, 201: substrate, 202: insulating layer, 290: characteristics, 291: characteristics, 292: characteristics, 371: substrate, 373: semiconductor region, 375: insulating layer, 376: conductive layer, 382: insulating layer, 384: insulating layer, 385: conductive layer, 386: conductive layer, 390: insulating layer, 391: insulating layer, 392: conductive layer, 393: insulating layer, 394: insulating layer, 395: conductive layer, 396: insulating layer, 397: conductive layer, 400: transistor, 505: conductive layer, 514: insulating layer, 516: insulating layer, 520: semiconductor layer, 522: insulating layer, 523: insulating layer, 524: insulating layer, 541: insulating layer, 542: conductive layer, 545: conductive layer, 550: insulating layer, 554: insulating layer, 560: conductive layer, 574: insulating layer, 580: insulating layer, 581: insulating layer, 582: insulating layer, 583: conductive layer, 584: insulating layer, 585: insulating layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: storage device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: Interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: memory device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 960: arithmetic unit, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: interface instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6000: storage system,6001: Host, 6002: Storage control circuit, 6003: Storage, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 10[1,1]: Transistor, 10[1,n]: Transistor, 10[2,1]: Transistor, 10[2,2]: Transistor, 10[i,j]: Transistor, 1 0[m,1]: transistor, 10[m,n]: transistor, 100[k]: memory cell array, 10A: transistor, 10B: transistor, 10C: transistor, 374a: low resistance region, 374b: low resistance region, 505a: conductive layer, 505b: conductive layer, 520a: semiconductor layer, 520b: semiconductor layer, 541a: insulating layer, 541b: insulating layer, 542a: conductive layer, 542b: conductive layer, 545a: conductive layer, 545b: conductive layer, 560a: conductive layer, 560b: conductive layer, 6001sb: server, 6003md: storage device, 80[1]: element layer, 80[2]: element layer, 80[k]: element layer, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, ADDR: signal, BL: wiring, BL[1]: wiring, BL[j]: wiring, BW: signal, CE: signal, CLK: signal, GW: signal, PL: wiring, P L[1]: wiring, PL[j]: wiring, RDA: signal, SL: wiring, SL[1]: wiring, SL[2]: wiring, SL[i]: wiring, T11: period, T12: period, T13: period, T14: period, T23: period, TrP: transistor, TrQ: transistor, VBL: potential, VR: potential, VW: potential, WAKE: signal, WDA: signal, WL: wiring, WL[1]: wiring, WL[2]: wiring, WL[i]: wiring,

Claims

1. A memory device having a plurality of transistors arranged in a matrix of m rows and n columns (m and n are each an integer of 2 or greater), m wirings WL, m wirings SL, n wirings BL, and n wirings PL, wherein a gate of the transistor arranged in the ith row and jth column (i is an integer of 1 to m, j is an integer of 1 to n) is electrically connected to the ith wiring WL, one of a source or a drain of the transistor arranged in the ith row and jth column is electrically connected to the jth wiring BL, the other of the source or the drain of the transistor arranged in the ith row and jth column is electrically connected to the ith wiring SL, and a back gate of the transistor arranged in the ith row and jth column is electrically connected to the jth wiring PL, and each of the plurality of transistors has a paraelectric gate insulating layer and a ferroelectric back gate insulating layer.

2. The memory device according to claim 1, wherein each of the plurality of transistors contains indium and oxygen in a semiconductor layer in which a channel is formed.

3. A memory device according to claim 1, wherein the gate insulating layer contains silicon and oxygen, and the back gate insulating layer contains one or both of hafnium and zirconium and oxygen.

4. A method for driving a memory device having a plurality of transistors arranged in a matrix of m rows and n columns (m and n are each an integer of 2 or greater), m wirings WL, m wirings SL, n wirings BL, and n wirings PL, wherein a gate of the transistor arranged in the ith row and jth column (i is an integer of 1 to m, j is an integer of 1 to n) is electrically connected to the ith wiring WL, one of a source or a drain of the transistor arranged in the ith row and jth column is electrically connected to the jth wiring BL, the other of the source or the drain of the transistor arranged in the ith row and jth column is electrically connected to the ith wiring SL, and a back gate of the transistor arranged in the ith row and jth column is electrically connected to the jth wiring PL, and each of the plurality of transistors has a paraelectric gate insulating layer and a ferroelectric back gate insulating layer, A method for driving a memory device, wherein a potential difference between a wiring WL other than the i-th wiring and the j-th wiring PL is made larger than a second potential difference, and data is written to the transistor arranged in the i-th row and j-th column.

5. A method for driving a storage device according to claim 4, wherein the second potential difference is 30% to 70% of the first potential difference.

6. A method for driving a memory device according to claim 4 or claim 5, wherein a potential V0 is supplied to the i-th wiring SL, a potential VBL higher than the potential V0 is supplied to the j-th wiring BL, and then a potential VR is supplied to the i-th wiring WL, a current value flowing through the j-th wiring BL is measured, and data held in the transistor arranged in the i-th row and j-th column is read out.

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