Switching element

Abstract

A gate-type switching element according to the present invention comprises: a semiconductor substrate which has a first trench and a second trench on an upper surface; and a gate electrode which is provided in the first trench and the second trench. A region between the first trench and the second trench has an n-type source layer, a low-concentration n-type layer, a p-type body layer, a p-type contact layer, and an n-type drift layer. The low-concentration n-type layer is disposed below the source layer, is in contact with a gate insulating film at side surfaces of the first trench and the second trench, and has a lower n-type impurity concentration than the source layer. The body layer is disposed below the low-concentration n-type layer. The contact layer extends from the upper surface of the semiconductor substrate to the body layer, and is in contact with the low-concentration n-type layer. The drift layer is disposed below the body layer. The space between the first trench and the second trench corresponds to a space where a FinFET effect occurs.

Description

Switching element

[0001] The technology disclosed in this specification relates to a switching element.

[0002] The switching element disclosed in GB 2572442A has multiple trench-type gate electrodes. In this switching element, the spacing between the trenches (i.e., the width of the body layer) is narrower than that of a typical switching element. Therefore, when an on-potential is applied to the gate electrode, the depletion layers formed on both sides of the body layer connect to each other, reducing the depletion layer charge. This increases the inversion layer charge, forming an inversion layer far from the gate interface (i.e., the interface between the gate insulating film and the semiconductor). Therefore, when electrons flow through the inversion layer, the effect of reduced mobility due to the gate interface is suppressed. Therefore, this switching element can reduce channel resistance. In this specification, the effect of reduced channel resistance due to narrow spacing between the trenches (i.e., the width of the fin-shaped body layer) is referred to as the FinFET effect.

[0003] In a switching element in which the FinFET effect occurs, an inversion layer is easily formed, and therefore the gate threshold is low. This specification proposes a technique for realizing a high gate threshold in a switching element in which the FinFET effect occurs.

[0004] The gate-type switching element disclosed in this specification includes a semiconductor substrate, a gate insulating film, and a gate electrode. The semiconductor substrate is made of a wide-gap semiconductor and has a first trench and a second trench on its upper surface. The gate insulating film covers the inner surfaces of the first trench and the second trench. The gate electrode is provided within the first trench and the second trench. A region of the semiconductor substrate between the first trench and the second trench includes a source layer, a low-concentration n-type layer, a body layer, a contact layer, and a drift layer. The source layer is an n-type layer that contacts the gate insulating film on the side surfaces of the first trench and the second trench. The low-concentration n-type layer is disposed below the source layer, contacts the gate insulating film on the side surfaces of the first trench and the second trench, and is a low-concentration n-type layer with a lower n-type impurity concentration than the source layer. The body layer is a p-type layer disposed below the low-concentration n-type layer, distributed from the side surface of the first trench to the side surface of the second trench, and in contact with the gate insulating film at the side surfaces of the first trench and the second trench. The contact layer is a p-type layer extending from the top surface of the semiconductor substrate to the body layer and in contact with the low-concentration n-type layer. The drift layer is an n-type layer disposed below the body layer and in contact with the gate insulating film at the side surfaces of the first trench and the second trench. The distance between the first trench and the second trench is the distance at which the FinFET effect occurs.

[0005] The source layer may be composed of an n-type layer distributed from the side surface of the first trench to the side surface of the second trench, or may be composed of multiple n-type layers separately provided on the side surfaces of the first trench and the second trench.

[0006] Furthermore, the low-concentration n-type layer may be composed of an n-type layer distributed from the side surface of the first trench to the side surface of the second trench, or may be composed of a plurality of n-type layers provided separately on the side surface of the first trench and the side surface of the second trench.

[0007] A wide-gap semiconductor is a semiconductor having a band gap wider than that of silicon. Examples of wide-gap semiconductors include silicon nitride (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ ), diamond, etc.

[0008] In this switching element, a low-concentration n-type layer is provided between the body layer and the source layer. When the gate potential is increased to turn on the switching element, an inversion layer is formed in the body layer and an electron accumulation layer is formed in the low-concentration n-type layer. Therefore, electrons flow from the source layer through the accumulation layer and inversion layer to the drift layer. Due to the FinFET effect, the on-resistance of this switching element is low. Furthermore, because the p-type contact layer is in contact with the low-concentration n-type layer, the carrier concentration in the low-concentration n-type layer is low. Therefore, the gate potential required to form the accumulation layer is higher than the gate potential required to form the inversion layer. Therefore, this structure can achieve a high gate threshold.

[0009] 1 is a cross-sectional view of a switching element 10; a graph showing an impurity concentration distribution in the z direction; a cross-sectional view showing a process of turning on the switching element 10; a cross-sectional view showing a process of turning on the switching element 10; a cross-sectional view showing a process of turning on the switching element 10; a graph showing a carrier density distribution in the z direction; a graph showing a relationship between width W and gate threshold Vth; a graph showing a relationship between width W when the FinFET effect occurs and p-type impurity concentration N Ａ 10 is a graph showing the switching element as a function of .theta.. The cross-sectional view of a modified example of the switching element.

[0010] The switching element 10 of the embodiment shown in Figure 1 is a trench-type metal-oxide-semiconductor field effect transistor (MOSFET). The switching element 10 has a semiconductor substrate 12. In each figure, the z direction is the thickness direction of the semiconductor substrate 12, the x direction is a direction parallel to the upper surface 12a of the semiconductor substrate 12, and the y direction is a direction parallel to the upper surface 12a and perpendicular to the x direction. The semiconductor substrate 12 is made of silicon nitride (i.e., SiC).

[0011] A plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. The trenches 14 are arranged at intervals in the x direction. Although two trenches 14a and 14b are shown in FIG. 1 as representative examples, many more trenches 14 are arranged at equal intervals in the x direction. Each trench 14 extends along the y direction on the upper surface 12a of the semiconductor substrate 12.

[0012] The switching element 10 has a gate insulating film 20, a gate electrode 22, an interlayer insulating film 24, a source electrode 26, and a drain electrode 28. The gate insulating film 20 covers the inner surface of each trench 14. The gate electrode 22 is disposed in each trench 14. Each gate electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 20. Each interlayer insulating film 24 covers the upper surface of the gate electrode 22. The source electrode 26 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 26 is insulated from the gate electrode 22 by the interlayer insulating film 24. The drain electrode 28 covers the lower surface 12b of the semiconductor substrate 12.

[0013] The region of the semiconductor substrate 12 sandwiched between the two trenches 14 is referred to as the inter-trench semiconductor region 30. Since each inter-trench semiconductor region 30 has the same structure, the following description will focus on the inter-trench semiconductor region 30 between trench 14 a and trench 14 b. As shown in FIG. 1 , each inter-trench semiconductor region 30 includes a source layer 32, a low-concentration n-type layer 34, a contact layer 36, a body layer 38, and a drift layer 40.

[0014] Two source layers 32a, 32b are provided in one inter-trench semiconductor region 30. Each source layer 32 is an n-type layer with a high n-type impurity concentration. Each source layer 32 is disposed at the upper end of the inter-trench semiconductor region 30 and is in ohmic contact with the source electrode 26. The source layer 32a contacts the gate insulating film 20 on the side surface of the trench 14a. The source layer 32b contacts the gate insulating film 20 on the side surface of the trench 14b.

[0015] Two low-concentration n-type layers 34a, 34b are provided in one inter-trench semiconductor region 30. Each low-concentration n-type layer 34 is an n-type layer having a lower n-type impurity concentration than the source layer. The low-concentration n-type layer 34a contacts the source layer 32a from below. The low-concentration n-type layer 34a contacts the gate insulating film 20 on the side surface of the trench 14a. The low-concentration n-type layer 34b contacts the source layer 32b from below. The low-concentration n-type layer 34b contacts the gate insulating film 20 on the side surface of the trench 14b.

[0016] The contact layer 36 is disposed at the center of the inter-trench semiconductor region 30 in the x direction. The contact layer 36 extends along the z direction from the upper surface 12 a. The contact layer 36 has a high p-type impurity concentration. The contact layer 36 is in ohmic contact with the source electrode 26.

[0017] The body layer 38 is a p-type layer having a lower p-type impurity concentration than the contact layer 36. The body layer 38 is in contact with the low-concentration n-type layers 34a, 34b and the contact layer 36 from below. The body layer 38 is connected to the source electrode 26 via the contact layer 36. The body layer 38 is continuously distributed from the side surface of the trench 14a to the side surface of the trench 14b. The body layer 38 is in contact with the gate insulating film 20 on the side surface of the trench 14a, and is in contact with the gate insulating film 20 on the side surface of the trench 14b.

[0018] The drift layer 40 is an n-type layer having a low concentration of n-type impurities. The drift layer 40 contacts the body layer 38 from below. The drift layer 40 is distributed from within each inter-trench semiconductor region 30 to below each trench 14. In the region below each trench 14, the drift layer 40 is distributed over almost the entire area of ​​the semiconductor substrate 12 in the x and y directions. In the inter-trench semiconductor region 30, the drift layer 40 contacts the gate insulating film 20 on the side surface of trench 14a and on the side surface of trench 14b. The drift layer 40 is separated from each low-concentration n-type layer 34 by the body layer 38.

[0019] A drain layer 42 is provided below the drift layer 40. The drain layer 42 is an n-type layer having a higher n-type impurity concentration than the drift layer 40. The drain layer 42 is in contact with the drift layer 40 from below. The drain layer 42 is in ohmic contact with the drain electrode 28 on the lower surface 12b of the semiconductor substrate 12.

[0020] 2 shows the concentration distribution in the z direction inside the semiconductor substrate 12. As shown in FIG. 2, the n-type impurity concentration of the low-concentration n-type layer 34 is lower than the n-type impurity concentration of the source layer 32 and higher than the n-type impurity concentration of the drift layer 40. The n-type impurity concentration of the low-concentration n-type layer 34 is 1×10 １９ cm －３ In this embodiment, the n-type impurity concentration of the low-concentration n-type layer 34 is lower than the p-type impurity concentration of the body layer 38. However, in other embodiments, the n-type impurity concentration of the low-concentration n-type layer 34 may be higher than the p-type impurity concentration of the body layer 38.

[0021] The interval W between the trenches 14 (i.e., the width of the inter-trench semiconductor region 30 in the x-direction) is narrower than that of a typical gate-type MOSFET. For example, the interval W is 400 nm or less. As will be described in detail later, the interval W is set to a value that allows the FinFET effect to be obtained when the switching element 10 is turned on.

[0022] The switching element 10 is used with a higher potential applied to the drain electrode 28 than to the source electrode 26. When the potential of the gate electrode 22 (hereinafter referred to as the gate potential) is sufficiently low, no inversion layer is formed in the body layer 38. In addition, in this state, the low-concentration n-type layer 34 is depleted by a depletion layer extending from the contact layer 36, and the carrier density in the low-concentration n-type layer 34 is extremely low. Thus, when the gate potential is sufficiently low, no current path exists in the body layer 38 and the low-concentration n-type layer 34, and the switching element 10 is off.

[0023] As shown in FIG. 3 , when the gate potential is gradually increased without forming an inversion layer, a depletion layer 90 is formed in the body layer 38 near the gate insulating film 20. Further increasing the gate potential expands the depletion layer 90 in the x direction, and the left and right depletion layers 90 merge at the center of the body layer 38. As shown in FIG. 4 , further increasing the gate potential accumulates electrons, which are minority carriers, in the body layer 38 near the gate insulating film 20, forming an inversion layer 92. Even with the inversion layer 92 formed, the switching element 10 does not turn on because no current path exists in the low-concentration n-type layer 34. As shown in FIG. 5 , further increasing the gate potential expands the inversion layer 92 in the x direction, and the left and right inversion layers 92 merge at the center of the body layer 38. Therefore, the resistance of the inversion layer 92 (i.e., channel resistance) decreases due to the FinFET effect. Even in this state, the switching element 10 does not turn on because no current path exists in the low-concentration n-type layer 34. 6, when the gate potential is further increased, electrons accumulate in the region of the low-concentration n-type layer 34 near the gate insulating film 20, forming an accumulation layer 94. Then, the source layer 32 and the drift layer 40 are connected by the accumulation layer 94 and the inversion layer 92. As a result, electrons flow from the source layer 32 to the drift layer 40 via the accumulation layer 94 and the inversion layer 92. That is, the switching element 10 is turned on. In this way, the switching element 10 is turned on when the accumulation layer 94 is formed. Therefore, the gate potential when the accumulation layer 94 is formed becomes the gate threshold value.

[0024] Because the inversion layer 92 is formed throughout the entire body layer 38 in the x-direction, electrons can flow within the body layer 38 at a location away from the gate interface (i.e., the boundary between the gate insulating film 20 and the semiconductor substrate 12). Therefore, electrons are less likely to be scattered by the gate interface states, etc., and the resistance when electrons flow within the body layer 38 is low. Thus, the FinFET effect reduces the channel resistance in the body layer 38. Furthermore, when the low-concentration n-type layer 34 is provided, the on-resistance increases by the amount of the accumulation layer 94 compared to when the low-concentration n-type layer 34 is not provided. However, the increase in on-resistance due to the provision of the low-concentration n-type layer 34 is much smaller than the decrease in on-resistance due to the FinFET effect. According to a simulation, the decrease in on-resistance due to the FinFET effect was approximately 33%, while the increase in on-resistance due to the addition of the low-concentration n-type layer 34 was approximately 5%. Therefore, the structure of the switching element 10 of this embodiment can achieve a low on-resistance.

[0025] Furthermore, in a switching element 10 exhibiting the FinFET effect, the depletion layers 90 extending from the left and right gate insulating films 20 are coupled within the body layer 38, which facilitates depletion of the body layer 38 and the formation of an inversion layer 92 in the body layer 38. Without the low-concentration n-type layer 34, the switching element turns on when the inversion layer 92 is formed, resulting in a low gate threshold. In contrast, in a switching element 10 according to an embodiment including the low-concentration n-type layer 34, as shown in FIG. 5 , when the inversion layer 92 is formed in the body layer 38, no current path exists in the low-concentration n-type layer 34, and the switching element 10 does not turn on. When the gate potential is further increased to form an accumulation layer 94 in the low-concentration n-type layer 34 as shown in FIG. 6 , the switching element 10 turns on. Because the accumulation layer 94 is formed after the inversion layer 92, the gate threshold of the switching element 10 is determined by the gate potential when the accumulation layer 94 is formed. As a result, the switching element 10 has a high gate threshold. According to a simulation, it was confirmed that the gate threshold value increases by 1.5 V when the low-concentration n-type layer 34 is provided, compared to when the low-concentration n-type layer 34 is not provided.

[0026] In this embodiment, the p-type contact layer 36 is adjacent to the low-concentration n-type layer 34, thereby realizing a structure in which the accumulation layer 94 is formed after the inversion layer 92. Providing the p-type contact layer 36 adjacent to the low-concentration n-type layer 34 causes a depletion layer to extend from the contact layer 36 to the low-concentration n-type layer 34. Because the width of the depletion layer tends to be wide in wide bandgap semiconductors, providing the contact layer 36 can reduce the carrier density of the entire low-concentration n-type layer 34. In particular, since the contact layer 36 has a higher p-type impurity concentration than the body layer 38, it is possible to significantly reduce the carrier density of the low-concentration n-type layer 34. By reducing the carrier density of the low-concentration n-type layer 34, the accumulation layer 94 can be formed after the inversion layer 92 when the gate potential is increased. Figure 7 shows the results of a simulation of the carrier densities in the body layer 38 and the low-concentration n-type layer 34 near the gate insulating film 20 for gate potentials Vg of 0 to 10 V. 7, when the gate potential is increased, the carrier density is less likely to increase in the low-concentration n-type layer 34 than in the body layer 38. Therefore, when the gate potential is increased, an inversion layer 92 is formed in the body layer 38, and then an accumulation layer 94 is formed in the low-concentration n-type layer 34. This makes it possible to achieve a high gate threshold value.

[0027] Furthermore, in a switching element 10 in which the FinFET effect occurs, the ease with which an inversion layer 92 is formed varies depending on the distance W between the trenches 14. This is because the depletion layers 90 extending from the left and right gate insulating films 20 combine within the body layer 38 when the gate potential is increased. If the low-concentration n-type layer 34 is not provided, the switching element turns on when the inversion layer 92 is formed, and therefore the gate threshold varies depending on the distance W between the trenches 14. FIG. 8 shows the relationship between the distance W between the trenches 14 and the gate threshold Vth when the low-concentration n-type layer 34 is not provided. Note that in FIG. 8, the p-type impurity concentration N Ａ But 1.0 x 10 １７ cm －３ , 3.4 × 10 １７ cm －３ , 5.0 × 10 １７ cm －３The p-type impurity concentration N Ａ In either case, the narrower the spacing W, the lower the gate threshold Vth. Therefore, without the low-concentration n-type layer 34, the variation in gate threshold Vth increases. In contrast, in the switching element 10 of the embodiment having the low-concentration n-type layer 34, as described above, the gate threshold Vth is determined by the gate potential when the accumulation layer 94 is formed. Therefore, the spacing W between the trenches 14 has almost no effect on the gate threshold. Therefore, the variation in gate threshold can be suppressed. According to a simulation, when the spacing W was changed from 180 nm to 140 nm, the gate threshold of the switching element without the low-concentration n-type layer 34 decreased by approximately 1.8 V, while the decrease in gate threshold of the switching element 10 with the low-concentration n-type layer 34 was approximately 0.5 V. Thus, the provision of the low-concentration n-type layer 34 can suppress the variation in gate threshold.

[0028] 8, the FinFET effect occurs in a region where the distance W between trenches is smaller than the dashed line 100. FIG. 9 shows the relationship between the dashed line 100 in FIG. 8 and the width W (nm) and the p-type impurity concentration N Ａ (cm －３ 9, the dashed line 100 indicates the coordinate system W=3.52×10 １１ N Ａ －０．５２６ The width W is expressed as a function of W<3.52×10 １１ N Ａ －０．５２６ Since the FinFET effect can be obtained when the width W satisfies this inequality.

[0029] The above describes the embodiment. Note that in FIG. 1 , two source layers 32 and two low-concentration n-layers 34 are provided. However, as shown in FIG. 10 , the source layer 32 may extend from the trench 14 a to the trench 14 b, and the low-concentration n-layer 34 may extend from the trench 14 a to the trench 14 b. In this case, by partially providing the contact layer 36 in the y direction, the contact layer 36 can be adjacent to the low-concentration n-layer 34.

[0030] Furthermore, in the above-described embodiment, the semiconductor substrate 12 is made of SiC, but the semiconductor substrate 12 may be made of other wide bandgap semiconductors.

[0031] The configurations of the switching elements disclosed in this specification are listed below. (Configuration 1) A gate-type switching element comprising: a semiconductor substrate made of a wide-gap semiconductor and having a first trench and a second trench on an upper surface thereof; a gate insulating film covering the inner surfaces of the first trench and the second trench; and a gate electrode provided in the first trench and the second trench; wherein a region of the semiconductor substrate between the first trench and the second trench comprises: an n-type source layer in contact with the gate insulating film on side surfaces of the first trench and the second trench; a low-concentration n-type layer located below the source layer, in contact with the gate insulating film on side surfaces of the first trench and the second trench, and having a lower n-type impurity concentration than the source layer; a p-type body layer located below the low-concentration n-type layer, distributed from the side surface of the first trench to the side surface of the second trench, and in contact with the gate insulating film on side surfaces of the first trench and the second trench; and a p-type contact layer extending from the upper surface of the semiconductor substrate to the body layer and in contact with the low-concentration n-type layer. a gate insulating film formed on a side surface of the first trench and the second trench, and an n-type drift layer disposed below the body layer and in contact with the gate insulating film on a side surface of the first trench and the second trench, wherein a distance between the first trench and the second trench is a distance at which a FinFET effect occurs. (Configuration 2) A switching element comprising: a semiconductor substrate made of silicon carbide; １９ cm －３ The switching element according to the first aspect, wherein the distance W (nm) between the first trench and the second trench and the p-type impurity concentration N Ａ (cm －３ ) but W<3.52×10 １１ N Ａ －０．５２６The switching element according to configuration 1 or 2, wherein the relationship is satisfied. (Configuration 4) The switching element according to any one of configurations 1 to 3, wherein the p-type impurity concentration of the contact layer is higher than the p-type impurity concentration of the body layer.

[0032] According to the second configuration, a high gate threshold can be achieved in a switching element using a silicon carbide semiconductor.

[0033] According to the configuration 3, the FinFET effect is preferably produced.

[0034] According to the configuration 4, a higher gate threshold can be achieved.

[0035] Although the embodiments have been described in detail above, they are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

Claims

1. A gate-type switching element comprising: a semiconductor substrate (12) made of a wide-gap semiconductor and having a first trench (14a) and a second trench (14b) on its upper surface; a gate insulating film (20) covering the inner surfaces of the first trench and the second trench; and a gate electrode (22) provided in the first trench and the second trench, wherein a region (30) of the semiconductor substrate between the first trench and the second trench comprises: an n-type source layer (32) in contact with the gate insulating film on the side surfaces of the first trench and the second trench; a low-concentration n-type layer (34) disposed below the source layer, in contact with the gate insulating film on the side surfaces of the first trench and the second trench, and having a lower n-type impurity concentration than the source layer; and a p-type body layer (38) disposed below the low-concentration n-type layer, distributed from the side surfaces of the first trench to the side surfaces of the second trench, and in contact with the gate insulating film on the side surfaces of the first trench and the second trench. a p-type contact layer (36) extending from the upper surface of the semiconductor substrate to the body layer and in contact with the low-concentration n-type layer; and an n-type drift layer (40) disposed below the body layer and in contact with the gate insulating film on side surfaces of the first trench and the second trench, wherein a distance between the first trench and the second trench is a distance at which a FinFET effect occurs.

2. The semiconductor substrate is made of silicon carbide, and the n-type impurity concentration of the low-concentration n-type layer is 1×10 １９ cm －３ The switching element of claim 1 , wherein:

3. The distance W (nm) between the first trench and the second trench and the p-type impurity concentration N Ａ (cm －３ ) but W<3.52×10 １１ N Ａ －０．５２６ The switching element according to claim 1 or 2, which satisfies the relationship:

4. The switching element according to claim 1 or 2, wherein the p-type impurity concentration of the contact layer is higher than the p-type impurity concentration of the body layer.

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