Memory cell and memory device including same

Abstract

A memory cell according to one embodiment and a memory device including same comprise: a first transistor having a source and a drain and formed, in a first doped region based on a second type, on a substrate based on a first type; a second transistor arranged on the substrate based on the first type; and a third transistor arranged on the substrate based on the first type and having a second doped region well based on the second type, a source and a drain formed, in the doped region based on the first type, on the second doped region well based on the second type, and a depletion channel formed between the source and the drain, wherein a signal corresponding to a value set in a storage node (SN) can be stored on a first rod to which the first transistor, the second transistor, and the third transistor are connected.

Description

Memory cell and memory device including same

[0001] Hereinafter, a technology is provided for a memory cell in which an opposite type of depletion mode read transistor is added to a structure in which a capacitance is formed through a storage node formed at a connection portion of a read transistor and a write transistor.

[0002] AI semiconductors can be viewed as specialized non-memory semiconductors that perform the large-scale computations required for AI services at ultra-high speeds and low power consumption. While CPUs (Central Processing Units) and GPUs (Graphics Processing Units) can process AI, they are not specifically designed for AI. This can lead to performance waste outside of AI computation, and inefficiencies such as cost and power consumption can arise. Therefore, dedicated AI semiconductors can be used to complement the limitations of basic semiconductors for AI computation (e.g., excessive power consumption and reduced computational efficiency). While AI semiconductors may not be universally applicable, they are optimized for AI algorithms, allowing them to deliver optimal power consumption and fast processing speeds for AI data processing.

[0003] In the memory semiconductor field, along with the development of AI semiconductor technology, development of memory semiconductor technology for AI data processing is also taking place. The amount of data exchanged between CPUs and memory for AI data processing is increasing, which can frequently lead to delays in processing tasks. This means that while the CPU can process tasks quickly, a bottleneck may occur when retrieving information from memory. To address this issue, technologies such as High Bandwidth Memory (HBM), Process Near Memory (PNM), Processing-in-Memory (PIM), and Computing-in-Memory (CIM) are being developed in the memory semiconductor field. HBM refers to a technology that increases the number of channels between the CPU and memory. PIM also refers to a technology in which the CPU and memory exist within a single electronic package, while CIM refers to a technology in which the CPU and memory are combined.

[0004] The background technology described above is technology that the inventor possessed or acquired in the process of deriving the disclosure of the present application, and cannot necessarily be said to be publicly known technology disclosed to the general public prior to the present application.

[0005] A memory cell and a memory device including the same according to one embodiment may configure a 3T0C DRAM memory cell in which a new transistor is connected in series to a read transistor of a 2T0C DRAM memory cell.

[0006] A memory cell and a memory device including the same according to one embodiment may further include a depletion mode read PMOS connected to an increase mode read NMOS, such that the channel conductivity of the depletion mode read PMOS increases, unlike the channel conductivity of the increase mode read NMOS, which decreases even when a storage node voltage (VSN) decreases.

[0007] However, technical challenges are not limited to the technical challenges described above, and other technical challenges may exist.

[0008] A memory cell according to one embodiment includes a first transistor having a source and a drain formed in a first doped region based on a second type on a substrate based on a first type, a second transistor arranged on the substrate based on the first type, and a third transistor arranged on the substrate based on the first type, wherein a second doped region well based on the second type is formed, the third transistor having a source and a drain formed in the doped region based on the first type on the second doped region well based on the second type, and a depletion channel formed between the source and the drain, and the first transistor, the second transistor, and the third transistor can store a signal corresponding to a value set at a storage node (SN) on a first rod connected to which the first transistor, the second transistor, and the third transistor are connected.

[0009] The first load may be connected to the drain of the first transistor, the gate of the second transistor, and the gate of the third transistor, and the drain of the second transistor and the source of the third transistor may be connected to the second load.

[0010] The absolute value of the threshold voltage of the third transistor may be greater than the absolute value of the threshold voltage (VT) of the second transistor.

[0011] The number of the second transistor and the third transistor may be at least one.

[0012] The above first type may be a p type, and the above second type may be an n type.

[0013] The substrate based on the first type may include B (Boron), and the first doping region based on the second type may include As (Arsenic).

[0014] The second doped region well based on the second type may include a lower concentration of As than the first doped region well based on the second type, and the doped region based on the first type may include a higher concentration of B than the substrate based on the first type.

[0015] The above first type may be an n type, and the above second type may be a p type.

[0016] The second load may be connected in series with the drain of the second transistor and the source of the third transistor.

[0017] A memory device including a memory cell according to one embodiment includes a word line each configured with a plurality of first word lines and a plurality of second word lines, a bit line each configured with a plurality of first bit lines and a plurality of second bit lines, a first transistor connected to one first word line of the plurality of first word lines and one first bit line of the plurality of first bit lines, a second transistor connected to one second word line of the plurality of second word lines, and a third transistor connected to one second bit line of the plurality of second bit lines, wherein the second transistor and the third transistor are transistors of opposite types.

[0018] A memory cell and a memory device including the same according to one embodiment constitute a 3T0C DRAM memory cell in which a new transistor is serially connected to the read transistor of a 2T0C DRAM memory cell, thereby increasing a read current (I READ ) by reducing the amount of change in the storage node voltage (V) at the same speed. SN ) can reduce the deterioration of the accuracy of PIM operations and reduce energy consumption due to refresh operations.

[0019] A memory cell and a memory device including the same according to one embodiment further include a depletion mode read PMOS connected to an increase mode read NMOS, wherein the storage node voltage (V SN ) decreases, unlike the channel conductance of the increasing mode read NMOS, which decreases as well, the channel conductance of the depletion mode read PMOS increases, which can cause the accuracy of AI operations in PIM to decrease slowly, thereby also reducing the frequency of the refresh operation.

[0020] Figure 1 illustrates an example circuit diagram of a 2T0C DRAM unit cell.

[0021] FIG. 2 illustrates an exemplary circuit diagram of a 3T0C DRAM memory cell according to one embodiment.

[0022] FIG. 3 illustrates an example of a 3T0C DRAM memory cell structure according to one embodiment.

[0023] FIG. 4 illustrates cross-sections of a 3T0C DRAM memory cell according to one embodiment.

[0024] FIG. 5 illustrates an exemplary circuit diagram of a 3T0C DRAM memory cell according to one embodiment.

[0025] FIG. 6a illustrates an exemplary transfer characteristic of a read transistor configured in a 3T0C DRAM memory cell according to one embodiment, and FIG. 6b illustrates an exemplary transfer characteristic of a read transistor configured in a 3T0C DRAM memory cell according to one embodiment.

[0026] FIG. 7 illustrates channel conductivity in a 3T0C DRAM memory cell structure according to one embodiment.

[0027] FIG. 8 is an exemplary circuit diagram simulating the channel conductivity of a 3T0C DRAM memory cell as a resistor according to one embodiment.

[0028] Figure 9 shows the storage node voltage (V) for a 2T0C DRAM unit cell and a 3T0C DRAM memory cell according to one embodiment. SN ) is shown as an example of a graph of the read channel conductance according to the decrease in the

[0029] FIG. 10 illustrates an exemplary circuit diagram of a memory device including a 3T0C DRAM memory cell according to one embodiment.

[0030] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Therefore, the actual implementation is not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or alternatives within the technical concepts described in the embodiments.

[0031] Although terms such as "first" or "second" may be used to describe various components, these terms should be interpreted solely to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

[0032] When it is said that a component is "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0033] Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "has" should be understood to indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but not to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0035] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted.

[0036] Transformers, a natural language processing model, are driving innovation in the AI ​​field. AI algorithms like Transformers are widely used, demonstrating high performance not only in natural language processing but also in fields such as computer vision and speech recognition. Consequently, demand for AI algorithms is increasing across various fields, and their related performance is also rapidly improving. Higher performance requires more data processing, and efficient processing of large amounts of data requires additional alternatives. Computing architectures for computation typically utilize the von Neumann architecture. The von Neumann architecture uses a bus to transfer data between the processor and memory, enabling computations. Therefore, computing large amounts of data can involve significantly more data transfer than typical data operations. Consequently, processing large amounts of data can require significant processing time and, consequently, significant power consumption, making the von Neumann architecture inefficient for AI computation.

[0037] To address this, the processing-in-memory (PIM) computing architecture, an alternative, minimizes data traffic by enabling data storage and computation within memory. Due to the aforementioned characteristics, PIM is well-suited for AI computations that process large amounts of data and can be an efficient computing architecture in terms of both time and power consumption. Memory devices used in PIM include SRAM and DRAM. However, SRAM has limited capacity due to its low density, making DRAM, with its high density and high throughput, a suitable candidate. Furthermore, DRAM's high throughput makes it even more useful for AI computations that process large amounts of data, ensuring high-speed operation and low power consumption.

[0038] Figure 1 illustrates an example circuit diagram of a 2T0C DRAM unit cell.

[0039] A 2T0C DRAM (two-transistor zero-capacitor dynamic random access memory) can be configured with a structure having two transistors and zero capacitors. In other words, a 2T0C DRAM can include two transistors without a capacitor. 2T0C DRAM may be suitable for AI operations due to its advantages such as high speed, low power, and non-destructive read operation. A 2T0C DRAM unit cell may include an enhancement mode write MOSFET and an enhancement mode read MOSFET. In a 2T0C DRAM unit cell, the drain of the enhancement mode write MOSFET may be connected to the gate of the enhancement mode read MOSFET. A storage node may be formed between the connected write MOSFET and read MOSFET. The 2T0C DRAM unit cell has a parasitic capacitance (C) present in the storage node. SN ), data (e.g., a value indicated by a charge or a voltage corresponding to a charge) can be stored and read. The charge stored in the parasitic capacitance is referred to as the storage node voltage (V SN ) can be formed. The formed storage node voltage (V SN ) can serve as the gate voltage of the read transistor. The storage node voltage (V SN ) can affect the channel conductivity of the read transistor.

[0040] 2T0C DRAM, a volatile device, loses stored charge due to leakage current over time after storing data. The charge loss is caused by a decrease in the channel conductance of the read transistor during a read operation and a read current (I READ ) causes a decrease in the read current (I READ ) can lead to a decrease in the accuracy of AI operations in PIM. Accordingly, 2T0C DRAM memory frequently requires refresh operations (re-writes) to rewrite data at regular intervals to maintain high accuracy, and frequent refresh operations can result in high power consumption.

[0041] In one embodiment, a memory cell comprises a 3T0C DRAM memory cell in which a new transistor is connected in series to the read transistor of a 2T0C DRAM memory cell, thereby increasing the read current (I READ ) by reducing the amount of change in the storage node voltage (V) at the same speed. SN ) can reduce the deterioration of the accuracy of PIM operations and reduce energy consumption due to refresh operations.

[0042] FIG. 2 illustrates an exemplary circuit diagram of a 3T0C DRAM memory cell according to one embodiment.

[0043] A memory cell (200) according to one embodiment (e.g., a 3T0C DRAM memory cell) may include three transistors without a capacitor. However, the number of the second transistor (220) and the third transistor (230) in the structure of the memory cell is not limited to that shown in FIG. 2, and the number of transistors included per memory cell may vary depending on the design. An additional example is described in FIG. 5.

[0044] A memory cell (200) may include a first transistor (210), a second transistor (220), and a third transistor (230). The first transistor (210) may be a write transistor, and the second transistor (220) and the third transistor (230) may be read transistors. The second transistor (220) and the third transistor (230) may have opposite types (e.g., polarities). For example, the second transistor (220) may be of a second type (e.g., n type), and the third transistor (230) may be of a first type (e.g., p type). The number of the second transistor (220) and the third transistor (230) in the memory cell (200) may be at least one.

[0045] The source (213) of the first transistor (210) may be connected to a write bit line (WBL) through a load (e.g., a fourth load (260)), and the gate (212) of the first transistor (210) may be connected to a write word line (WWL) through a load (e.g., a third load (250)). For reference, although it has been described in this specification that each terminal (e.g., a source, a drain, a gate) and / or a line of an individual transistor is connected through a rod (e.g., a metal rod), it is not limited thereto.

[0046] The second transistor (220) and the third transistor (230) may be connected in series. For example, the drain of the second transistor (220) and the source of the third transistor (230) may be connected. The source (223) of the second transistor (220) may be connected to a read word line (RWL) through a load (e.g., a fifth load (270)). The drain (233) of the third transistor (230) may be connected to a read bit line (RBL) through a sixth load (290). The gates of the second transistor (220) and the third transistor (230) may be connected to the same node (e.g., a storage node (SN)). As illustrated in FIG. 2, the drain (211) of the first transistor (210) may also be connected to the storage node (SN). A parasitic capacitor (C) is formed in the storage node (SN) to which the drain (211) of the first transistor (210), the gate (222) of the second transistor (220), and the gate (232) of the third transistor (230) are connected. SN ) can be formed. As described above, a parasitic capacitor (C SN ) can represent a data value according to the voltage value stored in the charge.

[0047] As will be described later in FIGS. 6A and 6B, the third transistor (230) may have an absolute value of a threshold voltage that is higher than the absolute value of the threshold voltage of the second transistor (220) while having a polarity opposite to that of the second transistor (220). For example, the second transistor (220) may be an n-type transistor in an increase mode, and the third transistor (230) may be a p-type transistor in a depletion mode. Then, when the voltages applied to the second transistor (220) and the third transistor (230) are lower than or equal to the corresponding threshold voltages but greater than 0, the transfer characteristics (e.g., current versus voltage) of the second transistor (220) and the transfer characteristics of the third transistor (230) may exhibit opposite tendencies. For example, the second transistor (220) may have a voltage (V) of the storage node in a voltage range greater than the corresponding threshold voltage (e.g., the first threshold voltage). SN ) can have an increasing current as the voltage of the storage node increases. Conversely, the third transistor (230) can have an increasing current as the voltage of the storage node increases in a voltage range that is less than the corresponding threshold voltage (e.g., the second threshold voltage) and greater than 0. SN ) can have a decreasing current as the voltage of the storage node (V SN ) may exhibit opposite voltage-to-current transfer characteristics in at least some of the voltage ranges where the voltage is greater than 0. Accordingly, as illustrated in FIG. 9 described below, the channel conductance reduction occurring in the second transistor (220) may be alleviated by the third transistor (230). Compared to the 2T0C DRAM structure of the comparative embodiment illustrated in FIG. 1, the memory cell (200) (e.g., 3TC0 DRAM) according to the embodiment illustrated in FIG. 2 exhibits a voltage (V) of the storage node SN ) can be maintained for a longer period of time.

[0048] Figures 3 and 4 below illustrate exemplary implementations of memory cells according to the circuit diagram of Figure 2. Figure 3 exemplarily illustrates a 3T0C DRAM memory cell structure according to one embodiment.

[0049] A 3T0C memory cell (200) may include a first transistor (210), a second transistor (220), and a third transistor (230).

[0050] The first transistor (210) may have a source (213) and a drain (211) formed in a first doped region based on a second type on a substrate (214) based on a first type. The second transistor (220) may be arranged on the substrate (214) based on the first type. For example, the second transistor (220) may have the same structure as the first transistor (210). In this case, the first transistor (210) and the second transistor (220) may be transistors of the second type (e.g., n type). However, the present invention is not limited thereto, and the second transistor (220) may have a gate length and width different from those of the first transistor (210). In addition, the second transistor (220) may be a transistor of a first type (e.g., p type) different from that of the first transistor (210).

[0051] The third transistor (230) may be a transistor of a first type (e.g., p-type) opposite to the second transistor (220), arranged on a substrate (214) based on the first type. The third transistor (230) may have a second doped region well (234) based on the second type formed on the substrate (214), doped regions (e.g., a source (231) and a drain (233)) based on the first type formed on the second doped region well (234), and a depletion channel formed between the source (231) and the drain (233).

[0052] A first transistor (210) may have a drain (211), a gate (212), and a source (213), a second transistor (220) may have a drain (221), a gate (222), and a source (223), and a third transistor (230) may have a drain (233), a gate (232), and a source (231). For example, the first transistor (210) and the second transistor (220) may be second type transistors (e.g., NMOS), and the third transistor (230) may be first type transistors (e.g., PMOS). In this specification, an example in which the first type is p type and the second type is n type is mainly described.

[0053] However, this is not limited to this, and conversely, the first type may be n-type and the second type may be p-type. In this case, the first transistor (210) and the second transistor (220) may be PMOS, and the third transistor (230) may be NMOS.

[0054] In addition, the 3T0C memory cell (200) may be arranged such that the first transistor (210), the second transistor (220), and the third transistor (230) are spaced apart from each other on a substrate (214) based on the first type, as shown in FIG. 3. Furthermore, the first transistor (210), the second transistor (220), and the third transistor (230) may be arranged side by side. For example, when the first transistor (210) is arranged on the substrate (214), the second transistor (220) may be arranged side by side facing the first transistor (210). In addition, the third transistor (230) may also be arranged side by side facing the second transistor (220). At this time, the first transistor (210), the second transistor (220), and the third transistor (230) may be arranged so that the drain (211) of the first transistor (210), the gate (222) of the second transistor (220), and the gate (232) of the third transistor (230) are positioned in a straight line. However, the present invention is not limited thereto, and the first transistor (210), the second transistor (220), and the third transistor (230) may be arranged in different directions or structures on the substrate (214).

[0055] FIG. 4 illustrates cross-sections of a 3T0C DRAM memory cell according to one embodiment.

[0056] The AA' cross-section shows the interior of a first rod (240) to which a first transistor (210), a second transistor (220), and a third transistor (230) are connected. The first rod (240) may be connected to a drain (211) of the first transistor (210), a gate (222) of the second transistor (220), and a gate (232) of the third transistor (230). A signal corresponding to a value set at a storage node (SN) may be stored on the first rod (240) to which the first transistor (210), the second transistor (220), and the third transistor (230) are connected. The third transistor (230) may include a second doped region well (234), a depletion channel (235) is formed on the second doped region well (234), and a gate (232) may be disposed on the depletion channel (235).

[0057] The BB' cross-section represents the interior of the first transistor (210). The first transistor (210) may have a first doped region (410) based on a second type formed on a substrate (214) based on a first type. For example, when the first transistor (210) is an NMOS, the first type may be a p-type, and the substrate (214) based on the first type may include B (Boron). In addition, the second type may be an n-type, and the first doped region (410) based on the second type may include As (Arsenic) and may be heavily doped.

[0058] The CC' cross-section represents the interior of the third transistor (230). The third transistor (230) may have a doping region (420) based on the first type on a second doping region well (234) based on the second type. For example, when the third transistor (230) is a PMOS, the second doping region well (234) based on the second type may include a lower concentration of As than the first doping region (410) based on the second type. Additionally, the doping region (420) based on the first type may include a higher concentration of B than the substrate (214) based on the first type.

[0059] The DD' cross-section shows the interior of the second load (280) to which the second transistor (220) and the third transistor (230) are connected. The drain (221) of the second transistor (220) and the source (231) of the third transistor (230) can be connected in series to the second load (280).

[0060] Additionally, the gate (212) of the first transistor (210) and the gate (222) of the second transistor (220) may be a metal or polysilicon having high electrical conductivity. The gate (232) of the third transistor (230) may be polysilicon.

[0061] FIG. 5 illustrates an exemplary circuit diagram of a 3T0C DRAM memory cell according to one embodiment.

[0062] For example, in FIG. 2, one second transistor (220) and one third transistor (230) are illustrated, but this is not limiting. For example, the memory cell (200) may include a plurality of second transistors and a plurality of third transistors. For example, the second transistors may include transistors of the second type (e.g., two NMOS transistors). The third transistors may include transistors of the first type (e.g., two PMOS transistors). However, the number of transistors is not limited to that illustrated in FIG. 5, and may vary depending on the design.

[0063] The second transistors and the third transistors may be connected in series along a read bit line (RBL) and a read word line (RWL). For example, the gates of the second transistors and the third transistors may both be commonly connected to a storage node (SN). The sources of the second transistors may be connected to a drain of another second transistor or a read word line (RWL). The sources of the third transistors may be connected to a drain of another third transistor or a read bit line (RBL).

[0064] Transistors connected in series in the memory cell (200) may include transistors of a first type (e.g., p type) arranged on one side of any node and transistors of a second type (e.g., n type) arranged on the other side. In other words, transistors of the same type may be connected in series. A source of one of the second transistors (e.g., N type transistors) and a drain of one of the third transistors (e.g., P type transistors) may be connected in series.

[0065] However, the arrangement of the transistors is not limited to that illustrated in FIG. 5. While FIG. 5 illustrates a series of second transistors arranged at the bottom and a series of third transistors arranged at the top, the series of transistors may be arranged in the opposite manner. For example, a series of third transistors may be arranged at the bottom and a series of second transistors may be arranged at the top.

[0066] FIG. 6a exemplarily shows the transfer characteristics of a read transistor (e.g., a second transistor (220)) configured in a 3T0C DRAM memory cell according to one embodiment, and FIG. 6b exemplarily shows the transfer characteristics of a read transistor (e.g., a third transistor (230)) configured in a 3T0C DRAM memory cell according to one embodiment.

[0067] In Fig. 6a, the transfer characteristics are shown when the second transistor (220) is an NMOS in enhancement mode, and in Fig. 6b, the transfer characteristics are shown when the third transistor (230) is a PMOS in depletion mode, which is opposite to the second transistor (220). Accordingly, the second transistor (220) has a threshold voltage (V) greater than 0 (e.g., positive (+)). T ), and the gate-source voltage (V GS ) is 0(zero) V, it can be turned on and current can flow. In addition, the transfer characteristics of the third transistor (230) have properties opposite to those of the second transistor (220), and the threshold voltage (V) of the third transistor (230) T ) is the threshold voltage (V) of the second transistor (220). T ) can have a larger value. If the third transistor (230) is used as a PMOS in the increase mode, the third transistor (230) can have a larger value than the storage node voltage (V SN) can be turned off regardless of the input voltage. In addition, when the second transistor (220) is a PMOS in an increase mode and the third transistor (230) is a NMOS in a depletion mode, the second transistor (220) and the third transistor (230) have a threshold voltage (V) less than 0 (e.g., negative (-)). T ) can have. Then, the threshold voltage (V) of the third transistor (230) T ) is the threshold voltage (V) of the second transistor (220). T ) can have a smaller value than the threshold voltage (VT) of the second transistor. This may mean that the absolute value of the threshold voltage of the third transistor can be greater than the absolute value of the threshold voltage (VT) of the second transistor.

[0068] FIG. 7 illustrates channel conductivity in a 3T0C DRAM memory cell structure according to one embodiment.

[0069] A storage node voltage (V) is applied to the storage node (SN) of the first load (240) to which the first transistor (210), the second transistor (220) and the third transistor (230) are connected. SN ) is formed, and the storage node voltage (V SN ) can form a channel in the second transistor (220) and the third transistor (230) connected through the second load (280). The storage node voltage (V SN ) changes the channel conductivity (G) of the second transistor (220). N ) and the channel conductivity (G) of the third transistor (230) P,dep ) can cause changes.

[0070] FIG. 8 is an exemplary circuit diagram simulating the channel conductivity of a 3T0C DRAM memory cell as a resistor according to one embodiment.

[0071] Storage node voltage (V) SN ) decreases, the channel conductivity (G) of the second transistor (220) N) also decreases the read current (I READ ) may decrease. However, the channel conductivity (G) of the third transistor (230) P,dep ) is the storage node voltage (V SN ) can be suppressed from decreasing the overall channel conductance, and the channel conductance (G N ) and channel conductance (G P,dep ) through all the read currents (I READ ) can also reduce the amount of change.

[0072] Figure 9 shows the storage node voltage (V) for a 2T0C DRAM unit cell and a 3T0C DRAM memory cell according to one embodiment. SN ) is shown as an example of a graph of the read channel conductance according to the decrease in the

[0073] As shown in Fig. 9, the read channel conductance of the 2T0C memory cell has a larger value than the read channel conductance of the 3T0C memory cell (200), indicating that more current is used, resulting in lower power efficiency. In addition, the 3T0C memory cell (200) shows the same trend in the storage node voltage (V SN ) is reduced, the overall power consumption is lowered and the read channel conductance decreases slowly because the change is relatively small compared to the 2T0C memory cell. This is because the read current (I READ ) may mean that the amount of change in the PIM decreases, and at the same time, the accuracy of the AI ​​operation in the PIM may also decrease slowly. Through this, the frequency of the refresh operation of the 3T0C memory cell (200) may decrease, and the power consumption due to frequent refresh operations may also decrease.

[0074] FIG. 10 illustrates an exemplary circuit diagram of a memory device including a 3T0C DRAM memory cell according to one embodiment.

[0075] The memory device (1000) includes a word line (WL) each configured with a plurality of first word lines (e.g., write word lines (WWL)) and a plurality of second word lines (e.g., read word lines (RWL)), a bit line (BL) each configured with a plurality of first bit lines (e.g., write bit lines (WBL)) and a plurality of second bit lines (e.g., read bit lines (RBL)), a first transistor (210) connected to one first word line of the plurality of first word lines and one first bit line of the plurality of first bit lines, a second transistor (220) connected to one second word line of the plurality of second word lines, and a third transistor (230) connected to one second bit line of the plurality of second bit lines, and a storage node is formed through the connection of the first transistor (210), the second transistor (220), and the third transistor (230), and a storage node is formed through the connection of the second transistor (220) and the third transistor (230). The memory cell array may include a plurality of memory cells forming a channel.

[0076] The word line and bit line can be connected to a controller and / or processor that controls the memory cell array. For example, when the processor applies a write input signal to the first transistor (210) through the first word line (WWL) and the first bit line (WBL), “1” or “0” data can be stored in the parasitic capacitor (Cp). In addition, when the processor applies a read input signal to the second transistor (220) and the third transistor (230) through the second word line (RWL) and the second bit line (RBL), the data stored in the parasitic capacitor (Cp) can be determined and then read.

[0077] The embodiments described above may be implemented using hardware components, software components, and / or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented using a general-purpose computer or a special-purpose computer, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and software applications running on the operating system. Furthermore, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, those skilled in the art will appreciate that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0078] Software may include a computer program, code, instructions, or a combination of one or more of these, and may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be stored on any type of machine, component, physical device, virtual equipment, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on a computer-readable recording medium.

[0079] The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

[0080] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the described embodiments. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0081] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In memory cells, A first transistor having a source and a drain formed in a first doped region based on a second type on a substrate based on a first type; A second transistor arranged on a substrate based on the first type; and A third transistor having a second doped region well based on the second type, arranged on a substrate based on the first type, a source and a drain formed in the doped region based on the first type on the second doped region well based on the second type, and a depletion channel formed between the source and the drain Including, Stores a signal corresponding to a value set in a storage node (SN) on a first rod to which the first transistor, the second transistor, and the third transistor are connected. Memory cells.

2. In paragraph 1, The first load is connected to the drain of the first transistor, the gate of the second transistor, and the gate of the third transistor, The drain of the second transistor and the source of the third transistor are connected to a second load, Memory cells.

3. In paragraph 1, The threshold voltage (V) of the second transistor T ) is a value whose absolute value of the threshold voltage of the third transistor is greater than the absolute value of the threshold voltage of the third transistor. Memory cells.

4. In paragraph 1, The number of the second transistor and the third transistor is at least one, Memory cells.

5. In paragraph 1, The first type above is p type, and the second type above is n type. Memory cells.

6. In paragraph 1, The substrate based on the first type includes B (Boron), and the first doping region based on the second type includes As (Arsenic). Memory cells.

7. In paragraph 1, The second doping region well based on the second type includes As at a lower concentration than the first doping region based on the second type, and the doping region based on the first type includes B at a higher concentration than the substrate based on the first type. Memory cells.

8. In paragraph 1, The above first type is n type, and the above second type is p type, Memory cells.

9. In paragraph 2, The second load is connected in series with the drain of the second transistor and the source of the third transistor. Memory cells.

10. In memory devices, A word line each composed of a plurality of first word lines and a plurality of second word lines; A bit line each composed of a plurality of first bit lines and a plurality of second bit lines; and A memory cell array comprising a plurality of memory cells, each memory cell including a first transistor connected to one of the plurality of first word lines and one of the plurality of first bit lines, a second transistor connected to one of the plurality of second word lines, and a third transistor connected to one of the plurality of second bit lines, wherein a storage node is formed through the connection of the first transistor, the second transistor, and the third transistor, and a channel is formed through the connection of the second transistor and the third transistor. Including, The second transistor and the third transistor are transistors of opposite types. Memory device.

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