Array substrate and display panel

Abstract

Disclosed in the present application are an array substrate and a display panel. The array substrate comprises a substrate and a thin film transistor disposed on the substrate. The thin film transistor comprises a gate, a first metal oxide active layer and a source and a drain. The first metal oxide active layer is located on one side of the gate, and comprises indium, lanthanide and copper. The source and the drain are connected to the first metal oxide active layer. Thus, copper can ameliorate shallow-level defects caused by doping metal oxides with lanthanide, thereby improving the positive bias stability of thin film transistors.

Description

Array substrate and display panel TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] With the increasingly high requirements on high resolution, high definition, fast response, low power consumption and other indicators of display devices, metal oxide transistors are more and more applied in high-end display devices such as liquid crystal display panels and organic light-emitting diode display panels due to their lower leakage current. However, due to the relatively low mobility of the current mainstream metal oxide transistors, they are still difficult to be applied in intelligent terminal high-end products with higher requirements on resolution and definition.

[0003] In recent years, with the breakthrough in the research on lanthanide-doped high-mobility oxide target material formula, the performance of metal oxide transistors has been improved, that is, on the basis of low leakage current, the mobility is further increased, and excellent light stability is also achieved, which widens the application prospect of metal oxide transistors. However, the stability of lanthanide-doped metal oxide transistors under voltage is poor, which is difficult to meet the requirements of display devices.

[0004] Therefore, it is necessary to propose a technical scheme to improve the stability of lanthanide-doped metal oxide transistors under voltage. SUMMARY

[0005] The present application provides an array substrate and a display panel to improve the positive bias stability of thin film transistors and improve the display effect of the display panel.

[0006] In a first aspect, some embodiments of the present application provide an array substrate. The array substrate includes a substrate and a thin film transistor disposed on the substrate. The thin film transistor includes a gate, a first metal oxide active layer, and a source and a drain. The first metal oxide active layer is located on one side of the gate and includes an indium element, a lanthanide element and a copper element. The source and the drain are connected to the first metal oxide active layer.

[0007] In a second aspect, some embodiments of the present application also provide a display panel, which includes the array substrate of any of the above embodiments. Advantages

[0008] In the array substrate and the display panel of some embodiments of the present application, the copper element is further doped in the first metal oxide active layer doped with the lanthanide element, which improves the shallow level defects caused by the lanthanide-doped metal oxide and improves the stability of the thin film transistor under positive bias, that is, improves the positive bias stability of the thin film transistor, and further improves the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a schematic diagram of a cross-sectional structure of an array substrate according to some embodiments of the present application.

[0010] FIG. 2 is a schematic diagram of a cross-sectional structure of an array substrate according to some other embodiments of the present application.

[0011] FIG. 3 is a schematic diagram of a cross-sectional structure of an array substrate according to yet some other embodiments of the present application.

[0012] FIG. 4 is a schematic diagram of a cross-sectional structure of an array substrate according to yet some other embodiments of the present application.

[0013] FIG. 5 is a schematic diagram of a planar structure of a display panel according to some embodiments of the present application.

[0014] FIG. 6 is a schematic diagram of a pixel driving circuit of a display panel according to some embodiments of the present application.

[0015] FIG. 7 is a schematic diagram of a pixel driving circuit of a display panel according to some other embodiments of the present application.

[0016] FIG. 8 is a schematic diagram of a gate driving circuit of a display panel according to some embodiments of the present application.

[0017] FIG. 9 is a transfer characteristic curve of a thin film transistor according to Embodiment 4 of the present application.

[0018] FIG. 10 is a transfer characteristic curve of a thin film transistor according to a comparative example.

[0019] Reference signs are as follows:

[0020] 100, display panel;

[0021] 10, thin film transistor;

[0022] 101, gate;

[0023] 1021, first metal oxide active layer; 1022, second metal oxide active layer;

[0024] 103, source; 104, drain;

[0025] 105, gate insulating layer; 106, interlayer insulating layer;

[0026] 107, light shielding layer; 108, etching stopper layer;

[0027] 20, pixel driving circuit; 201, switching transistor; 202, first driving transistor; 203, second driving transistor;

[0028] 21, gate driving circuit; 211, pull-up transistor; 212, pull-down transistor; 213, pull-up control transistor;

[0029] 22, pixel; 23, scan line; 24, data line;

[0030] VDD, first power voltage; VSS1, second power voltage; VSS2, third power voltage;

[0031] 30, substrate. Embodiments of the present application

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0033] Please refer to FIG. 1 to FIG. 4, FIG. 1 is a cross-sectional structure schematic diagram of an array substrate provided by some embodiments of the present application, FIG. 2 is a cross-sectional structure schematic diagram of an array substrate provided by another embodiments of the present application, FIG. 3 is a cross-sectional structure schematic diagram of an array substrate provided by yet another embodiments of the present application, and FIG. 4 is a cross-sectional structure schematic diagram of an array substrate provided by yet another embodiments of the present application. The thin film transistors shown in FIG. 1 and FIG. 2 are back channel etching type transistors, the thin film transistor shown in FIG. 3 is an etching blocking type transistor, and the thin film transistor shown in FIG. 4 is a top gate thin film transistor.

[0034] As shown in FIG. 1 to FIG. 4, a thin film transistor 10 is disposed on a substrate 30. The thin film transistor 10 includes a gate 101, a first metal oxide active layer 1021, and a source 103 and a drain 104. The first metal oxide active layer 1021 is located on one side of the gate 101. The source 103 and the drain 104 are connected with the first metal oxide active layer 1021.

[0035] In some embodiments, the gate 101, the source 103 and the drain 104 can include metal. The metal can include at least one of gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum (Al) alloy, aluminum nitride (AlNx), silver (Ag) alloy, tungsten (W), tungsten nitride (WNx), copper (Cu) alloy, molybdenum (Mo) alloy.

[0036] The first metal oxide active layer 1021 includes indium element (In), lanthanide element, and copper element (Cu). The indium element enables the thin film transistor 10 to have high mobility. The lanthanide element doped metal oxide active layer further increases the mobility of the thin film transistor 10, and the lanthanide element also improves the light stability of the thin film transistor 10. Further doping the copper element in the lanthanide element doped metal oxide active layer improves the shallow level defect caused by the lanthanide element to the metal oxide, improves the stability of the thin film transistor under positive bias, i.e., improves the positive bias stability of the thin film transistor 10. Further doping the copper element in the lanthanide element doped metal oxide active layer also increases the process window of the thin film transistor. In this way, the high mobility, high light stability, process window, and positive bias stability of the thin film transistor 10 are taken into account.

[0037] The lanthanide element can include at least one of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Optionally, the lanthanide element in the first metal oxide active layer 1021 can include praseodymium element.

[0038] In some embodiments, the copper element can exist in the form of copper oxide in the first metal oxide active layer 1021. In this way, the stability of the copper element in the first metal oxide active layer 1021 is improved, thereby ensuring the stability of the thin film transistor.

[0039] In some embodiments, in the first metal oxide active layer 1021, the number of atoms of the lanthanide element is less than the number of copper atoms. In this way, in the first metal oxide active layer 1021, the number of copper atoms is greater than the number of atoms of the lanthanide element, and the copper atoms can better improve the problem of poor positive bias stability caused by the lanthanide element doping.

[0040] In some embodiments, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 1% and less than or equal to 10%. In this way, the problem of shallow level defect state caused by the lanthanide element is effectively improved, and the positive bias stability of the thin film transistor 10 is improved.

[0041] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 3% and less than or equal to 8%. In this way, while improving the positive bias stability of the thin film transistor, the saturation threshold voltage of the thin film transistor 10 is improved to a suitable range, thereby reducing the power consumption required to turn on the thin film transistor 10.

[0042] It should be noted that the lanthanide-doped metal oxide has a low threshold voltage. The threshold voltage is too low, and the thin film transistor 10 is easy to open. The lanthanide-doped metal oxide is further doped with an appropriate amount of copper element, which can effectively suppress the high carrier concentration caused by the lanthanide-doped metal oxide, and can improve the saturation threshold voltage of the thin film transistor 10 to a suitable range, thereby optimizing the saturation threshold voltage of the thin film transistor 10.

[0043] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can be greater than or equal to 4.5% and less than or equal to 8%. In this way, while improving the positive bias stability of the thin film transistor 10, the saturation threshold voltage of the thin film transistor 10 is improved to a suitable range to reduce the power consumption required to open the thin film transistor 10, and the negative bias stability of the thin film transistor 10 can be further improved.

[0044] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can be greater than or equal to 1% and less than or equal to 5%. Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can be greater than or equal to 5.5% and less than or equal to 10%.

[0045] Exemplarily, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can be 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5% or 10%.

[0046] In other embodiments, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can also be greater than 10%. In this way, the shallow level defect state caused by the lanthanide element is significantly improved. Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can also be greater than 10% and less than or equal to 20%.

[0047] In other embodiments, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 can also be less than 1% and greater than or equal to 0.001%.

[0048] In some embodiments, in the first metal oxide active layer 1021, the percentage of the ratio of the number of atoms of the lanthanide element to the number of atoms of indium is greater than or equal to 0.1% and less than or equal to 5%. In this way, the switching characteristics of the thin film transistor 10 are ensured, and the thin film transistor 10 has high mobility and high light stability.

[0049] Optionally, in the first metal oxide active layer 1021, the percentage of the ratio of the number of atoms of the lanthanide element to the number of atoms of indium is greater than or equal to 0.2% and less than or equal to 4.5%. Optionally, in the first metal oxide active layer 1021, the percentage of the ratio of the number of atoms of the lanthanide element to the number of atoms of indium is greater than or equal to 0.5% and less than or equal to 3%.

[0050] Illustratively, in the first metal oxide active layer 1021, the percentage of the ratio of the number of atoms of the lanthanide element to the number of atoms of indium can be 0.1%, 0.2%, 0.5%, 0.6%, 0.7%, 0.9%, 1.0%, 1.1%, 1.2%, 1.5%, 1.6%, 1.7%, 1.9%, 2.0%, 2.1%, 2.2%, 2.5%, 2.6%, 2.7%, 2.9%, 3.0%, 3.1%, 3.2%, 3.5%, 3.6%, 3.7%, 3.9%, 4.0%, 4.1%, 4.2%, 4.5%, 4.6%, 4.7%, or 4.9%.

[0051] In some embodiments, the first metal oxide active layer 1021 further includes at least one of a gallium element, a zinc element, and a tin element, and the ratio of the number of atoms of indium to the number of atoms of any one of the gallium element, the zinc element, and the tin element is greater than or equal to 1.8 and less than or equal to 5. In this way, the thin film transistor 10 has high mobility, and the switching characteristics of the thin film transistor 10 are ensured.

[0052] Optionally, the first metal oxide active layer 1021 further includes at least one of a gallium element, a zinc element, and a tin element, and the ratio of the number of atoms of indium to the number of atoms of any one of the gallium element, the zinc element, and the tin element is greater than or equal to 2 and less than or equal to 4.5.

[0053] Optionally, the first metal oxide active layer 1021 further includes a zinc element, and the ratio of the number of atoms of indium to the number of atoms of zinc is greater than or equal to 1.8 and less than or equal to 5. In this way, the first metal oxide active layer 1021 includes a zinc element, which can further improve the mobility of the thin film transistor 10.

[0054] Optionally, the first metal oxide active layer 1021 further includes tin element, and the ratio of the number of indium atoms to the number of tin atoms is greater than or equal to 1.8 and less than or equal to 5. In this way, the first metal oxide active layer 1021 includes tin element, which can further improve the mobility of the thin film transistor 10.

[0055] Optionally, the first metal oxide active layer 1021 further includes gallium element, and the ratio of the number of indium atoms to the number of gallium atoms is greater than or equal to 1.8 and less than or equal to 5. In this way, the first metal oxide active layer 1021 includes gallium element, which can play a role in inhibiting high carrier concentration, reducing the off-state leakage current of the thin film transistor 10, and improving the stability of the thin film transistor 10.

[0056] Optionally, the first metal oxide active layer 1021 further includes two or three of gallium element, zinc element, and tin element.

[0057] In some embodiments, the metal oxide matrix in the first metal oxide active layer 1021 can include one or more mixtures of indium gallium zinc oxide, indium zinc oxide, indium gallium oxide, indium tin zinc oxide, and indium oxide.

[0058] In some embodiments, the metal oxide matrix in the first metal oxide active layer 1021 can be indium zinc oxide, and the lanthanide element can include praseodymium element. In the first metal oxide active layer 1021, the ratio of the number of copper atoms, the number of praseodymium atoms, the number of indium atoms, and the number of zinc atoms is (0.02-0.15):(0.001-0.09):(1.8-2.0):(0.8-1.2). In this way, the high mobility, positive bias stability, and high light stability of the thin film transistor 10 are taken into account.

[0059] Optionally, the metal oxide matrix in the first metal oxide active layer 1021 can be indium zinc oxide, and the lanthanide element can include praseodymium element. In the first metal oxide active layer 1021, the ratio of the number of copper atoms, the number of praseodymium atoms, the number of indium atoms, and the number of zinc atoms is (0.05-0.15):(0.001-0.09):(1.8-2.0):(0.8-1.2). In this way, the high mobility, positive bias stability, and high light stability of the thin film transistor 10 are taken into account, and the saturation threshold voltage of the thin film transistor is optimized.

[0060] Optionally, in the first metal oxide active layer 1021, the ratio of the number of copper atoms, the number of praseodymium atoms, the number of indium atoms, and the number of zinc atoms is (0.1-0.15):(0.001-0.09):(1.8-2.0):(0.8-1.2). In this way, the high mobility, the positive bias stability, the high light stability, and the saturated threshold voltage of the thin film transistor are considered, and the negative bias stability of the thin film transistor is improved.

[0061] As shown in FIG. 2, in some embodiments, the thin film transistor 10 can further include a second metal oxide active layer 1022. The second metal oxide active layer 1022 is disposed in contact with the first metal oxide active layer 1021, and the source 103 and the drain 104 are in contact with the second metal oxide active layer 1022. The proportion of the number of indium atoms in the second metal oxide active layer 1022 is less than the proportion of the number of indium atoms in the first metal oxide active layer 1021. In this way, the first metal oxide active layer 1021 as a front channel layer has high mobility so that the thin film transistor 10 has a large on-current, and the second metal oxide active layer 1022 as a back channel layer has low mobility so that the thin film transistor 10 has a low off-current.

[0062] In some embodiments, the second metal oxide active layer 1022 can further include at least one of a gallium element and a zinc element. In this way, the off-current of the thin film transistor 10 is reduced. In the second metal oxide active layer 1022, the ratio of the number of indium atoms to the number of atoms of any one of the gallium element and the zinc element is greater than or equal to 0.01 and less than or equal to 1. In this way, the proportion of the number of indium atoms in the second metal oxide active layer 1022 is less than the proportion of the number of indium atoms in the first metal oxide active layer 1021, and the mobility of the second metal oxide active layer 1022 is reduced.

[0063] In some embodiments, the second metal oxide active layer 1022 can not include a lanthanide element. In this way, it is ensured that the mobility of the second metal oxide active layer 1022 is less than the mobility of the first metal oxide active layer 1021.

[0064] In other embodiments, the second metal oxide active layer 1022 can further include a lanthanide element. In this way, the light stability of the second metal oxide active layer 1022 is improved. In other embodiments, the proportion of the number of atoms of the lanthanide element in the second metal oxide active layer 1022 is less than the proportion of the number of atoms of the lanthanide element in the first metal oxide active layer 1021.

[0065] In some embodiments, the second metal oxide active layer 1022 can further include copper element. In this way, the light stability of the second metal oxide active layer 1022 can be improved while the positive bias stability of the thin film transistor 10 is improved. In some embodiments, the percentage of the number of copper atoms in the second metal oxide active layer 1022 can be less than the percentage of the number of copper atoms in the first metal oxide active layer.

[0066] In some embodiments, the thin film transistor 10 can further include a third metal oxide active layer. The third metal oxide active layer is located on the side of the second metal oxide active layer 1022 that is away from the first metal oxide active layer 1021. In this way, the thin film transistor 10 can include three metal oxide active layers. It can be understood that the thin film transistor 10 can include more than three metal oxide active layers that are stacked.

[0067] As shown in FIGS. 1-4, the thin film transistor 10 is disposed on a substrate 30. The substrate 30 can include any one of a glass substrate, a flexible substrate, and a semiconductor substrate.

[0068] As shown in FIGS. 1-4, in some embodiments, the first metal oxide active layer 1021 and the second metal oxide active layer 1022 are parallel or substantially parallel to the substrate 30. In some embodiments, the thin film transistor 10 can be a vertical transistor, in which case the first metal oxide active layer 1021 and the second metal oxide active layer 1022 can be inclined or perpendicular to the substrate 30.

[0069] As shown in FIGS. 1-3, the thin film transistor 10 can be a bottom-gate thin film transistor 10. In this case, the gate 101 is located between the substrate 30 and the first metal oxide active layer 1021. A gate insulating layer 105 is disposed between the gate 101 and the first metal oxide active layer 1021. As shown in FIGS. 1 and 3, the source 103 and the drain 104 are disposed on and in contact with the first metal oxide active layer 1021. As shown in FIG. 2, the source 103 and the drain 104 are disposed on and in contact with the second metal oxide active layer 1022. The thin film transistor 10 can further include an interlayer insulating layer 106 that covers the source 103 and the drain 104, the first metal oxide active layer 1021, and the gate insulating layer 105.

[0070] In some embodiments, as shown in FIG. 1 and FIG. 3, in the case that the thin film transistor 10 is a bottom-gate thin film transistor and the channel layer of the thin film transistor 10 is a single layer, the orthogonal projection of the first metal oxide active layer 1021 on the substrate 30 can be located within the orthogonal projection of the gate 101 on the substrate 30. In this way, the gate 101 can play a role of light shielding, improve the problem that the first metal oxide active layer 1021 is prone to cause the photo-generated leakage current of the thin film transistor 10 under light, and also make the first metal oxide active layer 1021 more flat, thereby ensuring the performance of the first metal oxide active layer 1021.

[0071] In some embodiments, as shown in FIG. 2, in the case that the thin film transistor 10 is a bottom-gate thin film transistor and the channel layer of the thin film transistor 10 includes the first metal oxide active layer 1021 and the second metal oxide active layer 1022, the first metal oxide active layer 1021 is located on the side of the second metal oxide active layer 1022 close to the gate 101. The orthogonal projection of the second metal oxide active layer 1022 on the substrate 30 is located within the orthogonal projection of the first metal oxide active layer 1021 on the substrate 30.

[0072] As shown in FIG. 4, the thin film transistor 10 can be a top-gate thin film transistor. The first metal oxide active layer 1021 is located between the gate 101 and the substrate 30, and the gate 101 is located on the side of the first metal oxide active layer 1021 away from the substrate 30. The gate insulating layer 105 is located between the gate 101 and the first metal oxide active layer 1021.

[0073] Please continue to refer to FIG. 4, in some embodiments, in the case that the thin film transistor 10 is a top-gate thin film transistor 10, a light shielding layer 107 can also be arranged between the substrate 30 and the thin film transistor 10. The orthogonal projection of the first metal oxide active layer 1021 on the substrate 30 is located within the orthogonal projection of the light shielding layer 107 on the substrate 30. In this way, the light shielding layer 107 plays a role of shielding the light incident to the first metal oxide active layer 1021.

[0074] As shown in FIG. 3, in some embodiments, the thin film transistor 10 can also include an etching blocking layer 108. The etching blocking layer 108 is located between the source 103 and the first metal oxide active layer 1021, and between the drain 104 and the first metal oxide active layer 1021. In this way, the etching blocking layer 108 plays a role of protecting the first metal oxide active layer 1021.

[0075] It can be known from the above that, for the thin film transistor 10 of some embodiments of the present application, further doping of copper elements in the lanthanide-doped metal oxide active layer can improve the shallow energy level defect state caused by the doping of lanthanide elements, improve the positive bias stability of the thin film transistor 10, and reduce the difficulty of regulating the threshold voltage.

[0076] Based on the same inventive concept, the present application also provides a display panel. Please refer to FIG. 5 to FIG. 8, FIG. 5 is a schematic diagram of a planar structure of a display panel according to some embodiments of the present application, FIG. 6 is a circuit schematic diagram of a pixel driving circuit of a display panel according to some embodiments of the present application, FIG. 7 is a circuit schematic diagram of a pixel driving circuit of a display panel according to some other embodiments of the present application, and FIG. 8 is a circuit schematic diagram of a gate driving circuit of a display panel according to some embodiments of the present application.

[0077] The display panel 100 can be any one of a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, and a sub-millimeter light emitting diode display panel.

[0078] As shown in FIG. 5 to FIG. 8, the display panel 100 includes a plurality of scan lines 23, a plurality of data lines 24, a plurality of pixel driving circuits 20, a plurality of pixels 22, and a gate driving circuit 21.

[0079] The plurality of scan lines 23 and the plurality of data lines 24 are insulatedly intersected. The plurality of pixel driving circuits 20 are connected with the plurality of scan lines 23 and the plurality of data lines 24. The plurality of pixel driving circuits 20 are connected with the plurality of pixels 22 to drive the plurality of pixels 22 to emit light.

[0080] The gate driving circuit 21 is connected with the plurality of scan lines 23 to output a scan signal to the plurality of scan lines 23. The gate driving circuit 21 can be integrated in an integrated chip and the integrated chip is bound on the display panel 100, or the gate driving circuit 21 can be integrated in the display panel 100.

[0081] As shown in FIG. 6, in some embodiments, in the case that the display panel 100 is a liquid crystal display panel, the pixel driving circuit 20 can include a first driving transistor 202, a source of the first driving transistor 202 is connected with a data line 24, a drain of the first driving transistor 202 is connected with a pixel electrode (not shown), and a gate 101 of the first driving transistor 202 is connected with a scan line 23. The pixel electrode, a common electrode, and a liquid crystal between the pixel electrode and the common electrode constitute a liquid crystal capacitor Clc. The pixel electrode, a common electrode line, and an insulating layer between the pixel electrode and the common electrode line constitute a storage capacitor Cst.

[0082] As shown in FIG. 7, in some other embodiments, in the case where the display panel 100 is a current-driven light-emitting display panel such as an organic light-emitting diode display panel, the pixel driving circuit 20 can include a second driving transistor 203 and a switching transistor 201. The source of the switching transistor 201 is connected to the data line 24, and the gate of the switching transistor 201 is connected to the scan line 23. The gate of the second driving transistor 203 is connected to the drain of the switching transistor 201, the source of the second driving transistor 203 is connected to the first power supply voltage VDD, the drain of the second driving transistor 203 is connected to the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the second power supply voltage VSS1. The second power supply voltage VSS1 is less than the first power supply voltage VDD.

[0083] For the pixel driving circuit 20 shown in FIGS. 6 and 7, during the operation of the pixel driving circuit 20, the transistors in the pixel driving circuit 20 continuously receive positive bias and / or negative bias, so that the transistors in the pixel driving circuit 20 have higher requirements for bias stability.

[0084] The gate driving circuit 21 can include a plurality of cascaded gate driving units. As shown in FIG. 8, each gate driving unit can include a pull-up transistor 211, a pull-down transistor 212, and a pull-up control transistor 213. Taking the nth gate driving unit as an example for description, n is an integer greater than or equal to 2.

[0085] The pull-up control transistor 213 is configured to output a pull-up driving signal. The gate and the source of the pull-up control transistor 213 can receive a previous-stage scan signal G(n-i) output by a previous-stage gate driving unit, and the drain of the pull-up control transistor 213 outputs the previous-stage scan signal G(n-i) as the pull-up driving signal, i being an integer greater than or equal to 1.

[0086] The pull-up transistor 211 is connected to the scan line 23 and is configured to output a turn-on scan signal to the scan line 23, the turn-on scan signal causing the transistor connected to the scan line 23 to turn on. The gate of the pull-up transistor 211 is connected to the drain of the pull-up control transistor 213. The source of the pull-up transistor 211 can receive a clock signal CK, but is not limited thereto. The drain of the pull-up transistor 211 can be connected to the scan line 23. The pull-up transistor 211 turns on under the action of the pull-up driving signal and outputs the clock signal at a high level as the turn-on scan signal to the gates of the transistors (such as the switching transistor 201 and the first driving transistor 202) in the pixel driving circuit 20.

[0087] The pull-down transistor 212 is connected with the scan line 23 and is configured to output a turn-off scan signal to the scan line 23, the turn-off scan signal causing the transistor connected with the scan line 23 to be in a turn-off state. The gate of the pull-down transistor 212 can receive a previous-stage scan signal G(n-j), j being an integer greater than or equal to 1, and j can be different from i. The source of the pull-down transistor 212 receives the third power supply voltage VSS2. The drain of the pull-down transistor 212 is connected with the scan line 23.

[0088] In some embodiments, the gate driving circuit 21 can further include a pull-down maintaining transistor and other transistors.

[0089] During the operation of the gate driving circuit 21, the pull-up transistor 211 and the pull-down transistor 212 are under positive bias for a longer time than other transistors in the gate driving circuit 21, so that the pull-up transistor 211 and the pull-down transistor 212 have a higher requirement for the stability of the positive bias.

[0090] In some embodiments, at least one of the gate driving circuit 21 and the pixel driving circuit 20 includes the thin film transistor 10 described above, so as to improve the stability of the positive bias of the thin film transistor in the gate driving circuit 21 and the pixel driving circuit 20, and further improve the display effect of the display panel 100.

[0091] In some embodiments, the pixel driving circuit 20 can include the thin film transistor 10 described above. In some embodiments, at least one of the first driving transistor 202 and the second driving transistor 203 can include the thin film transistor 10 described above. In some embodiments, the switch transistor 201 can include the thin film transistor 10 described above.

[0092] In some embodiments, at least one of the pull-up transistor 211 and the pull-down transistor 212 includes the thin film transistor 10. Exemplarily, both the pull-up transistor 211 and the pull-down transistor 212 include the thin film transistor 10 described above.

[0093] In some embodiments, other circuits of the display panel 100 can also include the thin film transistor 10 described above. The other circuits can include but are not limited to a multiplexing circuit.

[0094] Therefore, in some embodiments of the present application, at least one of the pixel driving circuit 20 and the gate driving circuit 21 of the display panel 100 includes the thin film transistor 10 described above, so as to improve the display effect of the display panel 100.

[0095] Also based on the same inventive concept, the present application further provides a display device. The display device can be applied to electronic devices such as mobile terminals, tablet computers, desktop computers, and smart bracelets. The display device can include the display panel described above.

[0096] The performance of the thin film transistor 10 is verified in the following with specific examples and comparative examples. The structure of the thin film transistor of Example 1 to Example 4 and Comparative Example is shown in FIG. 2, the second metal oxide active layer of Example 1 to Example 4 and Comparative Example is the same, and the first metal oxide active layer is different. The composition of the first metal oxide active layer and the second metal oxide active layer of the thin film transistor of Example 1 to Example 4 and Comparative Example and the performance test results of the thin film transistor are shown in Table 1 and FIG. 9 and FIG. 10.

[0097] Wherein, FIG. 9 is the transfer characteristic curve of the thin film transistor of Example 4 provided by the present application, and FIG. 10 is the transfer characteristic curve of the thin film transistor of the comparative example. The test conditions corresponding to the transfer characteristic curves of FIG. 9 and FIG. 10 include that during the test, the gate of the thin film transistor is applied with a gate voltage increasing from -15V to 25V, the gate voltage is increased with an amplitude of 0.5V, the source of the thin film transistor is grounded, and the drain of the thin film transistor is connected to 0.1V and 15V voltage respectively. When the drain of the thin film transistor is connected to 0.1V voltage, the transfer characteristic curves of 12 thin film transistors (samples) are measured, and 12 transfer characteristic curves under the condition of 0.1V are obtained, as shown in FIG. 9, 101A corresponds to the curve in the dashed box, and in FIG. 10, 201A corresponds to the curve in the dashed box. When the drain of the thin film transistor is connected to 15V voltage, the transfer characteristic curves of 12 thin film transistors are measured, and 12 transfer characteristic curves under the condition of 15V are obtained, as shown in FIG. 9, 101B corresponds to the curve in the dashed box, and in FIG. 10, 201B corresponds to the curve in the dashed box. The saturation threshold voltage, subthreshold swing and saturation mobility in Table 1 are based on the transfer characteristic curves.

[0098] And, the 1-hour positive bias shift value is based on the positive bias stability test. Under the condition of the positive bias stability test, +30V gate voltage is applied to the gate of the thin film transistor at 60℃ for 3600s, and the transfer characteristic curve test is performed at a certain interval. The 1-hour positive bias shift value is the difference between the threshold voltage at time 3600s and time 0s. The 1-hour negative bias shift value is based on the negative bias stability test. Under the condition of the negative bias stability test, -30V gate voltage is applied to the gate at 60℃ and exposed to a light environment of 4500nit for 3600s, and the transfer characteristic curve test is performed at a certain interval. The 1-hour negative bias shift value is the difference between the threshold voltage at time 3600s and time 0s.

[0099] Table 1 Composition and performance test results of the first metal oxide active layer and the second metal oxide active layer of the thin film transistor of Example 1 to Example 4 and Comparative Example

[0100]

[0101] In combination with Table 1, the 1-hour positive bias shift values of Examples 1 to 4 are less than the 1-hour positive bias shift value of the comparative example. Therefore, some embodiments of the present application can improve the stability of thin film transistors under positive bias by further doping copper element in lanthanide-doped metal oxide.

[0102] In addition, the saturation threshold voltage of the thin film transistors of Examples 2 to 4 is greater than the saturation threshold voltage of the thin film transistor of the comparative example. Therefore, when the percentage ratio of copper atoms to indium atoms is within a certain range, the saturation threshold voltage of the thin film transistor increases as the doping amount of copper element increases within a certain range, thereby effectively improving the problem of negative threshold voltage bias of lanthanide-doped high mobility oxide devices.

[0103] Furthermore, the 1-hour negative bias shift values of Examples 3 and 4 are less than the 1-hour negative bias shift value of the comparative example. Therefore, when the percentage ratio of copper atoms to indium atoms is within a certain range, the negative bias stability of the thin film transistor can also be improved.

[0104] The above descriptions of the embodiments are only used to help understand the technical solutions of the present application and its core ideas; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, wherein, The display panel comprises an array substrate, and the array substrate comprises: a substrate; and a thin film transistor disposed on the substrate and comprising: a gate electrode; a first metal oxide active layer located on one side of the gate electrode and comprising an indium element, a lanthanide element and a copper element; and a source electrode and a drain electrode connected to the first metal oxide active layer. In the first metal oxide active layer, the percentage of the ratio of the number of copper atoms to the number of indium atoms is greater than or equal to 1% and less than or equal to 10%.

2. The array substrate according to claim 1, wherein, In the first metal oxide active layer, the percentage of the ratio of the number of copper atoms to the number of indium atoms is greater than or equal to 3% and less than or equal to 8%.

3. The array substrate of claim 1, wherein, In the first metal oxide active layer, the percentage of the ratio of the number of atoms of the lanthanide element to the number of indium atoms is greater than or equal to 0.1% and less than or equal to 5%.

4. The array substrate of claim 1, wherein, The first metal oxide active layer further comprises at least one of a gallium element, a zinc element and a tin element, and the ratio of the number of indium atoms to the number of atoms of any one of the gallium element, the zinc element and the tin element is greater than or equal to 1.8 and less than or equal to 5.

5. The array substrate of claim 1, wherein, In the first metal oxide active layer, the number of atoms of the lanthanide element is less than the number of copper atoms.

6. The array substrate of claim 1, wherein, The first metal oxide active layer further comprises a zinc element, and the lanthanide element comprises a praseodymium element.

7. The array substrate of claim 1, wherein, In the first metal oxide active layer, the ratio of the number of copper atoms, the number of praseodymium atoms, the number of indium atoms and the number of zinc atoms is (0.02-0.15):(0.001-0.09):(1.8-2.0):(0.8-1.2). The thin film transistor further comprises:

8. The array substrate of claim 1, wherein, a second metal oxide active layer stacked with the first metal oxide active layer and in contact with the source electrode and the drain electrode, and comprising an indium element, and the percentage of the number of indium atoms in the second metal oxide active layer is less than the percentage of the number of indium atoms in the first metal oxide active layer. The display panel comprises an array substrate, and the array substrate comprises:

9. A display panel, wherein, a substrate; and a thin film transistor disposed on the substrate and comprising: a gate electrode; a first metal oxide active layer located on one side of the gate electrode and comprising an indium element, a lanthanide element and a copper element; and a source electrode and a drain electrode connected to the first metal oxide active layer. In the first metal oxide active layer, the percentage of the ratio of the number of copper atoms to the number of indium atoms is greater than or equal to 1% and less than or equal to 10%.

10. The display panel of claim 9, wherein, In the first metal oxide active layer, the percentage of the ratio of the number of copper atoms to the number of indium atoms is greater than or equal to 3% and less than or equal to 8%.

11. The display panel of claim 9, wherein, In the first metal oxide active layer, the percentage of the ratio of the number of atoms of the lanthanide element to the number of indium atoms is greater than or equal to 0.1% and less than or equal to 5%.

12. The display panel of claim 9, wherein, The first metal oxide active layer further comprises at least one of a gallium element, a zinc element and a tin element, and the ratio of the number of indium atoms to the number of atoms of any one of the gallium element, the zinc element and the tin element is greater than or equal to 1.8 and less than or equal to 5.

13. The display panel of claim 9, wherein, In the first metal oxide active layer, the number of atoms of the lanthanide element is less than the number of copper atoms.

14. The display panel of claim 9, wherein, The first metal oxide active layer further comprises a zinc element, and the lanthanide element comprises a praseodymium element. In the first metal oxide active layer, the ratio of the number of copper atoms, the number of praseodymium atoms, the number of indium atoms and the number of zinc atoms is (0.02-0.15):(0.001-0.09):(1.8-2.0):(0.8-1.2).

15. The display panel of claim 9, wherein, The first metal oxide active layer further comprises a zinc element, and the lanthanide element comprises a praseodymium element. In the first metal oxide active layer, a ratio of a number of copper atoms, a number of praseodymium atoms, a number of indium atoms, and a number of zinc atoms is (0.02-0.15):(0.001-0.09):(1.8-2.0):(0.8-1.2).

16. The display panel of claim 9, wherein, The thin film transistor further comprises: A second metal oxide active layer is stacked with the first metal oxide active layer and is in contact with the source electrode and the drain electrode, and comprises an indium element, and a proportion of a number of indium atoms in the second metal oxide active layer is less than a proportion of a number of indium atoms in the first metal oxide active layer.

17. The display panel of claim 9, wherein, Further comprising: A plurality of scan lines; A plurality of pixel driving circuits connected with the plurality of scan lines respectively; A plurality of pixels connected with the plurality of pixel driving circuits respectively; And A gate drive circuit connected with the plurality of scan lines; At least one of the gate drive circuit and the pixel driving circuit comprises the thin film transistor.

18. The display panel of claim 17, wherein, The gate drive circuit comprises: A pull-up transistor connected with one of the scan lines and configured to output a turn-on scan signal to one of the scan lines; and A pull-down transistor connected with one of the scan lines and configured to output a turn-off scan signal different from the turn-on scan signal to one of the scan lines; At least one of the pull-up transistor and the pull-down transistor comprises the thin film transistor.

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