Test circuit, and test method for stacked die structure

Abstract

A test circuit, and a test method for a stacked die structure. The test circuit (100) comprises: a plurality of conductive paths (10), a test control circuit (11), a power source control circuit (12) and a defect detection circuit (13), wherein the test control circuit (11) is configured to sequentially receive, in response to a test clock signal, test control signals that are serially input, and generate and output a plurality of test enable signals corresponding to the plurality of conductive paths (10) on a one-to-one basis; the power source control circuit (12) is configured to control, when a test enable signal is in an active state, a corresponding conductive path (10) to sequentially execute charging and discharging operations as a target conductive path; and the defect detection circuit (13) is configured to detect a level change of each conductive path (10), so as to generate a plurality of detection identification signals, generate, on the basis of a result of comparison between each detection identification signal and a corresponding test enable signal, a plurality of detection results corresponding to the plurality of conductive paths (10) on a one-to-one basis, and output same. The test circuit and the test method can effectively cover the detection of all types of defects, thereby improving the accuracy and comprehensiveness of defect detection.

Description

Test circuit and test method of stacked chip structure

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202410727842.0, filed on June 6, 2024, entitled "Test circuit and test method of stacked chip structure", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the field of semiconductor, and in particular, to a test circuit and a test method of a stacked chip structure. BACKGROUND

[0004] With the development of integrated circuits, many applications have put forward requirements of miniaturization, high speed, high bandwidth and low power consumption for chips. With the gradual invalidation of Moore's law, it has become a new trend to increase chip performance, reduce size and power consumption by using advanced packaging technology. Among them, 3D stacked packaging is to stack multiple chips or wafers and form multiple vertical conductive paths to realize the interconnection of upper and lower chips, such as through silicon via (TSV) technology, through glass via (TGV) technology and hybrid bonding technology, which can shorten the interconnection lines between chips, realize high speed, low power consumption and small area.

[0005] Then the vertical interconnection technology of the current stacked chip structure is not fully mature, as shown in FIG. 1, during the preparation process, the conductive path may be caused by process reasons. Faults such as open circuit and short circuit, which cause the stacked chip structure to not work normally. Therefore, it is necessary to detect the faults existing in the conductive path through the test circuit to ensure the normal work of the stacked chip structure, however, the traditional test circuit and test method cannot effectively detect all types of defects existing in the conductive path, which will affect the reliability and stability of the stacked chip structure product.

[0006] SUMMARY

[0007] The present disclosure provides a test circuit and a test method of a stacked chip structure.

[0008] The technical solution of the present disclosure is implemented as follows:

[0009] In a first aspect, the embodiments of the present disclosure provide a test circuit, comprising: a plurality of conductive paths; a test control circuit configured to receive serially input test control signals in response to a test clock signal, and generate and output a plurality of test enable signals corresponding to the plurality of conductive paths one by one; wherein the test enable signal indicates whether the corresponding conductive path is executed as a target conductive path for defect detection in each defect detection; a power supply control circuit electrically connected with each of the conductive paths and the test control circuit, and configured to control the corresponding conductive path to execute charging and discharging operations as a target conductive path in sequence when the test enable signal is in an active state; and a defect detection circuit electrically connected with a first end of each of the conductive paths and the test control circuit, and configured to detect a level change of each of the conductive paths to generate a plurality of detection identification signals corresponding to the plurality of conductive paths one by one, and generate and output a plurality of detection results corresponding to the plurality of conductive paths one by one according to a comparison result of each of the detection identification signals and the test enable signal.

[0010] In some embodiments, the test control circuit is further configured to, after each defect detection is completed, re-generate and output a plurality of test enable signals after the test control signal is shifted and transmitted based on the test clock signal.

[0011] In some embodiments, the test control circuit is further configured to, after all of the conductive paths are executed as target conductive paths for defect detection, serially output the detection results output by the defect detection circuit as test result signals based on the test clock signal.

[0012] In some embodiments, the test control circuit is further configured to receive a result read identification signal, and read all of the detection results output by the defect detection circuit based on the test clock signal when the test control circuit is in a test result read stage indicated by the result read identification signal, and serially output the read detection results as the test result signals based on the test clock signal when the test control circuit is in a data transmission stage indicated by the result read identification signal.

[0013] In some embodiments, the test control circuit is further configured to reset the test enable signal in response to a first reset signal after all of the detection results are output.

[0014] In some embodiments, the test control circuit comprises a plurality of test control sub-circuits in cascade, the plurality of test control sub-circuits corresponding to the plurality of conductive paths one by one; a first input terminal of a first test control sub-circuit receives the test control signal, an output terminal of each test control sub-circuit is electrically connected to a first input terminal of a next test control sub-circuit, a second input terminal of each test control sub-circuit receives a corresponding detection result, a clock terminal of each test control sub-circuit receives the test clock signal, a control terminal of each test control sub-circuit receives the result read-out identification signal, a reset terminal of each test control sub-circuit receives the first reset signal, an output terminal of each test control sub-circuit outputs a corresponding test enable signal or a corresponding detection result, and the output terminal of the last test control sub-circuit is further configured to output the detection results in series as the test result signal.

[0015] In some embodiments, each test control sub-circuit comprises: a selector, a first input terminal of the selector being a first input terminal of the test control sub-circuit, a second input terminal of the selector receiving a corresponding detection result as a second input terminal of the test control sub-circuit, and a control terminal of the selector receiving the read-out identification signal as a control terminal of the test control sub-circuit; a first D flip-flop, an input terminal of the first D flip-flop being electrically connected to an output terminal of the selector, a clock terminal of the first D flip-flop receiving the test clock signal as a clock terminal of the test control sub-circuit, an output terminal of the first D flip-flop outputting the test enable signal as an output terminal of the test control sub-circuit, and a reset terminal of the first D flip-flop receiving the first reset signal.

[0016] In some embodiments, the defect detection circuit is further configured to receive a detection result latch signal and latch each detection result after each defect detection in response to the detection result latch signal.

[0017] In some embodiments, the defect detection circuit is further configured to, after performing the charging and discharging operations on any of the conductive paths as a target conductive path in turn, latch the detection result of each of the conductive paths according to a comparison result of each of the detection identification signals and the corresponding test enable signal in response to the received detection result latch signal; wherein, when the detection identification signal and the corresponding test enable signal are different, the corresponding detection result is maintained or updated as a first level, and when the detection identification signal and the corresponding test enable signal are the same, the corresponding detection result is maintained unchanged; the detection result being the first level indicates that the corresponding conductive path has a defect, and the detection result being the second level indicates that the corresponding conductive path has no defect, the first level being opposite to the second level.

[0018] In some embodiments, the defect detection circuit comprises a plurality of defect detection sub-circuits, and each of the defect detection sub-circuits corresponds to one of the conductive paths; each of the defect detection sub-circuits comprises: a test signal detection sub-circuit electrically connected to the first end of the corresponding conductive path, configured to detect a level change of the conductive path to generate and output the detection identification signal; and a test result latch sub-circuit electrically connected to the test signal detection sub-circuit and the test control circuit, configured to generate the detection result according to a comparison result of the detection identification signal and the corresponding test enable signal, and latch the detection result in response to the detection result latch signal.

[0019] In some embodiments, the test signal detection sub-circuit comprises: a first NOT gate, an input end of the first NOT gate being electrically connected to the first end of the corresponding conductive path; a second NOT gate, an input end of the second NOT gate being electrically connected to an output end of the first NOT gate, and an output end of the second NOT gate being electrically connected to an input end of the first NOT gate; and a second D flip-flop, an input end of the second D flip-flop being electrically connected to a power supply voltage, a clock end of the second D flip-flop being electrically connected to an output end of the first NOT gate, and an output end of the second D flip-flop outputting the detection identification signal; and the test result latch sub-circuit comprises: a first XOR gate, a first input end of the first XOR gate being electrically connected to an output end of the second D flip-flop, and a second input end of the first XOR gate receiving the corresponding test enable signal; a first OR gate, a first input end of the first OR gate being electrically connected to an output end of the first XOR gate; and a latch, an input end of the latch being electrically connected to an output end of the first OR gate, a control end of the latch receiving the detection result latch signal, an output end of the latch outputting the detection result, and the output end of the latch being further electrically connected to a second input end of the first OR gate.

[0020] In some embodiments, the reset terminal of the second D flip-flop receives a second reset signal, and the second D flip-flop resets the detection identification signal in response to the second reset signal each time the detection result is latched; the reset terminal of the latch receives a third reset signal, and the latch resets the detection result in response to the third reset signal after all the detection results are output.

[0021] In some embodiments, the power supply control circuit comprises: a first power supply control circuit electrically connected to the first end of each of the conductive paths and the test control circuit, configured to control the first end of the target conductive path to be electrically connected to a power supply voltage or a ground voltage when the test enable signal is in an active state; and a second power supply control circuit electrically connected to the second end of each of the conductive paths, configured to control the second end of the conductive path to be electrically connected to the ground voltage or the power supply voltage.

[0022] In some embodiments, the plurality of conductive paths are divided into a plurality of conductive path groups arranged in an array, each of the conductive path groups comprising l*m conductive paths arranged in an array, where l and m are positive integers greater than or equal to 2.

[0023] In some embodiments, the first power supply control circuit is further configured to, in each defect detection, take one of the conductive paths in each of the conductive path groups as the target conductive path based on the plurality of test enable signals, and control the first end of each of the target conductive paths to be electrically connected to the power supply voltage or the ground voltage.

[0024] In some embodiments, the second power supply control circuit is further configured to receive a test area selection signal and control the second end of the selected conductive path to be electrically connected to the ground voltage or the power supply voltage based on the test area selection signal; wherein the test area selection signal comprises a plurality of test area selection sub-signals corresponding one-to-one to a plurality of position areas, each of the test area selection sub-signals indicating whether the conductive path in the corresponding position area is selected; and each of the position areas comprises at least one of the conductive path groups.

[0025] In some embodiments, the first power supply control circuit comprises a plurality of first power supply control sub-circuits, and the second power supply control circuit comprises a plurality of second power supply control sub-circuits, and the plurality of first power supply control sub-circuits and the plurality of second power supply control sub-circuits correspond one-to-one to the plurality of conductive paths.

[0026] In some embodiments, the first power supply control sub-circuit comprises: a first AND gate, a first input end of the first AND gate receives a pull-down control signal, a second input end of the first AND gate receives the corresponding test enable signal; a first N-type transistor, a first end of the first N-type transistor is electrically connected with a first end of the conductive path, a second end of the first N-type transistor is electrically connected with the ground voltage, and a control end of the first N-type transistor is electrically connected with an output end of the first AND gate; the second power supply control sub-circuit comprises: a second AND gate, a first input end of the second AND gate receives a pull-up control signal, and a second input end of the second AND gate receives the corresponding test area selection sub-signal; a first P-type transistor, a first end of the first P-type transistor is electrically connected with a second end of the conductive path, a second end of the first P-type transistor is electrically connected with the power supply voltage, and a control end of the first P-type transistor is electrically connected with an output end of the second AND gate.

[0027] In some embodiments, the first power supply control sub-circuit comprises: a third AND gate, a first input end of the third AND gate receives a pull-up control signal, and a second input end of the third AND gate receives the corresponding test enable signal; a second P-type transistor, a first end of the second P-type transistor is electrically connected with a first end of the conductive path, a second end of the second P-type transistor is electrically connected with the power supply voltage, and a control end of the second P-type transistor is electrically connected with an output end of the third AND gate; the second power supply control sub-circuit comprises: a fourth AND gate, a first input end of the fourth AND gate receives a pull-down control signal, and a second input end of the fourth AND gate receives the corresponding test area selection sub-signal; a second N-type transistor, a first end of the second N-type transistor is electrically connected with a second end of the conductive path, a second end of the second N-type transistor is electrically connected with the ground voltage, and a control end of the second N-type transistor is electrically connected with an output end of the fourth AND gate.

[0028] In some embodiments, the power supply control circuit further comprises a plurality of holding circuits, and each of the plurality of holding circuits corresponds to one of the plurality of conductive paths; the holding circuit comprises: a third NOT gate, an input end of the third NOT gate is electrically connected with a second end of the corresponding conductive path; a fourth NOT gate, an input end of the fourth NOT gate is electrically connected with an output end of the third NOT gate, and an output end of the fourth NOT gate is electrically connected with an input end of the third NOT gate.

[0029] In some embodiments, the test circuit is applied in a stacked chip structure, the stacked chip structure comprising: a first chip and a second chip stacked on the first chip; the first power supply control circuit, the test control circuit and the defect detection circuit are all arranged in the first chip, the second power supply control circuit is arranged in the second chip, and the conductive paths are used for transmitting signals between the first chip and the second chip.

[0030] In some embodiments, the test circuit further comprises: a clock shielding circuit connected with the test control circuit, configured to receive an initial clock signal, and generate and output the test clock signal based on the initial clock signal when none of the conductive paths performs defect detection, and not output the test clock signal when any of the conductive paths performs defect detection.

[0031] In the second aspect, the embodiments of the present disclosure provide a test method of a stacked chip structure, comprising: sequentially receiving serially input test control signals in response to a test clock signal, generating and outputting a plurality of test enable signals corresponding to a plurality of conductive paths one by one; controlling the corresponding conductive path as a target conductive path to perform defect detection in response to the test enable signal in an active state; detecting the level change of each of the conductive paths during each defect detection to generate a plurality of detection identification signals corresponding to the plurality of conductive paths one by one; generating a plurality of detection results corresponding to the plurality of conductive paths one by one according to the comparison result of each of the detection identification signals and the corresponding test enable signal; and latching the detection results in response to a detection result latch signal after each defect detection ends.

[0032] In some embodiments, the test method further comprises: after all the conductive paths complete defect detection as target conductive paths or after each round of defect testing ends, sequentially serially outputting the detection results latched by the defect detection circuit as test result signals based on the test clock signal.

[0033] In some embodiments, the sequentially serially outputting the latched detection results as test result signals based on the test clock signal after all the conductive paths complete defect detection as target conductive paths or after each round of defect testing ends comprises: after all the conductive paths complete defect detection as target conductive paths, when the result readout identification signal indicates that it is in a test result readout stage, latching all the detection results in response to the test clock signal, and when the result readout identification signal indicates that it is in a data transmission stage, sequentially serially outputting the readout detection results as the test result signals in response to the test clock signal.

[0034] In some embodiments, the latching the detection result in response to the detection result latch signal comprises:

[0035] After performing the defect detection on any of the conductive paths as a target conductive path, in response to the received detection result latch signal, maintaining or updating each of the detection results according to the comparison result of the current each of the detection identification signal and the corresponding test enable signal; wherein, when the detection identification signal and the corresponding test enable signal are different, maintaining or updating the corresponding detection result as high level, when the detection identification signal and the corresponding test enable signal are the same, maintaining the corresponding detection result unchanged; the detection result as high level indicates that the corresponding conductive path has defects, and the detection result as low level indicates that the corresponding conductive path has no defects.

[0036] In some embodiments, the controlling the corresponding conductive path as a target conductive path to perform the defect detection in response to the test enable signal in the active state comprises: in response to the test enable signal in the active state, controlling the first end of the target conductive path to be electrically connected with the power supply voltage to perform the charging operation; after the charging operation is completed, controlling the second end of the target conductive path and the second end of the conductive path adjacent to the target conductive path to be electrically connected with the ground voltage respectively to perform the discharging operation.

[0037] In some embodiments, a plurality of the conductive paths are divided into a plurality of conductive path groups arranged in an array, each of the conductive path groups comprising l*m conductive paths arranged in an array, l and m are both positive integers greater than or equal to 2; the controlling the corresponding conductive path as a target conductive path to perform the defect detection in response to the test enable signal in the active state comprises: in response to a plurality of the test enable signals, taking 1 of the conductive paths in each of the conductive path groups as the target conductive path, and controlling the first end of each of the target conductive paths to be electrically connected with the power supply voltage to perform the charging operation; in response to a test area selection signal, controlling the second end of the selected conductive path to be electrically connected with the ground voltage to perform the discharging operation; wherein, the test area selection signal comprises a plurality of test area selection sub-signals corresponding to a plurality of position areas one by one, each of the test area selection sub-signals indicating whether the conductive path in the corresponding position area is selected; each of the position areas comprises at least one of the conductive path groups.

[0038] The embodiments of the present disclosure provide a test circuit and a test method. Through the test circuit and the test method, the test control signal inputted in series through one test port can indicate the defect detection of all conductive paths, the test port resource and the test circuit complexity can be effectively saved, the level change of all conductive paths is detected to generate the detection result of each conductive path while the defect test is performed on the target conductive path each time, the detection of all types of defects can be effectively covered, and the accuracy and comprehensiveness of the defect detection of the conductive path are improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is a schematic diagram of defect types of conductive paths in a stacked chip structure;

[0040] FIG. 2 is a schematic diagram of a structure of a test circuit provided by an embodiment of the present disclosure;

[0041] FIG. 3 is a signal timing diagram corresponding to the test circuit provided by the embodiment (FIG. 2) of the present disclosure;

[0042] FIG. 4 is a schematic diagram of a distribution of conductive paths provided by an embodiment of the present disclosure;

[0043] FIG. 5 is a schematic diagram of a distribution of conductive paths provided by an embodiment of the present disclosure;

[0044] FIG. 6 is a schematic diagram of a structure of a test circuit provided by an embodiment of the present disclosure;

[0045] FIG. 7 is a timing diagram of detection result signal output in the test circuit provided by the embodiment (FIG. 6) of the present disclosure;

[0046] FIG. 8 is a schematic diagram of a distribution of conductive paths provided by an embodiment of the present disclosure;

[0047] FIG. 9 is a schematic diagram of a structure of a test control circuit provided by an embodiment of the present disclosure;

[0048] FIG. 10 is a signal timing diagram corresponding to the test control circuit provided by the embodiment (FIG. 9) of the present disclosure;

[0049] FIG. 11 is a schematic diagram of a structure of a defect detection circuit provided by an embodiment of the present disclosure;

[0050] FIG. 12 is a schematic diagram of a structure of a defect detection sub-circuit provided by an embodiment of the present disclosure;

[0051] FIG. 13 is a signal timing diagram corresponding to the defect detection circuit provided by the embodiment of the present disclosure;

[0052] FIG. 14 is a schematic diagram of a structure of a power supply control circuit provided by an embodiment of the present disclosure;

[0053] Fig. 15 is a structural schematic diagram of a first power supply control circuit and a second power supply control circuit according to an embodiment of the present disclosure;

[0054] Fig. 16 is a structural schematic diagram of a first power supply control circuit and a second power supply control circuit according to another embodiment of the present disclosure;

[0055] Fig. 17 is a structural schematic diagram of a test area selection circuit according to an embodiment of the present disclosure;

[0056] Fig. 18 is a structural schematic diagram of a test circuit according to an embodiment of the present disclosure;

[0057] Fig. 19 is a signal timing diagram of the test circuit according to the embodiment of the present disclosure (Fig. 18);

[0058] Fig. 20 is a working scenario schematic diagram of a test circuit according to an embodiment of the present disclosure;

[0059] Fig. 21 is a working scenario schematic diagram of another test circuit according to an embodiment of the present disclosure;

[0060] Fig. 22 is a structural schematic diagram of another test circuit according to an embodiment of the present disclosure;

[0061] Fig. 23 is a signal timing diagram of the test circuit according to the embodiment of the present disclosure (Fig. 22);

[0062] Fig. 24 is a flowchart of a test method of a stacked chip structure according to an embodiment of the present disclosure DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0064] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0065] If similar descriptions of "first / second" appear in the application file, the following description is added, in the following description, the terms "first / second / third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first / second / third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0067] Before introducing the embodiments of the disclosure, the following three directions for describing the three-dimensional structure that the plane can use are defined. Taking the Cartesian coordinate system as an example, the three directions can include a first direction, a second direction, and a third direction.

[0068] The embodiments of the disclosure will be described in detail below with reference to the accompanying drawings.

[0069] In an embodiment of the disclosure, a test circuit 100 is provided, please refer to FIG. 2, the test circuit can be applied to a stacked chip structure 200, the stacked chip structure 200 at least includes a first chip Die0 and a second chip Die1 stacked on the first chip Die0, specifically, the stacked chip structure 200 can be a stacked semiconductor memory; the test circuit includes:

[0070] a plurality of conductive paths 10;

[0071] a test control circuit 11 configured to receive a serially input test control signal Test_in in response to a test clock signal Tclk, and generate and output a plurality of test enable signals Test_en<1:n> corresponding to the plurality of conductive paths 10 one by one; wherein the test enable signal Test_en<1:n> indicates whether the corresponding conductive path 10 is executed as a target conductive path for defect detection in each defect detection;

[0072] a power supply control circuit 12 electrically connected with each conductive path 10 and the test control circuit 11 respectively, configured to control the corresponding conductive path 10 to execute charging and discharging operations as a target conductive path in turn when the test enable signal Test_en<1:n> is in an active state;

[0073] a defect detection circuit 13 electrically connected with the first end of each conductive path and the test control circuit 11 respectively, configured to detect the level change of each conductive path 10 respectively to generate a plurality of detection identification signals corresponding to the plurality of conductive paths one by one, and generate and output a plurality of detection results Result<1:n> corresponding to the plurality of conductive paths 10 one by one according to the comparison result of each detection identification signal and the corresponding test enable signal.

[0074] For example, the first chip Die0 and the second chip Die1 are electrically connected by a plurality of conductive paths 10 to realize the transmission of data signals and control signals.

[0075] For example, the plurality of test enable signals Test_en<1:n> correspond one-to-one to the plurality of conductive paths TSV1- TSVn, wherein the test enable signals Test_en<1>, Test_en<2>... Test_en <n>respectively indicate whether the corresponding conductive paths TSV1, TSV2…TSVn are executed as target conductive paths for defect detection in each defect detection, as shown in FIG. 2, when the test enable signal Test_en<1> is in an active state and other test enable signals Test_en<2:n> are all in an inactive state, only the conductive path TSV1 is taken as a target conductive path (in gray) in this defect test, and the power supply control circuit 12 performs charging and discharging operations on the conductive path TSV1 in turn to perform defect detection.

[0076] It should be noted that in the test circuit and test method provided by the embodiments of the present disclosure, when all conductive paths are taken as target conductive paths to complete defect detection (i.e., the power supply control circuit performs the process of pull-up charging and then pull-down discharging), it is referred to as completing one round of defect test. Each round of defect test includes multiple defect detections, and each defect detection refers to taking different one or more conductive paths as target conductive paths to perform defect detection, i.e., performing charging and discharging operations on the target conductive paths once, and when the defect detection circuit detects the level change of all conductive paths to generate and output a detection result, it is referred to as completing one defect detection.

[0077] It should be further noted that the conductive paths in the embodiments of the present disclosure can be through silicon vias (TSVs) in addition to common through silicon vias (TSVs), and can also be other types of interconnection structures between chips, such as connection lines, through glass vias (TGVs), and Hybrid Bonding structures. The Copper Interconnect technology is a common Hybrid Bonding technology, and the embodiments of the present disclosure do not limit this. For ease of display, through silicon vias TSVs are taken as conductive paths in the embodiments of the present disclosure and the accompanying drawings for illustration.

[0078] It should be further noted that the embodiments only need one test port to serially input test control signals to indicate defect detection of all conductive paths, which can effectively save test port resources and test circuit complexity. At the same time, defect testing is performed on only the target conductive paths in each time, and the level changes of all conductive paths are detected to generate detection results of each conductive path, which can effectively cover detection of all types of defects and improve the accuracy and comprehensiveness of defect detection of conductive paths.

[0079] In some embodiments, referring to FIG. 2, the test control circuit is further configured to, after each defect detection is completed, regenerate and output the plurality of test enable signals Test_en<1:n> after shifting the test control signal Test_in based on the test clock signal Tclk.

[0080] Here, after each defect detection is completed, the test control signal Test_in is shifted by "1" in a walk manner, i.e. after the first defect test is completed, the test control signal Test_in is only shifted by 1 bit each time, and then a new target conductive path is detected for defect, and the cycle is repeated until all conductive paths are detected for defect.

[0081] For the working principle of the test circuit provided in the embodiment (Fig. 2), please refer to Fig. 4, and the specific process is as follows:

[0082] In the t1-t2 stage, before the first defect test starts, the test control circuit 11 receives the serially input test control signal Test_in based on the test clock signal Tclk.

[0083] At t2, the test control circuit 11 completes the reception of the test control signal, and generates a plurality of corresponding test enable signals Test_en<1> = 1, Test_en<2:n> = 0, the test enable signal Test_en<1> indicates that the corresponding conductive path TSV1 is executed for defect detection as a target conductive path; after t2, the serially input test control signal is no longer received based on the test clock signal until the first defect test is completed.

[0084] Here, after t2, the test clock signal can be shielded or the output of the signal shift transmission circuit of the test control circuit is locked.

[0085] In the t2-t3 stage, the power supply control circuit 12 first charges and then discharges the target conductive path TSV1 according to the effective test enable signal Test_en<1>, and the defect detection circuit 13 detects the level change of all conductive paths 10 (TSV1-TSVn) respectively to generate and output corresponding detection results Result<1:n>.

[0086] Specifically, when the target conductive path TSV1 does not have any defect, the defect detection circuit 13 can detect the change of TSV1 from high level to low level at time t3 to generate the detection identification signal flag<1> as "1", and the test enable signal Test_en<1> is in the active state (indicating that the level change should be detected and the flag<1> output as "1") in this defect test, at this time the corresponding detection result Result<1> is "0", indicating that the target conductive path TSV1 passes (Pass) without problem in this defect detection; when the target conductive path TSV1 has an open circuit or a short circuit (short) to the power supply voltage or the ground voltage, TSV1 is always low or high, the defect detection circuit 13 cannot detect the change of TSV1 from high level to low level at time t3, at this time the detection identification signal flag<1> generated is "0", and the test enable signal Test_en<1> is in the active state (indicating that the flag<1> should be output as "1") in this defect test, at this time the corresponding detection result Result<1> is "1", indicating that the target conductive path TSV1 does not pass (Fail) in this defect detection.

[0087] In addition, in the embodiments of the present disclosure, when TSV1 is the target conductive path, the defect detection circuit 13 can also simultaneously detect the level changes of other conductive paths 10 (TSV2-TSVn) respectively, especially the other conductive paths adjacent to the target conductive path TSV1. As shown in FIG. 4, only one of the adjacent conductive paths TSV2 is taken as an example for description: as shown by the solid line in FIG. 3, when only TSV1 is the target conductive path and the charging and discharging operations are sequentially performed, if the conductive path TSV2 does not have a short circuit (Short) defect to TSV1, the defect detection circuit 13 should not detect the change of TSV2 from high level to low level at t3 to generate a detection identification signal flag<2> of "0", and the test enable signal Test_en<2> in this defect test is in an invalid state (indicating that the level change should not be detected and the flag<2> is output as "0"), at this time, the corresponding detection result Result<2> output is 0, indicating that the conductive path TSV2 passes (Pass) the defect detection without any problem; as shown by the dotted line in FIG. 3, however, if the conductive path TSV2 has a short circuit (Short) defect to the target conductive path TSV1, the defect detection circuit 13 can detect that both TSV2 and TSV1 change from high level to low level at t3, at this time, the detection identification signal flag<2> generated is "1", while the test enable signal Test_en<2> in this defect test is in an invalid state (indicating that the flag<2> should be output as "0"), at this time, the corresponding detection result Result<2> output is "1", indicating that the conductive path TSV2 fails (Fail) the defect detection. In addition, if the conductive path TSV2 has a short circuit (Short) defect to the conductive path TSV1, when the conductive path TSV2 is the target conductive path for defect detection, the corresponding detection result Result<1> output by the conductive path TSV1 should also be "1", indicating that the conductive path TSV1 fails (Fail) the defect detection. The defect detection principles of the other conductive paths 10 adjacent to the target conductive path are similar, and will not be described again.

[0088] Therefore, the embodiments of the present disclosure can not only detect the open circuit or the short circuit defect of the target conductive path to the power supply voltage or the ground voltage, but also simultaneously detect the short circuit (Short) defect between the target conductive path and the other conductive paths.

[0089] At t4, after the charging and discharging operations are performed on TSV1 as the target conductive path, the corresponding detection results Result<1:n> of the conductive paths 10 (TSV1-TSVn) have been generated and output, and the first defect detection is completed.

[0090] At the t5 moment, after the first defect detection is completed, the test control signal Test_in is continuously shifted based on the test clock signal Tclk, and a plurality of test enable signals Test_en<1:n> are regenerated and output. Among them, when the test control signal Test_in is a serial data combination with only one bit being logic "1", only one of the plurality of generated test enable signals is in an active state to indicate that only one conductive path is the target conductive path, at this time, the walk "1" mode can be used for shifting, that is, the test control signal Test_in is shifted by 1 bit each time.

[0091] Specifically, at the t2 moment of the first defect detection, the test enable signal Test_en<1> is generated as logic "1" and Test_en<2:n> is generated as logic "0" based on the serial input test control signal Test_in (000…1), at the t5 moment, the test control signal Test_in can be moved by 1 bit based on Tclk, the data of Test_in is shifted to Test_en<1>, the data of Test_en<1> is shifted to Test_en<2>, …Test_en <n-1>Data shift to Test_en <n>At this time, the data "1" is shifted to Test_en<2> by Test_en<1>, and based on the regenerated test enable signals Test_en<1:n>, TSV2 is taken as the target conductive path to perform the next defect detection, and so on until all conductive paths are sequentially taken as the target conductive path to perform the defect detection once, which indicates that the defect detection in this round is completed, and at this time, the final detection result Result<1:n> can be output.

[0092] It should be noted that the serially input test control signal Test_in can be any data pattern, which can be serial data including only one bit of logical "1", or serial data including multiple bits of logical "1". For example, when the serially input test control signal Test_in is 000...00011 for the first time, the generated test enable signal Test_en<1:n> is 000...00011, which can specify two adjacent conductive paths TSV1 and TSV2 as the target conductive paths. After the first defect detection is completed, the test control signal Test_in needs to be shifted by 2 bits, and the generated test enable signal Test_en<1:n> after the shift is 000...01100, which specifies two adjacent conductive paths TSV3 and TSV4 as the target conductive paths for the next defect detection. This is repeated until the defect detection of all conductive paths is completed. This test data pattern can save half of the test time, but the defect cannot be detected between the short circuit of the two adjacent conductive paths. As shown in FIG. 5, when the serially input test control signal Test_in is 00010001...0001 for the first time, the generated test enable signal Test_en<1:n> is 00010001...0001, which can simultaneously specify one of every four conductive paths as the target conductive path (n conductive paths D0). In the first defect detection, n target conductive paths (n conductive paths D0) can be simultaneously specified. After the first defect detection is completed, the test control signal Test_in can be shifted and transmitted in the walk "1" manner. The generated test enable signal Test_en<1:n> after the shift is 00100010...0010, which can simultaneously specify another one of every four conductive paths as the target conductive path (n conductive paths D1). This is repeated, and only 3 shifts are needed to complete the defect detection of all conductive paths. This test data pattern can greatly save the test time.

[0093] It should be noted that the test enable signal Test_en<1:n> in FIG. 4 can also be low (logic "0") to indicate that it is in the active state, and the detection result Result<1:n> can also be low (logic "0") to indicate that the conductive path 10 has a defect, and high (logic "1") to indicate that the conductive path 10 has no defect. The high / low level of the above signals can be adjusted according to the actual design, and is not specifically limited here.

[0094] In some embodiments, referring to FIG. 6, the test control circuit 11 is further configured to, after the defect detection of all the conductive paths 10 as target conductive paths is completed, serially output the detection result Result<1:n> output by the defect detection circuit 13 as the test result signal Test_out based on the test clock signal Tclk.

[0095] It should be noted that the detection results Result<1:n> of all the conductive paths 10 can be serially output through one or a few output ports after all the defect detection is completed. When there are multiple output ports for outputting the detection results Result<1:n>, the multiple conductive paths 10 can be divided into multiple groups according to the position area where they are located, and the detection results of the conductive paths 10 in each group can be serially output by the corresponding output port. At this time, the test result signal Test_out is a multi-bit signal. Since the number of conductive paths in the stacked chip structure 200 can reach thousands or even tens of thousands, the embodiments of the present disclosure can not only avoid the waste of resources caused by the traditional parallel output of the detection results occupying a large number of test ports, but also determine which conductive paths in which positions have defects according to the order of serial output of the detection results Result<1:n>. When there is only one output port for serially outputting the detection results Result<1:n>, the test result signal Test_out and the test control signal Test_in are both single-bit signals at this time. The order of serial input of the test control signal Test_in and the order of serial output of the detection results Result<1:n> can be the same, as shown in FIG. 8. The transmission order can be set according to the adjacent position relationship of the conductive paths 10 to reduce the wiring on the data transmission path in the test control circuit 11 as much as possible, thereby saving the wire channel resources in the chip. In addition, the output of the detection results Result<1:n> in this case can reuse the receiving circuit and transmission path of the test control signal Test_in, which can simplify the complexity of the test control circuit and effectively reduce the chip area occupied by the test control circuit.

[0096] In some embodiments, with continued reference to FIG. 6, the test control circuit 11 is further configured to receive a result read identification signal Read_flag, and read the detection result Result<1:n> output by the defect detection circuit 13 based on the test clock signal Tclk when the result read identification signal Read_flag indicates that the test control circuit 11 is in a test result read stage, and serially output the read detection result Result<1:n> as the test result signal Test_out in sequence based on the test clock signal Tclk when the result read identification signal Read_flag indicates that the test control circuit 11 is in a data transmission stage.

[0097] With reference to FIG. 7, the output operation of the detection result by the test circuit provided in the present embodiment (FIG. 6) is described as follows:

[0098] Before the time T1, after all the conductive paths 10 complete the defect detection as the target conductive path, it indicates that the present round of defect test is completed, and the final detection result Result<1:n> corresponding to all the conductive paths 10 is generated and output by the defect detection circuit 13, at this time, the result read identification signal Read_flag is at a low level, indicating that the test control circuit 11 is in a data transmission stage (at this time, the transmitted data is the test control signal Test_in to control the conductive path to perform defect test), and the test control circuit 11 does not operate on the detection result Result<1:n>;

[0099] In the stage T1-T2, the result read identification signal Read_flag is flipped from low level to high level to indicate that the test control circuit 11 is in a test result read stage, at this time, the test control circuit 11 reads all the detection results Result<1:n> to the output end of the internal transmission circuit based on the test clock signal Tclk to wait for the test control circuit to output them in sequence;

[0100] In the stage T2-T3, the result read identification signal Read_flag is flipped from high level to low level again to indicate that the test control circuit 11 is in a data transmission stage, at this time, the test control circuit 11 serially outputs the detection results Result<1:n> already read to the output end of the internal transmission circuit as the test result signal Test_out in sequence based on the test clock signal Tclk, since the conductive path TSV1 is closest to the input port and the conductive path TSVn is closest to the output port, the first output detection result based on the test clock signal Tclk is Result <n>…The final output detection result is Result<1>, wherein the n-1th and n-2th output detection results Result<2> and Result<3> are "1", indicating that the corresponding conductive paths TSV2 and TSV3 have defects.

[0101] It should be noted that the high / low level of the result read identification signal Read_flag in FIG. 7 can be interchanged, i.e., the result read identification signal Read_flag can indicate that the test control circuit 11 is in the test result read stage when the high level, and indicate that the test control circuit 11 is in the data transmission stage when the result read identification signal Read_flag is in the low level, which is not specifically limited here.

[0102] In some embodiments, the test control circuit 10 is further configured to reset the test enable signals Test_en<1:n> in response to the first reset signal Rst1 after outputting all the detection results Result<1:n>.

[0103] It should be noted that after all the detection results Result<1:n> are serially output, it indicates that the current round of defect detection has been completed and the results have been recorded, and the control signals including the test enable signals in the test circuit 100 should be reset to prevent the test from being abnormal due to the related control signals not being reset when entering the next round of defect test or other tests.

[0104] In some embodiments, referring to FIG. 9, the test control circuit 11 includes a plurality of test control sub-circuits 111 cascaded, and the plurality of test control sub-circuits 111 correspond to the plurality of conductive paths 10 one by one.

[0105] The first input end of the first test control sub-circuit 111 receives the test control signal Test_in, the output end of each test control sub-circuit 111 is electrically connected to the first input end of the next test control sub-circuit 111, the second input end of each test control sub-circuit 111 receives a corresponding detection result Result<1:n>, the clock end of each test control sub-circuit 111 receives the test clock signal Tclk, the control end of each test control sub-circuit 111 receives the result read identification signal Read_flag, the reset end of each test control sub-circuit 111 receives the first reset signal Rst1, and the output end of each test control sub-circuit 111 outputs a corresponding test enable signal Test_en (i is a positive integer less than or equal to n) or one detection result Result , the output end of the last-stage test control sub-circuit 111 is further used for outputting the detection result Result The serial output in turn is the test result signal Test_out.

[0106] In some embodiments, referring to FIG. 9, each test control sub-circuit 111 includes:

[0107] a selector 1111, a first input of the selector 1111 being the first input of the test control sub-circuit 111, and a second input of the selector 1111 receiving the corresponding one of the detection results Result The control end of the selector 1111 is connected to the control end of the test control sub-circuit 111 to receive a read identification signal Read_flag.

[0108] The input end of the first D flip-flop 1112 is electrically connected to the output end of the selector 1111, the clock end of the first D flip-flop 1112 is connected to the control end of the test control sub-circuit 111 to receive a test clock signal Tclk, and the output end of the first D flip-flop 1112 is connected to the output end of the test control sub-circuit 111 to output a test enable signal Test_en The reset end of the first D flip-flop receives a first reset signal Rst1.

[0109] It should be noted that in the embodiments of the present disclosure, the input of the test control signal Test_in and the output of the detection result Result<1:n> share a set of transmission circuits. Referring to FIG. 10, before the T1 moment, the read-out identification signal Read_flag always indicates that the test control circuit 11 is in the data transmission stage, and the selector 1111 outputs the test control signal Test_in to the input end of the first D flip-flop 1112 based on the read-out identification signal Read_flag in the low voltage state (logic "0"), and the selector 1111 does not read the detection result Result At this time, the data transmitted / shifted by the test control circuit 11 is the test control signal Test_in to generate the corresponding test enable signals Test_en<1:n>, and the data Sreg<1:n> outputted by each test control sub-circuit based on the test clock signal Tclk as the corresponding test enable signals Test_en<1:n> (Sreg<1> as the test enable signal Test_en<1>, Sreg<2> as the test enable signal Test_en<2>…Sreg <n>Test_en as a test enable signal <n>); at the T1-T2 stage, when the read identification signal Read_flag indicates that the test control circuit 11 is in the detection result reading stage, each test control sub-circuit 111 reads the corresponding detection result Result<1:n> to the output end (the first test control sub-circuit reads the detection result Result<1> to its output end, the second test control sub-circuit reads the detection result Result<2> to its output end, and so on. The last test control sub-circuit reads the detection result Result <n>The selector 1111 selects the detection result Result (read to its output terminal) based on the read-out identification signal Read_flag in the high level state (logic "1"), specifically, the selector 1111 selects the detection result Result based on the read-out identification signal Read_flag in the high level state (logic "1"). The selector 1111 outputs the detection result Result to the output terminal 1112. The output of the first D flip-flop 1112 is input to the first D flip-flop 1112, and the first D flip-flop 1112 outputs the detection result Result based on a first rising edge (T4 time) of the test clock signal Tclk after the T1 time Read to its output, output is Sreg ; and in the T1-T2 stage, due to the clock selection of the selector 1111, the detection result Result As output, therefore, at this stage each stage test control sub-circuit is performing a read of the detection result Result the operation of the test control circuit 11, and does not perform the shift transfer operation of the data; in the T2-T3 stage, the read-out identification signal Read_flag indicates again that the test control circuit 11 is in the data transfer stage, and since the detection result Result<1:n> of the current round of defect test has been read to the output end of each test control sub-circuit 111, at this time the data shifted in the test control circuit 11 is the detection result Result<1:n>, and the corresponding detection result Result <n>After output, based on the test clock signal Tclk, the cascaded multiple test control sub-circuits will output other detection results Result <n-1>…Result<1> is sequentially shifted to the output terminal of the last stage test control sub-circuit, at which time the data Sreg output by the last stage test control sub-circuit <n>The test result signal Test_out is outputted as a test result signal.

[0110] In some embodiments, the transmission of the test control signal Test_in and the transmission of the detection result Result<1:n> can also be respectively set with a set of transmission circuits, although the circuit area and power consumption will be increased, in this scheme, the transmission of the test control signal and the transmission of the detection result can be synchronized and not interfere with each other, which can effectively improve the test efficiency and further ensure the accuracy of the test result.

[0111] In some embodiments, referring to FIG. 11, the defect detection circuit 13 is further configured to receive a detection result latch signal Update and latch each detection result Result<1:n> after each defect detection is completed in response to the detection result latch signal Update.

[0112] Here, after the charging and discharging operations are sequentially performed on the target conductive via (TSV2), the defect detection circuit 13 performs level detection on all conductive vias 10 to generate a plurality of detection identification signals flag<1:n>, and for each detection identification signal flag and a corresponding test enable signal Test_en comparing to generate a comparison result Com , comparison result Com After the generation (i.e. after each end of defect detection), the defect detection circuit 13 will latch the comparison result Com according to the detection result and the signal Update in time Output and latch as detection result Result and record the detection result of each conductive path 10 in each defect detection in time, to prevent the loss of detection data.

[0113] In some embodiments, continuing to refer to FIG. 11, the defect detection circuit 13 is further configured to, after the charging and discharging operations are sequentially performed on any conductive path 10 as the target conductive path, in response to the received detection result latch signal Update, according to the current detection identification signal flag and a corresponding test enable signal Test_en Comparison results of Com For each detection result Result latch after holding or updating;

[0114] wherein, upon detecting the identification signal flag and a corresponding test enable signal Test_en If not, keep or update the corresponding detection result Result For the first level, at detecting the flag signal flag and a corresponding test enable signal Test_en At the same time, the corresponding detection result Result is maintained Constant; detection result Result indicates that the corresponding conductive path 10 is defective, the detection result Result indicates that the corresponding conductive path 10 has no defect, and the first level is opposite to the second level.

[0115] Here, the detection result latch signal Update is at the first level when the current comparison result Com Maintain or update detection result Result When the detection result latch signal Update is the second level, the detection result Result Locked, at which time the comparison result Com To the detection result Result No effect; wherein the first level can be a high level or a low level, and the second level corresponds to a low level or a high level.

[0116] It should be noted that, as described above, each round of defect testing includes multiple defect detections, and each defect detection only takes 1 conductive path 10 as a target conductive path to perform defect detection. If there are n conductive paths 10 to be detected, n defect detections need to be performed in each round of defect testing. In the embodiment of the present disclosure, the defect detection circuit 13 detects the level change of all conductive paths 10 to generate a detection result Result<1:n> in each defect detection. n defect detections are performed, and the detection result Result<1:n> corresponding to the conductive path 10 is also generated n times. The detection result Result<1:n> generated each time may be different. As shown in FIG. 4, if the conductive path D1 at the X1 / Y1 position has a disconnection defect, the defect can only be detected in the defect detection in which the conductive path D1 is taken as a target conductive path. The detection result corresponding to the conductive path D1 at the X1 / Y1 position should be "1" (not pass). In other defect detections, the detection result corresponding to the conductive path D1 at the X1 / Y1 position is "0" (pass). If the conductive path D1 at the X1 / Y1 position has a short circuit defect to the conductive path D2 at the X1 / Y1 position, the defect can only be detected in the defect detection in which the conductive path D2 at the X1 / Y1 position is taken as a target conductive path. Therefore, the detection result Result<1:n> of which defect detection is correct, and how to update or keep the detection result Result<1:n> after each defect detection is a problem that needs to be considered.

[0117] In the embodiment of the present disclosure, the detection result Result<1:n> of each conductive path is updated or kept in the manner of "stick"1". Specifically, as shown in Table 1, the comparison result Com when the flag "1" is set (detection flag signal flag and a test enable signal Test_en not the same, i is a positive integer greater than or equal to 1 and less than or equal to n, indicates that the ith electrically conductive path has a defect, and the detection result Result of the ith electrically conductive path is updated "1", and the detection result is maintained until the end of the present round of detection to output the detection result Result and the comparison result Com corresponding to the i-th conductive path 10 when the detection flag signal flag[0] is "0" (step S1002) and a test enable signal Test_en the same), indicating that the i-th conductive path does not have a defect, maintaining the original detection result Result Invariable.

[0118] Table 1

[0119] In other embodiments, the detection results Result<1:n> of each conductive path can also be updated or maintained in a "stick" 0 manner, which is not limited in the embodiments of the present disclosure.

[0120] In some embodiments, continuing to refer to FIG. 11, the defect detection circuit 13 includes a plurality of defect detection sub-circuits 131, which correspond to the plurality of conductive paths 10 one by one.

[0121] Each defect detection sub-circuit 131 includes:

[0122] The test signal detection sub-circuit 132 is electrically connected to the first end of the corresponding conductive path 10, and is configured to detect the level change of the conductive path to generate and output a detection identification signal flag ;

[0123] The test result latch sub-circuit 133 is electrically connected with the test signal detection sub-circuit 132 and the test control circuit 11, and is configured to latch the test result according to the detection flag signal flag and a corresponding test enable signal Test_en comparing the results of the comparison generates a detection result Result and latches the detection result Result in response to the detection result latch signal Update .

[0124] In some embodiments, referring to FIG. 12, the test signal detection sub-circuit 132 includes:

[0125] a first NOT gate 1321, an input end of the first NOT gate 1321 being electrically connected with a first end of the corresponding conductive path 10;

[0126] a second NOT gate 1322, an input end of the second NOT gate 1322 being electrically connected with an output end of the first NOT gate 1321, and an output end of the second NOT gate 1322 being electrically connected with an input end of the first NOT gate 1321;

[0127] a second D flip-flop 1323, an input end of the second D flip-flop 1323 being electrically connected with the power supply voltage VDD, a clock end of the second D flip-flop 1323 being electrically connected with an output end of the first NOT gate 1321, and an output end of the second D flip-flop 1323 outputting a detection identification signal flag ;

[0128] The test result latching sub-circuit 133 comprises:

[0129] A first exclusive OR gate 1331, a first input end of the first exclusive OR gate 1331 is electrically connected with the output end of the second D flip-flop 1323, and a second input end of the first exclusive OR gate 1331 receives a corresponding test enable signal Test_en ;

[0130] a first OR gate 1332, a first input end of the first OR gate 1332 is electrically connected with an output end of the first XOR gate 1331;

[0131] a latch 1333, an input end of the latch 1333 is electrically connected with an output end of the first OR gate 1332, a control end of the latch 1333 receives a detection result latching signal Update, and an output end of the latch 1333 outputs a detection result Result The output end of the latch 1333 is further electrically connected with the second input end of the first OR gate 1332.

[0132] In some embodiments, continuing to refer to FIG. 12, the reset end of the second D flip-flop 1323 receives a second reset signal Rst2, and the second D flip-flop 1323 outputs the detection result Result the detection flag signal flag is set in response to the second reset signal Rst2 after each latching The reset is performed; a reset terminal of the latch 1333 receives a third reset signal Rst3, and the latch 1333 outputs the detection results Result A reset is performed.

[0133] It should be noted that the level change state of the conductive path 10 is detected again each time a defect is detected to generate a new detection flag signal flag To avoid the current detection flag signal flag the detection flag signal flag generated in the next defect detection Impacting, needs to be in the detection result Result The signal Update is latched after the detection result, and is reset at the same time. In order to avoid the influence of the current defect test on the next defect test or other tests, the latch 1333 needs to reset the output after all the detection results Result<1:n> are serially output.

[0134] It should be noted that the first reset signal Rst1 and the third reset signal Rst3 are both used to indicate the reset of the output of the related circuit after all the detection results Result<1:n> are serially output, and thus can be the same signal.

[0135] In combination with FIG. 13, the working principle of the defect detection circuit 13 provided in the embodiment (FIGS. 11-12) is described (here, taking the example that only one conductive path 10 is set as the target conductive path in each defect detection).

[0136] Starting from T10, the first defect detection of the current defect test is started according to the test enable signal Test_en<1:n> (Test_en<1> = logic "1", Test_en<2:n> = logic "0") output by the test control circuit, and the power supply control circuit 12 first performs charging and discharging on the conductive path TSV1 in turn.

[0137] At T11, the test signal detection sub-circuit 132 detects the level change of the conductive path TSV1. If the conductive path TSV1 does not have defects, the conductive path TSV1 is changed from charging to discharging, and the first end of the conductive path TSV1 is changed from high level to low level. At this time, the trigger signal Kick<1> output by the first NOT gate 1321 in the test signal detection sub-circuit 132 connected to the first end of the conductive path TSV1 is changed from low level to high level, and the second D flip-flop 1323 receives the change of the trigger signal Kick<1> based on the clock, and sets the detection identification signal flag<1> output by the input end connected to the power supply voltage VDD to high level (logic "1"). The test result latching sub-circuit 133 compares the detection identification signal flag<1> with the test enable signal Test_en<1> to generate and output the detection result Result<1>. Specifically, the first XOR gate 1311 performs XOR operation on the detection identification signal flag<1> (logic "1") and the test enable signal Test_en<1> (logic "1") to output the comparison result Com<1> of low level (logic "0"), and the first OR gate 1332 outputs the low level signal (logic "0") to the input end of the latch 1333 according to the comparison result Com<1> (logic "0") and the current detection result Result<1> (reset to logic "0" by the third reset signal Rst3 before the defect test starts).

[0138] While the other conductive paths TSV2-TSVn are not subjected to the complete charging and discharging operation by the power control circuit 12 due to the low level (logic "0") of the test enable signals Test_en<2:n>, the corresponding trigger signals Kick<2:n> should have a rising edge if there is no defect in the conductive paths TSV2-TSVn, and the corresponding detection flag signals flag<2:n> remain low (reset to logic "0" by the second reset signal Rst2 after each defect detection). The corresponding comparison results Com<2:n> and the corresponding first OR gate 1332 also output a low level (logic "0").

[0139] At T13, since the discharging operation of the conductive path TSV1 has been completed by the power control circuit 12 at the previous T12, the test signal detection sub-circuit 132 and the test result latching sub-circuit 133 should have completed the level detection operation on all conductive paths. At this time, the detection result latching signal Update changes from low to high, and the latch 1333 switches from the latching state to the pass-through state, i.e., the low level signal (logic "0") output by the first OR gate 1332 is output as the detection result Result , i.e. continue to keep the detection result as low level (logic "0") to indicate that the conductive path TSV1-TSVn is defect-free (pass).

[0140] At T14, the detection result latch signal Update changes from high level to low level, the latch 1333 switches from pass-through state to latching state, and the detection result Result output by this time defect detection is latched and stored in the latch 1333. Locking;

[0141] Since the output of the latch 1333 is connected to the second input of the first OR gate 1332, if any of the conductive paths TSVi is defective, the locked detection result Result If the output is high (logic "1"), the output of the corresponding first OR gate 1332 is set to high (logic "1"), and then the comparison result Com of the other defect test is outputted. The output of the first OR gate 1332 will no longer be affected by the output of the first AND gate 1330 and the detection result Result , the detection result Result The high level (logic "1") will be maintained all the time, based on which the detection result "1" purpose can be achieved; in the detection result Result Locked, detection of identification signal flag The reset can be performed based on the second reset signal Rst2 to avoid affecting the results of subsequent other defect detection.

[0142] It should be noted that the latch 1333 can also be in a latching state when the detection result latch signal Update is high, and in a pass-through state when the detection result latch signal Update is low, and the embodiments of the present disclosure do not limit this.

[0143] At T15, the test control circuit 13 controls the test enable signal Test_en<1:n> to perform shift transmission, and the logic "1" is shifted from the test enable signal Test_en<1> to the test enable signal Test_en<2>, so that the power supply control circuit 12 performs charging and discharging on the next target conductive path TSV2 in turn to start the second defect detection, and so on, until all conductive paths TSV1-TSVn are subjected to defect detection to generate the final detection result Result<1:n>.

[0144] It should be noted that in each defect detection, all conductive paths can be charged but only the target conductive path can be discharged; only the target conductive path can be charged but all conductive paths can be discharged; only the target conductive path can be charged and discharged, and other conductive paths are neither charged nor discharged, and the embodiments of the present disclosure do not limit this.

[0145] At T16, after the test control circuit has serially output the final detection result Result<1:n> based on the result readout identification signal Read_flag, the latch 1333 can be reset based on the third reset signal Rst3.

[0146] In some embodiments, referring to FIG. 14, the power supply control circuit 12 includes:

[0147] The first power supply control circuit 121 is electrically connected to the first end of each conductive path 10 and the test control circuit 11 respectively, and is configured to control the first end of the target conductive path to be electrically connected to the power supply voltage VDD or the ground voltage GND when the test enable signal Test_en<1:n> is in an effective state.

[0148] The second power supply control circuit 122 is electrically connected to the second end of each conductive path 10, and is configured to control the second end of the conductive path 10 to be electrically connected to the ground voltage GND or the power supply voltage VDD.

[0149] In some embodiments, referring to FIG. 4, FIG. 5 and FIG. 8, the plurality of conductive paths 10 are divided into a plurality of conductive path groups 110 arranged in an array, each conductive path group 110 including l*m conductive paths 10 arranged in an array, l and m are both positive integers greater than or equal to 2.

[0150] It should be noted that l and m can be the same positive integer or different positive integers, and in FIG. 4, FIG. 5 and FIG. 8, l = m = 2 is taken as an example for illustration. Specifically, the values of l and m can be adjusted according to the number, position and arrangement of the conductive paths, and the embodiments of the present disclosure do not limit this.

[0151] In some embodiments, referring to FIG. 5 and FIG. 14, the first power supply control circuit 121 is further configured to, in each defect detection, based on the plurality of test enable signals Test_en<1:n> take one conductive path (D1) in each conductive path group 110 as a target conductive path, and control the first end of each target conductive path to be electrically connected with the power supply voltage VDD or the ground voltage GND.

[0152] In some embodiments, referring to FIG. 4, FIG. 14 and FIG. 15, the second power supply control circuit 122 is further configured to receive a test area selection signal TSVSEL (taking p position areas as an example for illustration, p is a positive integer), and based on the test area selection signal TSVSEL control the second end of the selected conductive path (the conductive path D1 at the X1 / Y1 position) to be electrically connected with the ground voltage or the power supply voltage.

[0153] In some embodiments, referring to FIG. 4, FIG. 14 and FIG. 15, the second power supply control circuit 122 is further configured to receive a test area selection signal TSVSEL (taking p position areas as an example for illustration, p is a positive integer), and based on the test area selection signal TSVSEL control the second end of the selected conductive path (the conductive path D1 at the X1 / Y1 position) to be electrically connected with the ground voltage or the power supply voltage. <j>(j is a positive integer less than or equal to p) indicates whether the conductive path in the corresponding position area is selected; each position area includes at least one conductive path group 110.

[0154] Here, in each defect detection, the second power supply control circuit 122 can select all conductive paths of a single position area or a partial position area to discharge / charge based on the test area selection signal TSVSEL, so as to reduce the transient current and power consumption of the test circuit 100; when the test circuit 100 has strong endurance to the transient current and power consumption, in each defect detection, the second power supply control circuit 122 can also select all position areas to discharge / charge all conductive paths at the same time based on the test area selection signal TSVSEL, so as to simplify the control operation of the test circuit 100; the embodiments of the present disclosure are not limited thereto.

[0155] It should be noted that each position area can include only one conductive path group 110, as shown in FIG. 4, taking 16 position areas as an example, each position area includes a conductive path group 110 of one position combination, the conductive path group 110 at the X0 / Y0 position corresponds to the first position area, the conductive path group 110 at the X0 / Y1 position corresponds to the second position area, when the first position area is selected based on the test area selection signal TSVSEL, only all conductive paths in the conductive path group 110 at the X0 / Y0 position need to be charged or discharged, the instantaneous current and power consumption in the test circuit are small, but 16 test area selection sub-signals Tsvsel <j>The control circuit selects 16 conductive path groups 110 respectively, and the circuit area and transmission channel are large; each position area can also include multiple conductive path groups 110, and the four position areas are taken as examples for description with continuous reference to FIG. 4, each position area includes four position combined conductive path groups 110, the four conductive path groups 110 at X0 / Y0, X0 / Y1, X0 / Y2, X0 / Y3 positions correspond to the first position area (of course, X0 / Y0, X0 / Y1, X1 / Y0, X1 / Y1 can also be divided into the first position area, which is not limited), the four conductive path groups 110 at X1 / Y0, X1 / Y1, X1 / Y2, X1 / Y3 positions correspond to the second position area, when the first position area is selected based on the test area selection signal TSVSEL, all conductive paths at X0 / Y0, X0 / Y1, X0 / Y2, X0 / Y3 positions need to be charged or discharged at the same time, the instantaneous current and power consumption in the test circuit are large, but only four test area selection sub-signals Tsvsel <j>The 16 conductive path groups 110 are selected by the control circuit 16, which occupies less circuit area and transmission line channel; specifically, the adjustment can be made according to the instantaneous current, instantaneous power consumption, occupied area, occupied line channel and other circuit design elements, which is not limited in the embodiments of the present disclosure.

[0156] In some embodiments, the first power supply control circuit 121 can also select part of the conductive paths in a single position area or a partial position area as the target conductive paths for charging / discharging operation based on the test area selection signal TSVSEL and the test enable signal Test_en at the same time.

[0157] In some embodiments, please refer to FIG. 15, the first power supply control circuit 121 includes a plurality of first power supply control sub-circuits 123, and the second power supply control circuit 122 includes a plurality of second power supply control sub-circuits 124, and the plurality of first power supply control sub-circuits 123 and the plurality of second power supply control sub-circuits 124 correspond to the plurality of conductive paths 10 one by one.

[0158] In some embodiments, the first power supply control sub-circuit 123 is used to control the discharging of the conductive path 10, and the second power supply control sub-circuit 124 is used to control the charging of the conductive path 10, and please continue to refer to FIG. 15, the first power supply control sub-circuit 123 includes:

[0159] The first AND gate 1231 receives the pull-down control signal NDRV at the first input end, and receives the corresponding test enable signal Test_en at the second input end ;

[0160] The first N-type transistor 1232 has a first end electrically connected to the first end of the conductive path 10, a second end electrically connected to the ground voltage GND, and a control end electrically connected to the output end of the first AND gate 1231.

[0161] The second power supply control sub-circuit 124 includes:

[0162] The second AND gate 1241 has a first input end receiving the pull-up control signal PDRV and a second input end receiving a corresponding test area selection sub-signal Tsvsel <j>;

[0163] The first P-type transistor 1242 has a first end electrically connected to the second end of the conductive path 10, a second end electrically connected to the power supply voltage VDD, and a control end electrically connected to the output end of the second AND gate 1241.

[0164] It should be noted that in the embodiments of the present disclosure, the first power control sub-circuit 123 is configured to control discharging of the conductive path 10, and the second power control sub-circuit 124 is configured to control charging of the conductive path 10.

[0165] In some embodiments, the first power control sub-circuit 123 is configured to control charging of the conductive path 10, and the second power control sub-circuit 124 is configured to control discharging of the conductive path 10. Please refer to FIG. 16, the first power control sub-circuit 123 includes:

[0166] The third AND gate 1233 has a first input end receiving the pull-up control signal PDRV, and a second input end receiving a corresponding test enable signal Test_en ;

[0167] The first end of the second P-type transistor 1234 is electrically connected with the first end of the conductive path 10, the second end of the second P-type transistor 1234 is electrically connected with the power voltage VDD, and the control end of the second P-type transistor 1234 is electrically connected with the output end of the third AND gate 1233.

[0168] The second power supply control sub-circuit 124 comprises:

[0169] The first input end of the fourth AND gate 1243 receives a pull-down control signal NDRV, the second input end of the fourth AND gate 1243 receives a corresponding test area selection sub-signal Tsvsel <j>;

[0170] The first end of the second N-type transistor 1244 is electrically connected with the second end of the conductive path 10, the second end of the second N-type transistor 1244 is electrically connected with the ground voltage, and the control end of the second N-type transistor 1244 is electrically connected with the output end of the fourth AND gate 1243.

[0171] In some embodiments, still referring to FIG. 15 and FIG. 16, the second power supply control circuit 122 further comprises a plurality of holding circuits 125 corresponding to the plurality of conductive paths 10 one by one.

[0172] The holding circuit 125 comprises:

[0173] The third NOT gate 1251 has an input end electrically connected with the second end of the corresponding conductive path 10.

[0174] The fourth NOT gate 1252 has an input end electrically connected with the output end of the third NOT gate 1251, and an output end electrically connected with the input end of the third NOT gate 1251.

[0175] It should be noted that in other embodiments, the holding circuit 125 can also be arranged in the first power supply control circuit 121, and the holding circuit 125 can also be arranged in the first power supply control circuit 121 and the second power supply control circuit 122 respectively, and the present disclosure does not limit this.

[0176] In some embodiments, as shown in FIG. 17, the test circuit 100 further comprises a test area selection circuit 15, which comprises a plurality of test area selection sub-circuits 151 corresponding to the plurality of position areas one by one; each test area selection sub-circuit 151 comprises:

[0177] The first NAND gate 1511 has a first input end receiving a first position selection sub-signal TSV_X<1:r> and a second input end receiving a second position selection sub-signal TSV_Y<1:s>.

[0178] The second NAND gate 1512 has a first input end connected with the output end of the first NAND gate 1511 and an output end outputting a test area selection sub-signal Tsvsel<1:j>.

[0179] The third NAND gate 1513 has a first input end connected with the output end of the second NAND gate 1512, a second input end receiving a fourth reset signal Rst4, and an output end connected with the second input end of the second NAND gate 1512.

[0180] wherein s, r are positive integers, and s*r=j.

[0181] Fig. 18 shows a test circuit 100 provided by an embodiment of the present disclosure, wherein the input of the test control signal Test_in in the test control circuit 11 and the output of the detection result Result<1:n> share a set of transmission circuit structure (not shown in the figure) which can be referred to the description of Fig. 6, Fig. 7, Fig. 9 and Fig. 10 and the aforementioned embodiments; in combination with Fig. 19, the working principle of the test circuit 100 provided by the embodiment of the present disclosure (Fig. 18) is described (herein taking the test control signal Test_in as a serial data combination with only 1 bit being logic "1", the first power control sub-circuit 123 for controlling discharging the conductive path 10, and the second power control sub-circuit 124 for controlling charging the conductive path 10 as an example):

[0182] Before T31 moment, the test control circuit 11 serially inputs the test control signal Test_in based on the test clock signal Tclk, and completes the first defect detection based on the test enable signal Test_en<1> = 1, Test_en<2:n> = 0 and the conductive path TSV1 as the target conductive path (not shown in the figure, the working principle of this stage can be referred to the specific description of Fig. 4 and the aforementioned embodiments);

[0183] At T31 moment, after the first defect detection is completed, the test control circuit 11 performs 1-bit shift transmission (shift "1") on the test control signal Test_in based on the test clock signal Tclk, and regenerates and outputs a plurality of test enable signals Test_en<1:n>, at this time, only the test enable signal Test_en<2> is logic "1", and the rest of the test enable signals are logic "0", and the conductive path TSV2 as the target conductive path;

[0184] At T32 moment, the second power control sub-circuit 124 generates and outputs the pull-up control signal PDRV and the test area selection sub-signal Tsvsel <j>, all the conductive paths TSV2-TSV3 (assuming that the conductive path TSV2 and the conductive path TSV3 belong to the same location area) in the selected location area are charged at the same time;

[0185] At T33, the first power supply control sub-circuit 123 performs a pull-down discharge operation on the conductive via TSV2 based on the pull-down control signal NDRV and the test enable signal Test_en<1:n> (wherein only the test enable signal Test_en<2> is logic "1"), and the defect detection sub-circuit 131 will detect a change from high level to low level in the conductive path TSV2 to generate a detection identification signal flag<2> of high level (logic "1"), since the Test_en<2> (which can be understood as an expected level change detection result) and the detection identification signal flag<2> (which can be understood as an actual level change detection result) are the same, the output comparison result Com<2> is low level (logic "0");

[0186] As shown by the solid line in the figure, the conductive path TSV3 will not perform a discharge operation under normal circumstances, and the corresponding defect detection sub-circuit 131 will not detect a change from high level to low level in the conductive path TSV3, and the generated detection identification signal flag<3> (which can be understood as an actual level change detection result) and the Test_en<3> (which can be understood as an expected level change detection result) are both the same logic "0", and the output comparison result Com<3> is also low level (logic "0");

[0187] As shown by the dashed line in the figure, if there is a short circuit defect between the conductive paths TSV2 and TSV3, the conductive path TSV3 will perform a discharge operation synchronously with the conductive path TSV2 at T33, and the corresponding defect detection sub-circuit 131 will also detect a change from high level to low level in the conductive path TSV3, at this time the generated detection identification signal flag<3> (which can be understood as an actual level change detection result) is logic "1", and the logic "0" of the Test_en<3> (which can be understood as an expected level change detection result) is not the same, and the output comparison result Com<3> becomes high level (logic "1");

[0188] At T34, as shown by the dashed line in the figure, the defect detection sub-circuit 131 will lock the high level of the comparison result Com<3> of high level (logic "1") as a detection result Result<3> based on the detection result latching signal Update, and the high level (logic "1") of Result<3> indicates that there is a defect in the conductive path TSV3;

[0189] At the T35 moment, the test control circuit 11 continues to perform 1-bit shift transmission of the test control signal Test_in based on the test clock signal Tclk, at this time, only the test enable signal Test_en<3> is logic "1", and the rest of the test enable signals are all logic "0", and the conductive path TSV3 is taken as the target conductive path;

[0190] After that, the second power supply control sub-circuit 124 performs the pull-up control signal PDRV and the test area selection sub-signal Tsvsel <j>all the conductive paths TSV2-TSV3 in the selected location area are charged simultaneously;

[0191] At T36, the first power control sub-circuit 123 performs a pull-down discharge operation on the conductive via TSV3 based on the pull-down control signal NDRV and the test enable signal Test_en<1:n> (at this time only the test enable signal Test_en<3> is logic "1"), which is similar to the defect detection of the aforementioned target conductive path TSV2. As shown by the dashed line in the figure, when there is a short circuit defect between the conductive paths TSV2 and TSV3, the conductive path TSV2 will perform a discharge operation synchronously with the conductive path TSV3 at T36, and the defect detection sub-circuit 131 can detect that the conductive path TSV2 and the conductive path TSV3 are both changed from high level to low level. At this time, the detection flag signal flag<2> (which can be understood as the actual level change detection result) generated is logic "1", which is different from the logic "0" of Test_en<2> (which can be understood as the expected level change detection result), and the output comparison result Com<2> becomes high level (logic "1");

[0192] At T37, as shown by the dashed line in the figure, the defect detection sub-circuit 131 will lock the high level of the comparison result Com<2> (logic "1") as the detection result Result<2> based on the detection result latch signal Update. The high level (logic "1") of Result<2> indicates that there is a defect in the conductive path TSV2;

[0193] By analogy, until all conductive paths are detected as target conductive paths, and then the final detection results Result<1:n> are all serially output as the contents of the detection result signal Test_out based on the result read flag Read_flag. For details, please refer to the description of the foregoing embodiments and Figures 9 and 10.

[0194] In some embodiments, referring to Figure 20, the test circuit is applied to a stacked chip structure 200, which includes a first chip Die0 and a second chip Die1 stacked on the first chip Die0.

[0195] The first power control circuit 121, the test control circuit 11, and the defect detection circuit 13 are all arranged in the first chip Die0, the second power control circuit 122 is arranged in the second chip Die0, and the conductive path 10 is used to transmit signals between the first chip Die0 and the second chip Die0.

[0196] It should be noted that the stacked chip structure 200 can be a Wafer on Wafer (WoW) memory chip, the first memory chip Die 0 is a control circuit chip, the second memory chip Die 1 is a memory array chip, the first chip and the second chip are stacked along a third direction, and the third direction is perpendicular to the top surface of the chip.

[0197] In some embodiments, referring to FIG. 21, the test circuit is applied to the stacked chip structure 200, the stacked chip structure 200 includes: a first chip Die 0 and at least one second chip Die 1-Die L stacked on the first chip Die 0;

[0198] The first power supply control circuit 121, the test control circuit 11, and the defect detection circuit 13 are all arranged in the first chip Die 0, a plurality of second power supply control circuits 122-1…122-L are arranged in the plurality of second chips Die 1-Die L respectively, and the conductive path 10 is used to transmit signals between the first chip Die 0 and the second chip Die 1-Die L and between the second chips Die 1-Die L.

[0199] It should be noted that the stacked chip structure 200 can also be an HBM, the stacked chip structure 200 can include a plurality of second memory chips, the first chip and the plurality of second chips are stacked along a third direction, and the third direction is perpendicular to the top surface of the chip, the first memory chip Die 0 is a logic chip, and the second memory chips Die 1-Die L are all memory chips, L can be 4 / 8 / 12 / 16…, and the embodiments of the present disclosure are not limited thereto.

[0200] It should be noted that the pull-up control signal PDRV or the pull-down control signal NDRV received by the second power supply control sub-circuit 124 in the embodiments of the present disclosure can be transmitted from the first chip Die 0 to the second chip Die 1, so as to ensure that the control signals received by the second power supply control sub-circuit 124 in the second chip Die 1 and the control signals received by other circuits in the first chip Die 0 are consistent in timing, and prevent the problem of inconsistent timing of control signals of different chips in the test circuit from causing inaccurate defect detection results.

[0201] It should be noted that the test region selection circuit 15 in the embodiments of the present disclosure can be arranged in the first chip Die 0; or can be arranged in the second chip Die 1, in which case the first position selection sub-signal TSV_X<1:r> and the second position selection sub-signal TSV_Y<1:s> received by the test region selection sub-circuit 151 can be transmitted from the first chip Die 0 to the second chip Die 1.

[0202] In some embodiments, referring to FIG. 22, the test circuit 100 further includes:

[0203] The clock shielding circuit 14 is connected with the test control circuit 11, configured to receive the initial clock signal Oclk, and generate and output the test clock signal Tclk based on the initial clock signal Oclk when none of the conductive paths 10 performs the defect detection, and not output the test clock signal Tclk when any of the conductive paths 10 performs the defect detection.

[0204] It should be noted that, as shown in FIG. 23, none of the conductive paths 10 performing the defect detection includes the following three cases: before the current round of defect testing (before T21, the current round of defect testing has not started, and the test control signal Test_in needs to be input based on the test clock signal Tclk); during the interval between two times of defect detection (T22-T23, the first time of defect detection ends at T22 with TSV1 as the target conductive path, and the second time of defect detection starts at T23 for TSV2 as the target conductive path, and between T22 and T23, the test clock signal Tclk is required to shift the test enable signal Test_en<1:n>); and after the defect detection of all the conductive paths is completed, the test clock signal Tclk is required to serially output the test results Result<1:n> as the test result signal Test_out (not shown in the figure). As shown in FIG. 23, between T21 and T22, the test clock signal Tclk is not required to be output when the conductive path TSV1 performs the defect detection, so as to avoid the test enable signal Test_en<1:n> being shifted and transmitted incorrectly, resulting in inaccurate test results.

[0205] The clock shielding circuit 14 can shield the test clock signal Tclk when it does not need to receive or transmit data, so as to ensure the accuracy of the defect testing performed by the test circuit 100, and effectively save the power consumption of the test circuit 100.

[0206] The embodiment of the present disclosure further provides a test method of the stacked chip structure 200, referring to FIG. 24, the test method comprises:

[0207] Step S1: in response to the test clock signal Tclk, receiving the serially input test control signal Test_in in sequence, generating and outputting a plurality of test enable signals Test_en<1:n> corresponding to the plurality of conductive paths 10 one by one;

[0208] Step S2: in response to the test enable signal Test_en The corresponding conductive path 10 is taken as a target conductive path to perform defect detection;

[0209] Step S3: During each defect detection, the level change of each conductive path 10 is detected respectively to generate a plurality of detection identification signals flag<1:n> corresponding to the plurality of conductive paths 10 one by one;

[0210] Step S4: According to the comparison result Com<1:n> of each detection identification signal flag<1:n> and the corresponding test enable signal Test_en<1:n>, a plurality of detection results Result<1:n> corresponding to the plurality of conductive paths 10 one by one are generated;

[0211] Step S5: After each defect detection, the detection results Result<1:n> are latched in response to the detection result latch signal Update.

[0212] Through the above test method, only one test port serially input test control signal can indicate the defect detection of all conductive paths, which can effectively save the test port resources and test circuit complexity. At the same time, the level change of all conductive paths is detected to generate the detection result of each conductive path during each defect test of the target conductive path, which can effectively cover the detection of all types of defects and improve the accuracy and comprehensiveness of the defect detection of the conductive path.

[0213] In some embodiments, the test method further comprises:

[0214] Step S6: After all conductive paths 10 complete defect detection as target conductive paths or after each round of defect test, the latched detection results Result<1:n> are serially output as test result signals Test_out based on the test clock signal Tclk.

[0215] In some embodiments, step S6 specifically comprises:

[0216] Step S61: After all conductive paths 10 complete defect detection as target conductive paths, when the result readout identification signal Read_flag indicates that it is in the test result readout stage, the latched detection results Result<1:n> are read out in response to the test clock signal Tclk;

[0217] Step S62: and when the result readout identification signal Read_flag indicates that it is in the data transmission stage, the read detection results Result<1:n> are serially output as test result signals Test_out in response to the test clock signal Tclk.

[0218] In some embodiments, the "latching the detection result Result<1:n> in response to the detection result latching signal Update" in step S5 specifically comprises: after performing the defect detection on any target conductive path 10, in response to the received detection result latching signal Update, maintaining or updating each detection result Result<1:n> according to the comparison result Com<1:n> of the current each detection identification signal flag<1:n> and the corresponding test enable signal Test_en<1:n>.

[0219] wherein, the detection identification signal flag and a corresponding test enable signal Test_en If not, keep or update the corresponding detection result Result high, in detecting the flag signal flag and a corresponding test enable signal Test_en At the same time, the corresponding detection result Result is maintained Constant; detection result Result high, indicating that the corresponding conductive path 10 is defective, the detection result Result is low, indicating that the corresponding conductive path 10 does not have defects.

[0220] In some embodiments, step S2 in the test method specifically comprises:

[0221] S21: in response to the test enabling signal Test_en in the active state , the first end of the target conductive path is electrically connected with a power voltage VDD to perform a charging operation;

[0222] S22: after the charging operation is completed, the second end of the target conductive path and the second end of the conductive path adjacent to the target conductive path are electrically connected with a ground voltage GND respectively to perform a discharging operation.

[0223] In some embodiments, the plurality of conductive paths 10 are divided into a plurality of conductive path groups 110 arranged in an array, each conductive path group 110 including l*m conductive paths 10 arranged in an array, l and m are both positive integers greater than or equal to 2; in this case, step S2 in the test method specifically includes:

[0224] S23: in response to a plurality of test enable signals Test_en Each of the conductive paths 10 in each of the conductive path groups 110 is targeted as a target conductive path, and the first end of each of the target conductive paths is controlled to be electrically connected to the power supply voltage VDD to perform a charging operation.

[0225] S24: In response to a test area selection signal TSVSEL, the second end of the selected conductive path 10 is controlled to be electrically connected to the ground voltage GND to perform a discharging operation.

[0226] The test area selection signal TSVSEL includes a plurality of test area selection sub-signals Tsvsel <j>indicates whether the conductive path 10 in the corresponding location area is selected; each location area comprises at least one conductive path group 110.

[0227] It should be noted that the test methods provided in the above embodiments can be applied to the test circuit 100 in the foregoing embodiments. For details not disclosed in the embodiments of the test method, please refer to the description of the foregoing embodiments of the test circuit 100 for understanding, which will not be repeated here.

[0228] It should be noted that in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the sentence "includes a…" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0229] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0230] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A test circuit (100), comprising: a plurality of conductive paths (10); a test control circuit (11) configured to receive a serially input test control signal in turn in response to a test clock signal, to generate and output a plurality of test enable signals corresponding to the plurality of conductive paths (10) one by one; wherein the test enable signal indicates whether the corresponding conductive path (10) is executed as a target conductive path for defect detection in each time of defect detection; a power supply control circuit (12) electrically connected with each of the conductive paths (10) and the test control circuit (11) respectively, configured to control the corresponding conductive path (10) to execute charging and discharging operations in turn as a target conductive path when the test enable signal is in an active state; a defect detection circuit (13) electrically connected with a first end of each of the conductive paths (10) and the test control circuit (11) respectively, configured to detect a level change of each of the conductive paths (10) to generate a plurality of detection identification signals corresponding to the plurality of conductive paths (10) one by one, and to generate and output a plurality of detection results corresponding to the plurality of conductive paths (10) one by one according to a comparison result of each of the detection identification signals and the corresponding test enable signal.

2. The test circuit (100) according to claim 1, characterized in that The test control circuit (11) is further configured to, after each time of defect detection is completed, re-generate and output a plurality of test enable signals after the test control signal is shifted and transmitted based on the test clock signal.

3. The test circuit (100) according to any one of claims 1-2, characterized in that, The test control circuit (11) is further configured to, after all of the conductive paths (10) are completed for defect detection as target conductive paths, serially output the detection results output by the defect detection circuit (13) as test result signals in turn based on the test clock signal.

4. The test circuit (100) according to any one of claims 1 to 3, characterized in that, The test control circuit (11) is further configured to receive a result readout identification signal, and to read all of the detection results output by the defect detection circuit (13) based on the test clock signal when the test control circuit (11) is in a test result readout stage indicated by the result readout identification signal, and to serially output the read detection results as the test result signals in turn based on the test clock signal when the test control circuit (11) is in a data transmission stage indicated by the result readout identification signal.

5. The test circuit (100) according to claim 4, characterized in that The test control circuit (11) is further configured to reset the test enable signal in response to a first reset signal after all of the detection results are output.

6. The test circuit (100) according to any one of claims 1 to 5, characterized in that, The test control circuit (11) comprises a plurality of test control sub-circuits (111) connected in cascade, and a plurality of test control sub-circuits (111) correspond to a plurality of conductive paths (10) one by one. A first input terminal of each of the test control sub-circuits (111) receives the test control signal, an output terminal of each of the test control sub-circuits (111) is electrically connected to a first input terminal of a next stage test control sub-circuit, a second input terminal of each of the test control sub-circuits (111) receives a corresponding detection result, a clock terminal of each of the test control sub-circuits (111) receives the test clock signal, a control terminal of each of the test control sub-circuits (111) receives the result read-out identification signal, a reset terminal of each of the test control sub-circuits (111) receives the first reset signal, and an output terminal of each of the test control sub-circuits (111) outputs a corresponding test enable signal or a corresponding detection result, and the output terminal of the last stage test control sub-circuit (111) is further configured to serially output the detection results as the test result signal.

7. The test circuit (100) according to claim 6, characterized in that Each of the test control sub-circuits (111) comprises: a selector (1111), a first input terminal of the selector (1111) being the first input terminal of the test control sub-circuit (111), a second input terminal of the selector (1111) receiving a corresponding detection result as the second input terminal of the test control sub-circuit (111), and a control terminal of the selector (1111) receiving the read-out identification signal as the control terminal of the test control sub-circuit (111); a first D flip-flop (1112), an input terminal of the first D flip-flop (1112) being electrically connected to an output terminal of the selector (1111), a clock terminal of the first D flip-flop (1112) receiving the test clock signal as the control terminal of the test control sub-circuit (111), an output terminal of the first D flip-flop (1112) outputting the test enable signal as the output terminal of the test control sub-circuit (111), and a reset terminal of the first D flip-flop (1112) receiving the first reset signal.

8. The test circuit (100) according to any one of claims 1 to 7, characterized in that, The defect detection circuit (13) is further configured to receive a detection result latch signal and latch each of the detection results in response to the detection result latch signal after each defect detection is completed.

9. The test circuit (100) according to claim 8, characterized in that The defect detection circuit (13) is further configured to, after the charging and discharging operations are sequentially performed on any of the conductive paths (10) as a target conductive path, latch each of the detection results according to a comparison result of each of the detection identification signals and a corresponding test enable signal in response to the received detection result latch signal after each of the detection results is maintained or updated; wherein, when the detection identification signal and the corresponding test enable signal are different, the corresponding detection result is maintained or updated to be a first level, and when the detection identification signal and the corresponding test enable signal are the same, the corresponding detection result remains unchanged. The detection result being the first level indicates that the corresponding conductive path (10) has a defect, and the detection result being the second level indicates that the corresponding conductive path (10) has no defect, the first level being opposite to the second level.

10. The test circuit (100) according to claim 9, characterized in that The defect detection circuit (13) comprises a plurality of defect detection sub-circuits (131), and the plurality of defect detection sub-circuits (131) correspond to the plurality of conductive paths (10) one by one. Each defect detection sub-circuit (131) comprises: a test signal detection sub-circuit (132) electrically connected to the first end of the corresponding conductive path (10) and configured to detect the level change of the conductive path (10) to generate and output the detection identification signal; a test result latching sub-circuit (133) electrically connected to the test signal detection sub-circuit (132) and the test control circuit (11) and configured to generate the detection result according to the comparison result of the detection identification signal and the corresponding test enable signal and latch the detection result in response to the detection result latching signal.

11. The test circuit (100) according to claim 10, characterized in that: the test signal detection sub-circuit (132) comprises: a first NOT gate (1321) having an input end electrically connected to the first end of the corresponding conductive path (10); a second NOT gate (1322) having an input end electrically connected to the output end of the first NOT gate (1321) and an output end electrically connected to the input end of the first NOT gate (1321); a second D flip-flop (1323) having an input end electrically connected to a power supply voltage, a clock end electrically connected to the output end of the first NOT gate (1321), and an output end outputting the detection identification signal; the test result latching sub-circuit (133) comprises: a first XOR gate (1331) having a first input end electrically connected to the output end of the second D flip-flop (1323) and a second input end receiving the corresponding test enable signal; a first OR gate (1332) having a first input end electrically connected to the output end of the first XOR gate (1331); a latch (1333) having an input end electrically connected to the output end of the first OR gate (1332), a control end receiving the detection result latching signal, an output end outputting the detection result, and the output end also electrically connected to a second input end of the first OR gate (1332).

12. The test circuit (100) according to claim 11, characterized in that: The reset terminal of the second D flip-flop (1323) receives a second reset signal, and the second D flip-flop (1323) resets the detection identification signal in response to the second reset signal after each time the detection result is latched; The reset terminal of the latch (1333) receives a third reset signal, and the latch (1333) resets the detection result in response to the third reset signal after all the detection results are output.

13. The test circuit (100) according to any one of claims 1-12, characterized in that, The power supply control circuit (12) comprises: a first power supply control circuit (121) electrically connected to the first end of each of the conductive paths (10) and the test control circuit (11), configured to control the first end of the target conductive path (10) to be electrically connected to a power supply voltage or a ground voltage when the test enable signal is in an active state; a second power supply control circuit (122) electrically connected to the second end of each of the conductive paths (10), configured to control the second end of the conductive path (10) to be electrically connected to the ground voltage or the power supply voltage.

14. The test circuit (100) according to claim 13, characterized in that, a plurality of the conductive paths (10) are divided into a plurality of conductive path groups (110) arranged in an array, each of the conductive path groups (110) comprising l*m conductive paths (10) arranged in an array, l and m are both positive integers greater than or equal to 2.

15. The test circuit (100) according to any one of claims 13-14, characterized in that, The first power supply control circuit (121) is further configured to, in each defect detection, based on a plurality of the test enable signals, take one of the conductive paths (10) in each of the conductive path groups (110) as the target conductive path (10), and control the first end of each of the target conductive paths (10) to be electrically connected to the power supply voltage or the ground voltage.

16. The test circuit (100) according to any one of claims 13-15, characterized in that, The second power supply control circuit (122) is further configured to receive a test area selection signal, and based on the test area selection signal, control the second end of the selected conductive path (10) to be electrically connected to the ground voltage or the power supply voltage; The test area selection signal comprises a plurality of test area selection sub-signals corresponding to a plurality of position areas one by one, each of the test area selection sub-signals indicates whether the conductive path (10) in the corresponding position area is selected; each of the position areas comprises at least one of the conductive path groups (110).

17. The test circuit (100) according to claim 16, characterized in that, The first power supply control circuit (121) comprises a plurality of first power supply control sub-circuits (123), and the second power supply control circuit (122) comprises a plurality of second power supply control sub-circuits (124). The plurality of first power supply control sub-circuits (123) and the plurality of second power supply control sub-circuits (124) correspond to the plurality of conductive paths (10) one by one, respectively.

18. The test circuit (100) according to claim 17, characterized in that, The first power supply control sub-circuit (123) comprises: a first AND gate (1231), a first input end of the first AND gate (1231) receives a pull-down control signal, and a second input end of the first AND gate (1231) receives a corresponding test enable signal; a first N-type transistor (1232), a first end of the first N-type transistor (1232) is electrically connected with a first end of the conductive path (10), a second end of the first N-type transistor (1232) is electrically connected with the ground voltage, and a control end of the first N-type transistor (1232) is electrically connected with an output end of the first AND gate (1231); The second power supply control sub-circuit (124) comprises: a second AND gate (1241), a first input end of the second AND gate (1241) receives a pull-up control signal, and a second input end of the second AND gate (1241) receives a corresponding test area selection sub-signal; a first P-type transistor (1242), a first end of the first P-type transistor (1242) is electrically connected with a second end of the conductive path (10), a second end of the first P-type transistor (1242) is electrically connected with the power supply voltage, and a control end of the first P-type transistor (1242) is electrically connected with an output end of the second AND gate (1241).

19. The test circuit (100) according to claim 17, characterized in that, The first power supply control sub-circuit (123) comprises: a third AND gate (1233), a first input end of the third AND gate (1233) receives a pull-up control signal, and a second input end of the third AND gate (1233) receives a corresponding test enable signal; a second P-type transistor (1234), a first end of the second P-type transistor (1234) is electrically connected with a first end of the conductive path (10), a second end of the second P-type transistor (1234) is electrically connected with the power supply voltage, and a control end of the second P-type transistor (1234) is electrically connected with an output end of the third AND gate (1233); The second power supply control sub-circuit (124) comprises: a fourth AND gate (1243), a first input end of the fourth AND gate (1243) receives a pull-down control signal, and a second input end of the fourth AND gate (1243) receives a corresponding test area selection sub-signal; A second N-type transistor (1244) has a first end electrically connected to a second end of the conductive path (10), a second end electrically connected to the ground voltage, and a control end electrically connected to an output end of the fourth AND gate (1243).

20. The test circuit (100) according to any one of claims 12 to 19, characterized in that The power supply control circuit (12) further includes a plurality of holding circuits (125) corresponding to the plurality of conductive paths (10) one by one. The holding circuit (125) includes: A third NOT gate (1251) has an input end electrically connected to a second end of the corresponding conductive path (10); A fourth NOT gate (1252) has an input end electrically connected to an output end of the third NOT gate (1251), and an output end electrically connected to an input end of the third NOT gate (1251).

21. The test circuit (100) according to any one of claims 12 to 20, characterized in that, The test circuit (100) is applied to a stacked chip structure (200) including a first chip and a second chip stacked on the first chip. The first power supply control circuit (121), the test control circuit (11), and the defect detection circuit (13) are arranged in the first chip, the second power supply control circuit (122) is arranged in the second chip, and the conductive path (10) is used to transmit signals between the first chip and the second chip.

22. The test circuit (100) according to any of claims 1 to 21, characterized in that The test circuit (100) further includes: A clock shielding circuit (14) connected to the test control circuit (11) is configured to receive an initial clock signal, generate and output the test clock signal based on the initial clock signal when none of the conductive paths (10) performs defect detection, and not output the test clock signal when any of the conductive paths (10) performs defect detection.

23. A test method of a stacked chip structure (200), comprising: In response to a test clock signal, sequentially receiving a serially input test control signal, generating and outputting a plurality of test enable signals corresponding to a plurality of conductive paths (10) one by one; In response to the test enable signal in an active state, controlling the corresponding conductive path (10) to perform defect detection as a target conductive path; During each defect detection, detecting a level change of each conductive path (10) to generate a plurality of detection identification signals corresponding to the plurality of conductive paths (10) one by one; Generating a plurality of detection results corresponding to the plurality of conductive paths (10) one by one according to a comparison result of each detection identification signal and the corresponding test enable signal; After each defect detection, in response to a detection result latch signal, latching the detection result.

24. The test method of claim 23, further comprising: After defect detection of all the conductive paths (10) as target conductive paths is completed or after each round of defect testing is finished, the detection results latched by the defect detection circuit (13) are sequentially and serially output as test result signals based on the test clock signal.

25. The test method of claim 24, wherein, the after defect detection of all the conductive paths (10) as target conductive paths is completed or after each round of defect testing is finished, the detection results latched are sequentially and serially output as test result signals based on the test clock signal includes: after defect detection of all the conductive paths (10) as target conductive paths is completed, when the result read-out identification signal indicates that it is in a test result read-out stage, all the latched detection results are read out in response to the test clock signal, and when the result read-out identification signal indicates that it is in a data transmission stage, the read-out detection results are sequentially and serially output as the test result signals in response to the test clock signal.

26. The test method of claim 23, wherein, the latching the detection results in response to the detection result latching signal includes: after defect detection of any of the conductive paths (10) as a target conductive path is performed, each of the detection results is maintained or updated according to a comparison result of a current each of the detection identification signals and a corresponding test enable signal in response to the received detection result latching signal; wherein when the detection identification signal and the corresponding test enable signal are different, the corresponding detection result is maintained or updated as high level, and when the detection identification signal and the corresponding test enable signal are the same, the corresponding detection result is maintained unchanged; the detection result as high level indicates that the corresponding conductive path (10) has a defect, and the detection result as low level indicates that the corresponding conductive path (10) has no defect.

27. The test method of claim 23, wherein, the controlling defect detection of the corresponding conductive path (10) as a target conductive path in sequence in response to the test enable signal in an active state includes: in response to the test enable signal in an active state, controlling a first end of the target conductive path to be electrically connected with a power supply voltage to perform a charging operation; after the charging operation is completed, controlling a second end of the target conductive path and a second end of the conductive path (10) adjacent to the target conductive path to be electrically connected with a ground voltage respectively to perform a discharging operation.

28. The test method of claim 23, wherein, a plurality of the conductive paths (10) are divided into a plurality of conductive path groups (110) arranged in an array, each of the conductive path groups (110) includes l*m conductive paths (10) arranged in an array, l and m are both positive integers greater than or equal to 2; the controlling defect detection of the corresponding conductive path (10) as a target conductive path in response to the test enable signal in an active state includes: In response to a plurality of test enable signals, each of the conductive paths (10) in each of the conductive path groups (110) is taken as a target conductive path, and a first end of each of the target conductive paths is electrically connected to a power supply voltage to perform a charging operation. In response to a test area selection signal, a second end of the selected conductive path (10) is electrically connected to a ground voltage to perform a discharging operation. The test area selection signal includes a plurality of test area selection sub-signals corresponding to a plurality of position areas one by one, each of the test area selection sub-signals indicates whether the conductive path (10) in the corresponding position area is selected, and each of the position areas includes at least one of the conductive path groups (110).

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