Memory circuit

Abstract

The present disclosure provides a memory circuit. The memory circuit may at least comprise: an amplifier, wherein the amplifier has a first node and a second node, the first node is electrically connected to a first data line, the second node is electrically connected to a first reference data line, and the amplifier is configured to amplify a voltage difference between the first data line and the first reference data line; and a first transmission transistor, wherein a first end of the first transmission transistor is electrically connected to the first node, a second end of the first transmission transistor is electrically connected to a second data line, and the first transmission transistor is configured to be turned on on the basis of a control signal during at least a portion of a read-write phase, and to be turned on on the basis of the control signal during at least a portion of an idle phase.

Description

Memory circuit

[0001] Cross-reference to related applications

[0002] This application claims priority from the Chinese patent application No. 202410720494.4 filed on June 4, 2024, and entitled “Memory circuit”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of semiconductor, and in particular, to a memory circuit. BACKGROUND

[0004] With further miniaturization of the process and further requirements of chip size, memory manufacturers are under increasing pressure to reduce chip size. However, in the process of miniaturization, the original defects usually do not disappear, but may become more serious, such as transistor matching problems, which leads to the fact that the overall size cannot be reduced by reducing the number of transistors set to achieve a specific function, but by optimizing the overall size through reasonable layout.

[0005] SUMMARY

[0006] Embodiments of the present application provide a memory circuit, which is at least beneficial to further reduce the size of the memory circuit.

[0007] According to some embodiments of the present application, a memory circuit is provided, comprising: an amplifier, the amplifier having a first node and a second node, the first node being electrically connected with a first data line, the second node being electrically connected with a first reference data line, the amplifier being configured to amplify a voltage difference between the first data line and the first reference data line; a first transmission tube, a first end of the first transmission tube being electrically connected with the first node, a second end of the first transmission tube being electrically connected with a second data line, the first transmission tube being configured to be turned on according to a control signal at least in part of a read-write stage, and to be turned on according to the control signal at least in part of an idle stage.

[0008] The memory circuit further comprises: a second transmission tube, a first end of the second transmission tube being electrically connected with the second node, a second end of the second transmission tube being electrically connected with a second reference data line, at least one of the first transmission tube and the second transmission tube being configured to be turned on according to a control signal at least in part of a read-write stage, and to be turned on according to the control signal at least in part of an idle stage.

[0009] In the same idle stage, the first transmission tube or the second transmission tube is turned on, and in different idle stages, the first transmission tube and the second transmission tube are turned on alternately.

[0010] The first data line is a bit line, the first reference data line is a reference bit line, the second data line is a local data line, the first transfer tube is a first column selection tube, the local data line is electrically connected with the bit line through the first column selection tube, the control signal is a column selection signal, and the first column selection tube is turned on based on the column selection signal to adjust the potential of the first node to be equal to the potential of the local data line.

[0011] The amplifier comprises a first P-type amplifying tube, a second P-type amplifying tube, a first N-type amplifying tube, and a second N-type amplifying tube, a first end of the first P-type amplifying tube and a first end of the second P-type amplifying tube are connected to a first voltage node, a second end of the first P-type amplifying tube and a first end of the first N-type amplifying tube are connected, a second end of the second P-type amplifying tube and a first end of the second N-type amplifying tube are connected, a second end of the first N-type amplifying tube and a second end of the second N-type amplifying tube are connected to a second voltage node, the second end of the first P-type amplifying tube serves as a first node, the second end of the second P-type amplifying tube serves as a second node, the first node is connected with a gate of the second P-type amplifying tube and a gate of the second N-type amplifying tube, and the second node is connected with a gate of the first P-type amplifying tube and a gate of the first N-type amplifying tube.

[0012] The amplifier comprises a first P-type amplifying tube, a second P-type amplifying tube, a first N-type amplifying tube, a second N-type amplifying tube, a first isolation tube, a second isolation tube, a first bias cancellation tube, and a second bias cancellation tube, a first end of the first P-type amplifying tube and a first end of the second P-type amplifying tube are connected to a first voltage node, a second end of the first P-type amplifying tube and a first end of the first N-type amplifying tube are connected, a second end of the second P-type amplifying tube and a first end of the second N-type amplifying tube are connected, a second end of the first N-type amplifying tube and a second end of the second N-type amplifying tube are connected to a second voltage node, the second end of the first P-type amplifying tube serves as a second node, the second end of the second P-type amplifying tube serves as a first node, the first node is connected with a first end of the first isolation tube and a gate of the first P-type amplifying tube, a second end of the first isolation tube, a second end of the first bias cancellation tube, and a gate of the first N-type amplifying tube are connected with a bit line, a first end of the first bias cancellation tube is connected with the second node, the second node is connected with a first end of the second isolation tube and a gate of the second P-type amplifying tube, a second end of the second isolation tube, a second end of the second bias cancellation tube, and a gate of the second N-type amplifying tube are connected with a reference bit line, a first end of the second bias cancellation tube is connected with the first node, the first isolation tube and the second isolation tube are turned on based on an isolation signal, and the first bias cancellation tube and the second bias cancellation tube are turned on based on a bias cancellation signal.

[0013] The first end of the first transfer transistor is electrically connected to the bit line, and is electrically connected to the first node through the bit line and the first isolation transistor.

[0014] The first end of the first transfer transistor is electrically connected to the first node, and is electrically connected to the bit line through the first node and the first isolation transistor.

[0015] The read-write stage includes a bias cancellation stage, a charge sharing stage and an amplification stage performed in sequence, the first transfer transistor is further configured to be turned on according to the control signal during at least part of the charge sharing stage, and the turning-on time of the first isolation transistor and the second isolation transistor is after the turning-off time of the first transfer transistor during the charge sharing stage.

[0016] The first transfer transistor is configured to be turned on according to the control signal generated by the column operation command during at least part of the read-write stage, and to be turned on according to the control signal generated by the row operation command during at least part of the idle stage.

[0017] The column operation command includes a read command and a write command, and the row operation command includes a pre-charge command.

[0018] The first data line is a local data line, the first reference data line is a local reference data line, the second data line is a global data line, and the global data line is connected to the local data line through the first transfer transistor to adjust the potential of the first end of the first transfer transistor to be equal to the potential of the second end.

[0019] The memory circuit further includes a storage bank including a row decoder, a column decoder and a storage block located on opposite sides of the row decoder, the amplifier and the first transfer transistor are arranged in the storage block, and the column decoder is located between the row decoder and the storage block.

[0020] The column decoder includes a plurality of column decoding circuits, and the storage block includes a plurality of storage units arranged along the bit line direction, each column decoding circuit is configured to perform column decoding for a corresponding part of the plurality of storage units, and each column decoding circuit corresponds to a fixed number of storage units.

[0021] The memory circuit further comprises a first semiconductor structure and a second semiconductor structure stacked together, the bit line and the memory cell connected with the bit line are arranged in the first semiconductor structure, and the second semiconductor structure is provided with a plurality of repeating units, each of which comprises an amplification array, a row decoder arranged on opposite sides of the amplification array along a first direction, and a column decoder arranged on opposite sides of the amplification array along a second direction, the first direction being perpendicular to the second direction.

[0022] The memory circuit further comprises a first storage array, a second storage array, a first amplification array and a second amplification array, which are arranged in sequence in the extension direction of the bit line, the amplifiers are arranged in the first amplification array and the second amplification array, and the first transfer tube is arranged between the first amplification array and the first storage array, and between the second amplification array and the second storage array.

[0023] The local amplifiers are arranged between the first amplification array and the second amplification array, and are used to amplify the voltage difference between the local data line and the local reference data line.

[0024] In the extension direction of the bit line, the first N-type amplification tube, the first bias cancellation tube, the first isolation tube, the first P-type amplification tube, the second P-type amplification tube, the second isolation tube, the second bias cancellation tube and the second N-type amplification tube are arranged in sequence; or the first isolation tube, the first bias cancellation tube, the first N-type amplification tube, the second N-type amplification tube, the second bias cancellation tube, the second isolation tube, the first P-type amplification tube and the second P-type amplification tube are arranged in sequence; or the first P-type amplification tube, the second P-type amplification tube, the first isolation tube, the first bias cancellation tube, the first N-type amplification tube, the second N-type amplification tube, the second bias cancellation tube and the second isolation tube are arranged in sequence.

[0025] The first bias cancellation tube and the first N-type amplification tube share an active region, and the shared active region is connected with a metal layer through a corresponding contact hole. BRIEF DESCRIPTION OF DRAWINGS

[0026] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the embodiments, unless otherwise specified, the figures in the drawings do not constitute a proportional limitation.

[0027] Fig. 1 is a circuit schematic diagram of a memory circuit;

[0028] Figure 2 is a layout diagram of the memory circuit shown in Figure 1;

[0029] Figure 3 is a memory circuit provided by an embodiment of the present application;

[0030] Figure 4 is a memory circuit provided by another embodiment of the present application;

[0031] Figure 5 is a control signal timing diagram provided by an embodiment of the present application;

[0032] Figures 6-8 are circuit diagrams of various memory circuits provided by the present application;

[0033] Figure 9 is a control signal timing diagram and node potential change diagram of the memory circuit shown in Figure 1;

[0034] Figure 10 is a control signal timing diagram and node potential change diagram of the memory circuit shown in Figure 6;

[0035] Figure 11 is a control signal timing diagram and node potential change diagram of the memory circuit shown in Figure 8;

[0036] Figure 12 is an architecture diagram of a memory circuit provided by an embodiment of the present application;

[0037] Figure 13 is an architecture diagram of a memory circuit;

[0038] Figure 14 is an architecture diagram of a memory circuit provided by another embodiment of the present application;

[0039] Figure 15 is a layout diagram of a memory circuit provided by an embodiment of the present application;

[0040] Figures 16-18 are layout diagrams of various memory circuits provided by the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in detail with reference to the drawings. However, those skilled in the art will understand that many technical details are presented in the embodiments of the present application in order to better enable the reader to understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0042] Figure 1 is a circuit diagram of a memory circuit, and Figure 2 is a layout diagram of the memory circuit shown in Figure 1.

[0043] Referring to FIG. 1, the memory circuit includes an amplifier, the amplifier including a first P-type amplifying tube M1, a second P-type amplifying tube M2, a first N-type amplifying tube M7, a second N-type amplifying tube M8, a first isolation tube M3, a second isolation tube M4, a first offset cancellation tube M5, a second offset cancellation tube M6, a pre-charge tube M9, a first end of the first P-type amplifying tube M1 and a first end of the second P-type amplifying tube M2 being connected to a first voltage node PCS, a second end of the first P-type amplifying tube M1 being connected to a first end of the first N-type amplifying tube M7, a second end of the second P-type amplifying tube M2 being connected to a first end of the second N-type amplifying tube M8, a second end of the first N-type amplifying tube M7 being connected to a second end of the second N-type amplifying tube M8 to a second voltage node NCS, the second end of the first P-type amplifying tube M1 serving as a second node S2, the second end of the second P-type amplifying tube M2 serving as a first node S1, the first node S1 being connected to a first end of the first isolation tube M3, a second end of the first isolation tube M3, a second end of the first offset cancellation tube M5, and a gate of the first N-type amplifying tube M7 being connected to a bit line Bla, a first end of the first offset cancellation tube M5 being connected to the second node S2, the second node S2 being connected to a first end of the second isolation tube M4, a second end of the second isolation tube M4, a second end of the second offset cancellation tube M6, and a gate of the second N-type amplifying tube M8 being connected to a reference bit line Blb, a first end of the second offset cancellation tube M6 and a first end of the pre-charge tube M9 being connected to the first node S1, the first isolation tube M3 and the second isolation tube M4 being turned on based on an isolation signal ISO, the first offset cancellation tube M5 and the second offset cancellation tube M6 being turned on based on an offset cancellation signal Oc, the pre-charge tube M9 being turned on based on a pre-charge signal PreEq and transmitting a pre-charge potential to the first node S1. Wherein, the first P-type amplifying tube M1 and the second P-type amplifying tube M2 constitute a P-type amplifier PSA, and the first N-type amplifying tube M7 and the second N-type amplifying tube M8 constitute an N-type amplifier NSA.

[0044] According to the layout schematic diagram of FIG. 2, due to the presence of the pre-charge tube M9 in FIG. 1, the layout structure on the left and right sides of the amplifier is different and cannot be symmetrical, and the height of the layout structure on the right side is always greater than the height of the layout structure on the left side. However, since the pre-charge tube M9 plays a specific role in the amplifier, it cannot be simply removed to reduce the size of the layout structure. In addition, the pre-charge tube is not only provided in the circuit shown in FIG. 1, but can also be provided in other circuits to pre-charge the internal nodes of the other circuit structures.

[0045] Figure 3 is a memory circuit provided by an embodiment of the present application, comprising: an amplifier 10, the amplifier 10 having a first node S1 and a second node S2, the first node S1 being electrically connected with a first data line Data1, the second node S2 being electrically connected with a first reference data line Data1#, the amplifier 10 being configured to amplify a voltage difference between the first data line Data1 and the first reference data line Data1#; a first transfer tube T1, a first end of the first transfer tube T1 being electrically connected with the first node S1, a second end of the first transfer tube T1 being electrically connected with a second data line Data2, the first transfer tube T1 being configured to be turned on according to a control signal Ctrl during at least part of a read-write stage and during at least part of an idle stage.

[0046] In the present application, the first node S1 is enabled to receive the potential at the other end of the first transfer tube T1 by turning on the first transfer tube T1 during the idle stage, and thus the first node S1 is enabled to have a pre-charge potential by controlling the second data line Data2 to have the pre-charge potential during the turning on of the first transfer tube T1. That is, during the idle stage, the first transfer tube T1 functions as a pre-charge tube to transfer the pre-charge potential to the first node S1. In the present application, during the read-write stage, the data of which bit lines need to be read is determined based on column address information, and then the corresponding first transfer tube T1 is turned on to read and write data; and during the idle stage, no read-write operation is needed, and thus the first transfer tube T1 is turned on to make the potential of the first node S1 the same as the potential of the second data line Data2, and thus the first node S1 obtains the pre-charge potential.

[0047] By controlling the first node S1 of the amplifier 10 to be at the pre-charge potential, the internal noise of the amplifier 10 can be reduced. In the amplifier 10, the first node S1 and the second node S2 can be electrically connected, which means that after a switch transistor between the first node S1 and the second node S2 is turned on, the first node S1 and the second node S2 are connected together through the source-drain of the switch transistor, so that the potential of the second node S2 is also at the pre-charge potential; or in the amplifier 10, the potential of the first node S1 is used to control the potential of the second node S2, after the potential of the first node S1 is at the pre-charge potential, the corresponding transistor is controlled to be in a specific on state, and thus the second node S2 at the source or drain of the corresponding transistor is also at the pre-charge potential. The internal structure of the amplifier 10 is not limited in the present application, because only the first node S1 is enabled to be stably at the pre-charge potential, which is beneficial to reduce the internal noise of the amplifier 10.

[0048] In the absence of additional limitation, "electrically connected" in the present application means that two nodes or two wires are connected together through the source-drain of one or more switching transistors, either of the two nodes or two wires does not function as the control signal of the transistor in the process of connection, but does not hinder its function as the control signal for other functions.

[0049] In one embodiment, the second data line Data2 can be at the pre-charge potential all the time in the idle phase, and the first transmission transistor T1 is always on in the idle phase, so that the first node S1 is stabilized at the pre-charge potential; in another embodiment of the present application, the second data line Data2 can be at the pre-charge potential in part of the idle phase, and the first transmission transistor T1 is on at this time, and the first transmission transistor T1 is off after the potential of the first node S1 is pulled to the pre-charge potential.

[0050] Regarding the change of the potential of the second data line Data2 in the idle phase. In one embodiment, the pre-charge potential of the second data line Data2 can be provided by the corresponding power supply, that is, the power supply that originally provides the pre-charge potential for the second data line Data2 now also provides the pre-charge potential for the first node S1. In yet another embodiment, after the potential of the first node S1 is pulled to the pre-charge potential, the first transmission transistor T1 can be turned off, and the potential of the second data line Data2 is adjusted to other values, such as the power supply voltage VCC or the low level VSS. At this time, compared with FIG. 1, it is equivalent to adjusting the pre-charge transistor M9 that provides the pre-charge potential for the internal node of the amplifier 10 to pre-charge the second data line Data2. When multiple first data lines Data1 are connected to the same second data line Data2 through corresponding first transmission transistors T1, adjusting the pre-charge transistor to pre-charge the second data line Data2 also helps to reduce the total number of pre-charge transistors, and thus reduce the overall size.

[0051] In one embodiment, referring to FIG. 4, the memory circuit further comprises: a second transmission tube T2, a first end of the second transmission tube T2 being electrically connected with the second node S2, and a second end of the second transmission tube T2 being electrically connected with the second reference data line Data2#. At least one of the first transmission tube T1 and the second transmission tube T2 is configured to be turned on according to the control signal Ctrl during at least part of the read-write stage and during at least part of the idle stage. In other embodiments, the second transmission tube T2 and the second reference data line Data2# are not necessarily required, and the second data line Data2 can be used for reading and writing and as a source of pre-charge potential. If the second reference data line Data2# is provided and receives data from the first reference data line Data1#, the data in the second data line Data2 is usually opposite to the data in the second reference data line Data2# to form a differential signal, thereby reducing the impact of noise on data accuracy. Meanwhile, another amplifier can be provided to amplify the voltage difference between the second data line Data2 and the second reference data line Data2#.

[0052] In one embodiment, the first transmission tube T1 or the second transmission tube T2 is turned on during the same idle stage, and the first transmission tube and the second transmission tube are turned on alternately during different idle stages. Referring to FIG. 5, taking the first transmission tube T1 and the second transmission tube T2 as NMOS tubes as an example, a signal timing diagram of the control signal Ctrl received by the first transmission tube T1 and the second transmission tube T2 is shown, and it can be seen that only the first transmission tube T1 or the second transmission tube T2 is turned on during the same idle stage Idle, and the first transmission tube T1 and the second transmission tube T2 are turned on alternately during different idle stages Idle. It should be noted that the multiple high-level pulses received by the first switch tube T1 and the second switch tube T2 during the read-write stage Active do not mean that the same first transmission tube / second transmission tube is continuously turned on multiple times, but mean that multiple first transmission tubes T1 / multiple second transmission tubes T2 corresponding to multiple first data lines Data1 are turned on sequentially during the read-write stage. Here, only four first transmission tubes T1 and second transmission tubes T2 are taken as an example, and actually, more or fewer first transmission tubes T1 and second transmission tubes T2 can be turned on according to the needs of data reading.

[0053] In one embodiment, referring to FIG. 3, FIG. 4 and FIG. 6, the first data line Data1 is a bit line Bla, the first reference data line Data1# is a reference bit line Blb, the second data line Data2 is a local data line IO, the first transfer tube T1 is a first column selection tube M10, the local data line IO is electrically connected with the bit line Bla through the first column selection tube M10, the control signal Ctrl is a column selection signal CSL, and the first column selection tube M10 is turned on based on the column selection signal CSL to adjust the potential of the first node S1 to be equal to the potential of the local data line IO. In other embodiments, the first data line can also be a local data line, and the second data line is a global data line.

[0054] Further referring to FIG. 6, in one embodiment, the amplifier 10 includes a first P-type amplification tube M1, a second P-type amplification tube M2, a first N-type amplification tube M7, a second N-type amplification tube M8, a first isolation tube M3, a second isolation tube M4, a first offset cancellation tube M5, and a second offset cancellation tube M6. The first end of the first P-type amplification tube M1 and the first end of the second P-type amplification tube M2 are connected to a first voltage node PCS. The second end of the first P-type amplification tube M1 is connected to the first end of the first N-type amplification tube M7. The second end of the second P-type amplification tube M2 is connected to the first end of the second N-type amplification tube M8. The second end of the first N-type amplification tube M7 and the second end of the second N-type amplification tube M8 are connected to a second voltage node NCS. The second end of the first P-type amplification tube M1 serves as a second node S2. The second end of the second P-type amplification tube M2 serves as a first node S1. The first node S1 is connected to the first end of the first isolation tube M3 and the gate of the first P-type amplification tube M1. The second end of the first isolation tube M3, the second end of the first offset cancellation tube M5, and the gate of the first N-type amplification tube M7 are connected to a bit line Bla. The first end of the first offset cancellation tube M5 is connected to the second node S2. The second node S2 is connected to the first end of the second isolation tube M4 and the gate of the second P-type amplification tube M2. The second end of the second isolation tube M4, the second end of the second offset cancellation tube M6, and the gate of the second N-type amplification tube M8 are connected to a reference bit line Blb. The first end of the second offset cancellation tube M6 is connected to the first node S1. The first isolation tube M3 and the second isolation tube M4 are turned on based on an isolation signal ISO. The first offset cancellation tube M5 and the second offset cancellation tube M6 are turned on based on an offset cancellation signal Oc.

[0055] In the embodiment, the first isolation tube M3 and the second isolation tube M4 are arranged, so that the time when the bit line Bla voltage is transmitted to the first node S1 can be controlled according to the requirement, and the time when the potential of the first node S1 / the second node S2 is transmitted to the bit line Bla and / or the reference bit line Blb can also be controlled. In addition, the first bias elimination tube M5 and the second bias elimination tube M6 are arranged to eliminate the performance parameter mismatch problem of the first N-type amplification tube M7 and the second N-type amplification tube M8. In the embodiment, the pre-charge tube is not arranged in the amplifier 10, but the potential of the local data line IO is received by the first column selection tube M10 in the idle stage to adjust the potential of the first node S1 to the pre-charge potential.

[0056] In one embodiment, the memory circuit further comprises a second transmission tube, which is a second column selection tube M11 receiving a column selection signal CSL, one end of the second column selection tube M11 is electrically connected with the second node S2, and the other end of the second column selection tube M11 is connected with the second reference data line ION. In the idle stage, the potential of the second reference data line ION can be received by the second column selection tube M11 to adjust the potential of the second node S2 to the pre-charge potential. It should be noted that there are multiple parallel ways to adjust the potential of the first node S1 and / or the second node S2 to the pre-charge potential, which is related to the structure of the amplifier 10 in different embodiments, whether the second transmission tube T2 is included, and the internal switching mode of the amplifier 10. In different embodiments of the present application, the structure of the amplifier 10 can be changed as follows: the equalization tube can be arranged or not arranged, the source of the equalization tube is connected with the first node S1, the drain is connected with the second node S2, and is used to be turned on under the control of the equalization signal to pull the potentials of the first node S1 and the second node S2 to be the same; in parallel, the first bias elimination tube M5 and the second bias elimination tube M6 can be arranged or not arranged. The internal switching mode of the amplifier can be changed as follows: in the idle stage, the first bias elimination tube M5 and the second bias elimination tube M6 are turned on or not turned on.

[0057] In the two cases of setting the balance tube or the first / second bias cancellation tube to be turned on in the idle stage, the first node S1 and the second node S2 in the amplifier 10 can be pulled to the pre-charge potential by the first column selection tube M10 at the same time, without the second transmission tube, i.e., the second column selection tube M11; in the three cases of not setting the balance tube, not setting the first / second bias cancellation tube, and the first / second bias cancellation tube not being turned on in the idle stage, the first node S1 can be pulled to the pre-charge potential by the first column selection tube M10 first, the first node S1 controls the corresponding first P-type amplification tube M1 and the second P-type amplification tube M2 to be partially turned on, so that the potential of the second node S2 is adjusted to the pre-charge potential, or the second column selection tube M11 is set, and the second column selection tube M11 receives the pre-charge potential, so that the second node S2 is at the pre-charge potential.

[0058] In the idle stage, the first isolation tube M3 and the second isolation tube M4 are in the open state, and the first voltage node PCS and the second voltage node NCS can be at the pre-charge potential; in the read-write stage, the first isolation tube M3 and the second isolation tube M4 can be turned off in part of the period and turned on in the remaining period as needed, the first voltage node PCS can be set to the pre-charge potential or the power supply voltage as needed, the second voltage node NCS can be set to the pre-charge potential or low level as needed, and the power supply voltage is usually about twice the pre-charge potential. The above-mentioned various internal structure settings of the amplifier 10, the setting of the second transmission tube, and whether the first / second bias cancellation tube (M5 and M6) is switched in the idle stage are within the protection scope of the present application.

[0059] In some embodiments, the amplifier 10 does not set the bias cancellation tube (M5 and M6 in FIG. 6) connected between the gate and the drain of the N-type amplification tube and does not set the isolation tube. Referring to FIG. 7, the amplifier 10 includes a first P-type amplification tube M1, a second P-type amplification tube M2, a first N-type amplification tube M7, and a second N-type amplification tube M8, the first end of the first P-type amplification tube M1 and the first end of the second P-type amplification tube M2 are connected to the first voltage node PCS, the second end of the first P-type amplification tube M1 is connected to the first end of the first N-type amplification tube M7, the second end of the second P-type amplification tube M2 is connected to the first end of the second N-type amplification tube M8, the second end of the first N-type amplification tube M7 and the second end of the second N-type amplification tube M8 are connected to the second voltage node NCS, the second end of the first P-type amplification tube M1 is the first node S1, and the second end of the second P-type amplification tube M2 is the second node S2, the first node S1 is connected to the gate of the second P-type amplification tube M2 and the gate of the second N-type amplification tube M8, and the second node S2 is connected to the gate of the first P-type amplification tube M1 and the gate of the first N-type amplification tube M7.

[0060] In this embodiment, the amplifier 10 includes a P-type amplifier PSA and an N-type amplifier NSA, the P-type amplifier PSA includes a first P-type amplifier tube M1 and a second P-type amplifier tube, and the N-type amplifier NSA includes a first N-type amplifier tube M7 and a second N-type amplifier tube M8. In other embodiments, the amplifier 10 includes only the P-type amplifier PSA and the N-type amplifier NSA.

[0061] In some embodiments, referring to FIG. 6, a first end of the first transfer tube (i.e., the first column selection tube M10) is electrically connected with the bit line Bla, and the first transfer tube is electrically connected with the first node S1 through the bit line Bla and the first isolation tube M3. In this circuit, if it is necessary to adjust the potential of the first node S1 when the first transfer tube is turned on, it is also necessary to turn on the first isolation tube M3 at the same time to form a path between the first node S1 and the second data line Data2 (i.e., the local data line IO). When the optional second transfer tube (i.e., the second column selection tube M11) is provided in the memory circuit, a first end of the second transfer tube is electrically connected with the reference bit line Blb, and the second transfer tube is electrically connected with the second node S2 through the reference bit line Blb and the second isolation tube M4. By turning on the second transfer tube and the second isolation tube M4, the potential of the second node S2 can be adjusted to the pre-charge potential.

[0062] In other embodiments, referring to FIG. 8, a first end of the first transfer tube (i.e., the first column selection tube M10) is electrically connected with the first node S1, and the first transfer tube is electrically connected with the bit line Bla through the first node S1 and the first isolation tube M3. In this circuit, the potential of the first node S1 can be adjusted only by turning on the first transfer tube, without the need to turn on the first isolation tube M3 for isolating the first node S1 from the bit line Bla. In addition, since the first isolation tube M3 isolates the bit line Bla and the first node S1, when the capacitor sharing is performed between the storage unit and the bit line Bla, the first transfer tube can also be turned on to adjust the potential of the first node S1 to the pre-charge potential, so as to ensure that the subsequent amplifier 10 has a better initial state when amplifying, and only the first isolation tube M3 and the second isolation tube M4 need to be in the off state. When the optional second transfer tube (i.e., the second column selection tube M11) is provided in the memory circuit, a first end of the second transfer tube is electrically connected with the second node S2, and the second transfer tube is electrically connected with the reference bit line Blb through the second node S2 and the second isolation tube M4.

[0063] In some embodiments, the read-write stage includes a bias cancellation stage, a charge sharing stage and an amplification stage which are sequentially performed, and the charge sharing stage is located between the bias cancellation stage and the amplification stage. The first transfer tube of the memory circuit shown in FIG. 8 is further used for being turned on according to a control signal during at least part of the charge sharing stage.

[0064] Referring to FIGS. 9-11, FIG. 9 is a control signal timing and node potential change diagram of the memory circuit shown in FIG. 1, FIG. 10 is a control signal timing and node potential change diagram of the memory circuit shown in FIG. 6, and FIG. 11 is a control signal timing and node potential change diagram of the memory circuit shown in FIG. 8. The control signal timing and node potential change diagrams provided in FIGS. 9-11 include, in sequence and repeatedly, an idle stage Idel, an offset cancel stage (OC), a charge sharing stage (CS), an amplification stage Develop, and a precharge stage (PCG). There can be a certain time interval between different stages, and there is no requirement for strict continuity in timing. It should be noted that the precharge stage can be initiated at the time when the word line WL is disconnected (falling edge), or at the time when the precharge signal PreEq is active (rising edge). In the control signal timing diagram, the isolation signal ISO is the control signal of the first isolation transistor / second isolation transistor, the PreEq is the control signal of the precharge transistor, the offset cancel signal Oc is the control signal of the first offset cancel transistor / second offset cancel transistor, the WL is the control signal of the word line, the Bla / Blb is the potential of the bit line and reference bit line, and the PCS / NCS is the potential of the first voltage node and second voltage node. In this application, the first isolation transistor, the second isolation transistor, the precharge transistor, the first offset cancel transistor, and the second offset cancel transistor are all NMOS transistors, and the corresponding control signals are all high-level active, i.e., when the above-mentioned control signals are high, the corresponding transistors are turned on.

[0065] In FIG. 9, the column selection signal CSL is completely at a low level in the idle stage Idel, and the corresponding column selection transistor is turned off. The column selection signal CSL only appears as a high-level pulse in the amplification stage Develop to turn on the column selection transistor and perform data reading and writing. The three pulses in the amplification stage in FIG. 9 are similar to the four pulses in the read / write stage Active in FIG. 5, both of which refer to the number of column selection transistors that are turned on, rather than the number of times that the same column selection transistor is turned on in succession.

[0066] In FIG. 10, the column selection signal CSL not only appears as a high-level pulse in the amplification stage Develop, but also remains at a high level in the idle stage Idel to turn on the column selection transistor, so that the bit line Bla can receive the precharge potential of the local data line IO. At the same time, since the isolation signal ISO and the offset cancel signal Oc are also at a high level in the idle stage Idel, the first isolation transistor, the second isolation transistor, the first offset cancel transistor, and the second offset cancel transistor are turned on, and thus the potentials of the first node S1 and the second node S2 are pulled to the precharge potential.

[0067] It can be understood that the voltage of the local data line IO itself needs to be adjusted to the pre-charge potential before the isolation signal ISO is at a high level; in some embodiments, if the local reference data line ION is provided, and the first isolation transistor and the second isolation transistor are turned on based on the same isolation signal ISO, the potential of the local reference data line ION also needs to be adjusted to the pre-charge potential before the isolation signal ISO is at a high level; in yet some embodiments, the first isolation transistor and the second isolation transistor are turned on based on different isolation signals ISO independent of each other, for example, the first isolation transistor is turned on based on a first isolation signal, and the second isolation transistor is turned on based on a second isolation signal, then in the idle stage, only the first isolation transistor can be controlled to be turned on, and the second isolation transistor is turned off, so that the potential of the local reference data line ION does not need to be adjusted to the pre-charge potential before the first isolation transistor is turned on.

[0068] In the embodiment shown in FIG. 10, the column selection signal CSL is always at a high level in the idle stage Idle; in some other embodiments, the column selection signal CSL is only at a high level in part of the time period, as long as the potential of the first node S1 can be adjusted to the pre-charge potential. The part of the time period in which the column selection signal CSL is at a high level can be a continuous time period, or at least two time periods with intervals.

[0069] In FIG. 11, the column selection signal CSL also appears a high level pulse in the charge sharing stage CS. Since the bias cancellation signal Oc and the isolation signal ISO are both at a low level at the beginning of this stage, the interference between the bit line voltage change caused by the storage unit charge sharing and the voltage change of the first node S1 in the amplifier is small, so the potential of the first node S1 of the amplifier can be adjusted to the pre-charge potential before the first isolation transistor / second isolation transistor is turned on, thereby ensuring that the amplifier has a good initial state between amplifying the voltage difference.

[0070] In some embodiments, the first transfer transistor is used to be turned on according to a control signal generated by a column operation command in at least part of the time period of the read-write stage, and to be turned on according to the control signal generated by a row operation command in at least part of the time period of the idle stage.

[0071] In some embodiments, the column operation command includes a read command and a write command. When executing the read command or the write command, the column select transistor between the bit line and the corresponding local data line IO needs to be turned on based on the column address to be read or written, and the transfer transistor between the local data line IO and the corresponding global data line needs to be turned on, so as to realize the reading and writing of data. The command that needs to turn on the corresponding column select transistor and transfer transistor for reading and writing is referred to as a column operation command. The read data can not be output to the outside but only processed internally, and the data to be written can not come from the outside but come from the internal register or the internally randomly generated data pattern. That is, the column operation command can be input from the outside to the memory or generated internally by itself.

[0072] In some embodiments, the row operation command includes a pre-charge command. In the pre-charge command valid phase, the word line is closed, the storage transistor is disconnected, and no charge sharing occurs between the storage capacitor and the bit line. At this time, the amplifier and the bit line can be pre-charged to adjust the potential of the bit line and the potential of the first node electrically connected to the bit line in the amplifier to the pre-charge potential, so as to prepare for the next data reading and writing. In other embodiments, the row operation command can also include a row activation command. Since the interval time between the pre-charge command and the row activation command is usually fixed inside the memory, the row activation command can be delayed to obtain a command signal with the same timing as the pre-charge command, and then a control signal is generated based on the delayed row activation signal to turn on the first transfer transistor.

[0073] In some embodiments, the first data line Data1 is a local data line, the first reference data line Data1# is a local reference data line, the second data line Data2 is a global data line, and the global data line is connected to the local data line through the first transfer transistor T1 to adjust the potential of the first end of the first transfer transistor T1 to be equal to the potential of the second end. In the data reading process, the data is read out from the storage unit and gradually passes through the bit line, the local data line and the global data line, and is finally output to the data port.

[0074] FIG. 12 is a schematic diagram of the architecture of a memory circuit according to an embodiment of the present application. Referring to FIG. 12, in some embodiments, the memory circuit further includes a storage bank (referred to as Bank in the industry), which includes a row decoder XDEC, a column decoder YDEC, and a storage block half bank located on the opposite sides of the row decoder XDEC. The amplifier 10 and the first transfer transistor T1 are arranged in the storage block half bank, and the column decoder YDEC is located between the row decoder XDEC and the storage block half bank.

[0075] The row decoder XDEC, the column decoder YDEC, and the memory block half bank are arranged along the word line direction. The row decoder XDEC is configured to decode the row address. The column selector YDEC is configured to decode the column address. The decoding result of the row decoder XDEC can be a final decoding result, directly determining the target word line to be activated, or an intermediate decoding result, which needs further decoding to determine the final target word line to be activated. In addition, the row decoder XDEC receives a signal that can be an original address signal or an address signal that has been decoded one or more times. The row decoder XDEC further decodes the received row address signal. The column decoder YDEC can receive an original column address signal or an address signal that has been decoded one or more times, and can output a final bit line to be read or written or column address information that needs further decoding.

[0076] In one embodiment, further referring to FIG. 12, the memory circuit further includes a row pre-decoding circuit Row Pre decoder and a column pre-decoding circuit CSL Pre decoder. The row pre-decoding circuit Row Pre decoder is configured to decode the row address for the first time. The column pre-decoding circuit CSL Pre decoder is configured to decode the column address for the first time. In one embodiment, the row decoder XDEC decodes the row address for the second time. The sub-word line driver SWD in the memory block half bank decodes the row address for the third time, finally determining the row address of the target word line and activating the target word line. The column decoder YDEC is configured to decode the column address for the second time, to determine the final target bit line to be read or written. The target word line is usually one, and the number of target bit lines is usually multiple.

[0077] In some embodiments, the column decoder YDEC includes a plurality of column decoding circuits YDEC#. The memory block half bank includes a plurality of storage sections (Section 0-Section 72) arranged along the bit line direction. Each column decoding circuit YDEC# is configured to decode the column address for part of the plurality of storage sections. Each column decoding circuit YDEC# corresponds to a fixed number of storage sections.

[0078] Referring to FIG. 13, which is a schematic diagram of an architecture of a memory circuit. In the schematic diagram, column decoders YDEC are located on opposite sides of a memory block half bank, and each column decoder YDEC corresponds to a half number of memory units. As the capacity of the memory block increases, the number of memory units increases, and the number of word lines and bit lines included in each memory unit remains unchanged. Therefore, the number of memory units corresponding to each column decoder also increases, that is, the number of memory units corresponding to each column decoder is not fixed. In addition, the signal transmission distance between the column decoder and the nearest memory unit is a first distance, and the signal transmission distance between the column decoder and the farthest memory unit is a second distance. As the number of memory units increases, the difference between the first distance and the second distance becomes larger, which leads to more complex timing control of signals.

[0079] If each column decoding circuit YDEC# corresponds to a fixed number of memory units, as the number of memory units increases, the number of column decoding circuits YDEC# also needs to increase, and the signal transmission distance between each column decoding circuit and the corresponding memory unit remains unchanged. This circuit architecture can be quickly applied to memory blocks with different capacities, ensuring the rapid implementation of different projects.

[0080] In some embodiments, referring to FIG. 14, the memory circuit further includes a first semiconductor structure and a second semiconductor structure stacked together, the word lines, the bit lines, and the memory units are disposed in the first semiconductor structure, and the second semiconductor structure is provided with a plurality of repeating units, each repeating unit includes an amplification array SA array and a row decoder XDEC located on opposite sides of the amplification array SA array along a first direction and a column decoder YDEC located on opposite sides of the amplification array SA array along a second direction, the first direction being perpendicular to the second direction. In this embodiment, the memory units and the corresponding control circuits are disposed on different semiconductor structures, and each repeating unit described above can correspond to a memory bank. Therefore, it is beneficial to reduce the signal transmission distance between the memory bank and the corresponding control structure, and improve the control efficiency.

[0081] In some embodiments, referring to FIG. 15, the memory circuit further includes a first memory array 20, a second memory array 25, a first amplification array 22, and a second amplification array 24. In the direction of the bit line extension, the first memory array 20, the first amplification array 22, the second amplification array 24, and the second memory array 25 are arranged in sequence, the amplifiers 10 are disposed in the first amplification array 22 and the second amplification array 24, and the first transmission tube T1 is disposed between the first amplification array 22 and the first memory array 20, and between the second amplification array 24 and the second memory array 25.

[0082] In some embodiments, a local amplifier 23 is further arranged between the first amplification array 22 and the second amplification array 24, and the local amplifier 23 is configured to amplify the voltage difference between the local data line IO and the local reference data line ION; in other embodiments, the local amplifier 23 is arranged in the switch region 32, and the upper and lower sides of the switch region 32 are sub-word line drivers 31, and the left and right sides of the switch region 32 are the first amplification array 22 and the second amplification array 24, and the sub-word line drivers 31 are configured to drive and activate the word line, and the amplifiers 10 arranged in the first amplification array 22 and the second amplification array 24 are configured to amplify the voltage difference between the bit line Bla and the reference bit line Blb.

[0083] In some embodiments, in the bit line extension direction, the amplifiers 10 are arranged in the order of the first N-type amplification tube M7, the first bias cancellation tube M5, the first isolation tube M3, the first P-type amplification tube M1, the second P-type amplification tube M2, the second isolation tube M4, the second bias cancellation tube M6, and the second N-type amplification tube M8, as shown in FIG. 16. In this way, the amplifiers 10 themselves have a symmetrical layout. The positions of the first isolation tube M3 and the first bias cancellation tube M5 can be interchanged, and the positions of the second isolation tube M4 and the second bias cancellation tube M6 can also be interchanged synchronously to maintain the symmetry of the layout and the signal connection.

[0084] In other embodiments, in the bit line extension direction, the amplifiers 10 are arranged in the order of the first isolation tube M3, the first bias cancellation tube M5, the first N-type amplification tube M7, the second N-type amplification tube M8, the second bias cancellation tube M6, the second isolation tube M4, the first P-type amplification tube M1, and the second P-type amplification tube M2, as shown in FIG. 17. In this way, when the first amplification array 22 and the second amplification array 24 are adjacent and the layout arrangement directions are opposite, as long as no other structure is arranged between the first amplification array 22 and the second amplification array 24 or only P-type MOS tubes are arranged, the P-type MOS tubes in the first amplification array and the second amplification array can share the P-type substrate.

[0085] In yet some embodiments, in the direction of the bit line extension, the first P-type amplification tube M1, the second P-type amplification tube M2, the first isolation tube M3, the first bias cancellation tube M5, the first N-type amplification tube M7, the second N-type amplification tube M8, the second bias cancellation tube M6, and the second isolation tube M4 are arranged in sequence in the amplifier 10. In this way, the first P-type amplification tube M1 and the second P-type amplification tube M2 can be used to isolate the NMOS tubes and the first transmission tube T1 in the first amplification array 22, and isolate the NMOS tubes and the first transmission tube T1 in the second amplification array 24. When the first transmission tube T1 is an NMOS tube, the NMOS tubes and the first transmission tube T1 in the first amplification array 22 / second amplification array 24 can use N-type substrates with different substrate voltages.

[0086] In some embodiments, referring to FIGS. 17 and 18, the first bias cancellation tube M5 and the first N-type amplification tube M7 share an active area, and the shared active area is connected to a metal layer through a corresponding contact hole. As shown in the drawings, the active area on one side of the first bias cancellation tube M5 is merged with the active area on one side of the first N-type amplification tube M7, and only the contact hole on the active area on one side of the first N-type amplification tube M7 is retained, which is connected to the metal layer above through the contact hole. The contact hole on the active area on one side of the first bias cancellation tube M5 is removed (indicated by a dashed line).

[0087] In other embodiments, the contact hole on the active area on one side of the first N-type amplification tube M7 can also be removed, and the contact hole on the active area on one side of the first bias cancellation tube M5 is retained. Similarly, the second bias cancellation tube M6 and the second N-type amplification tube M8 can also share an active area, and the shared active area is connected to a metal layer through a corresponding contact hole. In some embodiments, referring to FIGS. 17 and 18, the first P-type amplification tube M1 and the second P-type amplification tube M2 share an active area, and the shared active area is connected to a metal layer through a corresponding contact hole.

[0088] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A memory circuit, comprising: an amplifier having a first node and a second node, the first node being electrically connected with a first data line, the second node being electrically connected with a first reference data line, the amplifier being configured to amplify a voltage difference between the first data line and the first reference data line; a first pass transistor having a first end electrically connected with the first node and a second end electrically connected with a second data line, the first pass transistor being configured to be turned on according to a control signal during at least a part of a read-write phase and during at least a part of an idle phase.

2. The memory circuit of claim 1, further comprising: a second pass transistor having a first end electrically connected with the second node and a second end electrically connected with a second reference data line, at least one of the first pass transistor and the second pass transistor being configured to be turned on according to a control signal during at least a part of a read-write phase and during at least a part of an idle phase.

3. The memory circuit of claim 2, wherein, The first pass transistor or the second pass transistor is turned on during a same idle phase, and the first pass transistor and the second pass transistor are turned on during different idle phases.

4. The memory circuit of claim 1, wherein, The first data line is a bit line, the first reference data line is a reference bit line, the second data line is a local data line, the first pass transistor is a first column selection transistor, the local data line is electrically connected with the bit line through the first column selection transistor, and the control signal is a column selection signal, the first column selection transistor being turned on based on the column selection signal to adjust a potential of the first node to be equal to a potential of the local data line.

5. The memory circuit of claim 4, wherein, The amplifier comprises a first P-type amplifying transistor, a second P-type amplifying transistor, a first N-type amplifying transistor, and a second N-type amplifying transistor, a first end of the first P-type amplifying transistor and a first end of the second P-type amplifying transistor being connected with a first voltage node, a second end of the first P-type amplifying transistor and a first end of the first N-type amplifying transistor being connected, a second end of the second P-type amplifying transistor and a first end of the second N-type amplifying transistor being connected, a second end of the first N-type amplifying transistor and a second end of the second N-type amplifying transistor being connected with a second voltage node, the second end of the first P-type amplifying transistor being the first node, the second end of the second P-type amplifying transistor being the second node, the first node being connected with a gate of the second P-type amplifying transistor and a gate of the second N-type amplifying transistor, and the second node being connected with a gate of the first P-type amplifying transistor and a gate of the first N-type amplifying transistor.

6. The memory circuit of claim 4, wherein, The amplifier comprises a first P-type amplifying tube, a second P-type amplifying tube, a first N-type amplifying tube, a second N-type amplifying tube, a first isolation tube, a second isolation tube, a first bias cancellation tube, and a second bias cancellation tube, a first end of the first P-type amplifying tube and a first end of the second P-type amplifying tube are connected to a first voltage node, a second end of the first P-type amplifying tube is connected to a first end of the first N-type amplifying tube, a second end of the second P-type amplifying tube is connected to a first end of the second N-type amplifying tube, a second end of the first N-type amplifying tube is connected to a second end of the second N-type amplifying tube, the second end of the first P-type amplifying tube serves as a second node, the second end of the second P-type amplifying tube serves as a first node, the first node is connected to a first end of the first isolation tube and a gate of the first P-type amplifying tube, a second end of the first isolation tube, a second end of the first bias cancellation tube, and a gate of the first N-type amplifying tube are connected to a bit line, a first end of the first bias cancellation tube is connected to the second node, the second node is connected to a first end of the second isolation tube and a gate of the second P-type amplifying tube, a second end of the second isolation tube, a second end of the second bias cancellation tube, and a gate of the second N-type amplifying tube are connected to a reference bit line, a first end of the second bias cancellation tube is connected to the first node, the first isolation tube and the second isolation tube are turned on based on an isolation signal, and the first bias cancellation tube and the second bias cancellation tube are turned on based on a bias cancellation signal.

7. The memory circuit of claim 6, wherein, The first end of the first transfer tube is electrically connected to the bit line and electrically connected to the first node through the bit line and the first isolation tube.

8. The memory circuit of claim 6, wherein, The first end of the first transfer tube is electrically connected to the first node and electrically connected to the bit line through the first node and the first isolation tube.

9. The memory circuit of claim 8, wherein, The read-write stage comprises a bias cancellation stage, a charge sharing stage, and an amplification stage which are sequentially performed, the first transfer tube is further configured to be turned on according to the control signal during at least part of the charge sharing stage, and the turning-on time of the first isolation tube and the second isolation tube is after the turning-off time of the first transfer tube during the charge sharing stage.

10. The memory circuit of claim 1, wherein, The first transfer tube is configured to be turned on according to the control signal generated by a column operation command during at least part of a read-write stage, and be turned on according to the control signal generated by a row operation command during at least part of an idle stage.

11. The memory circuit of claim 10, wherein, The column operation command comprises a read command and a write command, and the row operation command comprises a pre-charge command.

12. The memory circuit of claim 1, wherein, The first data line is a local data line, the first reference data line is a local reference data line, the second data line is a global data line, and the global data line is connected to the local data line through the first transfer tube to adjust the potential of the first end of the first transfer tube to be equal to the potential of the second end.

13. The memory circuit of claim 1, further comprising: The storage bank comprises a row decoder, a column decoder and a storage block located on opposite sides of the row decoder, the amplifier and the first transfer tube are arranged in the storage block, and the column decoder is located between the row decoder and the storage block.

14. The memory circuit of claim 13, wherein, The column decoder comprises a plurality of column decoding circuits, the storage block comprises a plurality of storage units arranged along the bit line direction, each column decoding circuit is used for column decoding corresponding partial storage units in the plurality of storage units, and each column decoding circuit corresponds to a fixed number of storage units.

15. The memory circuit of claim 4, further comprising: The first semiconductor structure and the second semiconductor structure are stacked, the bit line and the storage unit connected with the bit line are arranged in the first semiconductor structure, a plurality of repeating units are arranged in the second semiconductor structure, each repeating unit comprises an amplification array, a row decoder located on opposite sides of the amplification array along a first direction, and a column decoder located on opposite sides of the amplification array along a second direction, and the first direction is perpendicular to the second direction.

16. The memory circuit of claim 6, further comprising: The first storage array, the second storage array, the first amplification array and the second amplification array are arranged in sequence in the bit line extension direction, the amplifier is arranged in the first amplification array and the second amplification array, the first transfer tube is arranged between the first amplification array and the first storage array, and arranged between the second amplification array and the second storage array.

17. The memory circuit of claim 16, wherein, A local amplifier is further arranged between the first amplification array and the second amplification array, and the local amplifier is used for amplifying the voltage difference between the local data line and the local reference data line.

18. The memory circuit of claim 16, wherein, In the bit line extension direction, the first N-type amplification tube, the first bias cancellation tube, the first isolation tube, the first P-type amplification tube, the second P-type amplification tube, the second isolation tube, the second bias cancellation tube and the second N-type amplification tube are arranged in sequence in the amplifier; or, The first isolation tube, the first bias cancellation tube, the first N-type amplification tube, the second N-type amplification tube, the second bias cancellation tube, the second isolation tube, the first P-type amplification tube and the second P-type amplification tube are arranged in sequence; or The first P-type amplification tube, the second P-type amplification tube, the first isolation tube, the first bias cancellation tube, the first N-type amplification tube, the second N-type amplification tube, the second bias cancellation tube and the second isolation tube are arranged in sequence.

19. The memory circuit of claim 18, wherein, The first bias cancellation tube and the first N-type amplification tube share an active region, and the shared active region is connected with a metal layer through a corresponding contact hole.

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