Plastic-encapsulated boost semiconductor module and packaging structure

Abstract

The present invention relates to the technical field of semiconductors. Disclosed are a plastic-encapsulated BOOST semiconductor module and a packaging structure. A temperature monitoring soldering port area is connected to temperature pins, and the temperature pins comprise a first temperature monitoring pin and a second temperature monitoring pin. A high-side chip soldering and bonding area has a high-side chip pin soldering area, and the high-side chip pin soldering area is connected to a high-side chip pin. A Kelvin source pin soldering area is connected to a Kelvin source pin, a gate pin soldering area is connected to a gate pin, a drain pin soldering area is connected to a drain pin, and a power source soldering and bonding area is connected to a power source pin. The semiconductor module of the present invention reduces material costs and packaging time by means of plastic encapsulation, and reduces the size of the semiconductor module. A copper bridge bonding process enables the semiconductor module to carry higher current. Additionally, a multi-phase BOOST circuit is realized by connecting a plurality of single-phase semiconductor modules in parallel.

Description

Plastic package BOOST semiconductor module and packaging structure TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a plastic package BOOST semiconductor module and packaging structure. BACKGROUND

[0002] The third generation semiconductor has the characteristics of high temperature resistance, high pressure resistance, high frequency, high power and radiation resistance, such as SiC and GaN. The integrated power semiconductor module has the characteristics of high voltage and large current output, and the advantages of fast switching speed and high efficiency, which can greatly reduce product power consumption, improve energy conversion efficiency and reduce product volume. At present, power semiconductor modules are mainly used in radio frequency fields represented by 5G communication, national defense and military industry, aerospace, and power electronic fields represented by new energy vehicles, photovoltaic power generation and wind power generation "new infrastructure".

[0003] Plastic packaging is a packaging process that covers chips or devices with plastic for protection. Through plastic packaging, the originally exposed chips, devices and connection lines are protected by the external plastic body, preventing the semiconductor device from being attacked by the external environment (especially the humidity environment), and avoiding product failure. It has the advantages of low cost, thinness, simple process, and is suitable for automatic production, and is widely used in the field of semiconductor packaging.

[0004] BOOST circuit, also known as boost chopper circuit, is a typical DC conversion circuit that can convert low voltage to high voltage output. They are often composed of single-phase, two-phase, three-phase or even four-phase BOOST circuits in the form of parallel connection. This circuit has a wide range of applications in such as vehicle charger, power grid, photovoltaic, medical equipment, etc.

[0005] Prior art such as patent number CN201510088870.3 uses silicon-based IGBT and SBD for BOOST semiconductor module. Due to the material limitations of silicon itself, the BOOST semiconductor module will generate a lot of energy consumption in voltage conversion, and can only work at a lower temperature, such as an ambient temperature of less than 150 DEG C and a low frequency switching speed.

[0006] BOOST semiconductor module is mainly made by shell encapsulation glue, which has a high cost of encapsulation material, and needs to add a curing agent for curing, which takes a very long time. If the curing agent is too little, the encapsulation will not be completely cured, and if too much, the curing agent will be left over. It is greatly affected by the ambient temperature, and even cannot be cured at too low ambient temperature.

[0007] The existing BOOST semiconductor module using the third generation semiconductor such as SiC still uses shell encapsulation glue, and for a multi-phase BOOST semiconductor module, due to the poor consistency of the yield and performance parameters of SiC itself, when the multi-phase packaging is performed, one failed chip will lead to the scrapping of the whole module, and due to this situation, the overall cost of the SiC module is high. SUMMARY

[0008] The present application is aimed at the existing technology that the BOOST semiconductor module is mainly made by using the shell encapsulation glue, the shell encapsulation glue has a large size and a high material cost, the encapsulation glue needs to be added with a curing agent for curing, the curing time is extremely long, and too little curing agent will lead to incomplete curing of the encapsulation glue, and too much curing agent will lead to the residue of the curing agent, and the environmental temperature has a great influence, and too low environmental temperature will even lead to the phenomenon of being unable to cure. Therefore, a multi-phase parallel plastic packaging BOOST semiconductor module is proposed.

[0009] In order to solve the above technical problems, the present application is solved by the following technical scheme:

[0010] A plastic packaging BOOST semiconductor module comprises:

[0011] A bottom plate substrate and a heat dissipation substrate form a semiconductor cavity, the heat dissipation substrate is located above the bottom plate substrate, the bottom plate substrate is provided with a conductive layer, and the conductive layer is located in the semiconductor cavity;

[0012] The semiconductor cavity comprises a first side and a third side opposite to each other in a first direction, and a second side and a fourth side opposite to each other in a second direction; the first side, the second side, the third side and the fourth side are connected end to end;

[0013] In the first direction, the conductive layer is provided with an upper bridge region and a lower bridge region opposite to each other, wherein the upper bridge region is located on one side of the first side, and the lower bridge region is located on one side of the third side; the upper bridge region comprises an upper bridge chip welding and bonding area and a temperature monitoring welding port area; the temperature monitoring welding port area is close to the connection between the first side and the fourth side;

[0014] The lower bridge region comprises a lower bridge chip drain welding and bonding area, a drain pin welding area, a gate pin welding area, a Kelvin source pin welding area and a power source welding and bonding area;

[0015] The power source welding and bonding area is close to the connection between the third side and the fourth side; the second side is sequentially provided with the power source welding and bonding area, the Kelvin source pin welding area, the gate pin welding area and the drain pin welding area, and the power source welding and bonding area is close to one side of the fourth side, the drain pin welding area is close to the connection between the second side and the third side; the lower bridge chip drain welding and bonding area is close to the upper bridge chip welding and bonding area;

[0016] a plurality of upper bridge chips and a plurality of lower bridge chips, the plurality of upper bridge chips are mounted on the upper bridge chip soldering and bonding area, and the plurality of lower bridge chips are mounted on the lower bridge chip drain soldering and bonding area;

[0017] a plurality of upper bridge chip connection units and a plurality of lower bridge chip connection units, the plurality of upper bridge chips are electrically connected to each other through the upper bridge chip connection units, and the plurality of lower bridge chips and the power source bonding area are electrically connected to each other through the lower bridge chip connection units;

[0018] the lower bridge chip drain soldering and bonding area is provided with a region connection point, and the upper bridge chip connection unit is electrically connected to the lower bridge region through the region connection point;

[0019] the temperature monitoring soldering port area is connected with a temperature pin, and the temperature pin includes a temperature monitoring first pin and a temperature monitoring second pin; the upper bridge chip soldering and bonding area has an upper bridge chip pin soldering area, and the upper bridge chip pin soldering area is connected with an upper bridge chip pin;

[0020] the Kelvin source pin soldering area is connected with a Kelvin source pin, the gate pin soldering area is connected with a gate pin, the drain pin soldering area is connected with a drain pin, and the power source soldering and bonding area is connected with a power source pin; the source pin, the Kelvin source pin, the gate pin and the drain pin are arranged in sequence along the second side.

[0021] Preferably, the plurality of upper bridge chips and the plurality of lower bridge chips are arranged in a column along the first direction, and the plurality of upper bridge chips in the column are electrically connected to the upper bridge region by the same upper bridge chip connection unit, and the plurality of lower bridge chips in the column are electrically connected to the lower bridge region by the same lower bridge chip connection unit.

[0022] Preferably, the lower bridge region and the lower bridge region are mirror-symmetric along a virtual symmetry line extending in the second direction.

[0023] Preferably, the upper bridge chip pin is a T-shaped downward bending pin.

[0024] Preferably, the upper bridge chip soldering and bonding area is further connected with a multi-phase pin.

[0025] Preferably, the multi-phase pin is a T-shaped flat edge pin.

[0026] Preferably, the bottom plate substrate is an insulating ceramic substrate.

[0027] Preferably, the upper bridge chip connection unit and the lower bridge chip connection unit include a copper bridge, an aluminum bonding wire, a copper bonding wire or a silver bonding wire.

[0028] Preferably, the Kelvin source pin soldering area and the gate pin soldering area are provided with a Kelvin source wire bonding area therebetween; the Kelvin source wire bonding area is provided with a gate wire bonding area thereabove; the lower bridge chip is provided with a lower bridge chip Kelvin source wire bonding area and a lower bridge chip gate wire bonding area; the lower bridge chip Kelvin source wire bonding area is electrically connected to the Kelvin source wire bonding area through a Kelvin source bonding wire; and the lower bridge chip gate wire bonding area is electrically connected to the gate wire bonding area through a gate bonding wire.

[0029] To solve the above technical problems, the application further provides a packaging structure, which comprises a shell, a semiconductor module, a bottom plate substrate and a conductive layer in a receiving cavity of the shell, and each of a plurality of pins protrudes from the shell.

[0030] The application has the following technical effects:

[0031] The BOOST power semiconductor module designed by the application reduces material cost and packaging time through plastic packaging;

[0032] The BOOST power semiconductor module designed by the application reduces the volume of the BOOST power semiconductor module through optimization of the substrate frame, while retaining the function of top heat dissipation;

[0033] The application effectively reduces parasitic inductance by using copper bridge bonding, and allows a large current to pass while also providing part of the heat dissipation capacity.

[0034] The "T" shaped pin designed by the application leaves space for parallel connection of subsequent single-phase BOOST circuits, double-phase, triple-phase or even four-phase and above, so that multiple single-phase modules can be connected in parallel to realize a multi-phase BOOST circuit on the basis of ensuring the integrity of the single-phase module; in the multi-phase module, if a module is scrapped due to chip failure, only a single-phase module is lost, and the overall multi-phase module can still operate normally by removing the failed single-phase module and replacing it with a new good single-phase module. BRIEF DESCRIPTION OF DRAWINGS

[0035] FIG. 1 is a packaging structure diagram of the application;

[0036] FIG. 2 is a bottom plate substrate diagram of the application;

[0037] FIG. 3 is a semiconductor module diagram of the application loaded with a chip;

[0038] FIG. 4 is a semiconductor module diagram of the application with a connection unit;

[0039] FIG. 5 is a semiconductor module diagram of the application with a pin;

[0040] FIG. 6 is a semiconductor module diagram of the application with a bonding wire;

[0041] Figure 7 is a schematic diagram of a pin-bonded semiconductor module of the present application;

[0042] Figure 8 is a schematic diagram of a package structure with multiple phases of the present application;

[0043] Figure 9 is a schematic diagram of a parallel dual-phase package structure of the present application;

[0044] Figure 10 is a schematic diagram of a source through PCB wiring parallel dual-phase package structure of the present application;

[0045] Figure 11 is a schematic diagram of a parallel three-phase package structure of the present application;

[0046] Figure 12 is a schematic diagram of a dual-parallel dual-phase package structure of the present application;

[0047] Figure 13 is a schematic diagram of a three-parallel dual-phase package structure of the present application.

[0048] wherein, 1 - semiconductor module, 2 - base substrate, 3 - heat dissipation substrate, 1a - first side, 1b - second side, 1c - third side, 1d - fourth side, 21 - upper bridge region, 211 - upper bridge chip soldering and bonding area, 212 - temperature monitoring soldering port area, 213 - upper bridge chip, 214 - monitoring resistance, 215 - upper bridge chip connection unit, 216 - upper bridge chip pin soldering area, 21a - temperature monitoring first pin, 21b - temperature monitoring second pin, 21c - upper bridge chip pin, 21d - multiple phase pin, 22 - lower bridge region, 221 - lower bridge chip drain soldering and bonding area, 222 - drain pin soldering area, 223 - gate pin soldering area, 224 - Kelvin source pin soldering area, 225 - power source soldering and bonding area, 226 - lower bridge chip, 227 - lower bridge chip connection unit, 22a - drain pin, 22b - gate pin, 22c - source pin, 22d - Kelvin source pin, 228 - Kelvin source wire bonding area, 229 - gate wire bonding area, 2261 - lower bridge chip Kelvin source wire bonding area, 2262 - lower bridge chip gate wire bonding area, 2263 - gate bonding wire, 2264 - Kelvin source bonding wire, 23 - region connection point. DETAILED DESCRIPTION

[0049] The present application will be further described in conjunction with the accompanying drawings and examples.

[0050] Example 1

[0051] A plastic package BOOST semiconductor module, comprising: a bottom plate substrate 2 and a heat dissipation substrate 3, the bottom plate substrate 2 and the heat dissipation substrate 3 form a semiconductor cavity, the heat dissipation substrate 3 is above the bottom plate substrate 2, the bottom plate substrate 2 is provided with a conductive layer, and the conductive layer is located in the semiconductor cavity; the heat dissipation substrate 3 is provided on the whole surface, so as to facilitate heat dissipation of the semiconductor module 1, and the heat dissipation substrate 3 is made of aluminum oxide, aluminum nitride or silicon nitride.

[0052] The bottom plate substrate 2 is, for example, a Direct Bond Copper (DBC) ceramic substrate or an Active Metal Brazing (AMB) substrate.

[0053] As shown in FIG. 2, FIG. 3 and FIG. 4, the semiconductor cavity comprises a first side 1a and a third side 1c opposite in a first direction, and a second side 1b and a fourth side 1d opposite in a second direction; the first side 1a, the second side 1b, the third side 1c and the fourth side 1d are connected end to end.

[0054] The bottom plate substrate 2 is provided with a conductive layer, and the material of the conductive layer is, for example, copper foil; the conductive layer can form an upper bridge area 21 and a lower bridge area 22 by a copper foil pattern.

[0055] In the first direction, the conductive layer oppositely forms the upper bridge area 21 and the lower bridge area 22, wherein the upper bridge area 21 is located on one side of the first side 1a, and the lower bridge area 22 is located on one side of the third side 1c; the upper bridge area 21 comprises an upper bridge chip welding and bonding area 211 and a temperature monitoring welding port area 212; the temperature monitoring welding port area 212 is close to the connection between the first side 1a and the fourth side 1d.

[0056] The lower bridge area 22 comprises a lower bridge chip drain welding and bonding area 221, a drain pin welding area 222, a gate pin welding area 223, a Kelvin source pin welding area 224 and a power source welding and bonding area 225.

[0057] The power source welding and bonding area is close to the connection between the third side 1c and the fourth side 1d; the second side 1b is sequentially provided with the power source welding and bonding area 225, the Kelvin source pin welding area 224, the gate pin welding area 223 and the drain pin welding area 222, and the power source welding and bonding area is close to one side of the fourth side 1d, the drain pin welding area 222 is close to the connection between the second side 1b and the third side 1c; the lower bridge chip drain welding and bonding area 221 is close to the upper bridge chip welding and bonding area 211.

[0058] A plurality of upper bridge chips 213 and a plurality of lower bridge chips 226, the plurality of upper bridge chips 213 are mounted on the upper bridge chip welding and bonding area 211, and the plurality of lower bridge chips 226 are mounted on the lower bridge chip drain welding and bonding area 221.

[0059] The plurality of upper bridge chip connecting units 215 and the plurality of lower bridge chip connecting units 227, the plurality of upper bridge chips 213 are electrically connected to each other through the upper bridge chip connecting units 215, and the plurality of lower bridge chips 226 and the power source bonding area are electrically connected to each other through the lower bridge chip connecting units 227.

[0060] The lower bridge chip drain welding and bonding area 221 is provided with a region connection point 23, and the upper bridge chip connecting unit 215 is electrically connected to the lower bridge region 22 through the region connection point 23; the region connection point 23 is a welding point, which is a welding position of the upper bridge region and the lower bridge region.

[0061] The temperature monitoring welding port area 212 is connected with a temperature pin, which includes a temperature monitoring first pin 21a and a temperature monitoring second pin 21b; the upper bridge chip welding and bonding area 211 has an upper bridge chip pin welding area 216, and the upper bridge chip pin welding area 216 is connected with an upper bridge chip pin 21c;

[0062] The Kelvin source pin welding area 224 is connected with a Kelvin source pin 22d, the gate pin welding area 223 is connected with a gate pin 22b, the drain pin welding area 222 is connected with a drain pin 22a, and the power source pin welding and bonding area 225 is connected with a power source pin 22c; the source pin 22c, the Kelvin source pin 22d, the gate pin 22b and the drain pin 22a are arranged in sequence along the second edge 1b.

[0063] The plurality of upper bridge chips 213 and the plurality of lower bridge chips 226 are arranged in a column along the first direction, and the plurality of upper bridge chips 213 in the column are electrically connected to the upper bridge region 21 by the same upper bridge chip connecting unit 215; the plurality of lower bridge chips 226 in the column are electrically connected to the lower bridge region 22 by the same lower bridge chip connecting unit 227.

[0064] The lower bridge region 22 and the lower bridge region 22 are mirror-symmetric along the virtual symmetry line extending in the second direction.

[0065] The upper bridge chip pin 21c is a T-shaped downward bending pin.

[0066] The upper bridge chip 213 is a diode, and the lower bridge chip 226 is a metal-oxide-semiconductor field-effect transistor (MOSFET) chip, an insulate-gate bipolar transistor (IGBT) and the like, which can be based on traditional silicon technology or wide-bandgap technology, such as silicon carbide (SiC).

[0067] (Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET) chip, an insulate-gate bipolar transistor (IGBT) and the like, which can be based on traditional silicon technology or wide-bandgap technology, such as silicon carbide (SiC).

[0068] The upper bridge chip connecting unit 215 and the lower bridge chip connecting unit 227 include a copper bridge, an aluminum bonding wire, a copper bonding wire, or a silver bonding wire.

[0069] The Kelvin source pin soldering area 224 and the gate pin soldering area 223 are provided with a Kelvin source wire bonding area 228 therebetween; the Kelvin source wire bonding area 228 is provided with a gate wire bonding area 229 thereabove; the lower bridge chip 226 is provided with a lower bridge chip Kelvin source wire bonding area 228 and a lower bridge chip gate wire bonding area 2262; the lower bridge chip Kelvin source wire bonding area 228 is electrically connected with the Kelvin source wire bonding area 228 through a Kelvin source bonding wire 2264; and the lower bridge chip gate wire bonding area 2262 is electrically connected with the gate wire bonding area 229 through a gate bonding wire 2263.

[0070] Embodiment 2

[0071] Based on the embodiment 1, in FIG. 3, FIG. 4, and FIG. 5, the upper bridge chip connecting unit 215 in this embodiment adopts a copper tape, and a monitoring resistance 214 is provided on the temperature monitoring soldering port area 212; the upper bridge chip 213 is provided with three diodes, and the upper bridge chip pin 21c is the power anode of the diode, which is used for connecting with the PCB board. The diode cathodes are electrically connected with each other through the copper tape bridge; the lower bridge chip 226 is provided with three MOS tubes, and the MOS tubes and the power source bonding area are electrically connected with each other through the parallel copper tape bridge; and the upper bridge area 21 and the lower bridge area 22 are electrically connected with the area connecting point 23 through the copper tape bridge.

[0072] Embodiment 3

[0073] Based on the embodiment 1, different from the embodiment 2, in FIG. 6 and FIG. 7, the upper bridge chip connecting unit 215 in this embodiment adopts a bonding wire, which is any one of an aluminum bonding wire, a copper bonding wire, or a silver bonding wire; and the bonding wire used for the same semiconductor module is the same kind. The upper bridge chip 213 is provided with two diodes, and the upper bridge chip pin 21c is the power anode of the diode, which is used for connecting with the PCB board. The diode cathodes are electrically connected with each other through the bonding wire; the lower bridge chip 226 is provided with two MOS tubes, and the MOS tubes and the power source bonding area are electrically connected with each other through the bonding wire; and the upper bridge area 21 and the lower bridge area 22 are electrically connected with the area connecting point 23 through the bonding wire.

[0074] Embodiment 4

[0075] A packaging structure, as shown in FIG. 1, includes a shell, the shell includes a containing cavity, and the semiconductor module, the bottom plate substrate 2 and the conductive layer are located in the containing cavity, and each of the plurality of pins respectively protrudes out of the shell.

[0076] Embodiment 5

[0077] On the basis of the above embodiment, different from embodiment 4 is that the upper bridge chip welding and bonding area 211 in figure 8 is also connected with multi-phase pin 21d, and the multi-phase pin 21d is a T-shaped flat pin, which is convenient to form multi-phase BOOST semiconductor module 1 by leading out multi-phase pin 21d.

[0078] Embodiment 6

[0079] On the basis of embodiment 5, figure 9 is a double-phase packaging structure formed by connecting two single-phase BOOST semiconductor modules 1 in parallel.

[0080] Embodiment 7

[0081] On the basis of embodiment 5, different from embodiment 6 in figure 10 is that the source of the mos of two single-phase BOOST semiconductor modules 1 is connected in parallel through PCB wiring to obtain a double-phase packaging structure.

[0082] Embodiment 8

[0083] On the basis of embodiment 5, figure 11 is a three-phase packaging structure formed by connecting the source of the mos of three single-phase BOOST semiconductor modules 1 in parallel through PCB wiring.

[0084] Embodiment 9

[0085] On the basis of embodiment 6, figure 12 is a double parallel double-phase packaging structure formed by placing two parallel double-phase packaging structures in parallel.

[0086] Embodiment 10

[0087] On the basis of embodiment 7, figure 12 is a double parallel double-phase packaging structure formed by connecting two double-phase packaging structures in parallel.

[0088] Embodiment 11

[0089] On the basis of embodiment 6, figure 13 is a three parallel double-phase packaging structure formed by connecting three double-phase packaging structures in parallel.

[0090] Embodiment 12

[0091] On the basis of embodiment 8, figure 13 is a parallel three parallel double-phase packaging structure formed by connecting two three-phase packaging structures in parallel.

Claims

1. A plastic-encapsulated BOOST semiconductor module, characterized by, include: A base plate and a heat dissipation plate form a semiconductor cavity. A conductive layer is provided on the base plate and is located inside the semiconductor cavity. The semiconductor cavity includes a first side and a third side opposite to each other in a first direction, and a second side and a fourth side opposite to each other in a second direction; the first side, the second side, the third side and the fourth side are connected end to end; In the first direction, an upper bridge region and a lower bridge region are disposed opposite to each other on the conductive layer, wherein the upper bridge region is located on the side where the first side is located, and the lower bridge region is located on the side where the third side is located; The bridge area includes the bridge chip soldering and bonding area and the temperature monitoring soldering port area; the temperature monitoring soldering port area is located near the connection between the first and fourth sides. The underbridge region includes the drain welding and bonding area of ​​the underbridge chip, the drain pin welding area, the gate pin welding area, the Kelvin source pin welding area, and the power source welding and bonding area; The power source bonding area is located near the connection between the third and fourth sides; the second side has a power source bonding area, a Kelvin source pin bonding area, a gate pin bonding area, and a drain pin bonding area in sequence, with the power source bonding area located near the fourth side and the drain pin bonding area located near the connection between the second and third sides; the drain bonding and bonding area of ​​the lower bridge chip is located near the upper bridge chip bonding and bonding area. Multiple upper-bridge chips and multiple lower-bridge chips are mounted in the upper-bridge chip soldering and bonding area, and multiple lower-bridge chips are mounted in the lower-bridge chip drain soldering and bonding area. Multiple upper-bridge chip connection units and multiple lower-bridge chip connection units are provided. Multiple upper-bridge chips are electrically connected to each other through upper-bridge chip connection units, and multiple lower-bridge chips and power source welding bonding areas are electrically connected to each other through lower-bridge chip connection units. The drain welding and bonding area of ​​the lower bridge chip is provided with a regional connection point, and the upper bridge chip connection unit is electrically connected to the lower bridge area through the regional connection point. Multiple pins are present. The temperature monitoring soldering port area is connected to temperature pins, including a first temperature monitoring pin and a second temperature monitoring pin. The upper bridge chip soldering and bonding area has an upper bridge chip pin soldering area, which is connected to the upper bridge chip pins. The Kelvin source pin soldering area is connected to the Kelvin source pin, the gate pin soldering area is connected to the gate pin, the drain pin soldering area is connected to the drain pin, and the power source soldering and bonding area is connected to the power source pin; the power source pin, Kelvin source pin, gate pin, and drain pin are arranged sequentially along the second side; the upper bridge chip pin is a T-shaped downward bent pin; the upper bridge chip soldering and bonding area is also connected to a multi-phase pin, which is a T-shaped flat-edge pin.

2. The plastic-encased BOOST semiconductor module according to claim 1, characterized in that Multiple upper-bridge chips and multiple lower-bridge chips are arranged in a column along the first direction. In a column, multiple upper-bridge chips are electrically connected to the upper-bridge region by the same upper-bridge chip connection unit; in a column, multiple lower-bridge chips are electrically connected to the lower-bridge region by the same lower-bridge chip connection unit.

3. The plastic packaged BOOST semiconductor module according to claim 1, wherein The upper and lower bridge regions are mirror-symmetrical along the virtual symmetry line extending in the second direction.

4. The plastic packaged BOOST semiconductor module according to claim 1, wherein The substrate is an insulating ceramic substrate.

5. The plastic packaged BOOST semiconductor module according to claim 1, wherein The upper bridge chip connection unit and the lower bridge chip connection unit are copper bridges, aluminum bonding wires, copper bonding wires or silver bonding wires.

6. The plastic packaged BOOST semiconductor module according to claim 1, wherein A Kelvin source pin welding area and a gate pin welding area are provided between the Kelvin source pin welding area and the gate pin welding area; a gate wire bonding area is provided above the Kelvin source wire bonding area; a lower bridge chip Kelvin source wire bonding area and a lower bridge chip gate wire bonding area are provided on the lower bridge chip; the lower bridge chip Kelvin source wire bonding area is electrically connected to the Kelvin source wire bonding area through a Kelvin source bonding wire; and the lower bridge chip gate wire bonding area is electrically connected to the gate wire bonding area through a gate bonding wire.

7. A package structure, characterized by, The semiconductor module includes a housing, the housing including a receiving cavity, and the semiconductor module, the backplane substrate, and the conductive layer being located in the receiving cavity, each of the plurality of pins protruding from the housing.

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