Customisable architecture for neural interface electronics

Abstract

An electrical bus for a neural interface arrangement is provided, the bus comprising: a first electrical path for suppling electrical power to units of a chipset connected to the bus in use; a second electrical path for carrying analogue signals between said units; and a third electrical path for carrying digital signals between said units. Also provided is a neural interface arrangement comprising such a bus; at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit connected to the bus, wherein each sensing unit or stimulation unit is electrically connected to a respective electrode or to another sensing or stimulation device; and a control unit connected to the bus, for controlling operation of the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit via the bus, or for controlling signal flow to or from the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit via the bus. A method of forming a neural interface arrangement is also provided, the method comprising: defining a set or library of units that are compatible with one another; selecting a plurality of units from said set; and connecting the selected units to an electrical bus.

Description

[0001] CUSTOMISABLE ARCHITECTURE FOR NEURAL INTERFACE ELECTRONICS

[0002] Field of the invention

[0003] The present invention relates to an arrangement of units such as integrated circuits suitable for exchanging electrical signals with the human nervous system or brain, for example as part of an implantable medical device. The present invention enables and facilitates rearrangement of such units, to allow for efficient and effective customisation of electronics for medical devices to target different applications, for example during product development, or to suit individual patients’ needs. The present invention is not limited to neural interface applications, and may also be applied to other implantable devices.

[0004] Background to the invention

[0005] Neural implants are defined as electronic devices that are implanted within the human body and interact with the nervous system for managing and / or treating neurological and / or other medical conditions. Neural implants may be considered to be a subset of “active implantable medical devices”. (Other examples of “active implantable medical devices” include pacemakers and cardiac defibrillators.) Such neural implant devices have already had a positive impact on the lives of millions of people, where pharmaceutical interventions have not been an effective option. Examples include: cochlear implants for restoring hearing to the profoundly deaf, deep brain stimulation for managing symptoms of Parkinson’s disease and other movement disorders, vagus nerve stimulation for epilepsy, apnoea and treatment-resistant depression, and spinal cord stimulation to alleviate chronic pain without risk of opioid addiction.

[0006] Functional description of a neural implant: Neural implants typically use electrodes (typically made from conducting materials such as a metal) placed in direct contact or close proximity with the target neural tissue (e.g. a specific area in the brain, or nerve) to translate ionic currents flowing within the tissue to electronic currents flowing within metallic conductors. The electronics within (or connected to) neural implant electrodes may be used to affect or modify neural activity through electrical stimulation (‘neuromodulation’), and / or to observe neural activity through electrical sensing (‘neuromonitoring’), e.g. by measuring biopotential signals generated by the target neural tissue. An overall electronic system may combine these neural interface functions (sensing and / or stimulation) with digital processing and control, power management and wireless communication. The vast majority of existing neural implants are open-loop neuromodulation devices that have been derived from cardiac pacemakers. These provide a continuous tonic stimulation pattern (fixed frequency, pulse width and amplitude) to a small number of channels (e.g. typically 2-4 electrodes) based on parameters that are programmed by a clinician. : A typical neural implant, such as a deep brain stimulator, comprises two main components: a hermetically-sealed package (e.g. made of titanium) that houses the battery (either a primary cell or rechargeable), a circuit board that integrates the electronic system, and a feedthrough socket; along with the electrode lead. The lead features a plug on one end for connection to the feedthrough socket and electrode contacts on the other end for implantation into the targeted brain area. This design concept, originally derived and adapted from cardiac pacemakers, involves implanting the titanium package in a small pocket under the collarbone in the upper chest. The lead is then tunnelled under the skin across the neck and head, penetrating the skull to reach the designated brain region. Recent advancements have led to the development of devices that are mounted cranially under the scalp, necessitating shorter leads and enabling a significantly less invasive surgical implantation process.

[0007] Recent advances in closed- neuromodulation Developers and medical device manufacturers are seeking to extend capability of neural implants to improve outcomes but also to address entirely new medical applications. A recent development is that of closed- loop neuromodulation - to sense neural activity and use this to adjust the stimulation patterns. This brings many potential benefits such as increased battery lifetime (for non- rechargeable neural implants, surgery is typically required for battery replacement), reduced off-target / side effects (stimulation is applied only when it is needed), and adapting parameters to maintain good efficacy over time. An example of how this is being applied in deep brain stimulation is to detect the onset of movement and the on-demand termination of stimulation delivery. In addition to improving existing interventions, closed loop operation is providing opportunity to “sense and stimulate” in response to specific detectable

[0008] ‘biomarkers’ such as seizures in epilepsy and triggers to depression episodes.

[0009] Emerging modalities for neural interfacing The neurotechnology community are advancing new modalities that are revolutionising neuroscience by going beyond conventional electrode interfaces that interact directly with tissue in close contact. These offer unprecedented precision and versatility in reading and modulating brain activity. Innovations in optogenetics enable precise spatial and temporal control of neural circuits by using light to control genetically modified neurons. Techniques like ultrasound neuromodulation and magnetic stimulation provide non-invasive or minimally invasive options for targeting deep brain regions [1], Also, recent advances in temporal interference stimulation are providing opportunities to modulate activity at tissue targets away from the electrodes [2], Although these methods leverage different mechanisms of neural interfacing, many can be applied in conjunction with an active electronic device by interfacing to a sensor, transducer or actuator, instead of directly using electrodes, or by instrumenting the electrode interface differently.

[0010] Emerging applications and technical (unmet) requirements: Emerging applications in neural implants include brain computer interfaces (BCIs), enabling direct communication between the brain and external devices for communication and control (such as for patients with amyotrophic lateral sclerosis (ALS) or locked-in syndrome), and bioelectronic medicine, which utilise neural implants to modulate the autonomic or peripheral nervous system to provide innovative therapeutic approaches for various conditions, including immune- mediated inflammatory diseases (e.g. rheumatoid arthritis, multiple sclerosis, Crohn’s disease).

[0011] These new opportunities require significantly more sophisticated electronics (compared to existing devices) to provide effective bidirectional sense / stimulation capability (closed loop neuromodulation, e.g. [3]), high channel count recording (brain computer interfaces), e.g. [4], advanced stimulation profiles (bioelectronic medicine [5], e.g. [6]), whilst maintaining or reducing resource utilization (energy, volume), e.g. [7], This is combined with a drive to further miniaturise neural implants to reduce the invasiveness of the surgical implantation and associated risk, towards a minimally invasive workflow. Smaller neural implants means less space for electronics and a smaller battery capacity, thus requiring lower power electronics and / or wireless power transfer.

[0012] Problematically, the current method of circuit board level integration using off-the-shelf parts cannot alone meet the requirements of emerging neural implant applications. Space in the implant package is limited, so both the circuit complexity (i.e. number of components) and energy capacity (i.e. size of battery) are constrained.

[0013] Custom integrated circuits are thus desirable for advanced systems that require high integration density (such as increased system complexity at reduced size), enhanced performance (including improved energy efficiency and lower power consumption), and additional functionality (such as real-time processing capability).

[0014] The effort required, however, to develop custom high-performance integrated circuits for specific neural implant applications is often prohibitive from an economic standpoint. The majority of neural implant manufacturers do not have in-house capabilities to develop integrated circuits, nor can they tolerate the lengthy development timeline and associated risk. Companies with in-house capability typically do not make parts available to others in the industry, and design service providers with sector-specific expertise are few and limited in their own resources. In this regard, it is highly desirable that medical devices (in particular implantable medical devices) are developed using a specific process (e.g. using an ISO 13485 quality management system, and ISO 14790 risk management), which few companies that develop integrated circuits have in place.

[0015] The integration of a complete system onto a single custom integrated circuit, known as a system-on-chip (SoC) approach, within a specific CMOS technology, presents unique technical challenges. The various functions required in neural implants have distinct technology needs that may not be compatible. For instance, stimulation electronics, important for neural implants, need a high voltage supply to ensure sufficient headroom for the required stimulation magnitude across different electrode impedances. On the other hand, instrumentation circuits demand low noise capabilities, while digital processing circuits benefit most from advanced node digital logic and / or memory for enhanced efficiency (low power, compactness). Therefore, consolidating all these functions onto a single chip requires selection of a single semiconductor process technology and can be suboptimal, resulting in compromised overall performance.

[0016] An alternative approach is to integrate the system at circuit board level using a set of custom-designed chips (in a similar way to how systems are currently integrated using off- the-shelf parts). This would enable the partitioning of various neural interface specific functions across multiple chips. This allows each function to be implemented in the most suitable semiconductor process technology.

[0017] However, there remain a number of challenges: Chip interconnections - Chips fabricated with different process technologies often have different power supply and logic voltage levels. Combining these requires additional level converters and power management circuits, which, while solving the connectivity problem, would increase complexity and expand the board area. Realizing custom (or upscaling to high) channel count systems - Although the chips can communicate control and data signals using common digital bus standards like Serial Peripheral Interface (SPI) or Inter-Integrated Circuit (I2C), this approach becomes inefficient for scaling up to larger systems. This inefficiency stems from the need to design each chip to handle the worst-case scenario (the largest system configuration), leading to potential excess power consumption due to bus overhead, in smaller scale systems. Access to electrode lines - Although multiple chips can be cascaded using a shared digital bus system, this does not accommodate shared analogue I / O needs. For instance, a bidirectional sense and stimulation system requires electrode connections accessible to both sensing and stimulation chips, which cannot be directly interconnected due to the high voltages from the stimulation chip that the sensing chip cannot withstand. Shared reference lines - Extending the number of sensing channels through combining multiple chips would require access to common reference signals that may need to be dynamically configured. For example, a global reference signal should be selectable from any sense input across all sense chips. Precise timing - Additionally, the precise timing demands for certain functions, like triggering phase-locked stimulation, may necessitate extra asynchronous lines to overcome latency issues inherent in using a shared synchronous data bus. This complexity adds further challenges to system-level integration. Physical space / volume - As complexity increases, so do the number of parts such as discrete components and integrated circuits. This will expand the physical footprint required which is severely constrained. These challenges indicate that there is no straightforward methodology or approach to tailoring systems to various application needs, even if standard components were to be available for each required function in neural implants.

[0018] Neural implant electronics previously reported in the literature are either exclusively designed using off-the-shelf components or combine off-the-shelf components with custom ASICs. Examples include the Medtronic Summit RC+S [8], WAND system [9], Custom ASIC designs typically target a System-on-Chip (SoC) approach, implementing stimulation, e.g.

[0010] , recording, e.g.

[0011] , or bidirectional interfacing (combining both stimulation and sensing), e.g.

[0012] , There has also been some work towards creating a modular architecture to allow for scalability. For example, NeuroBus

[0013] , Interestim

[0014] , and the Integrated Neural Interface

[0015] implement a digital interface to allow for scalable electrode arrays. Other approaches implement existing standards, for example, the Networked Neuroprosthetic (NNP) system uses the controller area network (CAN) bus standard for multi-implant systems

[0016] , These systems however all rely on a basic digital bus, essentially combining independent systems, and thus do not address many of the challenges listed above.

[0019] Summary of the Invention

[0020] Aspects of the present invention are set out in the appended independent claims, while details of certain embodiments are set out in the appended dependent claims.

[0021] According to a first aspect of the invention there is provided an electrical bus for a neural interface arrangement, the bus comprising: a first electrical path for suppling electrical power to units of a chipset connected to the bus in use; a second electrical path for carrying analogue signals between said units; and a third electrical path for carrying digital signals between said units.

[0022] Preferably the first electrical path comprises: an analogue core power line; an analogue high voltage power line; and a digital core power line.

[0023] Preferably the second electrical path comprises: a first analogue line for providing a reference signal to said units; and one or more analogue lines for: transmitting stimulation or actuation signals to said units, and / or to one or more electrodes or other stimulation devices connected (directly or indirectly) to the bus; and / or monitoring the status of one or more electrodes connected (directly or indirectly) to the bus.

[0024] Preferably the third electrical path comprises: a first digital line for transmitting commands, control signals, and / or configuration signals between said units; and a second digital line for transmitting data outputs between said units.

[0025] The third electrical path may also, or alternatively, comprise a common digital line for transmitting commands, control signals, and / or configuration signals between said units, and for transmitting data outputs between said units.

[0026] The third electrical path may further comprise: a third digital electrical line for supplying a global clock and / or a synchronisation signal to said units; and / or a fourth digital electrical line for supplying an asynchronous signal, such as an asynchronous trigger and / or a blanking signal, to said units.

[0027] In certain embodiments, at least one path or line may incorporate a discontinuity, to divide the path or line into parts that are electrically isolated from one another.

[0028] In one example embodiment the second digital line may incorporate a discontinuity, to form a first digital trace and a second digital trace that are electrically isolated from one another; wherein the first digital trace is for carrying unprocessed data obtained by a subset of components connected to the bus; and the second digital trace is for carrying processed data to one or more other components connected to the bus.

[0029] In another example embodiment the first analogue line may incorporate a discontinuity, to form a first analogue trace and a second analogue trace that are electrically isolated from one another; wherein the first analogue trace is for carrying a first reference signal to a first subset of components connected to the bus; and the second analogue trace is for carrying a second reference signal to a second subset of components connected to the bus.

[0030] According to a second aspect of the invention there is provided a neural interface arrangement comprising: the electrical bus according to the first aspect; at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit connected to the bus, wherein each sensing unit or stimulation unit is electrically connected to a respective electrode or to another sensing or stimulation device; and a control unit connected to the bus, for controlling operation of the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit via the bus, or for controlling signal flow to or from the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit via the bus.

[0031] The neural interface arrangement may have more than one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit connected along the bus (rather than simply being connected at either end of the bus) and sharing at least some of the paths of the bus.

[0032] The first digital line of the bus may be configured to transmit commands, control signals, and / or configuration signals from the control unit to the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit.

[0033] When configured as a neuromonitoring system, for example, the neural interface arrangement may comprise at least one sensing unit configured to output a signal representing a biopotential measured / obtained by a respective electrode to the second digital line of the bus when enabled by the control unit.

[0034] The neural interface arrangement may comprise two or more sensing units; and the first analogue line of the bus may be configured to supply a common reference signal to said sensing units.

[0035] Optionally a first sensing unit may be configured to provide the common reference signal to another sensing unit via the first analogue line.

[0036] When configured as a neuromodulation system, the neural interface arrangement may comprise at least one stimulation unit configured to generate a stimulation signal and to output the stimulation signal to one or more electrodes or other stimulation devices, or to a multiplexer unit to which electrodes or other stimulation devices are connected, via one of said one or more analogue lines of the bus when enabled by the control unit.

[0037] Optionally the control unit may be configured to output an asynchronous trigger to the fourth digital electrical line of the bus, to trigger the at least one stimulation unit to generate and output the stimulation signal. Optionally the control unit may be configured to output a blanking signal to the at least one sensing unit via the fourth digital electrical line of the bus.

[0038] Optionally the neural interface arrangement may further comprise: a multiplexer unit to which at least two electrodes or other sensing or stimulation devices are connected; and an electrode monitor unit configured to monitor, via the multiplexer unit, whether there is residual charge on electrodes, to characterise electrodes, to measure impedance (e.g. brain impedance, or the impedance of a transducer such as a light emitting diode, thermistor, PIN diode, etc.), and / or to test continuity across leads; wherein said one or more analogue lines of the bus are configured to transmit measurements obtained by electrodes to the electrode monitor unit; and the electrode monitor unit is configured to output digitised measurements to the control unit via the second digital line of the bus.

[0039] Optionally the neural interface arrangement may further comprise a processing unit configured to: receive data transmitted by the bus from the sensing unit, stimulation unit, or electrode monitoring unit; process the received data; and output processed data to the bus.

[0040] In a particular example of a neuromonitoring system, the neural interface arrangement may comprise: a plurality of electrodes for measuring biopotential signals generated by target neural tissue; and a respective plurality of sensing units, each sensing unit being electrically connected (directly or indirectly) to a respective one of said electrodes, wherein each sensing unit comprises a recording system configured to record biopotentials input by the respective electrode; and an analogue-to-digital converter configured to digitise the recorded biopotentials; and wherein each sensing unit is configured to output the recorded biopotentials to the third electrical path of the bus when enabled by the control unit.

[0041] Each sensing unit may be configured to output the recorded biopotentials to the second digital line, which transmits the recorded biopotentials to the control unit.

[0042] The bus may be configured to transmit control and / or configuration signals to said sensing units from the control unit. In particular, the first digital line of the bus may be configured to transmit said control and / or configuration signals to said sensing units. Optionally the configuration signals may configure each sensing unit to: support unipolar and / or bipolar biopotentials input by said electrodes; enable and / or disable channels from the neural recording system; and / or adjust instrumentation settings.

[0043] Optionally the neural interface arrangement may comprise a first sensing unit electrically connected to a first electrode; and a second sensing unit electrically connected to a second electrode; wherein said electrodes input unipolar biopotentials to the sensing unit; and the first electrode connected to the first sensing unit provides a reference signal to the second sensing unit via the bus.

[0044] The first analogue line of the bus may be configured to transmit the reference signal from the first sensing unit to the second sensing unit.

[0045] The control unit may be configured to cause each sensing unit to output the recorded biopotentials to the bus using time division multiplexing.

[0046] In a particular example of a neuromodulation system, the neural interface arrangement may comprise: at least one stimulation unit electrically connected to a respective electrode substantially in contact with a targeted neural tissue; wherein the at least one stimulation unit is configured to generate charge-balanced stimuli and to output the stimuli to the respective electrode via the bus.

[0047] The neural interface arrangement may further comprise a multiplexer unit configured to route the stimuli transmitted by the bus to said electrode.

[0048] The or each stimulation unit may be configured to output the stimuli to said one or more analogue lines of the bus.

[0049] The neural interface arrangement may further comprise an electrode monitoring unit configured to: measure potential difference, direct current resistance, and / or alternating current impedance between at least two electrodes or other sensing or stimulation devices (e.g. diode(s) or transducer(s)); and output a digitised measurement to the bus when enabled by the control unit. The electrode monitoring unit may be configured to output the digitised measurement to the second digital line of the bus.

[0050] In certain examples the neural interface arrangement may further comprise at least one stimulation unit electrically connected to a respective stimulation device substantially in contact with a targeted neural tissue; wherein the at least one stimulation unit may be configured to generate stimuli and to output the stimuli to the stimulation device via the bus.

[0051] Optionally, the stimulation device may be one of: an electrical actuator, an optical actuator, an ultrasonic actuator, a thermal actuator, a chemical / chemogenetic actuator, or a mechanical actuator.

[0052] In other examples capable of employing multiple modes of stimulation, the neural interface arrangement may comprise at least one stimulation unit electrically connected via the bus to a respective electrode substantially in contact with a first targeted neural tissue, and to a respective stimulation device substantially in contact with a second targeted neural tissue, the at least one stimulation unit being configured to generate a stimulation current; wherein the stimulation unit is configured to output the stimulation current to said one or more analogue lines of the bus; and the multiplexer unit is configured to direct the stimulation current from said one or more analogue lines of the bus to the respective electrode and / or to the respective stimulation device. Optionally, the first targeted neural tissue and the second targeted neural tissue may be the same targeted neural tissue.

[0053] Optionally, the stimulation device may be an actuator or transducer such as a light source, e.g. an LED or laser diode.

[0054] The neural interface arrangement may further comprise a stimulation monitoring unit configured to monitor at least one of: currents flowing into the target tissue and / or into the respective electrode, and / or voltages applied to the respective electrode and / or applied across the stimulation device.

[0055] More generally, the bus may be configured to transmit control signals and configuration signals from the control unit to the stimulation unit, multiplexer unit, and / or electrode monitoring unit. For example, the first digital line of the bus may be configured to transmit said control and configuration signals to said at least one stimulation unit, multiplexer unit, and / or electrode monitoring unit.

[0056] Optionally the configuration signals may configure the at least one stimulation unit to generate monophasic, biphasic, or triphasic stimuli.

[0057] Optionally the configuration signals may configure the least one stimulation unit to generate monopolar, bipolar or multipolar stimulation.

[0058] Optionally the configuration signals may configure the electrode monitoring unit according to a measurement type, a measurement probe type, stimulus parameters, and / or measurement parameters.

[0059] Optionally the controller unit may be configured to output an asynchronous trigger to the fourth digital electrical line of the bus which triggers the at least one stimulation unit to generate and output the stimulation signal.

[0060] More generally, the first electrical path of the bus may be configured to carry at least one voltage required to power the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit.

[0061] The control unit may be connected to an external device and configured to control the flow of data to the external device.

[0062] The neural interface arrangement may further comprise at least one memory unit configured to store data; wherein the data includes one or more of: neural recording data, stimulation parameters, system configurations, and / or intermediate results generated during signal processing.

[0063] The neural interface arrangement may also comprise at least one environmental sensing unit configured to monitor physical conditions around the neural implant. For example, the environmental sensing unit may comprise one or more of: an inertial sensor such as an accelerometer, a temperature sensor, a humidity sensor, a magnetic field sensor, or a light sensor. The neural interface arrangement may further comprise at least one protection unit configured to safeguard sensitive circuitry and interconnects from potentially damaging electrical events such as electrostatic discharge (ESD), current or voltage surges (e.g. as may be induced by magnetic resonance imaging, or through defibrillators or electrocautery / electrosurgery), and short circuits.

[0064] Optionally, two or more of the units may collectively form a group, wherein the units of the group collectively share a common set of connections to the bus. The units may be grouped by function, and thus each group may be termed a “function group”.

[0065] Optionally, the group (including its constituent units) may be formed as an integrated circuit.

[0066] Optionally, the group, and one or more other such groups, may be integrated on a printed circuit board.

[0067] Optionally, the neural interface arrangement may have two or more such groups connected to a power management unit via the electrical bus.

[0068] In manufacture, in one example each unit may comprise an individual standard semiconductor package or a set of discrete components, the units being connected via the bus.

[0069] The bus may be a PCB substrate (optionally a flexible PCB).

[0070] The bus may have multiple layers connected by vias or interconnects.

[0071] In another example, each unit may be in the form of a system-in-package chipset.

[0072] In another example, each unit may be connected as a bare die onto an interconnect substrate, in the form of a multi-chip module or a system-on-package (alternatively sometimes referred to as a “system-in-package”) chipset.

[0073] In another example the units may be in the form of IP blocks within an integrated circuit. Two neural interface arrangements may be powered by a common power management unit. In this regard, according to a third aspect of the invention there is provided a system comprising: a first neural interface arrangement according to the second aspect; a second neural interface arrangement according to the second aspect; and a power management unit connected to the first electrical path of the first neural interface arrangement, and to the first electrical path of the second neural interface arrangement. Advantageously, the bus of the first neural interface arrangement may be galvanically isolated from the bus of the second neural interface arrangement, thereby galvanically isolating the first neural interface arrangement from the second.

[0074] According to a fourth aspect of the invention there is provided a system comprising: a first electrical bus; a second electrical bus; a third electrical bus; and a bus switching unit to which the first, second and third electrical buses are connected; wherein at least one of the first, second and third electrical buses is an electrical bus according to the first aspect; and wherein the bus switching unit is operable to select which of the first and second electrical buses is in communication with the third electrical bus.

[0075] The system may further comprise a control unit connected to the third electrical bus, for controlling the operation of the bus switching unit and / or for communicating with other control units connected to the first and / or second electrical buses.

[0076] The system may also comprise a processing unit connected to the third electrical bus, for receiving and / or transmitting data, and processing data, from whichever of the first and second electrical buses is in communication with the third electrical bus.

[0077] According to a fifth aspect of the invention there is provided a system comprising: an electrical bus according to the first aspect; at least one control block; and a bus switching unit. The bus switching unit is connected to at least two electrical paths, lines or traces of the electrical bus and to the at least one control block, and is operable to select which of the at least two electrical paths, lines or traces of the electrical bus is in communication with the control block.

[0078] Optionally , the at least one control block is configured to execute commands autonomously. According to a sixth aspect of the invention there is provided a method of supplying electrical power to components of a neural interface arrangement, and of carrying analogue signals and digital signals between said components, using an electrical bus according to the first aspect.

[0079] According to a seventh aspect of the invention there is provided a method of supplying electrical power to components of a neural interface arrangement, and of carrying analogue signals and digital signals between said components, wherein the neural interface arrangement is according to the second aspect.

[0080] According to an eighth aspect of the invention there is provided a method of forming a neural interface arrangement, the method comprising: defining a set (or library) of units that are compatible with one another; selecting a plurality of units from said set; and connecting the selected units to an electrical bus; wherein the units of said set include one or more of: a sensing unit, a stimulation unit, a multiplexer unit, an electrode monitoring unit, a control unit, a power management unit, and a processing unit. The electrical bus may be according to the first aspect, or the neural interface arrangement may be according to the second aspect.

[0081] Brief Description of the Drawings

[0082] Embodiments of the invention will now be described by way of example only with reference to the attached figures in which:

[0083] Figure 1 illustrates an electrical bus forming the core of a customisable neural interface arrangement (essentially a modular platform principle), the bus comprising separate electrical paths dedicated to supplying electrical power, to carrying analogue signals, and to carrying digital signals, to and from units of a chipset connected to the bus;

[0084] Figure 2 illustrates an example of a bus switching unit for selectively establishing connections between different buses;

[0085] Figure 3 illustrates an example of a neuromonitoring system based on the platform of Figure 1 ;

[0086] Figure 4 illustrates an example of a neuromodulation system based on the platform of Figure 1 ;

[0087] Figure 5 illustrates an example of a bidirectional neural interface based on the platform of Figure 1 ; Figure 6 illustrates an example of a bidirectional neural interface based on the platform of Figure 1 , capable of providing both electrical and optical stimulation;

[0088] Figure 7 illustrates an example of incorporating a discontinuity in part of the bus - in this case, splitting a data-carrying trace of the digital path, in order to isolate data input to a processor from data output from the processor;

[0089] Figure 8 illustrates another example of incorporating a discontinuity in part of the bus - in this case, splitting a reference-carrying trace of the analogue path, in order to enable different subsets of recording electrodes to be locally referenced;

[0090] Figure 9 illustrates an example of splitting the bus to isolate power domains;

[0091] Figure 10 illustrates an example of a chipset in which each unit is connected using a printed circuit board or other substrate;

[0092] Figure 11 shows an example of a bidirectional neural interface integrated on a circuit board, wherein the units are provided in discrete groups (which may be in the form of integrated circuits) dedicated to distinct functions;

[0093] Figure 12 is an illustrative low-level diagram of a corresponding system to that of Figure 11 ; Figure 13A and Figure 13B illustrate different views of an example of a chipset vertically stacked in a System-in-Package (SiP) configuration;

[0094] Figure 14 illustrates examples of chipsets in which the units are (a) connected laterally in a Multi-chip Module (MCM) configuration, and (b) stacked vertically in a System-on-Package (SoP) configuration; and

[0095] Figure 15 illustrates an example of a system-on-chip chipset in which individual units are implemented as IP (intellectual property) blocks within a single chip design.

[0096] In the figures, like elements are indicated by like reference numerals throughout.

[0097] Detailed Description of Preferred Embodiments

[0098] The present embodiments represent the best ways known to the Applicant of putting the invention into practice. However, they are not the only ways in which this can be achieved.

[0099] Initial overview

[0100] By way of an initial overview, the present work partitions a neural implant system or a neural interface subsystem into a set of circuits or chips (hereafter referred to as a “chipset”) that are capable of working together (or which are specifically designed or configured to work together, e.g. in the form of a “library” of such chips) and can be easily configured at system level without requiring ASIC redesign. Each circuit or chip (hereafter referred to as a “unit”) within the chipset may implement a specific function. The set of chips may include sensing, stimulation, electrode monitoring, multiplexing, processing, control, and power management chips.

[0101] The different chips are able to communicate data and share power lines as well as analogue signals internally (within the chipset) using a common, shared, bus, which is referred to herein as a “Neural Interface Bus” (NIB). This bus can also be used for an external controller to interface to the system as a whole, providing power, configuration and control to the chipset, as well as receiving data.

[0102] For the units of the chipset to be able to work together, and to be compatible with the bus, they should ideally be configured to read and write at substantially the same digital levels and use substantially the same power levels. The units of the chipset are able to remain compatible despite a degree of variability in these digital levels and power levels - for example a range of ±10% or ±20%.

[0103] Thus, in a general sense, the present work includes a method of forming a neural interface arrangement, the method comprising: defining a set (or “library”) of units that are compatible with one another; selecting a plurality of units from said set; and connecting the selected units to an electrical bus; wherein the units of said set include one or more of: a sensing unit, a stimulation unit, a multiplexer unit, an electrode monitoring unit, a control unit, a power management unit, and a processing unit. As will become apparent from the discussion below, the bus of the present work has a defined structure, to facilitate compatibility with the defined set of units and to facilitate interoperability between the units.

[0104] In the present work, the terms “path”, “line” and "trace” are used to refer to different electrical conductors or sets of electrical conductors within the bus. More particularly, “path” is used at a high-level to refer to electrical conductors for carrying signals directed to different functions, namely power, digital signals, and analogue signals. Each path may comprise one or more lines. The term “line” is used to refer to one or more electrical conductors within (or forming) a path, carrying the same type of signal (namely power, digital signals, or analogue signals). Each line may comprise one or more traces. The term “trace” is used to refer to a single electrical conductor within (or forming) a line. Neural Interface Bus (NIB)

[0105] Figure 1 illustrates an example of a Neural Interface Bus 100 in accordance with the present work, to which some example units (200, 300, 400, 500, 600, 700, 800) of a chipset are connected, along the bus, to form a neural interface arrangement 10. The bus 100 comprises first, second and third electrical paths 110, 120, 130. The first path 110 is dedicated to supplying electrical power to the units. The second path 120 is dedicated to carrying analogue signals between the units. The third path 130 is dedicated to carrying digital signals between the units. The paths 110, 120, 130 are arranged in parallel. As described in greater detail below, the paths 110, 120, 130 may each comprise one or more constituent lines, which are also arranged in parallel. Any of the constituent lines may themselves comprise a set of discrete parallel lines or traces.

[0106] In other words, the bus 100 is configured to separately convey, in parallel, three main signal types, namely power signals (path 110), analogue signals (path 120) and digital signals (path 130).

[0107] As illustrated, the first path 110 (the power supply portion) of the bus 100 may comprise a plurality of discrete power supply lines 111 , 112, 113. These power lines provide the supply voltages required for the different power domains across the chips, typically an analogue core power supply line 111 , an analogue high voltage power supply line 112, and a digital power supply line 113. The digital power supply line 113 provides the highest digital supply voltage level (typically the digital I / O supply) required by the system. If a reduced voltage digital supply is required (e.g. a digital core supply), this can be derived from the digital power supply 113. Alternatively, the bus 100 may be extended to include a separate digital core power supply line. A direct connection to a battery may be included to enable the option of efficient power conversion internally.

[0108] The second path 120 (the analogue signal portion) of the bus 100 may comprise a first analogue line 121 for providing a reference signal to the connected units, and one or more shared analogue lines 122 for sensing, stimulation and electrode monitoring, for example. As discussed in greater detail below, electrodes (or other sensing or stimulation devices) may be connected to such units, or may be connected directly to the bus.

[0109] In the illustrated example, the specific lines of the second (analogue) path 120 comprise: • A shared input reference line 121 for sharing and distributing an electrode reference voltage (or other reference signal) across multiple chips. This can enable bipolar amplifier (sense) channels to be connected in a unipolar configuration (i.e. one input per amplifier with shared reference) across the system. In practice, the input reference line 121 may comprise multiple traces, either through splitting the bus (as discussed in more detail below), or in the form of multiple parallel traces.

[0110] • A multi-line (e.g. four-line) bus 122 for relaying stimulation or actuation signals across the system, providing, for example, one or two lines for galvanically-isolated bipolar current-controlled stimulation; or one, two, three or four lines for unisolated multipolar current-controlled stimulation. Such a four-line bus can also be used for monitoring the electrode voltage, or characterising the electrode impedance, e.g. through applying two-, three-, or four-point kelvin probe measurements. Such a multi-line bus 122 (e.g. having four lines) could also be connected directly to one or more electrodes, with the actuation signals being carried by the bus from one unit to the electrode(s).

[0111] The third path 130 (the digital signal portion) of the bus 100 may comprise a first (low speed; digital core (low voltage)) digital electrical line 131 for transmitting commands, control signals, and / or configuration signals between the connected units; and a second (high speed) digital electrical line 132 for transmitting data outputs between the connected units. The first and second digital lines 131 , 132 may each comprise a set of shared traces. The third path 130 may also comprise a third digital electrical line 133 for supplying a global clock and / or a synchronisation signal to the connected units, and / or a fourth digital electrical line 134 for supplying asynchronous signals, e.g. an asynchronous trigger and / or a blanking signal to the connected units. It will be appreciated that trigger and blanking signals are merely examples of asynchronous signals, and that line 134 may be extended to supply other asynchronous signals.

[0112] Thus, the lines of the third (digital) path 130 may include lines for conveying shared signals such as a clock (line 133), asynchronous control (line 134), and two buses for communicating data: a relatively low speed digital bus (line 131) for receiving commands, control and configuration, and a relatively high speed digital bus (line 132) for transmitting data outputs. Alternatively, or in addition, the digital path 130 of the bus 100 may implement a single common bus for both configuration and data transmission purposes, for connected units having low throughput requirements.

[0113] In the illustrated example, the specific lines of the third (digital) path 130 comprise:

[0114] • A set of shared lines 131 for a relatively low speed digital interface standard (such as I2C or SPI) for configuring the various units.

[0115] • A set of shared lines 132 for a relatively high speed digital interface standard (such as SPI, or dual / quad SPI for higher throughput) for transmitting data that is generated by the various units. To enable scalability to a (relatively) large number of units, expander configurations can be implemented (e.g. a multi-line multiplexed chip select).

[0116] • A global system clock and system reset line 133 for synchronisation of the connected units.

[0117] • A line 134 for transmitting an asynchronous trigger (for initiating stimulation / actuation) and / or blanking signals (to enable protection of sensing circuitry).

[0118] Table 1 below provides an example configuration of a 25-line Neural Interface Bus 100. The table includes examples of typical voltage levels or voltage ranges each line may carry.

[0119] Table 1: An example configuration of a 25-line NIB

[0120] In the above table, values shown as “x / y” indicate two different voltage levels, i.e. x V or y V (potentially ±10% or ±20%), while “n to m” values indicate a range of possible voltages that can be supplied.

[0121] Units within the chipset library

[0122] A specific set of functions is defined to maximise versatility of the chipset as a whole, being able to cater to as many neural implant applications as possible. Each function is achieved using a different, dedicated unit. In practice, the units of the chipset may be provided in any suitable combination, e.g. in a customisable, modular manner. Notably the units are connected along the length of the bus 100 (rather than at either end of the bus) and share at least some of the paths of the bus. Figure 1 illustrates the following units as examples:

[0123] Sensing unit 200 - this may either be connected directly to an electrode (as in the case of electrode 210), or indirectly to an electrode (as in the case of electrode 410) via a multiplexer unit 400 (e.g. if stimulation and / or electrode monitoring is required). Each sensing unit 200 may provide a multi-channel neural recording system that provides low noise amplification, conditioning and digitization of biopotentials observed at the electrode inputs. The sensing unit 200 may be configured to support unipolar (common reference) or bipolar inputs, individual channels can be disabled, and instrumentation settings (e.g. amplifier gain, filter cut-off frequencies, sampling rate) can be adjusted. The NIB 100 provides all control and configuration input through the low bandwidth configuration bus (line 131), the digitised recording output (representing the biopotential measured / obtained by a respective electrode) is transmitted through the high bandwidth data bus (line 132), and common referencing is achieved through the shared reference line 121. There is additionally an asynchronous blank input (line 134) to enable the sensing unit 200 to integrate effectively with the stimulation unit 500, i.e. to operate effectively during and after stimulation. Power supplies are additionally provided through the NIB 100; the sensing unit 200 would typically utilise the analogue core power supply line 111 and the digital power supply line 113.

[0124] Stimulation unit 500 - this may interface directly to electrodes, or indirectly to electrodes via a multiplexer unit 400. In alternative examples the stimulation unit 500 may be used to power (either directly or via the multiplexer) a transducer or another actuator or stimulation device, for example a light-emitting diode or laser diode for illuminating tissue, such as in the case of optogenetic stimulation. The stimulation unit 500 includes a single or multichannel stimulator that can generate charge-balanced, monophasic, biphasic, or triphasic stimuli that are typically current-controlled. The stimulation channels may or may not be galvanically isolated. The stimulation unit 500 may be configured to support monopolar, bipolar or multipolar stimulation configurations and stimulus profiles can be programmed (e.g. anodic and cathodic phase magnitude and pulse durations, interphasic delay, etc). The NIB 100 provides all control and configuration input through the low bandwidth configuration bus (line 131) and the stimulation output is driven onto the (e.g. four) analogue stimulus / actuation lines 122. There also exists an asynchronous trigger input (line 134) to allow for precise timing of stimulation, and asynchronous blank output (line 134) to flag when stimulation is active. Power supplies are additionally provided through the NIB 100; the stimulation unit 500 would typically utilise all power supplies (i.e. the analogue core power supply line 111 , the analogue high voltage power supply line 112, and the digital power supply line 113).

[0125] Electrode monitor unit 600 - this interfaces indirectly to electrodes via a multiplexer unit 400. The electrode monitor unit 600 can be used to observe whether there is residual charge on electrodes, to characterise electrodes or for patient safety diagnostics (i.e. to test continuity across leads). In alternative examples the electrode monitor unit 600 may be used to characterise the path across two electrodes, for example brain impedance; or, if connected to a transducer instead of electrodes, to characterise the transducer itself, e.g. diode characteristic or to measure a resistance (e.g. to determine temperature). Indeed, despite being referred to as an “electrode” monitor unit, the electrode monitor unit 600 is not limited to use with electrodes and can be used to characterise the impedance of other things in its path. Specifically, it may be able to measure brain impedance, or the impedance of a transducer (such as a light emitting diode, PN-junction diode, PIN diode, thermistor, etc). The electrode monitor unit 600 contains a current waveform generator, an instrumentation amplifier and an analogue-to-digital convertor (ADC). The electrode voltage may be measured across any two electrodes (via multiplexer 400), a direct current (DC) resistance measurement may be performed by injecting a small DC current and measuring the DC voltage, or an alternating current (AC) impedance measurement may be performed by driving a small AC current and measuring the AC voltage waveform. The impedance unit may be configured to define the measurement type (voltage, resistance or impedance), the measurement probe type (two-point, three-point or four-point), and stimulus parameters (current magnitude, DC pulse duration or AC frequency) and measurement parameters (voltage range, sampling rate). The NIB 100 provides all control and configuration input through the low bandwidth configuration bus (line 131), the digitised measurement output is transmitted through the high bandwidth data bus (line 132), and measurement probe connected via the stimulation / actuation lines 122 . Power supplies are additionally provided through the NIB; the electrode monitor unit 600 would typically utilise all power supplies (i.e. the analogue core power supply line 111 , the analogue high voltage power supply line 112, and the digital power supply line 113). unit 400 - this interfaces the stimulation unit 500 and / or the electrode monitor unit 600 to electrodes (e.g. electrode 410), and / or provides a passthrough with high voltage isolation to the sensing unit(s) 200. The multiplexer unit 400 contains a switch network to allow for the stimulator or electrode monitor I / Os to each connect to any electrode contact or other multiplexed sensing or stimulation devices. The NIB 100 provides all control and configuration input through the low bandwidth configuration bus (line 131). Power supplies are additionally provided through the NIB; the multiplexer unit 400 would typically utilise all power supplies (i.e. the analogue core power supply line 111 , the analogue high voltage power supply line 112, and the digital power supply line 113).

[0126] Power management unit (PMU) 800 - this internally generates supply voltages for different power domains. The power management unit 800 may be used to internally generate all power supplies from a single input supply. This may directly interface with a primary cell or rechargeable battery or take supply from the output of an external power management unit such as for wireless power transfer. The different power domains are all coupled through the NIB 100, also providing control and configuration input through the low bandwidth configuration bus (line 131). Furthermore, the power management unit 800 may ensure stable and appropriate power delivery to all other components in the chipset. It may include voltage regulators, DC to DC conversion and current sources to meet specific block requirements, as well as power-on reset circuits to ensure proper system startup. Additional features may include battery management systems (if applicable), dynamic path switching (for example, switching between wireless power and battery sources) and monitoring circuits for maintaining power integrity throughout operation.

[0127] Control unit 300 this controls the chipset, coordinating all synchronisation and data communication across the chipset via the NIB 100, providing a single port 310 to external devices (whether wired or wireless). The control unit 300 may be implemented as a dedicated digital ASIC, or as an embedded system (e.g. microcontroller, MCU), or by means of reconfigurable hardware (e.g. a field-programmable gate array, FPGA), for example.

[0128] Processing unit 700 this facilitates on-node data reduction for internal (i.e. within the chipset) or external communication, or real-time signal processing (e.g. feature extraction, biomarker detection, etc.) for direct stimulation or other output (e.g. to an actuator). The processing unit 700 may internally include volatile or non-volatile memory, or interface to an external memory (i.e. another unit). The NIB 100 provides all control and configuration input through the low bandwidth configuration bus (line 131), and data input through the high bandwidth data bus (line 132). The processing unit 700 may also retransmit data onto the high bandwidth data bus by effectively splitting the high bandwidth data bus 132 into two sections (as illustrated in Figure 9 and described below). In such a manner, the processing unit 700 may, for instance, be used to receive raw data (e.g. spike recordings) at a relatively high data bandwidth, process it to extract features (e.g. spike events), and retransmit feature data (e.g. spike timings) at lower data bandwidth. Such a strategy may be used to realise large scale systems (e.g. 100s or 1000s of recording channels). The processing unit 700 may be implemented as a dedicated digital ASIC, or as an embedded system (e.g. microcontroller, MCU), or by means of reconfigurable hardware (e.g. a field- programmable gate array, FPGA), for example. 1000 for storing various types of data essential to system function, including neural recording data, stimulation parameters, system configurations, and intermediate results generated during signal processing. This can be implemented using on-chip registers in an FPGA or ASIC for fast, low-latency access. For larger or more flexible storage needs, standalone SRAM may be used due to its speed and volatility, while DRAM can offer greater capacity if the neural implant’s space and power budgets allow for it. In other examples, the memory unit may be provided by a microcontroller having embedded memory (typically both non-volatile memory such as flash memory, and volatile memory such as SRAM).

[0129] Protection unit 900 - for safeguarding sensitive circuitry and interconnects from potentially damaging electrical events such as electrostatic discharge (ESD), current or voltage surges (e.g. as may be induced by magnetic resonance imaging, or through defibrillators or electrocautery / electrosurgery), and short circuits. This unit may integrate components such as clamp diodes, transient voltage suppression (TVS) diodes, and dedicated ESD protection cells. It can also include watchdog timers that reset the system in case of malfunctions, enhancing robustness and fault recovery capabilities.

[0130] Environmental sensing unit - for monitoring physical conditions around the neural implant to ensure the device operates safely and effectively within its intended environment. It typically includes temperature sensors to detect overheating, humidity sensors to verify the integrity of encapsulation materials, and may also feature magnetic field or light sensors if the implant is expected to interact with external electromagnetic stimuli or illumination. Alternatively the environmental sensing unit may be, or may include, an inertial sensor such as an accelerometer.

[0131] Bus switching unit (BSLI) 150 - for controlling communication between different functional modules or subsystems within the implant. This can isolate components during faults, manage multiple power or communication domains, and support transitions into low-power modes. Additionally, it may enable dynamic routing or reconfiguration of the data bus and facilitate interoperability between modules operating under different communication protocols.

[0132] Combining functions within a single unit: It is possible to combine the functions of units listed above into a single unit, provided the technology is compatible. Specific examples include combining different combinations of the multiplexer unit 400, electrode monitor 600 unit and stimulation unit 500. Also the processing unit 700 and control unit 300 may be combined into a single digital unit. Furthermore, two or more units may be combined in the form of an integrated circuit. Connecting units to the NIB Each unit that is connected to the NIB 100 should ideally have a unique identifier (e.g. an identification number or physical address). This may be provided through a non-volatile memory within each unit (i.e. pre-programmed) or electronic fuse, a randomly generated identifier (e.g. a physically-unclonable function), or through hardwired connections (e.g. bondwire jumpers, or laser-trimmed connections). Different units (depending on function) may utilise the NIB 100 in different ways; some units may utilise the entire bus (i.e. all lines), whereas other units may utilise a subset of the bus.

[0133] One example of implementing the bus switching unit and the control unit would be to split the bus into different bus types as shown in Figure 2. As shown, the bus switching unit 150 may connect one or more bus groups, from bus group 100.1 to group 100.N from the left side of the diagram, to the bus 100 on the right side simultaneously or in a time multiplexed manner. This would allow communication from the control unit 300 to other control units on the bus groups 100.1 to 100.N (such other control units are not shown in Figure 2). Specifically, this would allow commands to be broadcast to multiple buses and extensive networks of units to be built in various topologies such as mesh, star, tree and grid. In other examples, the BSU 150 could be integrated with other units during physical implementation and / or be programmable. In certain cases the bus switching unit 150 may advantageously be used to integrate multiple low speed buses onto a single high speed bus, or to synchronise across different clock domains.

[0134] Furthermore, as shown in Figure 2, different bus groups may have different numbers or configurations of electrical paths. As illustrated, group 100.1 has four electrical paths connected to the bus switching unit 150 whilst group 100.N has three electrical paths connected to the bus switching unit 150.

[0135] In a broad sense, the configuration of Figure 2 comprises a first electrical bus (bus group 100.1), a second electrical bus (depicted as bus group 100.N; there may be others) and a third electrical bus 100. The bus switching unit 150 is connected to the first, second and third electrical buses 100.1 , 100.N, 100. At least one of the first, second and third electrical buses may be an NIB carrying signals as discussed above. The bus switching unit 150 is operable to select which of the first and second electrical buses 100.1 , 100.N is in communication with the third electrical bus 100. In the illustrated example, the control unit 300 is connected to the third electrical bus 100. The control unit 300 may be used to control the operation of the bus switching unit 150, as well being able to communicate with other control units on the other buses as discussed above. The processing unit 700 is also connected to the third electrical bus 100, for receiving and / or transmitting data, and processing data, from whichever of the first and second electrical buses is in communication with the third electrical bus 100.

[0136] Applicable systems

[0137] The following are some examples of possible configurations of neural interface arrangements built around the NIB 100, for real-life applications:

[0138] A neuromonitoring system

[0139] Figure 3 illustrates an example of a neuromonitoring system 11 comprising two sensing units 200 and a control unit 300. Each sensing unit 200 is connected to a respective electrode 210. Each sensing unit 200 consists of signal conditioning circuitry to amplify and filter the incoming signals, followed by analogue to digital converter(s) for digitisation. Power is provided through the NIB 100 via the analogue core and digital core supplies (lines 111 and 113 of the power supply path 110). Each sensing unit is connected to the high speed data bus 132, and may off-load recording data on the high speed data bus 132 when enabled by the controller 300. On the other hand, the low speed configuration bus 131 is used for configuration of the sense channels. Electrode inputs, whether in a unipolar or bipolar configuration, are directly connected to the sensing units 200. However, for a unipolar configuration, the reference signal (line 121) is bidirectional. An electrode connected to a first sensing unit 200 (e.g. unit A) may be the reference of a second sensing unit 200 (e.g. unit B) by driving the shared reference line 121 . In this case, the reference of the second sensing unit (unit B) would be an input and the reference of the first sensing unit (unit A) would be an output. Driving the shared reference line 121 may involve directly connecting the electrode input to the reference line, or buffering the electrode voltage. The digital controller configures each sense unit through the low speed configuration bus 131 , and controls the data flow through the high speed data bus 132 using Master Clock (MCLK) and Master Receive Slave Transmit (MRST) signals, with MCLK and MRST both being provided via line 133. One possible implementation of data flow control is time division multiplexing through the use of the Chip Select (CS) lines in the high speed data bus 132.

[0140] A neuromodulation system

[0141] Figure 4 illustrates an example of a neuromodulation system 12 comprising a stimulation unit 500, a multiplexer unit 400, an electrode monitor unit 600, and a control unit 300. The primary function of the stimulation unit 500 is to transfer a set amount of charge to connected electrodes 410 through a voltage / current stimulus. Secondary functions of the stimulation unit 500 include (1) charge balancing the electrodes to ensure minimal DC currents flow through the electrodes, and (2) electrode / impedance monitoring, whereby using a small current the impedance of the electrodes or tissue (through a four-point kelvin measurement) is digitised. Power for the stimulation unit 500 is provided through the NIB 100 via the analogue core, analogue high voltage (or battery) and digital power supplies (lines 111 , 112 and 113). The multiplexer unit 400 routes the signal output by the stimulation channel(s) 122 to the electrode(s) 410 to be stimulated. Power for this unit would be provided through the interface via the analogue high voltage (or battery) and digital power supplies (lines 112 and 113). Configuration of both the stimulation unit 500 (for instance the operation, i.e. to stimulate or charge balance or monitor) and the multiplexer 400 is done through the low speed configuration bus 131. Data from the electrode monitor unit 600 is sent through the high speed data bus 112 as determined by the digital controller 300 using MCLK and MRST signals provided via line 133. To ensure precise timing, the stimulation unit 500 may be triggered by a trigger signal using the digital trigger input 134 present on the bus.

[0142] In alternative examples of neuromodulation systems, the stimulation unit 500 may be used to power (either directly or via the multiplexer) a transducer or another actuator or stimulation device, for example a light-emitting diode or laser diode for illuminating tissue, such as in the case of optogenetic stimulation. Accordingly, the units of such a system are able to interact with the nervous system through light or other means, rather than through electrical signals.

[0143] A bidirectional neural interface

[0144] Combining both of the above examples into a single system results in a bidirectional neural interface 13 comprising a sensing unit 200, a multiplexer / isolator unit 400, a stimulation unit 500, an electrode monitor unit 600, and a digital controller unit 300, as illustrated in Figure 5. Given the high voltages required by the stimulating operation, a change in the multiplexer is required such that when stimulation is present on an electrode (or other stimulation device), that same electrode (or other stimulation device) is isolated from the sense unit to avoid overvoltage. Here this is implemented as a separate multiplexer / isolator unit. Additionally, due to stimulation artefacts, during a stimulation event, the blanking signal present in the interface is asserted (via line 134) to keep the recording channels in reset. MCLK and MRST signals are both provided via line 133, and trigger signals are provided via line 134.

[0145] The stimulation unit block 500 shown in Figures 4 and 5 is responsible for delivering output signals based on commands from the control unit 300. It should be noted that, while direct electrical stimulation via electrodes may be a primary application, the present architecture is designed to be flexible and may be used to drive various types of actuators, not just electrical stimulators.

[0146] For example, the stimulation unit 500 may provide controlled current or voltage outputs suitable for a plurality of different transducers and / or actuators. For example, the stimulation unit 500 may provide signals suitable for:

[0147] • Optical Actuation (Optogenetics): Driving Light Emitting Diodes (LEDs) or laser diodes to deliver light pulses for optogenetic stimulation of genetically modified cells. An example of this is discussed in more detail below, in relation to Figure 6.

[0148] • Ultrasonic Actuation: Driving ultrasonic transducers.

[0149] • Thermal Actuation: Driving thermal elements for heating or cooling.

[0150] • Chemical / Chemogenetic Actuation: Controlling pumps, valves or electrically active materials valves for control of localized chemical delivery.

[0151] • Mechanical Actuation: actuation of motors or pumps to alter shape, pressure or force in a controlled manner.

[0152] In other words, the stimulation unit 500 may be electrically connected to a respective stimulation device substantially in contact with a targeted neural tissue. The stimulation unit 500 is configured to generate stimuli and to output the stimuli to the stimulation device via the bus 100. The stimulation device may be one of: an electrical actuator, an optical actuator, an ultrasonic actuator, a thermal actuator, a chemical / chemogenetic actuator, or a mechanical actuator.

[0153] Figure 6 shows an example of a bidirectional neural interface chipset 14 for recording electrical signals and stimulating the target neural tissue either electrically (via electrodes 410) or optically (e.g. by means of LEDs 420 or other suitable light sources such as laser diodes). The multiplexer unit 400 is operable to direct the stimulation current from the stimulation unit 500 to the electrodes 410, LEDs 420, or both for optogenetic neuromodulation. The optogenetics neural interface 14 may also have a stimulus monitoring unit 550 which monitors the currents flowing into the tissue and electrodes 410 as well as the voltages on the electrodes 410 and across the LEDs 420.

[0154] More generally, the stimulation unit 500 may be electrically connected via the bus 100 and the multiplexer unit 400 to a respective electrode 410 substantially in contact with a first targeted neural tissue, and to a respective stimulation device 420 (e.g. an LED or laser diode) substantially in contact with a second targeted neural tissue. The stimulation unit 500 is configured to generate a stimulation current and to output the stimulation current to one or more analogue lines 122 of the bus 100. The multiplexer unit 400 is configured to direct the stimulation current from said one or more analogue lines of the bus to the respective electrode 410 and / or to the respective stimulation device 420.

[0155] In essence, the stimulation unit 500 may act as a versatile driver stage, capable of interfacing with different actuator modalities connected via the NIB, depending on the specific application requirements. Similarly, the electrode connections, when routed to the sensing unit 200, may be used to detect analogue voltage signals from a variety of sensors such as chemical, electrical, current (via a resistor), mechanical pressure or strain, optical via a diode, etc.

[0156] In the example of the stimulation device 420 being an LED, although the LED is primarily an output device (for creating an optical output), by employing the stimulus monitoring unit 550 it also becomes possible to characterise the operation of the LED, for example to sense its temperature and thereby enable the LED to be used as a temperature sensor.

[0157] Online processing

[0158] With reference to Figure 7, another possible element in the system is a processing core 700 whose function is to receive and process incoming data from both the sensing unit(s) 200 and the stimulation unit 500. The processor would be connected to the high speed data bus 132 to obtain the data. It would also be connected to the low speed bus 131 for configuration. Once the data is processed by the processor 700, it may be passed to another unit (not shown) along the chain, through either the existing high speed data bus 132 (shared with the sensing and / or stimulation units) or an isolated bus 132.2 (not shared with the sensing and / or stimulation units) depending on the bandwidth available on the shared data bus 132. In this regard, Figure 7 provides an example of splitting part of the bus 100 (in this case, splitting the high speed data bus 132) into separate electrically- isolated parts, namely a first part 132.1 and a second part 132.2, by incorporating a discontinuity within the high speed data bus 132 to form the first and second parts 132.1 , 132.2. The other paths of the bus 100 remain undivided.

[0159] In other words, in this example the high speed digital line 132 incorporates a discontinuity, to form a first digital trace 132.1 and a second digital trace 132.2 that are electrically isolated from one another. The first digital trace 132.1 carries unprocessed data obtained by a subset of components (e.g. sensing units A and B) connected to the bus 100, to the processor 700, and the second digital trace 132.2 carries processed data from the processor 700 to one or more other components (e.g. another processor, not shown in Figure 7) connected to the bus 100.

[0160] Splitting the bus into multiple domains

[0161] Scaling control and data flow to many devices without scaling the number of lines on the bus is possible by splitting the bus along digital and analogue domains, where the function of a subgroup of devices on the bus can be contained within such a domain. Alternatively, isolating power domains may be required, for example, to isolate stimulation sources. Three specific examples are:

[0162] Analogue reference splitting, e.g. as illustrated in Figure 8, where the bus controls separate subgroups of analogue recording channels which are referenced to several independent reference signals 121.1 and 121.2, one for each subgroup of recording channels. This type of bus splitting enables subgroups of recording electrodes at specific locations in the body to be locally referenced. The local reference uses one of the recording electrodes in a subgroup.

[0163] In other words, in this example the first analogue line 121 incorporates a discontinuity, to form a first analogue trace 121.1 and a second analogue trace 121.2 that are electrically isolated from one another. The first analogue trace 121.1 carries a first reference signal to a first subset of components (e.g. sensing units A and B) connected to the bus 100, and the second analogue trace 121.2 carries a second reference signal to a second subset of components (e.g. sensing unit C and control unit 300) connected to the bus 100. Where possible, splitting the reference line (e.g. in the manner as described above) may be preferable to having multiple reference lines, in order to reduce the resulting line capacitances.

[0164] Digital data bus , e.g. as outlined above with reference to Figure 7, to enable scaling of the amount of data that can be recorded by a system by placing a processing node 700 at the junction between two high-speed data buses 132.1 , 132.2, with one side (bus 132.1) connected to a group of recording channels 200 sending raw data, and on the other side (bus 132.2) to a bus which may ferry compressed data from several recording subgroups. In this way multiple levels of processing and compression can be implemented in a pyramid structure to enable scaling of the bus to higher system-level data rates, or reducing the data transfer power consumption by reducing the data transfer clock frequency. At the highest level of the pyramid, there is a central system component controlling all peripheral buses. domains e.g. as illustrated in Figure 9, to implement floating stimulation sources allowing for concurrent independent stimulation. Truly isolated power supplies will also require all digital lines to be isolated, in addition to splitting all analogue lines. The only shared line would be the power input (e.g. battery input supply). One way of achieving such a configuration would be to use a specialised power management unit 800 that takes in the power input, internally generates galvanically isolated supplies (i.e. isolated versions of analogue core, analogue high voltage and digital core), and additionally provides galvanically isolated digital I / Os for the configuration and data buses and asynchronous lines. Each power domain would have completely independent analogue portions (e.g. achieved through splitting the reference line 121 and the stimulation line 122).

[0165] In other words, this essentially results in a first neural interface arrangement 16.1 and a second neural interface arrangement 16.2, galvanically isolated from one another but connected together via the power management unit 400. In particular, the bus of the first neural interface arrangement 16.1 is galvanically isolated from the bus of the second neural interface arrangement 16.2. Accordingly, the high speed digital line 132.1 of the first neural interface arrangement 16.1 is isolated from the high speed digital line 132.2 of the second neural interface arrangement 16.2. The low speed digital line 131.1 of the first neural interface arrangement 16.1 is isolated from the low speed digital line 131.2 of the second neural interface arrangement 16.2. The third and fourth digital electrical lines 133.1 / 134.1 of the first neural interface arrangement 16.1 are isolated from the third and fourth digital electrical lines 133.2 / 134.2 of the second neural interface arrangement 16.2. The analogue path 120.1 of the first neural interface arrangement 16.1 is isolated from the analogue path 120.2 of the second neural interface arrangement 16.2. The power management unit 400 supplies power to the first electrical path 110.1 of the first neural interface arrangement 16.1 , and to the first electrical path 110.2 of the second neural interface arrangement 16.2, whilst keeping the constituent lines of the electrical paths (i.e. the analogue core, analogue high voltage and digital core lines) isolated from one another.

[0166] Physical embodiments of the system using chipset approach

[0167] On the physical layer, the chipset can be implemented in different embodiments, including, but not limited to:

[0168] 1. Printed Circuit Board (PCB) chipset - each unit, connected using a PCB substrate, is comprised of either an individual standard semiconductor package (e.g. QFN - quad-flat no-leads, etc) or a set of discrete components which achieve equivalent functionality.

[0169] An example of such an arrangement is illustrated in Figure 10, in which each unit 21a, 21b of the chipset is connected to a PCB substrate 23. The units 21a, 21b are conventionally- packaged integrated circuits (chips) that are typically individually packaged. Solder connections 22 are made between the units 21a, 21 b and the top PCB interconnect layer of the PCB 23. The PCB 23 includes interconnect layers, e.g. 24a and 24b, which are typically made of copper. A first set of vias 25 extend from the units (e.g. unit 21a) into the PCB 23, to connect to respective interconnect layers. A second set of vias 26 extend from the respective interconnect layers to a bottom PCB interconnect layer 27. Accordingly, the units 21a, 21b are connected, by means of the vias 25, 26 and interconnect layers 24a, 24b, to the bottom PCB interconnect layer 27, from which connections can then be made to other components or circuitry.

[0170] Although Figure 10 has been described above as using a PCB substrate 23, in other examples the substrate 23 could be another substrate (e.g. a ceramic, or silicon interposer). In a more general sense, Figure 10 illustrates the concept of 2D / 2.5D integration of chips (i.e. a PCB with individual chips at a large scale, and / or a silicon substrate with chiplets at small scale). It will be appreciated that, in the examples of Figures 1 and 3-9, the units are primarily depicted and described as being discrete independent components, each being separately connected to the bus. However, this need not necessarily be the case. In particular, two or more of the units may collectively form a discrete group, wherein the units of the group collectively share a common set of connections to the bus. The units may be grouped by function, and thus each group may be termed a “function group”. A plurality of such groups or “function groups” may be provided. An example of such an arrangement is provided in Figure 11 , which shows a high-level example of a bidirectional neural interface chipset having three such function groups integrated on a printed circuit board 60. Figure 12 shows low-level detail of a corresponding system.

[0171] Referring to Figure 11 in more detail, the units are provided in three discrete groups 61 , 62, 63. Each group 61 , 62, 63 is responsible for a dedicated function, and may therefore be termed “function groups”: a first function group 61 for sensing, a second function group 62 for stimulation, and a third function group 63 for controlling, storing and processing data. In the illustrated example, the first function group 61 comprises a control unit 300 and a sensing unit 200. The second function group 62 comprises a protection unit 900, a multiplexer unit 400 connected to electrodes 410, a stimulation unit 500, and an electrode monitor unit 600. The third function group 63 comprises a control unit 300, a memory unit 1000 and a processor unit 700.

[0172] Each group of units (or “function group”) may be provided as a discrete integrated circuit, having a respective set of connections to the bus 100, serving all the constituent units of the group within the integrated circuit.

[0173] Thus, as illustrated in Figure 11 the connections to the bus 100 may be provided in a groupwise manner, to and from each integrated circuit, rather than in a unit-by-unit manner as in the examples of Figures 1 and 3-9.

[0174] Similarly to the examples described in relation to Figures 3 to 6, the NIB 100 of the example of Figure 11 comprises the following paths:

[0175] • a first path 110 for supplying power to the neural interface;

[0176] • a first analogue line 121 for providing a reference signal to the connected units, and

[0177] • one or more shared analogue lines 122 for sensing, stimulation and electrode monitoring; • a first (low speed; digital core (low voltage)) digital electrical line 131 for transmitting commands, control signals, and / or configuration signals between the connected units;

[0178] • a second (high speed) digital electrical line 132 for transmitting data outputs between the connected units; and

[0179] • a third digital electrical line 133 for supplying a global clock and / or a synchronisation signal to the connected units, and / or a fourth digital electrical line 134 for supplying asynchronous signals.

[0180] The NIB 100 of Figure 11 connects the three different function groups 61 , 62, 63 integrated on the circuit board 60, supplying the signals discussed above. The NIB 100 may be extended outside the circuit board 60, which may allow for further expansion of the bidirectional neural interface. For example, the NIB 100 may connected to a power management unit 800, for providing power to the groups served by the NIB 100. The power management unit 800 may generate different supply voltages for different power domains supplied to each unit as needed.

[0181] The following should also be noted:

[0182] • Data and configuration buses can be combined.

[0183] • There can be more than one data and configuration bus running at different speeds.

[0184] • The power bus 110 can include several different voltages.

[0185] • Single or multiple units can be included in separate integrated circuits in practical implementations.

[0186] • A unit can “listen to” multiple buses.

[0187] Turning now to Figure 12, this shows an illustrative low-level diagram of the components of the first, second and third groups (integrated circuits) 61 , 62, 63 integrated on a circuit board 60 via the NIB 100, and the interconnections between the components. More particularly, the proposed bus architecture interconnects three principal subsystems, which may each be provided as a respective integrated circuit, namely: the sensing circuit (or first function group) 61 , the stimulation circuit (or second function group) 62, and the system controller (or third function group) 63.

[0188] As described above, two types of digital buses 131 , 132 are employed: low-speed and highspeed buses (respectively), which not only transmit data but also carry configuration parameters to the respective subsystems. An additional set of digital buses 133 / 134 (designated as MCLK, MRST, TRIGGER, and BLANK) transmit asynchronous digital signals and are utilized for time-critical or event-driven communication.

[0189] The control unit 63 acts as the primary interface for external user interactions. It is responsible for interpreting user commands and relaying raw or processed data back to a user interface. The control unit 63 is interfaced with the high-speed, low-speed, and asynchronous buses by means of a bus switching unit (BSU) and a control block. The control block is designed to handle simple command execution autonomously, thereby conserving computational resources of the processor core for more complex processing tasks. The BSU enables synchronous data transfer to be accessible concurrently by both the control block and the processor core.

[0190] Upon receipt of a user command, the control block generates appropriate control signals and dispatches them across the appropriate bus pathways to the relevant target subsystems. For example, if a stimulation command is issued while a sensing operation is active, the control block will transmit a command to the stimulation circuitry via the low- speed digital bus 131 to initiate stimulation. Simultaneously, it will issue a command via the high-speed digital bus 132 to the sensing circuitry to suspend data acquisition. This event is logged by the processor core in its event memory. During stimulation, the stimulation circuitry 62 will transmit asynchronous status signals to both the sensing circuitry 61 and the system controller 63, enabling system-wide awareness and coordination.

[0191] As mentioned above, the control unit 63 of Figure 12 incorporates a bus switching unit. It will be appreciated that the setup of this bus switching unit is different from the setup of the bus switching unit 150 discussed above in relation to Figure 2. In particular, rather than being connected between multiple distinct NIBs as in the case of Figure 2, the bus switching unit of Figure 12 is connected to two digital electrical lines 131 , 132 of a single NIB 100 and is operable to select which of those two digital electrical lines 131 , 132 is in communication with the control block and processor core as illustrated. In other examples, such a bus switching unit may be connected to other electrical paths, lines or traces of the NIB 100, to route signals (or power) to or from those paths, lines or traces as required. Even though the examples of Figures 10 to 12 show multiple units integrated in a single circuit board 23, 60, this is not the only way the units can be integrated. One or more units may be integrated in separate circuit boards.

[0192] 2. System-in-Package (SiP) chipset - Alternatively to the example discussed in relation to Figures 10 to 12, the functional architecture comprising the sensing unit 61 , stimulation unit 62, and control unit 63 may be realized as a System-in-Package (SiP) configuration as shown in Figures 13A and 13B. In this implementation, discrete chiplets corresponding to each functional unit - namely a sensing chiplet 72, a stimulation chiplet 73 and a control chiplet 74 (e.g., an FPGA or ASIC) - are integrated onto a common substrate 71 using wirebond 78 or other microelectronic interconnection techniques. Vertical integration through chip stacking may also be employed, wherein two or more chiplets are mounted in a stacked configuration to minimize lateral footprint and enable enhanced interconnect density. The substrate may be implemented as a ball grid array (e.g., TFBGA) to facilitate external connectivity, e.g. via bump bonds 77. Electrical interconnects within the package replicate the bus architecture described previously, including high-speed and low-speed digital data buses, power distribution lines, and control signal lines (e.g., MCLK, MRST, TRIGGER, BLANK). This packaging approach enables a compact, modular, and potentially volumetrically optimized embodiment of the architecture, suitable for scalable and high- density implantable or wearable neurotechnology applications.

[0193] 3. Multi-chip Module (MCM) or System-on-Packaqe (SoP) chipset - each unit is mounted and connected as a bare die onto an interconnect substrate. The dies can be connected via standard bonding methods, e.g. wire bonding, flip chip bonding, etc. The substrate can be a multi-layer laminated PCB, based on a co-fired ceramic, or a thin-film interposer. A SoP is a specific type of MCM where the individual dies are referred to as chiplets, and the package substrate is typically a silicon or glass interposer with thin-film high pitch interconnects (although in other examples the substrate may be an organic substrate). This is also referred to as heterogeneous integration. Individual dies can be integrated laterally (i.e. 2D integration) or stacked vertically (i.e. 2.5D integration) depending on the connectivity required and space constraints.

[0194] Examples of such arrangements are shown in Figure 14. In example (a) the units, in the form of chips or chiplets 31a, 31 b, 31c, are connected laterally to an interconnect substrate (e.g. interposer) 33 by means of chip-to-chip bond connections 32, in some cases also using wirebonds 38. The interconnect substrate 33 includes thin-film interconnect layers 34. A first set of fine vias 35 extend from the units (e.g. unit 31a) into the substrate 33, to connect to respective interconnect layers. A second set of vias 36 (e.g. through silicon vias) extend through the substrate 33 from the respective interconnect layers 34 to respective backside connections (e.g. bumps) 37. Accordingly, the units 31a, 31b, 31c are connected, by means of the vias 35, 36 and interconnect layers 24a, 24b, to the backside connections 37, from which connections can then be made to other components or circuitry. In practice, the chips would typically be integrated at die level (unpackaged silicon), and the entire system would be packaged together as a single component.

[0195] In example (b) some vertical stacking is used to connect the units, in the form of chips or chiplets 31a, 31 b, 31c, 31d to an interconnect substrate (e.g. interposer) 33. Intermediate substrates 39 having through substrate vias (e.g. through silicon vias) 40 are used to connect units 31a and 31b to the substrate 33. Wirebonds 38 are used to connect unit 31c to unit 31 d, and to connect unit 31 d to the substrate 33. As above, the interconnect substrate 33 may include thin-film interconnect layers and vias (not shown) to connect the units 31a, 31b, 31c, 31 d to backside connections 37, from which connections can then be made to other components or circuitry. Again, in practice, the chiplets would typically be integrated at die level (unpackaged silicon), and the entire system would be packaged together as a single component.

[0196] Although Figure 14 illustrates 2D integration (individual chips connected) and 2.5D integration (individual chips bonded to a substrate to make a composite chip), the same principles could also be extended to 3D packaging whereby different chip substrates are fused / bonded together.

[0197] 4. System-on-Chip (SoC) chipset - as illustrated for example in Figure 15, the units that were previously described as being discrete individual units may be implemented as IP blocks 51 within the design of a single chip or integrated circuit 50. A key constraint is the various IP blocks 51 should all be designed within the same process technology. This is particularly suited to custom channel count systems that can be easily connected at block level with minimal redesign.

[0198] In the illustrated example, the IP blocks 51 are located within the front-end-of-line (FEOL)

[0199] 52 of the integrated circuit (chip) 50. Integrated circuit vias 53 and interconnection layers 54 are provided through the back-end-of-line (BEOL) 55 of the chip, to connect the IP blocks 51 to bondpads 56, from which connections can then be made to other components or circuitry.

[0200] Modifications and Alternatives

[0201] Detailed embodiments and some possible alternatives have been described above. As those skilled in the art will appreciate, a number of modifications and further alternatives can be made to the above embodiments whilst still benefiting from the inventions embodied therein. It will therefore be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the scope of the claims appended hereto.

[0202] For example, even though the bus architecture is described above and depicted as being interconnected with functional blocks like “Sensing unit”, “Stimulation unit”, etc., linked by signal and power lines, these are by no means the only components that may be connected to or incorporated in the bus architecture. The bus architecture may also incorporate (or be connected to) various passive electronic components which, whilst not explicitly shown in the high-level block diagrams, are often necessary for practical implementation. These passive electronic components may include resistors, capacitors, and inductors placed strategically within the bus and may have several purposes:

[0203] • Signal Filtering: To remove unwanted frequency components, such as filtering out high-frequency noise from sensor signals or blocking DC offsets before amplification or processing.

[0204] • Potential Dividers: To scale down voltage levels between different chips or modules that operate at different voltage potentials.

[0205] • Impedance Matching: To optimise signal transfer and minimise reflections between different parts of the system, e.g. for high-frequency signals.

[0206] The passive electronic components may either be individual discrete components or networks of components that achieve the required goal, or custom chips that integrate multiple passive components (e.g. multiple capacitors) within a single substrate to avoid integrating multiple discrete components. Furthermore, the overall system may include dedicated chips or more complex elements connected to the bus. These may include:

[0207] • Power Management Integrated Circuits (PMICs): These chips manage power distribution, voltage regulation, and battery charging. • Associated components like batteries (for energy storage) and capacitors (for smoothing power delivery and handling transient current demands) may also be connected to the power lines within the bus architecture.

[0208] • Devices for protection from electrostatic discharge (ESD) or other high voltage events such as defibrillation or electrocautery.

[0209] • Switches for the connection or disconnection of system elements.

[0210] Even though in the examples above, each signal is transmitted to the units in individual lines, this may not always be the case. For example, the transmission of data and configuration signals may be carried out by a single common line in the NIB. Alternatively, there may be more than one signal line that transmits both data and configuration signals between units which run at different speeds. The NIB may also have multiple power lines which can transmit different voltages to the units.

[0211] Also, the above examples generally employ a single NIB, but there may be more than one NIB transmitting signals to at least one unit within the chipset. In other words, each unit may listen to multiple NIBs.

[0212] Furthermore, in the examples described above the bus connections are represented as wired connections, but this is by no means essential. For example, one or more of the bus connections may be wireless. In such systems, different bus types such as the “high speed data bus” and “low speed configuration bus” may be set at different carrier frequencies. For example, the high speed data bus may be set at a MHz carrier frequency whilst the low speed configuration bus may be set at a kHz carrier frequency.

[0213] References

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[0216] [4] E. Musk, Neuralink, “An Integrated Brain-Machine Interface Platform With Thousands of Channels”, J Med Internet Res 2019; 21 (10):e16194, doi: 10.2196 / 16194

[0217] [5] M. Cracchiolo et al., “Bioelectronic medicine for the autonomic nervous system: clinical applications and perspectives”, J. Neural Eng. 18 (2021) 041002, doi 10.1088 / 1741- 2552 / abe6b9

[0218] [6] A. Rapeaux et al., “An HFAC block-capable and module-extendable 4-channel stimulator for acute neurophysiology”, J. Neural Eng. 17 (2020) 046013, doi 10.1088 / 1741- 2552 / ab947a

[0219] [7] S. Martinez et al., “Trends in Volumetric-Energy Efficiency of Implantable Neurostimulators: A Review From a Circuits and Systems Perspective”, IEEE Transactions on Biomedical Circuits and Systems, vol. 17, no. 1 , pp. 2-20, Feb. 2023, doi: 10.1109 / TBCAS.2022.3228895

[0220] [8] S. Stanslaski et al., “A Chronically Implantable Neural Coprocessor for Investigating the Treatment of Neurological Disorders”, IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 6, pp. 1230-1245, Dec. 2018, doi: 10.1109 / TBCAS.2018.2880148

[0221] [9] A. Zhou et al., “A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates”, Nat Biomed Eng 3, 15-26 (2019). doi 10.1038 / s41551-018-0323-x

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Claims

CLAIMS1. An electrical bus for a neural interface arrangement, the bus comprising: a first electrical path for suppling electrical power to units of a chipset connected to the bus in use; a second electrical path for carrying analogue signals between said units; and a third electrical path for carrying digital signals between said units.

2. The electrical bus according to claim 1 , wherein the first electrical path comprises: an analogue core power line; an analogue high voltage power line; and a digital core power line.

3. The electrical bus according to claim 1 or claim 2, wherein the second electrical path comprises: a first analogue line for providing a reference signal to said units; and one or more analogue lines for: transmitting stimulation or actuation signals to said units, and / or to one or more electrodes or other stimulation devices connected to the bus; and / or monitoring the status of one or more electrodes connected to the bus.

4. The electrical bus according to any preceding claim, wherein the third electrical path comprises: a first digital line for transmitting commands, control signals, and / or configuration signals between said units; and a second digital line for transmitting data outputs between said units.

5. The electrical bus according to any preceding claim, wherein the third electrical path comprises: a common digital line for transmitting commands, control signals, and / or configuration signals between said units, and for transmitting data outputs between said units.

6. The electrical bus according to claim 4 or claim 5, wherein the third electrical path further comprises:a third digital electrical line for supplying a global clock and / or a synchronisation signal to said units.

7. The electrical bus according to any of claims 4 to 6, wherein the third electrical path further comprises: a fourth digital electrical line for supplying an asynchronous signal, such as an asynchronous trigger and / or a blanking signal, to said units.

8. The electrical bus according to any preceding claim, wherein at least one path or line incorporates a discontinuity, to divide the path or line into parts that are electrically isolated from one another.

9. The electrical bus according to claim 8 when dependent on claim 4, wherein the second digital line incorporates a discontinuity, to form a first digital trace and a second digital trace that are electrically isolated from one another; the first digital trace is for carrying unprocessed data obtained by a subset of components connected to the bus; and the second digital trace is for carrying processed data to one or more other components connected to the bus.

10. The electrical bus according to claim 8 when dependent on claim 3, wherein the first analogue line incorporates a discontinuity, to form a first analogue trace and a second analogue trace that are electrically isolated from one another; the first analogue trace is for carrying a first reference signal to a first subset of components connected to the bus; and the second analogue trace is for carrying a second reference signal to a second subset of components connected to the bus.

11. A neural interface arrangement comprising: the electrical bus according to any preceding claim; at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit connected to the bus, wherein each sensing unit or stimulation unit is electrically connected to a respective electrode or to another sensing or stimulation device; and a control unit connected to the bus, for controlling operation of the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit via the bus, or forcontrolling signal flow to or from the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit via the bus.

12. The neural interface arrangement according to claim 11 , having more than one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit connected along the bus and sharing at least some of the paths of the bus.

13. The neural interface arrangement according to claim 11 or claim 12 when dependent on claim 4, wherein the first digital line of the bus is configured to transmit commands, control signals, and / or configuration signals from the control unit to the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit.

14. The neural interface arrangement according to any of claims 11 to 13 when dependent on claim 4, wherein the neural interface arrangement comprises at least one sensing unit configured to output a signal representing a biopotential measured / obtained by a respective electrode to the second digital line of the bus when enabled by the control unit.

15. The neural interface arrangement according to any of claims 11 to 14 when dependent on claim 3, wherein the neural interface arrangement comprises two or more sensing units; and the first analogue line of the bus is configured to supply a common reference signal to said sensing units.

16. The neural interface arrangement according to claim 15, wherein a first sensing unit is configured to provide the common reference signal to another sensing unit via the first analogue line.

17. The neural interface arrangement according to any of claims 11 to 16 when dependent on claim 3, wherein the neural interface arrangement comprises at least one stimulation unit configured to generate a stimulation signal and to output the stimulation signal to one or more electrodes or other stimulation devices, or to a multiplexer unit to which electrodes or other stimulation devices are connected, via one of said one or more analogue lines of the bus when enabled by the control unit.18 The neural interface arrangement according to claim 17 when dependent on claim 7, wherein the control unit is configured to output an asynchronous trigger to the fourth digital electrical line of the bus, to trigger the at least one stimulation unit to generate and output the stimulation signal.

19. The neural interface arrangement according to claim 17 or claim 18 when dependent on claim 7, wherein the control unit is configured to output a blanking signal to the at least one sensing unit via the fourth digital electrical line of the bus.

20. The neural interface arrangement according to any of claims 11 to 19 when dependent on claim 3 and claim 4, further comprising: a multiplexer unit to which at least two electrodes or other sensing or stimulation devices are connected; and an electrode monitor unit configured to monitor, via the multiplexer unit, whether there is residual charge on electrodes, to characterise electrodes, to measure impedance, and / or to test continuity across leads; wherein said one or more analogue lines of the bus are configured to transmit measurements obtained by electrodes to the electrode monitor unit; and the electrode monitor unit is configured to output digitised measurements to the control unit via the second digital line of the bus.

21. The neural interface arrangement according to any of claims 11 to 20, further comprising a processing unit configured to: receive data transmitted by the bus from the sensing unit, stimulation unit, or electrode monitoring unit; process the received data; and output processed data to the bus.

22. The neural interface arrangement according to claim 12, comprising: a plurality of electrodes for measuring biopotential signals generated by target neural tissue; and a respective plurality of sensing units, each sensing unit being electrically connected to a respective one of said electrodes, wherein each sensing unit comprisesa recording system configured to record biopotentials input by the respective electrode; and an analogue-to-digital converter configured to digitise the recorded biopotentials; and wherein each sensing unit is configured to output the recorded biopotentials to the third electrical path of the bus when enabled by the control unit.

23. The neural interface arrangement according to claim 22 when dependent on claim 4, wherein each sensing unit is configured to output the recorded biopotentials to the second digital line, which transmits the recorded biopotentials to the control unit.

24. The neural interface arrangement according to claim 22 or claim 23, wherein the bus is configured to transmit control and / or configuration signals to said sensing units from the control unit.

25. The neural interface arrangement according to claim 24 when dependent on claim 4, wherein the first digital line is configured to transmit said control and / or configuration signals to said sensing units.

26. The neural interface arrangement according to claim 24 or claim 25, wherein the configuration signals configure each sensing unit to: support unipolar and / or bipolar biopotentials input by said electrodes; enable and / or disable channels from the neural recording system; and / or adjust instrumentation settings.

27. The neural interface arrangement according to any of claims 22 to 26, comprising a first sensing unit electrically connected to a first electrode; and a second sensing unit electrically connected to a second electrode; wherein said electrodes input unipolar biopotentials to the sensing unit; and the first electrode connected to the first sensing unit provides a reference signal to the second sensing unit via the bus.

28. The neural interface arrangement according to claim 27 when dependent on claim3, wherein the first analogue line of the bus is configured to transmit the reference signal from the first sensing unit to the second sensing unit.

29. The neural interface arrangement according to any of claims 22 to 28, wherein the control unit is configured to cause each sensing unit to output the recorded biopotentials to the bus using time division multiplexing.

30. The neural interface arrangement according to claim 11 , comprising: at least one stimulation unit electrically connected to a respective electrode substantially in contact with a targeted neural tissue; wherein the at least one stimulation unit is configured to generate charge-balanced stimuli and to output the stimuli to the respective electrode via the bus.

31. The neural interface arrangement according to claim 30, further comprising a multiplexer unit configured to route the stimuli transmitted by the bus to said electrode.

32. The neural interface arrangement according to claim 30 or claim 31 when dependent on claim 3, wherein the or each stimulation unit is configured to output the stimuli to said one or more analogue lines of the bus.

33. The neural interface arrangement according to any of claims 30 to 32, further comprising an electrode monitoring unit configured to: measure potential difference, direct current resistance, and / or alternating current impedance between at least two electrodes or other sensing or stimulation devices; and output a digitised measurement to the bus when enabled by the control unit.

34. The neural interface arrangement according to claim 33 when dependent on claim4, wherein the electrode monitoring unit is configured to output the digitised measurement to the second digital line of the bus.

35. The neural interface arrangement according to claim 11 , comprising: at least one stimulation unit electrically connected to a respective stimulation device substantially in contact with a targeted neural tissue; whereinthe at least one stimulation unit is configured to generate stimuli and to output the stimuli to the stimulation device via the bus.

36. The neural interface arrangement according to claim 35, wherein the stimulation device is one of: an electrical actuator, an optical actuator, an ultrasonic actuator, a thermal actuator, a chemical / chemogenetic actuator, or a mechanical actuator.

37. The neural interface arrangement according to claim 11 , comprising: at least one stimulation unit electrically connected via the bus to a respective electrode substantially in contact with a first targeted neural tissue, and to a respective stimulation device substantially in contact with a second targeted neural tissue, the at least one stimulation unit being configured to generate a stimulation current; wherein the stimulation unit is configured to output the stimulation current to said one or more analogue lines of the bus; and the multiplexer unit is configured to direct the stimulation current from said one or more analogue lines of the bus to the respective electrode and / or to the respective stimulation device.

38. The neural interface arrangement according to claim 37, wherein the stimulation device is an actuator or transducer such as a light source.

39. The neural interface arrangement according to claim 37 or claim 38, further comprising: a stimulation monitoring unit configured to monitor at least one of: currents flowing into the target tissue and / or into the respective electrode, and / or voltages applied to the respective electrode and / or applied across the stimulation device.

40. The neural interface arrangement according to any of claims 31 to 39, wherein the bus is configured to transmit control signals and configuration signals from the control unit to the stimulation unit, multiplexer unit, and / or electrode monitoring unit.

41. The neural interface arrangement according to claim 40 when dependent on claim 4, wherein the first digital line of the bus is configured to transmit said control and configuration signals to said at least one stimulation unit, multiplexer unit, and / or electrode monitoring unit.

42. The neural interface arrangement according to claim 40 or claim 41 , wherein the configuration signals configure the at least one stimulation unit to generate monophasic, biphasic, or triphasic stimuli.

43. The neural interface arrangement according to any of claims 40 to 42, wherein the configuration signals configure the least one stimulation unit to generate monopolar, bipolar or multipolar stimulation.

44. The neural interface arrangement according to any of claims 40 to 43 when dependent on claim 33 or claim 34, wherein the configuration signals configure the electrode monitoring unit according to a measurement type, a measurement probe type, stimulus parameters, and / or measurement parameters.

45. The neural interface arrangement according to any of claims 30 to 44 when dependent on claim 7, wherein the controller unit is configured to output an asynchronous trigger to the fourth digital electrical line of the bus which triggers the at least one stimulation unit to generate and output the stimulation signal.

46. The neural interface arrangement according to any of claims 11 to 45, wherein the first electrical path of the bus is configured to carry at least one voltage required to power the at least one sensing unit, stimulation unit, multiplexer unit or electrode monitoring unit.

47. The neural interface arrangement according to any of claims 11 to 46, wherein said control unit is connected to an external device and is configured to control the flow of data to the external device.

48. The neural interface arrangement according to any of claims 11 to 47, wherein the neural interface arrangement comprises at least one memory unit configured to store data; wherein the data includes one or more of: neural recording data, stimulation parameters, system configurations, and / or intermediate results generated during signal processing.

49. The neural interface arrangement according to any of claims 11 to 48, wherein the neural interface arrangement comprises at least one environmental sensing unit configured to monitor physical conditions around the neural implant.

50. The neural interface arrangement according to any of claims 11 to 49, wherein the neural interface arrangement comprises at least one protection unit configured to safeguard sensitive circuitry and interconnects from potentially damaging electrical events.51 . The neural interface arrangement according to any of claims 11 to 50, wherein two or more of the units collectively form a group, wherein the units of the group collectively share a common set of connections to the bus.

52. The neural interface arrangement according to claim 51 , wherein the group is formed as an integrated circuit.

53. The neural interface arrangement according to claim 51 or 52, wherein the group, and one or more other such groups, are integrated on a printed circuit board.

54. The neural interface arrangement according any of claims 51 to 53, having two or more such groups connected to a power management unit via the electrical bus.

55. The neural interface arrangement according to any of claims 11 to 51 , wherein each unit comprises an individual standard semiconductor package or a set of discrete components, the units being connected via the bus.

56. The neural interface arrangement according to claim 55, wherein the bus is a PCB substrate.

57. The neural interface arrangement according to claim 55 or claim 56, wherein the bus has multiple layers connected by vias or interconnects.

58. The neural interface arrangement according to any of claims 11 to 54, in the form of a system-in-package chipset.

59. The neural interface arrangement according to any of claims 11 to 54, wherein each unit is connected as a bare die onto an interconnect substrate, in the form of a multi-chip module or a system-on-package chipset.

60. The neural interface arrangement according to any of claims 11 to 54, wherein the units are in the form of IP blocks within an integrated circuit.

61. A system comprising: a first neural interface arrangement according to any of claims 11 to 50; a second neural interface arrangement according to any of claims 11 to 50; and a power management unit connected to the first electrical path of the first neural interface arrangement, and to the first electrical path of the second neural interface arrangement.

62. The system according to claim 61 , wherein the bus of the first neural interface arrangement is galvanically isolated from the bus of the second neural interface arrangement.

63. A system comprising: a first electrical bus; a second electrical bus; a third electrical bus; and a bus switching unit to which the first, second and third electrical buses are connected; wherein at least one of the first, second and third electrical buses is an electrical bus according to any of claims 1 to 10; and wherein the bus switching unit is operable to select which of the first and second electrical buses is in communication with the third electrical bus.

64. The system according to claim 63, further comprising a control unit connected to the third electrical bus, for controlling the operation of the bus switching unit and / or for communicating with other control units connected to the first and / or second electrical buses.

65. The system according to claim 63 or 64, further comprising a processing unit connected to the third electrical bus, for receiving and / or transmitting data, and processingdata, from whichever of the first and second electrical buses is in communication with the third electrical bus.

66. A system comprising: an electrical bus according to any of claims 1 to 10; at least one control block; and a bus switching unit; wherein the bus switching unit is connected to at least two electrical paths, lines or traces of the electrical bus and to the at least one control block, and is operable to select which of the at least two electrical paths, lines or traces of the electrical bus is in communication with the control block.

67. The system according to claim 66, wherein the at least one control block is configured to execute commands autonomously.

68. A method of supplying electrical power to components of a neural interface arrangement, and of carrying analogue signals and digital signals between said components, using an electrical bus according to any of claims 1 to 10.

69. A method of supplying electrical power to components of a neural interface arrangement, and of carrying analogue signals and digital signals between said components, wherein the neural interface arrangement is as claimed in any of claims 11 to 60.

70. A method of forming a neural interface arrangement, the method comprising: defining a set of units that are compatible with one another; selecting a plurality of units from said set; and connecting the selected units to an electrical bus; wherein the units of said set include one or more of: a sensing unit, a stimulation unit, a multiplexer unit, an electrode monitoring unit, a control unit, a power management unit, and a processing unit.71 . The method according to claim 70, wherein the electrical bus is according to any of claims 1 to 10, or wherein the neural interface arrangement is according to any of claims 11 to 60.

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