Memory device and electronic apparatus

Abstract

The present invention shortens the time required for reading. A memory device includes a memory cell array, a plurality of read circuits, and a memory control unit. The memory cell array is configured by a two-dimensional matrix arrangement of memory cells that include: a volatile storage unit that stores data by using a latch circuit; and a nonvolatile storage unit that stores data by using a variable resistance element. The read circuits are each arranged for respective columns of the memory cell array and read data from the volatile storage part of the memory cells included in the respective columns. The memory control unit controls writing and reading of data in the volatile storage unit of the memory cell.

Description

Memory device and electronic device

[0001] The present disclosure relates to memory devices and electronic devices.

[0002] Non-volatile SRAM (NVSRAM: Non-Volatile RAM) is a type of static random access memory (SRAM) that adds a non-volatile element to the memory cell. While normal SRAM loses data when power is turned off, NVSRAM stores data in the non-volatile element, allowing it to retain data even when power is turned off. Therefore, NVSRAM can perform power gating of the SRAM without backing up data to external memory, thereby reducing power consumption. Furthermore, because the memory cell contains a non-volatile element, data can be restored from the non-volatile element to the SRAM in one clock cycle. This allows for immediate system recovery. Furthermore, during normal operation, NVSRAM achieves write and read speeds similar to those of SRAM.

[0003] As such an NVSRAM, a nonvolatile memory having a memory cell array in which memory cells each having a volatile memory section similar to an SRAM and a nonvolatile memory section having nonvolatile elements are arranged in a matrix has been proposed (see, for example, Patent Document 1). In this nonvolatile memory, as with a general SRAM, writing and reading of data to and from the volatile memory section of the memory cell array is performed from peripheral circuits via bit lines. When reading, data from memory cells in a selected column of the memory cell array is read by a read circuit such as a sense amplifier.

[0004] JP 2013-125567 A

[0005] However, the above-described conventional technology has a problem in that it takes a long time to store data from a volatile memory unit in a nonvolatile memory unit. In the store, a process is performed in which data from the volatile memory unit is read and written to nonvolatile elements in the nonvolatile memory unit. A verify step is required to determine whether the write was successful. However, in the above-described conventional technology, the data is read for each column of the memory cell array during the verify step, which results in a problem in that it takes a long time to store data in word units.

[0006] Therefore, the present disclosure proposes a memory device that reduces the time required for reading, and an electronic device that includes the memory device.

[0007] The memory device disclosed herein includes a memory cell array configured with memory cells arranged in a two-dimensional matrix, each memory cell having a volatile memory section that stores data using a latch circuit and a non-volatile memory section that stores data using a variable resistance element, a plurality of read circuits arranged in each column of the memory cell array and that read data from the volatile memory sections of the memory cells included in that column, and a memory control section that controls the writing and reading of data in the volatile memory sections of the memory cells.

[0008] 1 is a diagram illustrating a configuration example of a memory device according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating a configuration example of a memory cell array according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a configuration example of a memory cell according to the first embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of an operation of the memory device 1 according to the first embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of an operation of the memory device 1 according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a configuration of a read circuit according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of an operation of the read circuit according to the first embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a configuration of a nonvolatile memory drive circuit according to the first embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of writing and reading of a volatile memory according to the first embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example of reading of a volatile memory according to the first embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of restoring according to the first embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of storing according to the first embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of storing according to a conventional nonvolatile memory. FIG. 14 is a diagram illustrating an example of storing according to a memory device according to the first embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example of storing according to a memory device according to the first embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example of storing according to a memory device according to the first embodiment of the present disclosure. Fig. 1 is a diagram showing another configuration example of a memory cell array according to a second embodiment of the present disclosure; Fig. 2 is a diagram showing a configuration example of a memory cell according to a second embodiment of the present disclosure; Fig. 3 is a diagram showing a configuration example of a memory cell according to a second embodiment of the present disclosure; Fig. 4 is a diagram showing a configuration example of a memory system to which the technology according to the present disclosure can be applied;

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. 1. First embodiment 2. Second embodiment 3. Memory system configuration

[0010] 1 is a diagram showing an example of the configuration of a memory device according to a first embodiment of the present disclosure. The figure is a block diagram showing an example of the configuration of a memory device 1. The memory device 1 is an NVSRAM including memory cells having a volatile storage unit and a nonvolatile storage unit.

[0011] The memory device 1 includes a memory cell array 10, a nonvolatile memory control unit (NV Control) 20, a read circuit (NV Peri.) 30, a word driver (Word Driver) 40, and a pre-charge unit (Pre-charge) 50. The memory device 1 further includes a column switch 60, a volatile memory read circuit (SRAM Peri.) 70, and a volatile memory control unit (SRAM Control & Decoder) 80.

[0012] Furthermore, the memory device 1 is wired with signal lines CK, CE, WE, A[0:y], D[0:x], Q[0:x], GLPG, NVINI, NVCE, GSR1, GSR2, and CTRL. These signal lines are used to communicate with the memory device control unit 2, which will be described later in FIG. 20. The signal line CK transmits a clock signal. The signal line CE transmits an enable signal. The signal line WE transmits a write signal. The signal line A[0:y] transmits an address. The signal line D[0:x] transmits write data. The signal line Q[0:x] transmits read data. Signal lines GLPG, NVINI, NVCE, GSR1, GSR2, and CTRL are signal lines that transmit control signals for the nonvolatile storage unit (nonvolatile storage unit 120).

[0013] The memory cell array 10 is configured by arranging memory cells (memory cells 100) each including a volatile memory section (volatile memory section 110) and a nonvolatile memory section (nonvolatile memory section 120) in a two-dimensional matrix. The volatile memory section 110 stores data using a latch circuit, similar to an SRAM. The nonvolatile memory section 120 stores data using a variable resistance element. Details of the configuration of the memory cells 100 will be described later.

[0014] The nonvolatile memory control unit 20 controls the nonvolatile memory unit 120 of the memory cell 100 .

[0015] The read circuit 30 reads data from the volatile storage unit 110 of the memory cell 100. The read circuit 30 is arranged for each column of the memory cell array 10.

[0016] The word driver 40 outputs a control signal to the memory cells 100 arranged in a row of the memory cell array 10. The word driver 40 is arranged for each row of the memory cell array 10.

[0017] The pre-charging section 50 pre-charges the bit lines of the memory cells 100 during writing.

[0018] The column switching unit 60 selects a specific column of the memory cell array 10. The column switching unit 60 is an example of a "selection unit" in the present disclosure.

[0019] The volatile memory section read circuit 70 writes and reads data to and from the volatile memory section 110 of the memory cell 100 .

[0020] The volatile memory control unit 80 controls the volatile memory unit 110 of the memory cell 100 .

[0021] 1 shows an example of a memory cell array 10 divided into multiple regions in the column direction, with a readout circuit 30, a pre-charging unit 50, a column switching unit 60, and a volatile memory readout circuit 70 arranged in each region.

[0022] The nonvolatile memory control unit 20 and the volatile memory control unit 80 are examples of the "memory control unit" of the present disclosure.

[0023] [Configuration of Memory Cell Array] FIG. 2 is a diagram showing an example configuration of a memory cell array according to the first embodiment of the present disclosure. This diagram is a block diagram showing an example configuration of a memory cell array 10. The memory cell array 10 in this diagram corresponds to one area described in FIG. 1 . This diagram also shows a read circuit 30, a pre-charging unit 50, a column switching unit 60, and a volatile memory read circuit 70. The read circuit 30 includes a non-volatile memory control circuit 31 and a sense amplifier 32. The volatile memory read circuit 70 includes a pre-charging unit 71, a sense amplifier 72, a write drive unit 73, and an I / O control unit 74.

[0024] As described above, the nonvolatile memory control circuit 31, sense amplifier 32, and pre-charging unit 50 that constitute the read circuit 30 are arranged for each column of the memory cell array 10. Common bit lines (bit lines BL and bit lines BLB) are wired to the nonvolatile memory control circuit 31, sense amplifier 32, pre-charging unit 50, and the multiple memory cells 100 arranged in the column. By the action of the read circuit 30 arranged for each column, store and restore processes, which are processes related to the nonvolatile memory unit 120, can be performed simultaneously on the multiple memory cells 100 in a specific row. The dashed lines in Figure 2 represent the memory cells 100 that are the target of store and restore.

[0025] One volatile memory read circuit 70 is arranged for each of the columns of the memory cell array 10 in Fig. 2. A pre-charging unit 71, a sense amplifier 72, and a write drive unit 73 of the volatile memory read circuit 70 are connected to bit lines (bit lines GBL and GBLB). Signals of the bit lines BL and BLB of the column selected by the column switching unit 60 are transmitted to the bit lines GBL and GBLB. The sense amplifier 72 is an example of a "second sense amplifier" in the present disclosure.

[0026] As described above, the column switching unit 60 selects a column of the memory cell array 10. The column switching unit 60 can select a column by switching the bit lines BL and BLB of each column of the memory cell array 10 and connecting them to the bit lines GBL and GBLB.

[0027] The volatile memory read circuit 70 writes to and reads from the volatile memory units 110 of the memory cells 100 in the column selected by the column switching unit 60. When writing, the write drive unit 73 writes to the volatile memory units 110 of the memory cells 100 in the column selected as described above. When reading, data from the volatile memory units 110 of the memory cells 100 in the column selected as described above is read via the sense amplifier 72. The dashed dotted lines in Figure 2 represent the memory cells 100 that are the target of writing and reading.

[0028] 3 is a diagram showing an example of the configuration of a memory cell according to the first embodiment of the present disclosure. The figure is a circuit diagram showing an example of the configuration of a memory cell 100. The figure also shows a nonvolatile storage unit control circuit 31, a sense amplifier 32, a pre-charging unit 50, a column switching unit 60, a pre-charging unit 71, a sense amplifier 72, a write driver 73, and an I / O controller 74.

[0029] The memory cell 100 includes a volatile memory unit 110, a nonvolatile memory unit 120, and MOS transistors 131 and 132. The MOS transistors 131 and 132 connect the volatile memory unit 110 and the nonvolatile memory unit 120. The gates of the MOS transistors 131 and 132 are connected to a signal line SR1.

[0030] The volatile memory unit 110 includes inverter gates 114 and 115 and MOS transistors 111 to 113. The inverter gate 114 and the inverter gate 115 have their input terminals connected to their output terminals to form a latch circuit. This latch circuit performs storage. This latch circuit is connected to a bit line via a MOS transistor 111 and a MOS transistor 112. The MOS transistor 111 is disposed between the latch circuit and the bit line BL. The MOS transistor 112 is disposed between the latch circuit and the bit line BLB. The MOS transistor 113 is a transistor that controls the supply of power to the inverter gate 114 and the inverter gate 115.

[0031] The nonvolatile memory unit 120 includes variable resistance elements 123 and 124 and MOS transistors 121 and 122. The variable resistance elements 123 and 124 are elements that transition between a high resistance state and a low resistance state. One of the variable resistance elements 123 and 124 is in a high resistance state, and the other is in a low resistance state. Data is stored based on which of the variable resistance elements 123 and 124 is in the high resistance state. The variable resistance elements 123 and 124 are connected to a bit line via the MOS transistor 121. The MOS transistor 121 is arranged between the variable resistance element 123 and the bit line BL. The MOS transistor 122 is arranged between the variable resistance element 124 and the bit line BLB.

[0032] The column switching unit 60 includes an analog switch circuit arranged for each bit line BL and bit line BLB. The MOS transistors 61 and 62 and the inverting gate 63 in FIG. 3 constitute the analog switch circuit.

[0033] [Operation of Memory Device] FIG. 4A is a diagram showing an example of the operation of the memory device 1 according to the first embodiment of the present disclosure. The figure is a truth table showing an example of the operation of the memory device 1. In the figure, "SRAM Read" represents reading from the volatile storage unit 110. "SRAM Write" represents writing to the volatile storage unit 110. "NV Read" is an operation in which the read circuit 30 reads data from the volatile storage unit 110. "NV Restore" is a restore operation in which data stored in the non-volatile storage unit 120 is returned to the volatile storage unit 110. "NV Store" is a store operation in which data from the volatile storage unit 110 is saved in the non-volatile storage unit 120. "NV Initial" is an operation in which specified data is written to the non-volatile storage unit 120.

[0034] "CE" in FIG. 4A represents the value of signal line CE. "WE" represents the value of signal line WE. "NCVCE" represents the value of signal line NVCE. "GSR1" represents the value of signal line GSR1. "GLPG" represents the value of signal line GLPG. "GSR2" represents the value of signal line GSR2. "CTRL" represents the value of signal line CTRL. "NVINI" represents the value of signal line NVINI.

[0035] The memory device 1 can perform a process that combines "NV Read," "NV Store," and "NV Restore." This process is performed under the control of the nonvolatile memory control unit 20.

[0036] [Combination Processing] FIG. 4B is a diagram showing an example of the operation of the memory device 1 according to the first embodiment of the present disclosure. The left side of the diagram represents a "Store free" operation. This is an operation for storing data when the data in the nonvolatile storage unit 120 differs from the data in the volatile storage unit 110. First, the nonvolatile storage unit control unit 20 performs an "NV Read." This causes the data in the volatile storage unit 110 to be read by the read circuit 30. This read data is held in a holding unit (holding unit 207) inside the read circuit 30. Next, the nonvolatile storage unit control unit 20 performs an "NV Restore." This causes the data in the nonvolatile storage unit 120 to be restored to the volatile storage unit 110. Next, the nonvolatile storage unit control unit 20 performs an "NV Read." This causes the data held in the nonvolatile storage unit 120 to be read by the read circuit 30. Next, the nonvolatile storage unit control unit 20 performs an "NV Store." At this time, the read circuit 30 compares the data held in the holding unit 207 with the data read by the previous "NV Read", and if the data differs, writes the data held in the holding unit 207 to the non-volatile memory unit 120.

[0037] The right side of FIG. 4B shows the operation of "verify", which is verification. First, the nonvolatile memory unit control unit 20 performs "NV Store". As a result, the data in the volatile memory unit 110 is saved in the nonvolatile memory unit 120. Next, the nonvolatile memory unit control unit 20 performs "NV Read". As a result, the data held in the volatile memory unit 110 is read out to the read circuit 30 and held therein. Next, the nonvolatile memory unit control unit 20 performs "NV Restore". As a result, the data in the nonvolatile memory unit 120 is restored to the volatile memory unit 110. Next, the nonvolatile memory unit control unit 20 performs "NV Read". As a result, the data in the volatile memory unit 110 is read out to the read circuit 30 and held therein. Next, the nonvolatile memory unit control unit 20 performs "NV Store". At this time, the read circuit 30 compares the data held in the holding unit 207 with the data read by the previous "NV Read", and if the data differs, writes the data held in the holding unit 207 to the non-volatile memory unit 120.

[0038] 5A is a diagram illustrating a configuration example of a read circuit according to the first embodiment of the present disclosure. The figure is a circuit diagram illustrating a configuration example of the read circuit 30. As described above, the read circuit 30 includes a nonvolatile memory unit control circuit 31 and a sense amplifier 32.

[0039] The nonvolatile memory control circuit (NV control) 31 includes a holding unit (Read register) 207, AND gates 205 and 206, an exclusive OR gate 204, OR gates 202 and 203, an inverting gate 201, and a nonvolatile memory drive circuit (NV DRV) 210. The holding unit 207 holds data read from the volatile memory unit 110. The AND gates 205 and 206 control the input of the output of the holding unit 207 and the output of the sense amplifier 32 to the exclusive OR gate 204. The exclusive OR gate 204 determines whether the output of the holding unit 207 and the output of the sense amplifier 32 are different. The OR gate 203 controls the input of the output signal of the exclusive OR gate 204 to the nonvolatile memory drive circuit 210.

[0040] The nonvolatile memory unit drive circuit 210 outputs the data held in the holding unit 207 to the bit lines BL and BLB. The nonvolatile memory unit drive circuit 210 outputs data to the bit lines BL and BLB based on the output of the exclusive OR gate 204. That is, the nonvolatile memory unit drive circuit 210 outputs the data from the holding unit 207 to the bit lines BL and BLB when the output of the holding unit 207 and the output of the sense amplifier 32 are different. The nonvolatile memory unit drive circuit 210 includes non-inverting gates 211 and 212 and an inverting gate 213.

[0041] The OR gate 202 and the inverting gate 201 generate a control signal for the signal line CTRLB.

[0042] 5B is a diagram showing an example of the operation of the readout circuit according to the first embodiment of the present disclosure. The figure is a truth table showing an example of the operation of the readout circuit 30. In the figure, "SAO" represents the output signal of the sense amplifier 32. "Reg_Q" represents the output signal of the holding unit 207. "NVINI" represents the signal on the signal line NVINI. "STREN" represents the output of the OR gate 203.

[0043] 6 is a diagram showing an example configuration of a nonvolatile memory driving circuit according to the first embodiment of the present disclosure. This figure is a circuit diagram showing an example configuration of a non-inverting gate 211 arranged in the non-volatile memory driving circuit 210. The non-inverting gate 211 can be configured with MOS transistors 224 and 225, a NAND gate 221, an inverting gate 222, and a NOR gate 223. The non-inverting gate 212 can also have a similar configuration.

[0044] 7 is a diagram illustrating an example of writing and reading of the volatile storage unit according to the first embodiment of the present disclosure, which is a timing chart illustrating the operations of "SRAM Write" and "SRAM Read" in FIG.

[0045] In addition, "CK" in FIG. 7 represents the signal on the signal line CK. "PRE" represents the signal on the signal line PRE. "WRE" represents the signal on the signal line WRE. "CL" represents the signal on the signal line CL. "WL" represents the signal on the signal line WL. "SAE" represents the signal on the signal line SAE. "BL" represents the signal on the bit line BL. "BLB" represents the signal on the bit line BLB. "d" and "db" represent signals of the latch circuit. "Q" represents the signal on the signal line Q. The signals "BLB" and "db" are indicated by dashed lines.

[0046] Writing and reading of the volatile memory unit 110 is similar to that of a general SRAM, with writing and reading of the memory cells 100 being performed on precharged bit lines. Also, writing and reading are performed on the memory cells 100 in the column selected by the column switching unit 60. The volatile memory unit control unit 80 generates each control signal based on an external signal.

[0047] [Bulk Reading of Volatile Memory Unit] FIG. 8 is a diagram showing an example of reading of the volatile memory unit according to the first embodiment of the present disclosure. This figure is a timing chart showing the operation of "NV Read" in FIG. 4A. "NV_SAE" in this figure represents the signal on the signal line NV_SAE. "SAO" represents the output signal of the sense amplifier 32. In "NV Read," the selected word is simultaneously read out from the number of sense amplifiers 32, and the data is stored in the holding unit 207, making it ready for comparison. At this time, all column switching units 60 are turned off to prevent short circuits. The nonvolatile memory unit control circuit 31 generates each control signal.

[0048] [Restore] FIG. 9 is a diagram illustrating an example of a restore operation according to the first embodiment of the present disclosure. This figure is a timing chart illustrating the operation of "NV Restore" in FIG. 4A. In this figure, "LPG" represents the signal on the signal line LPG. "GSR1" represents the signal on the signal line GSR1. "SR1" represents the signal on the signal line SR1. "NV Restore" is a restore operation that restores data stored in the nonvolatile memory unit 120 to the volatile memory unit 110, and can be performed using the resistance difference between the two variable resistance elements 123 and 124. The restore operation can be performed in one clock cycle. The internal charge of the volatile memory unit 110 is removed in the first half clock cycle, and in the next half clock cycle, the data is written to the latch circuit based on the internal voltage difference of the volatile memory unit 110 resulting from the resistance difference between the variable resistance elements 123 and the like of the nonvolatile memory unit 120. The restore operation can be performed in units of selected words (multiple words can also be selected). Simultaneous restore of all words is also possible.

[0049] [Store] FIG. 10 is a diagram showing an example of a store according to the first embodiment of the present disclosure. This figure is a timing chart showing a case where a store is performed by "NV Initial" in FIG. 4A. In this figure, "GSR2" represents the signal on the signal line GSR2. "SR2" represents the signal on the signal line SR2. "CTRL" represents the signal on the signal line CTRL. "Update" represents the Update signal in FIG. 5A. "Reg_Q" represents the output of the holding unit 207 (Reg_Q in FIG. 5A). "NVINI" represents the signal on the signal line NVINI. First, "NV Read" is performed to read data from the volatile storage unit 110. In the next "NV Initial," a store is performed in the nonvolatile storage unit 120 regardless of the value of the data in the nonvolatile storage unit 120.

[0050] 11 is a diagram showing an example of a store according to the first embodiment of the present disclosure. This figure is a timing chart showing the operation of "Store free" in FIG. 4B. "NV Read," "NV Restore," and "NV Read" read and compare data from the volatile memory unit 110 and the non-volatile memory unit 120, and control the store if the two data are different. The waveforms show an example in which the data in the volatile memory unit 110 is "1" and the data in the non-volatile memory unit 120 is "0."

[0051] [Effect] Figures 12A and 12B are diagrams showing an example of a store in a conventional nonvolatile memory. Figure 12A shows an example of a memory cell array 10, a column switching unit 60, a sense amplifier 72, and a nonvolatile storage unit control circuit 31 in a conventional nonvolatile memory. Note that in Figure 12A, "memory cell" is written as "MC." Figure 12A also shows an example of a case where verification is performed on memory cells 100 in all columns of the memory cell array 10. In this conventional example, reading is only possible for each column selected by the column switching unit 60, so the operation must be repeated a number of times equal to the number of memory cells 100.

[0052] FIG. 12B is a flowchart illustrating the verify process. The initial value of the loop variable mc is "0." First, data is read from the volatile memory unit 110 (step S101). Next, data from the nonvolatile memory unit 120 is read into the readout circuit 30 (step S102). Next, the nonvolatile memory unit control circuit 31 compares the data from the volatile memory unit 110 with the data from the nonvolatile memory unit 120, and stores the data if they are different (step S103). Next, if mc is less than 255 (step S104, No), the process adds 1 to mc and returns to step S101. If mc is 255 or greater (step S104, Yes), the process is terminated. When the number of multiplexes is 4 and the number of word accesses is 64, the process must be repeated 256 times.

[0053] 13A and 13B are diagrams illustrating an example of a store in the memory device according to the first embodiment of the present disclosure. FIG. 13A illustrates an example of the memory cell array 10, nonvolatile memory control circuit 31, sense amplifier 32, column switching unit 60, and sense amplifier 72 in the memory device 1 according to the present disclosure. In FIG. 13A, "NV control (nonvolatile memory control circuit)" is written as "NV CTRL." Also, "sense amplifier" is written as "SA." In FIG. 13A, memory cells 100 can be simultaneously read in the number equal to the number of sense amplifiers 32. Furthermore, store and restore can be performed in word units.

[0054] 13B is a flowchart showing the verify process. First, data is read from the volatile memory unit 110 word by word (step S111). Next, data from the nonvolatile memory unit 120 is read into the read circuit 30 word by word (step S112). Next, the nonvolatile memory unit control circuit 31 compares the data from the volatile memory unit 110 with the data from the nonvolatile memory unit 120, and if the data differs, stores the data word by word (step S113). Next, if mc is less than 63 (step S114, No), the process adds 1 to mc and proceeds to step S111. If mc is 63 or greater (step S114, Yes), the process is terminated. Even when the number of multiplexes is 4 and the number of word accesses is 64, verify can be completed in 64 repetitions.

[0055] In this way, in the memory device 1 according to the first embodiment of the present disclosure, the read circuit 30 is arranged for each column of the memory cell array 10, and therefore reading from the memory cells 100 can be performed collectively in word units, thereby reducing the time required for reading.

[0056] (2. Second Embodiment) A variation of the memory device 1 will be described.

[0057] 14 is a diagram showing an example of the configuration of a memory cell array according to the second embodiment of the present disclosure. This diagram shows an example in which the sense amplifiers arranged above and below the memory cell array 10 are shared. This sharing allows one sense amplifier 32 to be used for both "SRAM Read" and "NV Read." However, a switching unit (NV Read SW) 75 is added to prevent short circuits.

[0058] 15 is a diagram showing another example of the configuration of the memory cell array according to the second embodiment of the present disclosure. Similar to FIG. 3, this diagram shows an example in which the nonvolatile storage control circuit 31 and the sense amplifier 32 are arranged above the memory cell array 10.

[0059] 16 is a diagram showing another configuration example of the memory cell array according to the second embodiment of the present disclosure, in which the nonvolatile storage control circuit 31 and the sense amplifier 32 are arranged below the memory cell array 10.

[0060] FIG. 17 is a diagram illustrating another exemplary configuration of a memory cell array according to the second embodiment of the present disclosure. This diagram illustrates variations in the number of sense amplifiers 32. The memory device 1 of the present disclosure can achieve higher speeds by including more sense amplifiers than the sense amplifiers 72 typically used to read data from the volatile memory unit 110. As shown in the diagram, sense amplifiers 32 can be arranged every two columns. This configuration is particularly effective when there are a large number of I / Os and the number of bits that can be simultaneously stored in the nonvolatile memory unit 120 is limited by the current value that can flow through the semiconductor chip. However, this configuration requires a switching unit (NV Read SW) 76 that selects the "NV Read" state.

[0061] 18 and 19 are diagrams illustrating an example of the configuration of a memory cell according to the second embodiment of the present disclosure. 18 and 19 illustrate an example in which the volatile memory unit 110 has two ports.

[0062] The variable resistance element 123 of the nonvolatile memory unit 120 may be an MTJ (Magnetic Tunnel Junction) element or an element used in a resistance random access memory (ReRAM).

[0063] The configuration of the memory device 1 other than that described above is the same as the configuration of the memory device 1 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0064] (3. Configuration of Memory System) A memory system (memory system 4) that uses the memory device 1 of the first embodiment described above will be described.

[0065] [Configuration of Memory System] Fig. 20 is a diagram showing an example configuration of a memory system to which the technology according to the present disclosure can be applied. The figure is a block diagram showing an example configuration of a memory system 4. The memory system 4 includes an interface unit 3, a memory device control unit 2, and a memory device 1. The memory system 4 is an example of an "electronic device" according to the present disclosure.

[0066] The interface unit 3 is for communicating with the host system.

[0067] The memory device control unit 2 controls writing and reading of the memory device 1 based on commands from the host system, etc. The memory device control unit 2 generates various control signals shown in FIG.

[0068] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0069] The present technology can also be configured as follows. (1) A memory device comprising: a memory cell array configured with memory cells arranged in a two-dimensional matrix, each memory cell having a volatile memory unit that stores data using a latch circuit and a non-volatile memory unit that stores data using a variable resistance element; a plurality of read circuits arranged in each column of the memory cell array and reading data from the volatile memory units of the memory cells included in the column; and a memory control unit that controls writing and reading of data to and from the volatile memory units of the memory cells. (2) The memory device according to (1), in which the plurality of read circuits simultaneously read data from the volatile memory units of the memory cells in a specific row of the memory cell array in a column of the memory cell array to which the plurality of read circuits respectively correspond. (3) The memory device according to (1) or (2), in which the read circuit comprises: a sense amplifier that reads data from the volatile memory unit; and a non-volatile memory unit control circuit that includes a holding unit that holds the data read by the sense amplifier and controls writing of the data held in the holding unit to the non-volatile memory unit of the memory cell from which the sense amplifier reads the data. (4) The memory device according to (3), wherein the nonvolatile storage unit control circuit further controls writing of data held in the holding unit to the nonvolatile storage unit when the data held in the holding unit and the data input from the sense amplifier are different. (5) The memory device according to any of (1) to (4), wherein the memory control unit further controls writing of data in the nonvolatile storage unit of the memory cell to the volatile storage unit. (6) The memory device according to any of (1) to (5), further comprising a selection unit that selects a column of the memory cell array. (7) The memory device according to (6), further comprising a second sense amplifier that reads data from the volatile storage unit of any memory cell in the selected column, wherein the memory control unit controls reading of data via the second sense amplifier. (8) The memory device according to (6), wherein the read circuit further reads data from the volatile storage unit of any memory cell in the selected column.(9) An electronic device having: a memory cell array configured by arranging memory cells in a two-dimensional matrix, each memory cell having a volatile memory portion that stores data using a latch circuit and a non-volatile memory portion that stores data using a variable resistance element; a memory device including: a plurality of read circuits arranged in each column of the memory cell array for reading data from the volatile memory portions of the memory cells included in the column; and a memory device control portion that controls the memory device.

[0070] REFERENCE SIGNS LIST 1 memory device 4 memory system 10 memory cell array 20 nonvolatile memory section control section 30 read circuit 31 nonvolatile memory section control circuit 32, 72 sense amplifier 60 column switching section 70 volatile memory section read circuit 80 volatile memory section control section 100 memory cell 110 volatile memory section 114, 115 inversion gate 120 nonvolatile memory section 123, 124 variable resistance element 207 holding section 210 nonvolatile memory section drive circuit

Claims

1. A memory device comprising: a memory cell array in which memory cells are arranged in a two-dimensional matrix, each memory cell having a volatile memory section that stores data using a latch circuit and a non-volatile memory section that stores data using a variable resistance element; a plurality of read circuits arranged in each column of the memory cell array for reading data from the volatile memory sections of the memory cells included in that column; and a memory control section that controls the writing and reading of data to and from the volatile memory sections of the memory cells.

2. The memory device according to claim 1, wherein the plurality of read circuits simultaneously read from the volatile storage unit the memory cells in a specific row of the memory cell array in the column of the memory cell array to which the plurality of read circuits respectively correspond.

3. The memory device according to claim 1, wherein the read circuit comprises: a sense amplifier that reads data from the volatile memory unit; and a non-volatile memory unit control circuit that has a storage unit that stores the data read by the sense amplifier and controls writing of the data stored in the storage unit to the non-volatile memory unit of the memory cell from which the sense amplifier reads the data.

4. The memory device according to claim 3, wherein the non-volatile memory control circuit further controls writing of the data held in the holding unit to the non-volatile memory unit when the data held in the holding unit and the data input from the sense amplifier are different.

5. The memory device according to claim 1, wherein the memory control unit further controls writing of data from the nonvolatile storage unit of the memory cell to the volatile storage unit.

6. The memory device according to claim 1, further comprising a selection unit for selecting a column of the memory cell array.

7. The memory device according to claim 6, further comprising a second sense amplifier that reads data from the volatile storage unit of any memory cell in the selected column, and wherein the memory control unit controls the reading of data via the second sense amplifier.

8. The memory device according to claim 6, wherein the read circuit further reads data from the volatile storage unit of any one of the memory cells in the selected column.

9. Electronic equipment having a memory device comprising: a memory cell array configured by arranging memory cells in a two-dimensional matrix, each memory cell having a volatile memory section that stores data using a latch circuit and a non-volatile memory section that stores data using a variable resistance element; a plurality of read circuits arranged in each column of the memory cell array for reading data from the volatile memory sections of the memory cells included in that column; a memory control section that controls the writing and reading of data in the volatile memory sections of the memory cells; and a memory device control section that controls the memory device.

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