Linearity enhanced n-path filters

Abstract

An N-path filter including a plurality of capacitors, wherein each capacitor of the plurality of capacitors is connected to a switch of a plurality of switches, a plurality of gates, wherein each switch of the plurality of switches is coupled to a gate of the plurality of gates, and wherein a CLK signal is applied to each gate of the plurality of gates, and a negative feedback circuit configured for sensing a drain source voltage (VDS) variation of each switch of the plurality of switches, and adjusting a gate source voltage (VGS) based on the VDS.

Description

LINEARITY ENHANCED N-PATH FILTERS CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application 63 / 655911 filed June 4, 2024 and U.S. Provisional Application 63 / 655931 filed June 4, 2024, the entire disclosures of which are hereby incorporated by reference. BACKGROUND

[0002] N-path filters have emerged as a new type of tunable band-pass filter that is gaining interest in radio frequency (RF) radio applications. Unlike the traditional, discrete RF filters, which are bulky and expensive, N-path filters are amenable to integration in standard silicon technologies such as Complementary Metal Oxide Semiconductor (CMOS), thus reducing size, cost and power consumption. In addition, this class of filter allows highly programmable implementations with respect to frequency response and bandwidth, allowing extreme on-chip configurability. Specifically, these filters leverage periodic switching to achieve band-pass filtering in a wide range of frequencies, by programming the number of filter coefficients by switching in an out more capacitance, varying the direct current (DC) gain of each filter coefficient, and adjusting / tuning the clock frequency. This ability to fine-tune the filtering characteristics makes N-path filters particularly useful in rejecting undesired interference in RF radios and also generating programmable delay spreads for self-interference cancellers.

[0003] Generally, N-path filters are a type of tunable band pass filter. These filters offer good configurability, allowing them to dynamically adjust their frequency response to reject undesired interference for RF radios. Due to their high configurability and compact area, they are potential to replace bulky discrete RF filters currently used in wireless devices, which can significantly reduce costs and improve developments of wireless communications such as 5G, WiFi, and internet of things (IoT) devices. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -1-

[0004] Moreover, the use and application of N-path filters goes well beyond radio and wireless communication. Any application that requires a combination of an integrated solution (on-chip) combined with highly programmable frequency response is suitable for the use of N-path filters. Example applications outside of wireless and radio frequency systems include wireline transceivers, quantum controller applications, biological chips for wearable and implantable devices with many other applications beyond this set.

[0005] While N-path filters appear very promising, there are significant performance challenges with integrating this class of filter. Specifically, the linear performance of this class of filter is limited by the non-linearity of the sampling switch used to sample and combine the input signal. This is particularly problematic in wireless radio applications where unwanted interference demands very high linearity of the radio front-end. As such, currently, the main limitation of this technology is its insufficient linearity for high-output power applications.

[0006] A major limiting factor of N-path filters is non-linear characteristics of their switches. Specifically, in a commonly used top-plate configuration, the signal- dependent drain and source voltages of the switches cause variation in gate source voltage (VGS), gate to drain voltage (VGD), and drain source voltage (VDS), which modulate the on-state switch resistance. This inconsistent on-state switch resistance causes non-linear behavior in the N-path filter. Further, the linearity of state-of-the-art N-path filter circuits is insufficient for some high-output power radio applications such as long-range communication and industry IoT in 5G systems. Accordingly, N-path filters with improved linearity are still needed. SUMMARY

[0007] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -2-

[0008] In one aspect, disclosed herein is an N-path filter including a plurality of capacitors, wherein each capacitor of the plurality of capacitors is connected to a switch of a plurality of switches, a plurality of gates, wherein each switch of the plurality of switches is coupled to a gate of the plurality of gates, and wherein a CLK signal is applied to each gate of the plurality of gates, and a negative feedback circuit configured for sensing a drain source voltage (VDS) variation of each switch of the plurality of switches, and adjusting a gate source voltage (VGS) based on the VDS.

[0009] In some embodiments, the N-path filter is a bottom plate N-path filter, a top plate N-path filter, or a mixer N-path filter. In some embodiments, the N-path filter is a differential top plate N-path filter. In some embodiments, the N-path filter is a differential bottom plate N-path filter.

[0010] In some embodiments, the negative feedback circuit comprises an inverter. In some embodiments, the inverter is configured for sensing a first voltage drop (VD1) or a second voltage drop (VD2). In some embodiments, the inverter is further configured for pulling the CLK signal lower than a maximum supplied voltage (VDD) when the inverter senses an increase in VD2. In some embodiments, inverter is further configured for pulling the CLK signal higher than the VDD when the inverter senses a decrease in VD2. In some embodiments, the inverter is further configured for pulling the CLK signal lower than the VDD when the inverter senses a decrease in VD1. In some embodiments, the inverter is further configured for pulling the CLK signal higher than the VDD when the inverter senses an increase in VD1. In some embodiments, the feedback circuit further includes alternating current (AC) coupling, and direct current (DC) biasing, wherein the AC coupling and the DC biasing are disposed between the gate of the plurality of gates and the inverter. In some embodiments, the N-path filter is configured for attaining a Third-Order Intercept Point (IIP3) of about 34.2dBm.

[0011] In some embodiments, the plurality of switches are N-channel Metal- Oxide-Semiconductor (NMOS) switches, (Complementary Metal-Oxide-Semiconductor) CMOS switches, or a combination thereof. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -3-

[0012] In some embodiments, the negative feedback circuit further includes a first capacitor. In some embodiments, the negative feedback circuit is configured for, when the CLK signal is high, pre-charging the first capacitor to a constant voltage VDD0, while the switch of the plurality of switches is on.

[0013] In some embodiments, the negative feedback circuit is further configured for, when the CLK signal is low, reducing a resistance variation as the gate of the switch becomes VD+VDD0.

[0014] In some embodiments, the negative feedback circuit further includes a second switch (M2), a third switch (M3), a fourth switch (M4), a fifth switch (M5), and a sixth switch (M6), where the CLK signal is applied to the second switch M2 and the fifth switch M5, and where an inverted CLK signal is applied to the third switch M3, the fourth switch M4, and the sixth switch M6.

[0015] In some embodiments, the N-path filter is configured for attaining a Third- Order Intercept Point (IIP3) of about 32dBm.

[0016] In some embodiments, the N-path filter has a substantially constant ONresistance (ron).

[0017] In another aspect, disclosed herein is a tunable canceler comprising one or more N-path filters as disclosed herein. DESCRIPTION OF THE DRAWINGS

[0018] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0019] FIGURE 1A is an example N-path filter, in accordance with the present technology;

[0020] FIGURE 1B is an example negative feedback circuit, in accordance with the present technology; 3915-P1407WO.UW TPF:lrc (50142.02WO2) -4-

[0021] FIGURES 1C-1D are example N-path filters, in accordance with the present technology;

[0022] FIGURES 1E-1F are example N-path filters in FIGs.1C-1D, respectively, with negative feedback applied to the switches, in accordance with the present technology;

[0023] FIGURE 1G is an example mixer, in accordance with the present technology;

[0024] FIGURE 1H is an example of the mixer of FIG. 1G with negative feedback applied to the switches, in accordance with the present technology;

[0025] FIGURE 1I is another example negative feedback circuit, in accordance with the present technology;

[0026] FIGURES 2A-2B are example figures of the negative feedback circuit of FIG.1I, where the clock (CLK) signal is low and high, respectively, in accordance with the present technology;

[0027] FIGURE 3 is an example canceler utilizing the N-path filters disclosed herein, in accordance with the present technology;

[0028] FIGURE 4A is a graph of performance of an N-path filter including the negative feedback circuit of FIG.1B, in accordance with the present technology; and

[0029] FIGURE 4B is a graph of performance of an N-path filter including the negative feedback circuit of FIG.1I, in accordance with the present technology. DETAILED DESCRIPTION

[0030] In one aspect, disclosed herein is an N-path filter configured for further reducing the variation of the on-state switch resistance and enhancing the linearity of the differential N-path filter.

[0031] In one aspect, disclosed herein is a mixer configured for further reducing the variation of the on-state switch resistance and enhancing the linearity of the mixer.

[0032] In another aspect, disclosed herein is an N-path filter using switched capacitor circuits which allows clock signals to dynamically track the input signal, 3915-P1407WO.UW TPF:lrc (50142.02WO2) -5-significantly reducing the switch resistance variation and enhancing the linearity of the N- path filter.

[0033] FIG. 1A is an example N-path filter 100, in accordance with the present technology. In different embodiments, the N-path filter 100 is a bottom plate N-path filter, a top plate N-path filter, or a mixer N-path filter. In some embodiments, the N-path filter 100 is a differential top plate N-path filter or a differential bottom plate N-path filter.

[0034] In some embodiments, the N-path filter includes a plurality of capacitors 110A, 110B, 110C, 110D, 110E, 110F. In some embodiments, each capacitor of the plurality of capacitors 110A, 110B, 110C, 110D, 110E, 110F is connected to a switch of a plurality of switches 105A, 105B, 105C, 105D, 105E, 105F.

[0035] In some embodiments, the plurality of switches 105A, 105B, 105C, 105D, 105E, 105F are N-channel Metal-Oxide-Semiconductor (NMOS) switches, (Complementary Metal-Oxide-Semiconductor) CMOS switches, or a combination thereof.

[0036] In some embodiments, the N-path filter further includes a plurality of gates 105A, 105B, 105C, 105D, 105E, 105F where each switch of the plurality of switches 115A, 115B, 115C, 115D, 115E (M1), 115F (M2) is coupled to a gate of the plurality of gates 105A, 105B, 105C, 105D, 105E, 105F. In some embodiments, a clock (CLK) signalφ1, φ2… φiis applied to each gate of the plurality of gates 105A, 105B, 105C, 105D, 105E,105F.

[0037] In some embodiments, the N-path filter 100 includes a positive inputterminal (Vin+) 125 and a negative input terminal (Vin-) 130. In some embodiments, thepositive input terminal 125 is a non-inverting input. As used herein, the part that is connected to the positive input terminal, that is the switches and the (optional) capacitorsthat are connected between the positive input terminal and the vbiasor ground or positiveoutput terminal, is referred to as the “positive part of the N-path filter or mixer” and the part that is connected to the negative input terminal, that is the switches and the (optional)capacitors that are connected between the negative input terminal and the vbiasor groundor positive output terminal, are referred to as the “negative part.” In some embodiments, 3915-P1407WO.UW TPF:lrc (50142.02WO2) -6-the negative input terminal 130 is an inverting input. In some embodiments, a difference between the positive input terminal and the negative input terminal is a differential input voltage.

[0038] In some embodiments, the N-path filter 100 further includes a first transistor 120A coupled to the positive input terminal 125. In some embodiments, the N- path filter further includes a second transistor 120B coupled to the negative input terminal 130.

[0039] In operation, as a drain source voltage (VDS) of each switch of the plurality of switches 105A, 105B, 105C, 105D, 105E, 105F increases, an on-state resistance increases too and thus, a larger gate source voltage (VGS) is utilized to maintain the original on-state switch resistance. In some embodiments, the VDS is not controllable, as it is signal-dependent, and neither is the VGS, as it is constant alternating constant (AC) ground, for the N-path to have the desired operation. This leaves the gate (such as gate 105E) of the switch (such as switch 115E M1) as the only controllable node. In some embodiments, the N-path filter 100 leverages the complementary behavior of a differentialbottom-plate N-path filter. As Vin+ increases, Vin- decreases and vice versa.

[0040] In some embodiments, the N-path filter 100 further includes a negative feedback circuit 1000, as shown and described in detail in FIGs.1B and 1I.

[0041] FIG.1B is an example negative feedback circuit 1000, in accordance with the present technology. In some embodiments, the negative feedback circuit 1000 may be implemented into an N-path filter having a bottom plate configuration as shown in FIG. 1B. However, in other embodiments, the negative feedback circuit 1000 may be implemented into an N-path filter having a top plate configuration, or a mixer configuration.

[0042] In some embodiments, the negative feedback circuit 1000 includes one or more inverters 1005A, 1005B. In some embodiments, the inverter 1005B senses theincrease in a second voltage drop (VD2) and thus decrease in a first voltage drop (VD1). Insome embodiments, the inverter pulls the CLK signal φiapplied to the gate 105E, slightly3915-P1407WO.UW TPF:lrc (50142.02WO2) -7-lower than the maximum supplied voltage (VDD). However, when the inverter 1005A,1005B senses a decrease in VD2(and thus increase in VD1), it pulls the CLK signal φiapplied to the gate of 105E slightly higher than before, again close to VDD. The result is that the VGS of each device is now influenced by its own VDS, as the increase in VDS causes an increase in VGS and decrease in VDS causes decrease in VGS. Similarly, the inverter 1005A may perform the same functions as the inverter 1005B for the gate 105F.

[0043] Accordingly, in operation each inverter 1005A, 1005B is configured forsensing VD1or VD2. In some embodiments, the inverter 1005A is further configured forpulling the CLK signal φihigher than the VDD when the inverter senses a decrease in VD2,and for pulling the CLK signal lower φithan the VDD when the inverter 1005A senses adecrease in VD1. Further, the inverter 1005B is configured for pulling the CLK signal φihigher than the VDD when the inverter senses an increase in VD1.

[0044] In operation, the negative feedback circuit 1000 uses feedback to sense the switch’s VDS variation and fine-tune the VGS accordingly, in order to maintain a moreconsistent on-state resistance with a variable Vin, and thus the VDS voltage. Thus, in someembodiments, the N-path filter has a substantially constant ON resistance (ron).

[0045] In some embodiments, the inverters 1005A, 1005B that track the drainvoltages are relatively weaker than the inverters 1010 that are driven by the CLK signal φi.Also, in some embodiments, the pull-down network of the CLK-driven inverters 1010 is substantially strong, and the pull-up network of the VDS-driven inverters 1005A, 1005B is weaker, in order to ensure that no switching happens during the OFF-state, that may otherwise be caused by a low VDS.

[0046] In some embodiments, the feedback circuit 1000 further includes: alternating current (AC) coupling 130A, 130B. In some embodiments, the feedback circuit 1000 further includes direct current (DC) biasing 130A, 130B, wherein the AC coupling and the DC biasing 130A, 130B are disposed between the gate (such as gate 105E and gate 105F) of the plurality of gates and the inverter 1005A, 1005B. In some embodiments, AC 3915-P1407WO.UW TPF:lrc (50142.02WO2) -8-coupling and DC biasing 130A, 130B can be placed at the input of the VDS-driven inverters 1005A, 1005B for better performance.

[0047] It should be understood that the negative feedback circuit 1000 is applicable to any CMOS technology, and for N-Path filters with any number of phases and targeting any frequency range.

[0048] FIGs.1C-1D are example N-path filters, in accordance with the present technology. FIGs.1E-1F are example N-path filters in FIGs. 1C-1D, respectively, with negative feedback applied to the switches, in accordance with the present technology. FIGs.1G is an example mixer, in accordance with the present technology. FIG.1H is an example of the mixer of FIG. 1G with negative feedback applied to the switches, in accordance with the present technology. In FIG. 1E one terminal of all the switches is connected to one common bias voltage or ground, which is a shared connection among all the switches. In FIG.1C one terminal of all the switches of the positive part of the N-path filter is connected to the positive terminal of the N-path filter, which is a shared connection among those switches, and one terminal of all the switches of the negative part of the N- path filter is connected to the negative terminal of the N-path filter, which is a shared connection among those switches. Changes in voltage at the non-shared terminal of any switch at the positive part of the N-path filter or mixer (the terminal that does not have a shared connection among the switches of the positive part of the N-path filter or mixer) (200 or 202 or Out_1+) comes with a similar, opposite (towards the opposite direction) change at the respective terminal of the respective switch at the negative part of the N-path filter or mixer (201 or 203 or Out_1-). In some embodiments the input of an inverting amplifier is connected at the non-shared terminal of each switch of the positive part of the N-path filter or mixer (200 or 202 or 204) and the output of this inverting amplifier is connected to the gate of the respective switch at the negative part of the N-path filter or mixer (200G or 202G or 204G). Also, the input of an inverting amplifier is connected at the non-shared terminal of each switch of the negative part of the N-path filter or mixer 3915-P1407WO.UW TPF:lrc (50142.02WO2) -9-(201 or 203 or 205) and the output of this inverting amplifier is connected to the gate of the respective switch at the positive part of the N-path filter or mixer (201G or 203G or 205G).

[0049] In operation, as the Vin+ in FIGs. 1E and 1G increases, an on-state resistance of the switches that are connected to this terminal increases too and thus, a larger gate source voltage (VG) is utilized to maintain the original on-state switch resistance. In operation, as the Vin- in FIGs.1E and 1G increases, an on-state resistance of the switches that are connected to this terminal increases too and thus, a larger gate source voltage (VG) is utilized to maintain the original on-state switch resistance. In some embodiments, the VDS is not controllable, as it is signal-dependent, and neither is the VGS, as it is constant alternating constant (AC) ground, for the N-path to have the desired operation. In some embodiments, the VGS and the VDS are not controllable, as it is signal-dependent, as it is constant alternating constant (AC) ground, for the N-path to have the desired operation. This leaves the gate (such as gate 105E) of the switch (such as switch 115E M1) as the only controllable node. In some embodiments, the N-path filter 100 leverages the complementary behavior of a differential bottom-plate N-path filter or mixer and aims to maintain a constant on-state resistance among all of the switches in it. As Vin+ increases, Vin- decreases and vice versa.

[0050] FIG.1I is another example negative feedback circuit 1000, in accordance with the present technology. In some embodiments, the negative feedback circuit 1000 may be implemented into an N-path filter having a bottom plate configuration as shown in FIG.1I. However, in other embodiments, the negative feedback circuit 1000 may be implemented into an N-path filter having a top plate configuration, or a mixer configuration.

[0051] In some embodiments, the negative feedback circuit 1000 includes a first capacitor C1 150. In some embodiments, the negative feedback circuit 1000 further includes the switch M1115E. In some embodiments, the negative feedback circuit further includes and a second switch M2205A, a third switch M3205B, a fourth switch M4205C, a fifth switch M5205D, and a sixth switch M6205E (collectively referred to as a “plurality 3915-P1407WO.UW TPF:lrc (50142.02WO2) -10-of negative feedback switches 205A, 205B, 205C, 205D, 205E”). In some embodiments, the CLK signal φ is applied to the second switch M2205A and the fifth switch M5205D,and an inverted CLK signal φ� is applied to the third switch M3205B, the fourth switch M4205C, and the sixth switch M6305E.

[0052] In some embodiments, the CLK signal φ can be represented as shown in Equation 1. ^^^^^^^^1 + ^^^^^^^^^^^^0,^^^^ℎ^^^^^^^^^^^^ (^^^^^^^^^^^^0 < ^^^^^^^^^^^^)Equation 1

[0053] is a first voltage drop, VDD0is a constant voltage, and VDDis a voltage at the drain (VDD).

[0054] In some embodiments, the feedback circuit 1000 dynamically tracks VDto reduce resistance ON variation. In some embodiments,lower than nominal VDDto avoid device breakdown.

[0055] Depending on the value of the CLK signal φ, the feedback circuit 1000 may increase the linearization of the N-path filter as shown and described in detail in FIGs. 2A-2B.

[0056] It should be understood that the negative feedback circuit 1000 is applicable to any CMOS technology, for N-Path filters with various numbers of phases and targeting various frequency range.

[0057] FIGURES 2A-2B are example figures of the negative feedback circuit 1000 of FIG. 1I, where the clock (CLK) signal φ is low and high, respectively, in accordance with the present technology.

[0058] In FIG. 2A, when the CLK signal φ is low, the first capacitor C1150 ispre-charged to VDD0. In FIG. 2B, when the CLK signal φ is high, VDadded toisapplied to the gate (such as switch 105E in FIG.1A) of the switch M1115E.

[0059] In operation, for each set of switches (such as plurality of switches 105A, 105B, 105C, 105D, 105E, 105F in FIG.1A), when the CLK signal φ is low, the capacitorC1 150 is pre-charged to a constant voltage of VDD0while the switch M1 115E is off.3915-P1407WO.UW TPF:lrc (50142.02WO2) -11-When the CLK signal φ goes high, the gate of the switch M1 115E becomes VD+VDD0,dynamically tracking VDand reducing the resistance variation, and thus enhancing thelinearity of the switch 115E M1. The pre-charging voltage VDD0may be selected to belower than the nominal supply voltage VDD(for example 0.9VDD), which can stilleffectively turn on the switch M1115E. In some embodiments, this may also obviate the need for using thick oxide devices for second switch M2205A and third switch M3205B without causing transistors breakdown.

[0060] In some embodiments, negative feedback circuit 1000 can be implemented in a broad class of CMOS technology with compact area as compared to prior discrete RF filters.

[0061] FIGURE 3 is an example canceler 4000 utilizing the N-path filters 100A, 100B disclosed herein, in accordance with the present technology. In some embodiments, the canceler 4000 is a tunable canceler. In some embodiments, the canceler 4000 includes one or more N-path filters as shown and described herein. In some embodiments, thecanceler 4000 includes one or more complex Gmstages (complex taps). In someembodiments, the canceler 4000 may cancel frequencies with a poly-phase filter (PPF) module.

[0062] Conventional cancelers often have limited configurability, such as having only 20 dB of gain tuning range. Further, conventional cancelers may have limited linearity based on the switches of the N-path filters 100A, 100B. Other conventional cancelers may lack independent phase tuning and have a negative trade-off between delay spread and circuit bandwidth.

[0063] Advantageously, the canceler 4000 is able to tune amplitude, phase, group delay, and center frequency. In some embodiments, an amplitude and phase can be tunedby the one or more complex Gmstages (complex tap Gm). A group delay may be tuned bycapacitor CB. Further, a center frequency may be controlled by an LO frequency (LO-0,LO-2, LO-3). Further, the capacitor Csattenuates a strong power amplifier (PA) outputsignal. In some embodiments, the canceler 4000 allows for a large group delay. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -12-

[0064] FIG. 4A is a graph of performance of an N-path filter including the negative feedback circuit of FIG. 1B, in accordance with the present technology. On the vertical axis is the output power in dBm. On the horizontal axis is the input power in dBm. The simulated in-band IIP3 referenced to an input impedance of 50Ω of the N-path filter shown in FIG. 1B (proposed), a differential top-plate, and a differential bottom-plate N- path filter, implemented in a TSMC 40nm process and using a 2.5GHz clock frequency with four different phases are shown. The proposed N-path filter achieves an IIP3 of 34.2dBm at the input power of -10dBm, which is about 16dB and 10dB higher as compared to prior top-plate and bottom-plate configurations, respectively.

[0065] FIGURE 4B is a graph of performance of an N-path filter including the negative feedback circuit of FIG. 1I, in accordance with the present technology. On the vertical axis is the output power in dBm. On the horizontal axis is the input power in dBm. The simulated in-band IIP3 referenced to an input impedance of 50Ω of the N-path filter of FIG.1I (proposed), a top-plate, and a bottom-plate N-path filter are shown. The proposed N-path filter achieves an IIP3 of 32dBm at the input power of -10dBm, which is about 13dB and 7dB higher as compared to prior top-plate and bottom-plate configurations, respectively.

[0066] Thus, the N-path filter of FIG. 1I is capable of being implemented into radio transceivers to sustain higher input signal power and increase the radio linearity, which is demanded by some 5G applications such as long-range communication and industrial internet of things (IoT) devices.

[0067] The simulation results show the proposed design enhance the IIP3 of the N-path filter by more than 10dB compared to prior design. Thus, this can be potentially used in RF radio transceivers to sustain higher input signal power and increase the radio linearity, which is demanded by some 5G applications.

[0068] While illustrative embodiments have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -13-

[0069] The complete disclosure of all patents, patent applications, and publications, and electronically available material cited herein are incorporated by reference in their entirety. Supplementary materials referenced in publications (such as supplementary tables, supplementary figures, supplementary materials and methods, and / or supplementary experimental data) are likewise incorporated by reference in their entirety. In the event that any inconsistency exists between the disclosure of the present application and the disclosure(s) of any document incorporated herein by reference, the disclosure of the present application shall govern. The foregoing detailed description and examples have been given for clarity of understanding only. No unnecessary limitations are to be understood therefrom. The invention is not limited to the exact details shown and described, for variations obvious to one skilled in the art will be included within the invention defined by the claims.

[0070] The description of embodiments of the disclosure is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While the specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure.

[0071] Specific elements of any foregoing embodiments can be combined or substituted for elements in other embodiments. Moreover, the inclusion of specific elements in at least some of these embodiments may be optional, wherein further embodiments may include one or more embodiments that specifically exclude one or more of these specific elements. Furthermore, while advantages associated with certain embodiments of the disclosure have been described in the context of these embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the disclosure.

[0072] As used herein and unless otherwise indicated, the terms “a” and “an” are taken to mean “one”, “at least one” or “one or more”. Unless otherwise required by context, singular terms used herein shall include pluralities and plural terms shall include the singular. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -14-

[0073] Unless the context clearly requires otherwise, throughout the description and the claims, the words ‘comprise’, ‘comprising’, and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”. Words using the singular or plural number also include the plural and singular number, respectively. Additionally, the words “herein,” “above,” and “below” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of the application.

[0074] Unless otherwise indicated, all numbers expressing quantities of components, molecular weights, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless otherwise indicated to the contrary, the numerical parameters set forth in the specification and claims are approximations that may vary depending upon the desired properties sought to be obtained by the present invention. At the very least, and not as an attempt to limit the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.

[0075] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. All numerical values, however, inherently contain a range necessarily resulting from the standard deviation found in their respective testing measurements.

[0076] All headings are for the convenience of the reader and should not be used to limit the meaning of the text that follows the heading, unless so specified.

[0077] All of the references cited herein are incorporated by reference. Aspects of the disclosure can be modified, if necessary, to employ the systems, functions, and concepts of the above references and application to provide yet further embodiments of the disclosure. These and other changes can be made to the disclosure in light of the detailed description. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -15-

[0078] It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the claims. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -16-

Claims

CLAIMS We claim:

1. An N-path filter comprising: a plurality of capacitors, wherein each capacitor of the plurality of capacitors is connected to a switch of a plurality of switches; a plurality of gates, wherein each switch of the plurality of switches is coupled to a gate of the plurality of gates, and wherein a CLK signal is applied to each gate of the plurality of gates; and a negative feedback circuit configured for: sensing a drain source voltage (VDS) variation of each switch of the plurality of switches; and adjusting a gate source voltage (VGS) based on the VDS.

2. The N-path filter of Claim 1, wherein the N-path filter is a bottom plate N- path filter, a top plate N-path filter, or a mixer N-path filter.

3. The N-path filter of Claim 2, wherein the N-path filter is a differential top plate N-path filter.

4. The N-path filter of Claim 2, wherein the N-path filter is a differential bottom plate N-path filter.

5. The N-path filter of Claim 1, wherein the negative feedback circuit comprises an inverter.

6. The N-path filter of Claim 5, wherein the inverter is configured for: sensing a first voltage drop (VD1) or a second voltage drop (VD2).

7. The N-path filter of Claim 6, wherein the inverter is further configured for pulling the CLK signal lower than a maximum supplied voltage (VDD) when the invertersenses an increase in VD2.3915-P1407WO.UW TPF:lrc (50142.02WO2) -17-8. The N-path filter of Claim 6, wherein the inverter is further configured forpulling the CLK signal higher than the VDD when the inverter senses a decrease in9. The N-path filter of Claim 6, wherein the inverter is further configured forpulling the CLK signal lower than the VDD when the inverter senses a decrease in VD1.

10. The N-path filter of Claim 6, wherein the inverter is further configured forpulling the CLK signal higher than the VDD when the inverter senses an increase in VD1.

11. The N-path filter of Claim 5, wherein the feedback circuit further comprises: alternating current (AC) coupling; and direct current (DC) biasing, wherein the AC coupling and the DC biasing are disposed between the gate of the plurality of gates and the inverter.

12. The N-path filter of Claim 5, wherein the N-path filter is configured for attaining a Third-Order Intercept Point (IIP3) of about 34.2dBm.

13. The N-path filter of Claim 1, wherein the plurality of switches are N-channel Metal-Oxide-Semiconductor (NMOS) switches, (Complementary Metal-Oxide- Semiconductor) CMOS switches, or a combination thereof.

14. The N-path filter of Claim 1, wherein the negative feedback circuit further comprises: a first capacitor.

15. The N-path filter of Claim 14, wherein the negative feedback circuit is configured for: when the CLK signal is high: pre-charging the first capacitor to a constant voltage VDD0, while the switchof the plurality of switches is on. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -18-16. The N-path filter of Claim 14, wherein the negative feedback circuit is further configured for: when the CLK signal is low: reducing a resistance variation as the gate of the switch becomes VD+VDD0.

17. The N-path filter of Claim 14, wherein the negative feedback circuit further comprises: a second switch (M2); a third switch (M3); a fourth switch (M4); a fifth switch (M5); and a sixth switch (M6), wherein the CLK signal is applied to the second switch M2 and the fifth switch M5, and wherein an inverted CLK signal is applied to the third switch M3, the fourth switch M4, and the sixth switch M6.

18. The N-path filter of Claim 14, wherein the N-path filter is configured for attaining a Third-Order Intercept Point (IIP3) of about 32dBm.

19. The N-path filter of Claim 1, wherein the N-path filter has a substantially constant ON resistance (ron).

20. A tunable canceler comprising one or more N-path filters according to any one of claims 1-19. 3915-P1407WO.UW TPF:lrc (50142.02WO2) -19-

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