Driving circuit, driving method, and display apparatus

Abstract

Disclosed in the present application are a driving circuit (100), a driving method, and a display apparatus (300). The driving circuit (100) comprises a plurality of rows of gate lines (120) and a plurality of gate driving units (110), wherein an input end of each row of gate line (120) is connected to an output end of the corresponding gate driving unit (110), and receives a gate driving signal, so as to control the turning on or off of a thin film transistor connected to the gate line (120); each row of gate line (120) comprises at least a first gate line segment (121) and a second gate line segment (122), and a first refresh rate adjustment circuit (131) is provided between the first gate line segment (121) and the second gate line segment (122); and the first refresh rate adjustment circuit (131) is configured to control the connection and disconnection between the first gate line segment (121) and the second gate line segment (122).

Description

Driving circuit, driving method and display device

[0001] The present application claims priority to the Chinese patent application No. 2024107525803, filed on June 12, 2024, and entitled "Driving circuit, driving method and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a driving circuit, a driving method and a display device. BACKGROUND

[0003] With the development of display technology, people's requirements for display panels are also getting higher and higher. For example, when displaying dynamic pictures such as videos and games, the refresh frequency of the display panel needs to be high to prevent flickering, and when displaying static pictures such as web pages, the refresh frequency of the display panel needs to be low to reduce power consumption.

[0004] In current display panels, the same refresh rate is usually used for all pixels. However, in some product applications, different display partitions of the same display panel do not necessarily need to refresh data at the same display frame. If different display partitions of the same display panel, such as static regions and dynamic regions, use the same refresh rate to refresh data, using high refresh rate will increase the power consumption of the display panel, and using low refresh rate will cause flickering when displaying dynamic pictures. In order to realize different refresh rates for different partitions, different gate driving circuits are usually used for different refresh partitions, which will make the frame design of the screen wider and increase the difficulty of wiring. SUMMARY

[0005] The purpose of the present application is to provide a driving circuit, a driving method and a display device, which can increase the transmittance of the display panel.

[0006] The present application discloses a driving circuit, which comprises a plurality of gate lines and a plurality of gate driving units. The input end of each gate line is connected to the output end of a corresponding gate driving unit to receive a gate driving signal and control the opening or closing of a thin film transistor connected to the gate line. Each gate line comprises at least a first gate line segment and a second gate line segment, and a first refresh rate adjustment circuit is arranged between the first gate line segment and the second gate line segment. The first refresh rate adjustment circuit is used to control the conduction and shutdown between the first gate line segment and the second gate line segment.

[0007] The application also discloses a driving method for driving a circuit, the driving circuit comprising a plurality of gate lines and a plurality of gate driving units, an input end of each gate line being connected to an output end of a corresponding gate driving unit to receive a gate driving signal for controlling opening or closing of a thin film transistor connected to the gate line; wherein each gate line comprises at least a first gate line segment and a second gate line segment, and a first refresh rate adjusting circuit is arranged between the first gate line segment and the second gate line segment; the first refresh rate adjusting circuit is used for controlling conduction and non-conduction between the first gate line segment and the second gate line segment.

[0008] The driving method comprises the following steps:

[0009] Before displaying a next frame, a gate driving signal and a data signal are generated;

[0010] Refresh rate data of display areas corresponding to the first gate line segment and the second gate line segment of the next frame are received; and

[0011] When refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are different, the first refresh rate adjusting circuit is controlled to be non-conductive, and the gate driving signal is output to the thin film transistor connected to the first gate line segment and is controlled to be opened; when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are the same, the first refresh rate adjusting circuit is controlled to be conductive, and the gate driving signal is output to the thin film transistor connected to the first gate line segment and the second gate line segment and is controlled to be opened.

[0012] The application also discloses a display device, which comprises a driving circuit and a display panel, the driving circuit being used for driving the display panel; the driving circuit comprises a plurality of gate lines and a plurality of gate driving units, an input end of each gate line being connected to an output end of a corresponding gate driving unit to receive a gate driving signal for controlling opening or closing of a thin film transistor connected to the gate line; wherein each gate line comprises at least a first gate line segment and a second gate line segment, and a first refresh rate adjusting circuit is arranged between the first gate line segment and the second gate line segment; the first refresh rate adjusting circuit is used for controlling conduction and non-conduction between the first gate line segment and the second gate line segment.

[0013] Compared with the scheme that one gate drive circuit is arranged for each partition, the gate line is divided into at least two segments, the refresh rate adjustment circuit is arranged between the gate line segments, the conduction and turn-off between the gate line segments are controlled through the refresh rate adjustment circuit, the refresh rate between the two gate line segments can be changed, the dynamic change of the different refresh rates of the partitions is realized, the gate drive circuit does not need to be arranged for each partition, the frame size is avoided to be increased, the wiring difficulty is increased, the gate line can be divided into multiple segments according to the required partition size, the area size of the partition is adjusted, and the dynamic change of the different refresh rates of the different partitions is realized. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings included are intended to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, serve to explain the principles of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0015] Fig. 1 is a drive circuit schematic diagram of the first embodiment of the present application;

[0016] Fig. 2 is a drive circuit schematic diagram of the second embodiment of the present application;

[0017] Fig. 3 is a drive signal waveform schematic diagram of the second embodiment of the present application;

[0018] Fig. 4 is a drive circuit schematic diagram of the third embodiment of the present application;

[0019] Fig. 5 is a drive signal waveform schematic diagram of the third embodiment of the present application;

[0020] Fig. 6 is a drive circuit schematic diagram of the fourth embodiment of the present application;

[0021] Fig. 7 is a drive signal waveform schematic diagram of the fourth embodiment of the present application;

[0022] Fig. 8 is a drive circuit schematic diagram of the fifth embodiment of the present application;

[0023] Fig. 9 is a drive signal waveform schematic diagram of the fifth embodiment of the present application;

[0024] Fig. 10 is a drive circuit schematic diagram of the sixth embodiment of the present application;

[0025] Fig. 11 is a drive circuit schematic diagram of the seventh embodiment of the present application;

[0026] Fig. 12 is a drive method flowchart schematic diagram of the eighth embodiment of the present application;

[0027] FIG. 13 is a structural schematic diagram of a display device of a ninth embodiment of the present application. DETAILED DESCRIPTION

[0028] It needs to be understood that the terms used herein, the specific structural and functional details disclosed, are only for the purpose of describing specific embodiments, and are representative, but the present application can be embodied in many alternative forms, and should not be interpreted as being limited to the embodiments set forth herein.

[0029] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0030] Referring to FIG. 1, as a first embodiment of the present application, a driving circuit 100 is disclosed, which includes a plurality of gate lines 120 and a plurality of gate driving units 110, an input end of each of the gate lines 120 is connected to an output end of a corresponding one of the gate driving units 110, and receives a gate driving signal to control opening or closing of a thin film transistor connected to the gate line 120; wherein each of the gate lines 120 includes at least a first gate line segment 121 and a second gate line segment 122, and a first refresh rate adjusting circuit 131 is arranged between the first gate line segment 121 and the second gate line segment 122; the first refresh rate adjusting circuit 131 is used to control conduction and turn-off between the first gate line segment 121 and the second gate line segment 122.

[0031] The present application divides the gate line 120 into at least two segments, and a refresh rate adjusting circuit 130 is arranged between the gate line 120 segments, and the conduction and turn-off between the gate line 120 segments is controlled by the refresh rate adjusting circuit 130, so that the refresh rates between the two gate line 120 segments are different, the display of different refresh rates in different partitions is realized, and thus it is not necessary to separately set a gate driving circuit 101 for each partition, the frame size is avoided to be increased, and the wiring difficulty is increased, and the gate line 120 can be divided into multiple segments according to the number and size of the required partitions, the size of the partitioned area is adjusted, and the dynamic change of different refresh rates in different partitions is realized, which provides a basis for any partition of the same display panel 200.

[0032] As shown in FIG. 2 and FIG. 3, as a second embodiment of the present application, which is a further refinement and improvement of the above-mentioned first embodiment, the present embodiment is applicable to liquid crystal display panel 200 and OLED display panel 200, the first refresh rate adjustment circuit 131 includes a first control unit 133 and a second control unit 134, the gate drive unit 110 outputs the gate drive signal to the input end of the first gate line segment 121, the input end of the first control unit 133 is connected to the output end of the first gate line segment 121, the output end is connected to the input end of the second gate line segment 122, and the control end is connected to the first control signal; the input end of the second control unit 134 is connected to the first level signal, the output end is connected to the input end of the second gate line segment 122, and the control end is connected to the second control signal; wherein the first level signal is a low-level signal, and the first control signal and the second control signal are a pair of opposite signals that are alternately turned on at least one frame.

[0033] The first gate line segment 121 corresponds to the first sub-area 210, and the second gate line segment 122 corresponds to the second sub-area 220; the first control unit 133 includes a first control switch T1, and the second control unit 134 includes a second control switch T2; the first control switch T1 and the second control switch T2 are arranged between the first gate line segment 121 and the second gate line segment 122 in each row of gate lines 120; the gate drive signal of each row is input to the second sub-area 220 through the respective first control switch T1 at the end of the first sub-area 210; the present embodiment discloses a design of the first refresh rate adjustment circuit 131 as a circuit structure including two TFTs (T1 & T2), the first control switch T1 is controlled by the frequency reduction signal DF, i.e. the first control signal, and the second control switch T2 is controlled by the second control signal DFB; DF and DFB are a pair of opposite signals, and the first level signal is a relatively low-voltage constant voltage source.

[0034] If the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are different, in the first time period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, the first refresh rate adjusting circuit 131 disconnects the first gate line segment 121 and the second gate line segment 122, and inputs a first level signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned off; in the second time period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, the first refresh rate adjusting circuit 131 connects the first gate line segment 121 and the second gate line segment 122, and inputs a gate driving signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned on; so that the area of the first gate line segment 121 realizes display at the first refresh rate, and the area of the second gate line segment 122 realizes display at the second refresh rate, wherein the first refresh rate is n times of the second refresh rate, and the multiple relationship between the first refresh rate and the second refresh rate is determined by the interval time setting of the first time period and the second time period; if the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are the same, the first refresh rate adjusting circuit 131 keeps conducting in the first time period and the second time period, and the first time period and the second time period are continuous time periods, that is, the end time of the first time period is the start time of the second time period.

[0035] As shown in FIG. 4 and FIG. 5, as a third embodiment of the present application, and further refinement and perfection of the above-mentioned second embodiment, the present embodiment mainly aims at further improvement of the OLED display panel 200, the driving circuit 100 comprises an OLED pixel driving circuit 102, the OLED pixel driving circuit 102 further comprises a plurality of cascaded light-emitting control lines 140, the light-emitting control lines 140 are arranged in parallel and one-to-one corresponding to the gate lines 120, the light-emitting control lines 140 comprise a first light-emitting control line segment 141 and a second light-emitting control line segment 142, and a light-emitting control circuit 150 is arranged between the first light-emitting control line segment 141 and the second light-emitting control line segment 142, the light-emitting control circuit 150 is used for controlling the conduction and turn-off between the first light-emitting control line segment 141 and the second light-emitting control line segment 142; the light-emitting control circuit 150 and the first refresh rate adjusting circuit 131 can use the same control signal, i.e. the first control signal and the second control signal; wherein the light-emitting control circuit 150 comprises a first light-emitting control unit 151 and a second light-emitting control unit 152, the input end of the first light-emitting control unit 151 is connected to the output end of the first light-emitting control line segment 141, the output end is connected to the input end of the second light-emitting control line segment 142, and the control end is connected to the first control signal; the input end of the second light-emitting control unit 152 is connected to the second level signal, the output end is connected to the input end of the second light-emitting control line segment 142, and the control end is connected to the second control signal.

[0036] Wherein the first light-emitting control unit 151 comprises a first light-emitting control switch T1', and the second light-emitting control unit 152 comprises a second light-emitting control switch T2', in the present embodiment, the gate lines 120 and the light-emitting control lines 140 of the OLED display panel 200 are both segmented, and the segmented positions are in the same column region, i.e. the lengths of the two segments after segmentation of the gate lines 120 are the same as the lengths of the two segments after segmentation of the light-emitting control lines 140, and the widths of the corresponding display regions are consistent.

[0037] In the OLED pixel driving circuit 102, one sub-pixel corresponding pixel driving circuit 100 usually has at least two TFT devices, wherein the TFT responsible for resetting and data writing only needs to be turned on for a short time within a frame time, and the driving signal required by such TFT is called Scan signal; another TFT responsible for controlling light emission only needs to be turned off for a short time within a frame time, and the driving signal required by such TFT is called light emission control signal Emit, Emit signal is output by light emission control line 140, in OLED display panel 200, the frequency change of different partitions of display panel 200 needs the frequency of Scan signal and Emit signal to change at the same time; as shown in Figure 3, wherein E(1~n) is the signal waveform of a certain Emit signal of the entire screen n rows of pixels in the first partition 210, each E(n) is at a low potential for a short time within a frame time, and is shifted by one row period (1 / n frame period) for each line; E'(1~n) is the Emit signal input waveform of n rows of pixels in the corresponding second partition 220, wherein DF and DFB are a pair of opposite signals that are alternately turned on every frame, and the second level signal is a relatively high voltage constant voltage source.

[0038] When the refresh rates of the two display areas corresponding to the first gate line segment and the second gate line segment 122 are different, taking the refresh rate of the first partition 210 as twice the refresh rate of the second partition 220 as an example, for example, the refresh rate of the first partition 210 is 120Hz, and the refresh rate of the second partition 220 is 60Hz; in the first time period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected by the first gate line segment 121 to be turned on, the first refresh rate adjusting circuit 131 disconnects the connection between the first gate line segment 121 and the second gate line segment 122, and inputs a first level signal to the second gate line segment 122 to control the thin film transistor connected by the second gate line segment 122 to be turned off, the light emission control signal will be turned off for a short time after each pixel in the first partition 210 emits light, and the light emission control signal will be turned off for a frame time after each pixel in the second partition 220 emits light; in the second time period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected by the first gate line segment 121 to be turned on, the first refresh rate adjusting circuit 131 connects the first gate line segment 121 and the second gate line segment 122, and inputs a gate driving signal to the second gate line segment 122 to control the thin film transistor connected by the second gate line segment 122 to be turned on; so that the area of the first gate line segment 121 realizes 120Hz refresh rate display, and the area of the second gate line segment 122 realizes 60Hz refresh rate display.

[0039] As shown in FIG. 6 and FIG. 7, as the fourth embodiment of the present application, the driving circuit 100 further comprises a level signal control circuit 160, which comprises a first driving switch Ta and a second driving switch Tb; the first refresh rate adjustment circuit 131 comprises a first control switch T1 and a second control switch T2; the driving circuit 100 comprises an OLED pixel driving circuit 102, which further comprises a plurality of cascaded light-emitting control lines 140, which are arranged in parallel with and one-to-one corresponding to the gate lines 120; the light-emitting control lines 140 comprise a first light-emitting control line segment 141 and a second light-emitting control line segment 142, and a first light-emitting control switch T1' and a second light-emitting control switch T2' are arranged between the first light-emitting control line segment 141 and the second light-emitting control line segment 142; the input end of the first control switch T1 is connected to the output end of the first gate line segment 121, the output end is connected to the input end of the second gate line segment 122, and the control end is connected to the first control signal; the input end of the second control switch T2 is connected to the first level signal, the output end is connected to the input end of the second gate line segment 122, and the control end is connected to the output end of the first driving switch Ta; the input end of the first light-emitting control switch T1' is connected to the output end of the first light-emitting control line segment 141, the output end is connected to the input end of the second light-emitting control line segment 142, and the control end is connected to the first control signal; the input end of the second light-emitting control switch T2' is connected to the second level signal, the output end is connected to the input end of the second light-emitting control line segment 142, and the control end is connected to the output end of the first driving switch Ta; wherein the first driving switch Ta is a three-terminal TFT device, and the second driving switch Tb is a four-terminal TFT device, which has a bottom gate compared with the three-terminal device of the first driving switch Ta, and the bottom gate voltage can adjust the threshold voltage of the TFT.

[0040] Further, the control end of the first driving switch Ta is connected with a first control signal, the input end is connected with a first level signal, the output end is connected with the control end of the second control switch T2 and the second light-emitting control switch T2', and the first control end of the second driving switch Tb; the input end of the second driving switch Tb is connected with a second level signal and a second control end, and the output end is connected with the first control end; the first level signal is a low level signal, and the second level signal is a high level signal; the gate line 120 and the light-emitting control line 140 of the OLED display panel 200 are both subjected to segmented processing, and the segmented positions are in the same column region, that is, the lengths of the two segments after the gate line 120 is segmented are the same as the lengths of the two segments after the light-emitting control line 140 is segmented, and the widths of the corresponding display regions are consistent; in the case of fixed partition, the input waveform of the second partition 220 can be adjusted by adjusting the duty ratio of the DF signal, so as to realize the refresh rate adjustment of the second partition 220, so that the refresh rate of the second partition 220 is 1 / n (n is a positive integer) of the refresh rate of the first partition 210, as shown in FIG. 7.

[0041] The embodiment can cancel the direct input of the DFB signal from the external drive, and automatically generate the DFB signal opposite to the DF through the DF signal and VGH / VGL. Specifically, in the first stage: when the DF is a high voltage (such as 15V), at this time, Ta is opened, and the VGL voltage (such as -7V) is written to the DFB node; at the moment of writing the low voltage, since the bottom gate of Tb is controlled by VGH, the potential is relatively high (such as 15V), so Tb remains open, and VGH&VGL are simultaneously output to the DFB node. Through the design of the size of the TFT device, such as (Ta Width) > 10*(Tb Width), therefore, the DFB node is gradually written to a low potential by VGL; in the second stage: when the DF is converted to a low voltage (such as a voltage of -7V), the VGL is a low voltage (such as -7V), at this time, Ta is closed, so VGH continuously outputs a high voltage (15V) to DFB through Tb.

[0042] As shown in FIG. 8 and FIG. 9, as the fifth embodiment of the present application, it is a further extension of any of the above embodiments, the each row of gate lines 120 further comprises a third gate line segment 123, that is, a gate line 120 is divided into three segments, wherein the driving circuit 100 further comprises a second refresh rate adjustment circuit 132, the second refresh rate adjustment circuit 132 is arranged between the second gate line segment 122 and the third gate line segment 123; the second refresh rate adjustment circuit 132 is used to control the conduction and turn-off between the second gate line segment 122 and the third gate line segment 123; the plurality of gate driving units 110 are divided into a first group of gate driving units 111 and a second group of gate driving units 112, the first group of gate driving units 111 and the second group of gate driving units 112 are respectively arranged at both ends of the gate line 120, the first group of gate driving units 111 is connected with the input end of the first gate line segment 121, and the second group of gate driving units 112 is connected with the input end of the third gate line segment 123.

[0043] The embodiment can divide the display area of the display panel 200 into three areas, i.e., divide each row of the gate lines 120 into three segments, the first gate line segment 121 corresponds to the first sub-area 210, the second gate line segment 122 corresponds to the second sub-area 220, and the third gate line segment 123 corresponds to the third sub-area 230. The refresh rate adjustment circuit 130 is arranged between the adjacent two ends to control the connection between the adjacent two gate line segments 120. Generally, in order to avoid the signal distortion or the voltage reduction caused by the decrease in brightness of the area far away from the gate driving circuit 101 due to the overlong gate line 120 in the case of large size, the gate driving unit 110 is arranged on both sides of the display panel 200. The first refresh rate adjustment circuit 131 and the second refresh rate adjustment circuit 132 control the refresh rates of the three areas in combination. If the refresh rates of the first sub-area 210 and the third sub-area 230 are the same, in the first time period or the first frame time, the first sub-area 210 and the third sub-area 230 simultaneously receive the gate driving signal, and the two refresh rate adjustment circuits 130 are disconnected between the first gate line segment 121 and the second gate line segment 122 and between the second gate line segment 122 and the third gate line segment 123. In the second time period or the second frame time, the first sub-area 210, the second sub-area 220, and the third sub-area 230 simultaneously receive the gate driving signal, and one of the refresh rate adjustment circuits 130 between the first gate line segment 121 and the second gate line segment 122 and between the second gate line segment 122 and the third gate line segment 123 is turned on. In addition, if the first refresh rate is 120 Hz, the second refresh rate is 60 Hz, and the third refresh rate is 30 Hz, in the first time period, both of the refresh rate adjustment circuits 130 are closed, and the second gate driving unit group 112 does not input the gate driving signal to the third gate line segment 123, that is, only the first sub-area 210 displays. In the second time period, the first refresh rate adjustment circuit 131 is turned on, the second refresh rate adjustment circuit 132 remains closed, the first sub-area 210 and the second sub-area 220 display, and the third sub-area 230 does not display. In the third time period, the first refresh rate adjustment circuit 131 and the second refresh rate adjustment circuit 132 are both turned on, the first sub-area 210, the second sub-area 220, and the third sub-area 230 all display, and the gate line segment 120 in the third sub-area 230 receives the driving signal of the second gate driving unit group 112.

[0044] Further, the waveforms of the first control signal and the second control signal of the first refresh rate adjustment circuit and the second refresh rate adjustment circuit can be the same or different. Assuming that the first control signal of the first refresh rate adjustment circuit is DF1, the second control signal is DFB1, the first control signal of the second refresh rate adjustment circuit is DF2, and the second control signal is DFB2, when the three regions display the same refresh rate, the waveforms of DF1 and DF2 are the same, and the waveforms of DFB1 and DFB2 are also the same. When the refresh rates of the middle region and the two side regions are different, the waveforms of DF1 and DF2 are different, and the waveforms of DFB1 and DFB2 are also different. Assuming that the refresh rate of the middle region is 60 Hz, and the refresh rate of the two side regions is 120 Hz, when DF1 is high, DF2 is low, or when DF1 is low, DF2 is high.

[0045] It should be particularly pointed out that the second subregion 220 can display at 120 Hz, and the first subregion 210 and the third subregion 230 can display at 60 Hz. Specifically, the driving circuit 100 includes a frame start signal generation module 170, which is connected to the first gate drive unit group 111 and the second gate drive unit group 112, respectively. When the refresh rate of the region corresponding to the second gate line segment 122 is 2N, and the refresh rate of the regions corresponding to the first gate line segment 121 and the third gate line segment 123 is N, the frame start signal generation module 170 generates a first frame start signal and a second frame start signal, respectively, and outputs them to the odd row gate drive unit 110 and the even row gate drive unit 110 of the first gate drive unit group 111, so that the first gate drive unit group 111 generates corresponding gate drive signals. The frame start signal generation module 170 generates a third frame start signal and a fourth frame start signal, and outputs them to the even row gate drive unit 110 and the odd row gate drive unit 110 of the second gate drive unit group 112, so that the second gate drive unit group 112 generates corresponding drive signals. The gate drive signals generated by the first gate drive unit group 111 are input to the first gate line segment 121 and the second gate line segment 122, and the gate drive signals generated by the second gate drive unit group 112 are input to the third gate line segment 123 and the second gate line segment 122.

[0046] The second partition 220 can be given a driving signal when the first partition 210 is displayed, and the second partition 220 can also be given a driving signal when the third partition 230 is displayed, and the driving signals of the first partition 210 and the third partition 230 can be cross staggered, that is, when the first row of the first partition 210 is displayed, the first row of the second partition 220 is synchronously displayed, after the first row of the first partition 210 is displayed, the second row of the third partition 230 starts to be displayed, and at the same time, the second row of the second partition 220 is also synchronously displayed, which is equivalent to that in four frames of time, the first partition 210 displays two frames, does not display two frames, the third partition 230 also displays two frames, does not display two frames, the two frames of time in which the first partition 210 does not display are in which the third partition 230 displays, the two frames of time in which the third partition 230 does not display are in which the first partition 210 displays, and the second partition 220 displays in four frames of time, so the refresh rate of the middle region can be doubled.

[0047] As shown in FIG. 10, as a sixth embodiment of the present application, it is a further expansion of any of the above embodiments, the gate line 120 of each row further comprises a third gate line segment 123, the driving circuit 100 further comprises a second refresh rate adjustment circuit 132, the second refresh rate adjustment circuit 132 is arranged between the second gate line segment 122 and the third gate line segment 123; the second refresh rate adjustment circuit 132 is used to control the conduction and turn-off between the second gate line segment 122 and the third gate line segment 123; wherein the plurality of gate driving units 110 are divided into a first gate driving unit group 111, a second gate driving unit group 112 and a third gate driving unit group 113, the first gate driving unit group 111 and the second gate driving unit group 112 are respectively arranged at both ends of the gate line 120, the input end of the first gate line segment 121 is connected with the first gate driving unit group 111, the input end of the third gate line segment 123 is connected with the second gate driving unit group 112, and the third gate driving unit group 113 is connected to the input segment of the second gate line segment 122 through a wire.

[0048] In the present example, the gate driving unit 110 is divided into three groups, each group corresponds to control a partition, but the first gate driving unit group 111 can control two partitions of the first partition 210 and the second partition 220 in combination with the first refresh rate adjustment circuit 131, when the second partition 220 wants to realize a refresh rate higher than that of the partitions on both sides, a driving signal can be inputted and controlled by the second gate driving unit group 112.

[0049] As shown in FIG. 11, as a seventh embodiment of the present application, it is a further extension of the above-mentioned first embodiment, the first refresh rate adjustment circuit 131 includes a first control unit 133 and a second control unit 134, and different from the above-mentioned second embodiment, the output end of the first control unit 133 is connected to the output end of the first gate line segment 121, the input end is connected to the input end of the second gate line segment 122, and the output end of the gate drive unit 110 receives the gate drive signal, and the control end is connected to the first control signal; the input end of the second control unit 134 is connected to the first level signal, the output end is connected to the input end of the first gate line segment 121, and the control end is connected to the second control signal; wherein the first level signal is a low level signal, and the first control signal and the second control signal are a pair of opposite signals that are alternately turned on frame by frame.

[0050] In this example, the gate drive signal is first input into the second partition 220, and then output to the first partition 210 or the third partition 230 through the refresh rate adjustment circuit 130, so that the refresh rate of the middle partition is greater than that of the two side partitions. Of course, the original partition refresh rate changing mode can also be continued, that is, the gate drive signal is first given to the gate line 120 segment of the two side partitions to realize the refresh rate changing mode of decreasing refresh rate from the two sides to the middle. The two modes can be combined for use, that is, the refresh rate can be decreased from the middle to the two sides, or the refresh rate can be decreased from the two sides to the middle area, or the refresh rate can be sequentially decreased from the left side to the right side, and other adjustment modes can be realized, thereby improving the degree of freedom of partition refresh rate changing.

[0051] As shown in FIG. 12, as an eighth embodiment of the present application, a driving method is also disclosed, which is used to drive the driving circuit 100 as described in any of the above embodiments, and the driving method includes the following steps:

[0052] S1: generating a gate drive signal and a data signal before displaying the next frame;

[0053] S2: receiving refresh rate data of the display area corresponding to the first gate line segment and the second gate line segment of the next frame;

[0054] S3: when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are different, controlling the first refresh rate adjustment circuit to be turned off, and the gate drive signal is output to the thin film transistor connected to the first gate line segment and turned on; when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are the same, controlling the first refresh rate adjustment circuit 131 to be turned on, and the gate drive signal is output to the thin film transistor connected to the first gate line segment 121 and the second gate line segment 122 and turned on.

[0055] Referring to FIG. 2 and FIG. 12, in the embodiment, the adjustment of the partition refresh rate is mainly realized by controlling the first refresh rate adjustment circuit 131 to be turned off and turned on; generally, if the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are both 120Hz in the current frame, if the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are adjusted to be different, then in the first time period, the first refresh rate adjustment circuit 131 disconnects the connection between the first gate line segment 121 and the second gate line segment 122, the gate drive unit 110 outputs a gate drive signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, and at the same time, inputs a first level signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned off, so as to clear the residual voltage of the pixels corresponding to the second gate line segment 122; in the second time period, the gate drive unit 110 outputs a gate drive signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, the first refresh rate adjustment circuit 131 turns on the connection between the first gate line segment 121 and the second gate line segment 122, and inputs a gate drive signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned on; so that the area of the first gate line segment 121 realizes display at the first refresh rate, and the area of the second gate line segment 122 realizes display at the second refresh rate, wherein the first refresh rate is n times of the second refresh rate, and the multiple relationship between the first refresh rate and the second refresh rate is determined by the interval time setting of the first time period and the second time period; if the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are the same, the first refresh rate adjustment circuit 131 keeps being turned on in the first time period and the second time period, and the first time period and the second time period are continuous time periods, that is, the end time of the first time period is the start time of the second time period.

[0056] As shown in FIG. 13, as an eighth embodiment of the present application, the present application further discloses a display device 300, which comprises the driving circuit 100 for driving the display panel 200 and the display panel 200, the driving circuit 100 comprises the gate driving circuit 101, the gate driving circuit comprises a plurality of gate driving units 110, the gate driving unit 110 receives the frame start signal generated by the frame start signal generation module 170 of the timing control chip 180 and generates the gate driving signal by the clock signal to be output to the segmented gate line segment, and the change of the partition refresh rate is realized by combining the control circuit of the refresh rate adjustment circuit; on the basis of not increasing the additional gate driving circuit, the frequency reduction module, i.e. the refresh rate adjustment circuit, is adopted to realize the refresh partition design of more than or equal to 3 partitions in the horizontal direction, so that the power consumption is reduced, and the additional product frame is not increased.

[0057] It should be noted that the steps involved in the present scheme are not limited to the order of execution, i.e. the steps written in the front can be executed first, or executed later, or even executed simultaneously, as long as the present scheme can be implemented, which should be considered as belonging to the protection scope of the present application. The inventive concept of the present application can form very many embodiments, but the length of the application file is limited and cannot be listed one by one, therefore, on the premise of not conflicting, the above described embodiments or technical features can be combined to form new embodiments, and the combination of each embodiment or technical feature will enhance the original technical effect.

[0058] The above is a further detailed description of the present application in combination with specific optional embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A drive circuit, wherein, The driving circuit comprises a plurality of gate lines and a plurality of gate driving units, an input end of each gate line is connected to an output end of a corresponding gate driving unit, and receives a gate driving signal to control opening or closing of a thin film transistor connected to the gate line. The first refresh rate adjustment circuit is arranged between the first gate line segment and the second gate line segment, and is configured to control conduction and non-conduction between the first gate line segment and the second gate line segment.

2. The drive circuit of claim 1, wherein, The first refresh rate adjustment circuit comprises a first control unit and a second control unit, the gate driving unit outputs a gate driving signal to an input end of the first gate line segment, an input end of the first control unit is connected to an output end of the first gate line segment, an output end of the first control unit is connected to an input end of the second gate line segment, and a control end of the first control unit is connected to a first control signal; an input end of the second control unit is connected to a first level signal, an output end of the second control unit is connected to the input end of the second gate line segment, and a control end of the second control unit is connected to a second control signal. The first level signal is a low-level signal, and the first control signal and the second control signal are a pair of opposite signals that are alternately turned on at least once every frame.

3. The drive circuit of claim 2, wherein, The driving circuit comprises an OLED pixel driving circuit, the OLED pixel driving circuit further comprises a plurality of light-emitting control lines arranged in cascade, the light-emitting control lines are arranged in parallel with and one-to-one correspondence with the gate lines, the light-emitting control lines comprise a first light-emitting control line segment and a second light-emitting control line segment, and a light-emitting control circuit is arranged between the first light-emitting control line segment and the second light-emitting control line segment, and the light-emitting control circuit is configured to control conduction and non-conduction between the first light-emitting control line segment and the second light-emitting control line segment. The light-emitting control circuit comprises a first light-emitting control unit and a second light-emitting control unit, an input end of the first light-emitting control unit is connected to an output end of the first light-emitting control line segment, an output end of the first light-emitting control unit is connected to an input end of the second light-emitting control line segment, and a control end of the first light-emitting control unit is connected to a first control signal; an input end of the second light-emitting control unit is connected to a second level signal, an output end of the second light-emitting control unit is connected to the input end of the second light-emitting control line segment, and a control end of the second light-emitting control unit is connected to a second control signal.

4. The drive circuit of claim 1, wherein, The driving circuit further comprises a level signal control circuit, and the level signal control circuit comprises a first driving switch and a second driving switch. The first refresh rate adjustment circuit comprises a first control switch and a second control switch. The driving circuit comprises an OLED pixel driving circuit, the OLED pixel driving circuit further comprises a plurality of light-emitting control lines arranged in cascade, the light-emitting control lines are arranged in parallel with and one-to-one correspondence with the gate lines, the light-emitting control lines comprise a first light-emitting control line segment and a second light-emitting control line segment, and a first light-emitting control switch and a second light-emitting control switch are arranged between the first light-emitting control line segment and the second light-emitting control line segment. An input end of the first control switch is connected to an output end of the first gate line segment, an output end of the first control switch is connected to an input end of the second gate line segment, and a control end of the first control switch is connected to a first control signal. The input end of the second control switch is connected with a first level signal, the output end is connected with the input end of the second gate line segment, and the control end is connected with the output end of the first drive switch; The input end of the first light-emitting control switch is connected with the output end of the first light-emitting control line segment, the output end is connected with the input end of the second light-emitting control line segment, and the control end is connected with a first control signal; The input end of the second light-emitting control switch is connected with a second level signal, the output end is connected with the input end of the second light-emitting control line segment, and the control end is connected with the output end of the first drive switch; The control end of the first drive switch is connected with the first control signal, the input end is connected with the first level signal, the output end is connected with the control end of the second control switch and the second light-emitting control switch, and the first control end of the second drive switch; The input end of the second drive switch is connected with the second level signal and the second control end, and the output end is connected with the first control end. The first level signal is a low level signal, and the second level signal is a high level signal.

5. The drive circuit of claim 2, wherein, The driving circuit further comprises a second refresh rate adjustment circuit, which is arranged between the second gate line segment and the third gate line segment; the second refresh rate adjustment circuit is used for controlling the conduction and the turn-off between the second gate line segment and the third gate line segment. The plurality of gate drive units are divided into a first gate drive unit group and a second gate drive unit group, the first gate drive unit group and the second gate drive unit group are arranged at two ends of the gate line respectively, the input end of the first gate line segment is connected with the first gate drive unit group, and the input end of the third gate line segment is connected with the second gate drive unit group.

6. The drive circuit of claim 5, wherein, The driving circuit comprises a frame start signal generation module, and the frame start signal generation module is connected with the first gate drive unit group and the second gate drive unit group respectively. When the refresh rate of the region corresponding to the second gate line segment is 2N, and the refresh rate of the regions corresponding to the first gate line segment and the third gate line segment is N, the frame start signal generation module generates a first frame start signal and a second frame start signal respectively, and outputs the first frame start signal and the second frame start signal to the odd row gate drive units and the even row gate drive units of the first gate drive unit group, so that the first gate drive unit group generates corresponding gate drive signals; the frame start signal generation module generates a third frame start signal and a fourth frame start signal, and outputs the third frame start signal and the fourth frame start signal to the even row gate drive units and the odd row gate drive units of the second gate drive unit group, so that the second gate drive unit group generates corresponding drive signals; The gate drive signals generated by the first gate drive unit group are input to the first gate line segment and the second gate line segment, and the gate drive signals generated by the second gate drive unit group are input to the third gate line segment and the second gate line segment.

7. The drive circuit of claim 1, wherein, The each row of gate lines further comprises a third gate line segment, and the driving circuit further comprises a second refresh rate adjusting circuit, which is arranged between the second gate line segment and the third gate line segment; the second refresh rate adjusting circuit is used for controlling the turn-on and turn-off between the second gate line segment and the third gate line segment. The multiple gate driving units are divided into a first gate driving unit group, a second gate driving unit group and a third gate driving unit group, the first gate driving unit group and the second gate driving unit group are arranged at two ends of the gate line respectively, the first gate driving unit group is connected with the input end of the first gate line segment, the second gate driving unit group is connected with the input end of the third gate line segment, and the third gate driving unit group is connected to the input segment of the second gate line segment through a wire.

8. The drive circuit of claim 1, wherein, The first refresh rate adjusting circuit comprises a first control unit and a second control unit, the output end of the first control unit is connected with the output end of the first gate line segment, the input end is connected with the input end of the second gate line segment and the output end of the gate driving unit receives a gate driving signal, and the control end is connected with a first control signal; The input end of the second control unit is connected with a first level signal, the output end is connected with the input end of the first gate line segment, and the control end is connected with a second control signal; The first level signal is a low level signal, and the first control signal and the second control signal are a pair of opposite signals which are alternately turned on frame by frame.

9. The drive circuit of claim 1, wherein, The gate line is divided into multiple segments according to the number of partitions, and the refresh rates of different partitions are different.

10. The drive circuit of claim 2, wherein, The first gate line segment corresponds to a first partition, and the second gate line segment corresponds to a second partition; the first control unit comprises a first control switch, and the second control unit comprises a second control switch; the first control switch and the second control switch are arranged between the first gate line segment and the second gate line segment in each row of gate lines, and the gate driving signal of each row is input into the second partition through the respective first control switch at the end of the first partition.

11. The drive circuit of claim 3, wherein, The gate line and the light emitting control line are both segmented, and the segmented positions are in the same column region; the lengths of the two segments of the gate line after segmentation are the same as the lengths of the two segments of the light emitting control line after segmentation, and the widths of the corresponding display regions are consistent.

12. The drive circuit of claim 5, wherein, The first gate line segment corresponds to a first partition, the second gate line segment corresponds to a second partition, and the third gate line segment corresponds to a third partition; a refresh rate adjusting circuit is arranged between the two adjacent gate line segments to control the connection between the two adjacent gate line segments; the first gate driving unit and the second gate driving unit are arranged at two sides of the display panel respectively.

13. A driving method for driving a circuit, wherein, The driving circuit comprises multiple rows of gate lines and multiple gate driving units, the input end of each row of gate lines is connected with the output end of a corresponding gate driving unit, receives a gate driving signal, and controls the opening or closing of a thin film transistor connected with the gate line; The first gate line segment and the second gate line segment are provided with a first refresh rate adjustment circuit; the first refresh rate adjustment circuit is used for controlling the turn-on and turn-off between the first gate line segment and the second gate line segment. The driving method comprises the steps of: generating a gate driving signal and a data signal before displaying a next frame of picture; receiving refresh rate data of display areas corresponding to the first gate line segment and the second gate line segment of the next frame; and when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are different, controlling the first refresh rate adjustment circuit to turn off, and the gate driving signal being output to a thin film transistor connected to the first gate line segment and turned on; when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are the same, controlling the first refresh rate adjustment circuit to turn on, and the gate driving signal being output to thin film transistors connected to the first gate line segment and the second gate line segment and turned on.

14. The driving method of claim 13, wherein, The first refresh rate adjustment circuit comprises a first control unit and a second control unit, the gate driving unit outputs a gate driving signal to an input end of the first gate line segment, an input end of the first control unit is connected to an output end of the first gate line segment, an output end of the first control unit is connected to an input end of the second gate line segment, and a control end of the first control unit is connected to a first control signal; an input end of the second control unit is connected to a first level signal, an output end of the second control unit is connected to the input end of the second gate line segment, and a control end of the second control unit is connected to a second control signal; The first level signal is a low-level signal, and the first control signal and the second control signal are a pair of opposite signals which are alternately turned on at least once per frame; The step of when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are different, controlling the first refresh rate adjustment circuit to turn off, and the gate driving signal being output to a thin film transistor connected to the first gate line segment and turned on; when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are the same, controlling the first refresh rate adjustment circuit to turn on, and the gate driving signal being output to thin film transistors connected to the first gate line segment and the second gate line segment and turned on comprises the steps of: If the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment are different, in a first time period, the gate drive unit outputs a gate drive signal to the first gate line segment to control the thin film transistor connected by the first gate line segment to open, the first refresh rate adjustment circuit disconnects the first gate line segment and the second gate line segment, and inputs a first level signal to the second gate line segment to control the thin film transistor connected by the second gate line segment to close; in a second time period, the gate drive unit outputs a gate drive signal to the first gate line segment to control the thin film transistor connected by the first gate line segment to open, the first refresh rate adjustment circuit connects the first gate line segment and the second gate line segment, and inputs a gate drive signal to the second gate line segment to control the thin film transistor connected by the second gate line segment to open; so that the area of the first gate line segment realizes display of the first refresh rate, and the area of the second gate line segment realizes display of the second refresh rate. If the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment are the same, the first refresh rate adjustment circuit keeps conducting in the first time period and the second time period.

15. The driving method of claim 13, wherein, The gate line further comprises a third gate line segment, and the driving circuit further comprises a second refresh rate adjustment circuit, which is arranged between the second gate line segment and the third gate line segment; the second refresh rate adjustment circuit is used for controlling the conduction and the disconnection between the second gate line segment and the third gate line segment. The plurality of gate drive units are divided into a first gate drive unit group and a second gate drive unit group, the first gate drive unit group and the second gate drive unit group are arranged at two ends of the gate line, the first gate drive unit group is connected with the input end of the first gate line segment, and the second gate drive unit group is connected with the input end of the third gate line segment; the first gate line segment corresponds to a first sub-area, the second gate line segment corresponds to a second sub-area, and the third gate line segment corresponds to a third sub-area. When the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are different, the first refresh rate adjustment circuit is controlled to be disconnected, and the gate drive signal is output to the thin film transistor connected by the first gate line segment and is controlled to open; when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are the same, the first refresh rate adjustment circuit is controlled to be connected, and the gate drive signal is output to the thin film transistor connected by the first gate line segment and the second gate line segment and is controlled to open. If the refresh rates of the first subregion and the third subregion are the same, and the refresh rates of the first subregion and the second subregion are different, in the first time period or the first frame time, the first subregion and the third subregion simultaneously receive the gate driving signals, the two refresh rate adjustment circuits are disconnected between the first gate line segment and the second gate line segment, and between the second gate line segment and the third gate line segment, and in the second time period or the second frame time, the first subregion, the second subregion and the third subregion simultaneously receive the gate driving signals, and one of the refresh rate adjustment circuits between the first gate line segment and the second gate line segment, and between the second gate line segment and the third gate line segment is turned on; If the refresh rates of the first subregion, the second subregion and the third subregion are different, in the first time period, the two refresh rate adjustment circuits are turned off, and the second gate driving unit group does not input the gate driving signal to the third gate line segment, and the first subregion displays; in the second time period, the first refresh rate adjustment circuit is turned on, the second refresh rate adjustment circuit remains turned off, the first subregion and the second subregion display, and the third subregion does not display, and in the third time period, the first refresh rate adjustment circuit and the second refresh rate adjustment circuit are both turned on, and the first subregion, the second subregion and the third subregion all display, and the gate line segment in the third subregion receives the driving signal of the second gate driving unit group.

16. The driving method of claim 14, wherein, The driving circuit further comprises a level signal control circuit, and the level signal control circuit comprises a first driving switch and a second driving switch. The first refresh rate adjustment circuit comprises a first control switch and a second control switch. The driving circuit comprises an OLED pixel driving circuit, and the OLED pixel driving circuit further comprises a plurality of light-emitting control lines arranged in cascade, the light-emitting control lines are arranged in parallel with and one-to-one correspondence with the gate lines, the light-emitting control lines comprise a first light-emitting control line segment and a second light-emitting control line segment, and a first light-emitting control switch and a second light-emitting control switch are arranged between the first light-emitting control line segment and the second light-emitting control line segment. The input end of the first control switch is connected to the output end of the first gate line segment, the output end is connected to the input end of the second gate line segment, and the control end is connected to the first control signal. The input end of the second control switch is connected to the first level signal, the output end is connected to the input end of the second gate line segment, and the control end is connected to the output end of the first driving switch. The input end of the first light-emitting control switch is connected to the output end of the first light-emitting control line segment, the output end is connected to the input end of the second light-emitting control line segment, and the control end is connected to the first control signal. The input end of the second light-emitting control switch is connected to the second level signal, the output end is connected to the input end of the second light-emitting control line segment, and the control end is connected to the output end of the first driving switch. The control end of the first driving switch is connected to the first control signal, the input end is connected to the first level signal, and the output end is connected to the control ends of the second control switch and the second light-emitting control switch, and the first control end of the second driving switch. The input end of the second driving switch is connected to the second level signal and the second control end, and the output end is connected to the first control end. The first level signal is a low level signal, and the second level signal is a high level signal. When the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are different, the first refresh rate adjustment circuit is controlled to be turned off, and the gate drive signal is output to the thin film transistor connected to the first gate line segment and is turned on. If the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment are different, in a first time period, the gate drive unit outputs a gate drive signal to the first gate line segment to control the first control switch connected to the first gate line segment to be turned on, the first refresh rate adjustment circuit disconnects the connection between the first gate line segment and the second gate line segment, and inputs a first level signal to the second gate line segment to control the second control switch connected to the second gate line segment to be turned off; in a second time period, the gate drive unit outputs a gate drive signal to the first gate line segment to control the first control switch connected to the first gate line segment to be turned on, the first refresh rate adjustment circuit connects the first gate line segment and the second gate line segment, and inputs a gate drive signal to the second gate line segment to control the second control switch connected to the second gate line segment to be turned on; so that the area of the first gate line segment realizes display at the first refresh rate, and the area of the second gate line segment realizes display at the second refresh rate. If the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment are the same, the first refresh rate adjustment circuit remains turned on in the first time period and the second time period.

17. The driving method of claim 14, wherein, The first refresh rate is n times of the second refresh rate, and the multiple relationship between the first refresh rate and the second refresh rate is determined by the interval time setting of the first time period and the second time period. The first time period and the second time period are consecutive time periods, that is, the end time of the first time period is the start time of the second time period.

18. A display device, wherein, The display device includes a driving circuit and a display panel, the driving circuit is used for driving the display panel, the driving circuit includes a plurality of gate lines and a plurality of gate drive units, the input end of each gate line is connected to the output end of a corresponding gate drive unit, receives a gate drive signal, and controls the opening or closing of the thin film transistor connected to the gate line. The first gate line segment and the second gate line segment are connected by the first refresh rate adjustment circuit.

19. The display device of claim 18, wherein, The driving circuit further includes a level signal control circuit, and the level signal control circuit includes a first driving switch and a second driving switch. The first refresh rate adjustment circuit includes a first control switch and a second control switch. The first level signal is a low level signal, and the second level signal is a high level signal. The driving circuit comprises an OLED pixel driving circuit, the OLED pixel driving circuit further comprises a plurality of light-emitting control lines arranged in cascade, the light-emitting control lines are arranged in parallel and one-to-one correspondence with the gate lines, the light-emitting control lines comprise a first light-emitting control line segment and a second light-emitting control line segment, and a first light-emitting control switch and a second light-emitting control switch are arranged between the first light-emitting control line segment and the second light-emitting control line segment; The input end of the first control switch is connected to the output end of the first gate line segment, the output end is connected to the input end of the second gate line segment, and the control end is connected to a first control signal; The input end of the second control switch is connected to a first voltage level signal, the output end is connected to the input end of the second gate line segment, and the control end is connected to the output end of the first driving switch; The input end of the first light-emitting control switch is connected to the output end of the first light-emitting control line segment, the output end is connected to the input end of the second light-emitting control line segment, and the control end is connected to the first control signal; The input end of the second light-emitting control switch is connected to a second voltage level signal, the output end is connected to the input end of the second light-emitting control line segment, and the control end is connected to the output end of the first driving switch; The control end of the first driving switch is connected to the first control signal, the input end is connected to the first voltage level signal, the output end is connected to the control ends of the second control switch and the second light-emitting control switch, and the first control end of the second driving switch is connected; The input end of the second driving switch is connected to the second voltage level signal and the second control end, and the output end is connected to the first control end. The first voltage level signal is a low voltage level signal, and the second voltage level signal is a high voltage level signal.

20. The display device of claim 19, wherein, Each row of gate lines further comprises a third gate line segment, the driving circuit further comprises a second refresh rate adjustment circuit, the second refresh rate adjustment circuit is arranged between the second gate line segment and the third gate line segment, and the second refresh rate adjustment circuit is used for controlling the conduction and turn-off between the second gate line segment and the third gate line segment. The plurality of gate driving units are divided into a first gate driving unit group and a second gate driving unit group, the first gate driving unit group and the second gate driving unit group are arranged at two ends of the gate lines respectively, the first gate driving unit group is connected to the input end of the first gate line segment, and the second gate driving unit group is connected to the input end of the third gate line segment.

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