Gate drive device

Abstract

A gate drive device (1) for a plurality of power semiconductor elements (QA, QB) that are connected in series comprises: gate drive voltage supply units (11-A, 11-B) that are provided so as to respectively correspond to the power semiconductor elements and that output gate drive voltages; gate lines (12-A, 12-B) that supply, to respective control terminals of the corresponding power semiconductor elements, the gate drive voltages output from the gate drive voltage supply units; and a magnetic coupling unit (13) that magnetically couples the gate lines, wherein the gate drive voltage output by the gate drive voltage supply unit that is provided so as to correspond to the power semiconductor element which is disposed on the highest potential-side is set to be greater than the gate drive voltage output by the gate drive voltage supply unit that is provided so as to correspond to another power semiconductor element other than the power semiconductor element which is disposed on the highest potential-side.

Description

Gate Driver

[0001] The present disclosure relates to gate drivers.

[0002] 2. Description of the Related Art Various gate drive devices have been proposed for turning on and off semiconductor switching elements, which are power semiconductor elements connected in series.

[0003] For example, in a semiconductor switch circuit comprising a plurality of voltage-driven semiconductor elements connected in series to form arms, and a gate drive circuit that supplies gate signals to the gate terminals of each of the plurality of voltage-driven semiconductor elements in each arm, there is known a control device for series-connected voltage-driven semiconductor elements, characterized in that gate lines connecting the gate drive circuit to the gate terminals of each voltage-driven semiconductor element in each arm are magnetically coupled to each other (see, for example, Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2002-204578

[0005] In the invention described in Patent Document 1 (JP 2002-204578 A), the gate lines of a voltage-driven semiconductor element (power semiconductor element) are magnetically coupled, and if the current values ​​flowing through the gate lines differ when the voltage-driven semiconductor element is turned on or off, the impedance of the gate lines is instantaneously changed in accordance with the difference, thereby matching the gate currents and suppressing variations in switching timing. However, in the invention described in Patent Document 1 (JP 2002-204578 A), even if the characteristics of the voltage-driven semiconductor element, the resistance value of the gate resistor, the gate threshold voltage (the gate voltage at which the voltage-driven semiconductor element begins to turn on), and the timing of the gate signal are all the same, a time difference occurs in the switching timing of the voltage-driven semiconductor element's on and off operations, and the degree of imbalance in the voltage applied between the drain terminal and source terminal of the voltage-driven semiconductor element during on and off operations (hereinafter sometimes simply referred to as "voltage imbalance") increases.

[0006] Therefore, in a gate drive device for a plurality of power semiconductor elements connected in series, there is a demand for a technology that can align the switching timing for the on and off operations of each of the power semiconductor elements to suppress imbalances in the voltages applied to the power semiconductor elements.

[0007] According to one aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series comprises: a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; gate lines that supply the gate drive voltage output from the gate drive voltage supply unit to the control terminals of each of the corresponding power semiconductor elements; and a magnetic coupling unit that magnetically couples each of the gate lines to each other, and the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element that is arranged on the highest potential side among the plurality of power semiconductor elements connected in series is set to be higher than the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the other power semiconductor elements other than the power semiconductor element that is arranged on the highest potential side.

[0008] Here, in the above gate drive device, each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and the positive potential output by the positive potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side may be set to be higher than the positive potentials output by the positive potential output units in the gate drive voltage supply units provided corresponding to the other power semiconductor elements.

[0009] Furthermore, in the above gate drive device, each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side may be set to be higher than the negative potentials output by the negative potential output units in the gate drive voltage supply units provided corresponding to the other power semiconductor elements.

[0010] Furthermore, in the above gate drive device, each of the gate drive voltage supplies has a positive potential output section that outputs a positive potential of the gate drive voltage, and a negative potential output section that is connected in series to the positive potential output section and outputs a negative potential of the gate drive voltage, and the positive potential output by the positive potential output section and the negative potential output by the negative potential output section in the gate drive voltage supply section provided corresponding to the power semiconductor element arranged on the highest potential side may be set to be greater than the positive potential output by the positive potential output section and the negative potential output by the negative potential output section in the gate drive voltage supply sections provided corresponding to the other power semiconductor elements, respectively.

[0011] In the gate drive device, the difference between the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the other power semiconductor elements may be set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set made up of a plurality of power semiconductor elements connected in series.

[0012] According to another aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series includes a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage, a gate line supplying the gate drive voltage output from the gate drive voltage supply unit to a control terminal of each of the corresponding power semiconductor elements, and a magnetic coupling unit magnetically coupling each of the gate lines to each other, and the output timing of a gate signal that switches on to off the power semiconductor element located on the highest potential side among the plurality of power semiconductor elements connected in series is set later than the output timing of a gate signal that switches on to off the other power semiconductor elements other than the power semiconductor element located on the highest potential side.

[0013] Here, in the gate drive device, the time difference between the output timing of the gate signal that switches the power semiconductor element located on the highest potential side from on to off and the output timing of the gate signals that switch the other power semiconductor elements from on to off is set according to the magnitude of the voltage of the DC power supply that is connected to one of the two terminals of a set consisting of multiple power semiconductor elements connected in series.

[0014] According to a further aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series comprises: a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; a gate line that supplies the gate drive voltage output from the gate drive voltage supply unit to a control terminal of each of the corresponding power semiconductor elements; a magnetic coupling unit that magnetically couples each of the gate lines to each other; and a gate resistor provided corresponding to each of the power semiconductor elements and arranged on a current path between the gate drive voltage supply unit and the gate line corresponding to the gate drive voltage supply unit, wherein the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series is set to be larger than the resistance values ​​of the gate resistors provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

[0015] In the gate drive device, the difference between the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side and the resistance values ​​of the gate resistors provided corresponding to the other power semiconductor elements is set according to the magnitude of the voltage of the DC power supply connected to one of the two terminals of a set consisting of a plurality of power semiconductor elements connected in series.

[0016] According to yet another aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series includes a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage, a gate line supplying the gate drive voltage output from the gate drive voltage supply unit to a control terminal of each of the corresponding power semiconductor elements, a magnetic coupling unit magnetically coupling each of the gate lines to each other, and a capacitor connected between the current output terminal and the control terminal of the power semiconductor element that is arranged on the highest potential side among the plurality of power semiconductor elements connected in series.

[0017] Here, in the gate drive device, the capacitance of the capacitor may be set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set made up of a plurality of power semiconductor elements connected in series.

[0018] In the gate drive device, the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series may be set to be higher than the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

[0019] Furthermore, in the above gate drive device, each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and the positive potential output by the positive potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side may be set to be higher than the positive potentials output by the positive potential output units in the gate drive voltage supply units provided corresponding to the other power semiconductor elements.

[0020] Furthermore, in the above gate drive device, each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side may be set to be higher than the negative potentials output by the negative potential output units in the gate drive voltage supply units provided corresponding to the other power semiconductor elements.

[0021] Furthermore, in the above gate drive device, each of the gate drive voltage supplies has a positive potential output section that outputs a positive potential of the gate drive voltage, and a negative potential output section that is connected in series to the positive potential output section and outputs a negative potential of the gate drive voltage, and the positive potential output by the positive potential output section and the negative potential output by the negative potential output section in the gate drive voltage supply section provided corresponding to the power semiconductor element arranged on the highest potential side may be set to be greater than the positive potential output by the positive potential output section and the negative potential output by the negative potential output section in the gate drive voltage supply sections provided corresponding to the other power semiconductor elements, respectively.

[0022] In the gate drive device, the difference between the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the other power semiconductor elements may be set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set made up of a plurality of power semiconductor elements connected in series.

[0023] In addition, in the gate drive device, the output timing of the gate signal that switches from OFF to ON the power semiconductor element that is located on the highest potential side among the multiple power semiconductor elements connected in series may be set earlier than the output timing of the gate signals that switch from OFF to ON the other power semiconductor elements other than the power semiconductor element that is located on the highest potential side.

[0024] In the gate drive device, the time difference between the output timing of the gate signal that switches the power semiconductor element located on the highest potential side from off to on and the output timing of the gate signals that switch the other power semiconductor elements from off to on may be set according to the magnitude of the voltage of a DC power supply that is connected to one of two terminals of a set of multiple power semiconductor elements connected in series.

[0025] Furthermore, the gate drive device may further comprise gate resistors provided corresponding to each of the power semiconductor elements and arranged on a path of current flowing from the gate drive voltage supply unit toward the gate line corresponding to the gate drive voltage supply unit, and the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series may be set to be smaller than the resistance values ​​of the gate resistors provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

[0026] In the gate drive device, the difference between the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side and the resistance values ​​of the gate resistors provided corresponding to the other power semiconductor elements may be set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set made up of a plurality of power semiconductor elements connected in series.

[0027] According to one aspect of the present disclosure, in a gate drive force conversion device for a plurality of power semiconductor elements connected in series, the switching timing for the on and off operations of each of the power semiconductor elements can be aligned to suppress imbalances in the voltages applied to the power semiconductor elements.

[0028] 1 is a circuit diagram showing a gate driver for on-off driving two power semiconductor elements connected in series according to the first to third embodiments of the present disclosure. FIG. 2 is a diagram illustrating a magnetic coupling unit in the gate driver according to the first to seventh embodiments of the present disclosure. FIG. 3 is a diagram illustrating a power conversion device including the gate driver according to the first to seventh embodiments of the present disclosure. FIG. 4 is a circuit diagram showing an arm provided in the power conversion device shown in FIG. 3. FIG. 5 is a circuit diagram explaining a voltage imbalance caused by a time difference in switching timing between the on operation and the off operation of the power semiconductor elements. FIG. 6 is a diagram illustrating simulated waveforms of drain-source voltage and drain-source current when two power semiconductor elements connected in series are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A). FIG. 7 is a diagram illustrating simulated waveforms of gate-source voltage when two power semiconductor elements connected in series are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A). 1 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements are switched from an off operation to an on operation in the invention described in Patent Document 1 (Japanese Patent Laid-Open No. 2002-204578); 2 is a diagram showing simulated waveforms of the gate-source voltage when two series-connected power semiconductor elements are switched from an off operation to an on operation in the invention described in Patent Document 1 (Japanese Patent Laid-Open No. 2002-204578); 3 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements are switched from an on operation to an off operation in the gate drive device according to the first embodiment of the present disclosure; 4 is a diagram showing a simulated waveform of the gate-source voltage when two series-connected power semiconductor elements are switched from an on operation to an off operation in the gate drive device according to the first embodiment of the present disclosure; 5 is a diagram showing an example of the relationship between the power supply voltage and the difference voltage of the gate drive voltages output by the gate drive voltage supplies in the gate drive device according to the first embodiment of the present disclosure.1 is a circuit diagram showing a gate driver for on-off driving three power semiconductor elements connected in series according to the first to third embodiments of the present disclosure. FIG. 2 is a diagram showing simulated waveforms of drain-source voltage and drain-source current when three power semiconductor elements connected in series are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A). FIG. 3 is a diagram showing simulated waveforms of gate-source voltage when three power semiconductor elements connected in series are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A). FIG. 4 is a diagram showing simulated waveforms of drain-source voltage and drain-source current when three power semiconductor elements connected in series are switched from on operation to off operation in the gate driver according to the first embodiment of the present disclosure. FIG. 5 is a diagram showing simulated waveforms of gate-source voltage when three power semiconductor elements connected in series are switched from on operation to off operation in the gate driver according to the first embodiment of the present disclosure. FIG. 10 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements are switched from an on operation to an off operation in the gate drive device according to the second embodiment of the present disclosure. FIG. 11 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements are switched from an on operation to an off operation in the gate drive device according to the third embodiment of the present disclosure. FIG. 12 is a circuit diagram showing a gate drive device for on / off driving two series-connected power semiconductor elements according to the fourth to seventh embodiments of the present disclosure. FIG. 13 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements are switched from an on operation to an off operation in the gate drive device according to the fourth embodiment of the present disclosure. FIG. 14 is a diagram showing simulated waveforms of the gate-source voltage when two series-connected power semiconductor elements are switched from an on operation to an off operation in the gate drive device according to the fourth embodiment of the present disclosure.FIG. 1 is a circuit diagram showing a gate driver for on-off driving three power semiconductor elements connected in series according to fourth to seventh embodiments of the present disclosure. FIG. 2 is a diagram showing simulated waveforms of drain-source voltage and drain-source current when two power semiconductor elements connected in series in the gate driver according to the fourth embodiment of the present disclosure are switched from off operation to on operation. FIG. 3 is a diagram showing simulated waveforms of gate-source voltage when two power semiconductor elements connected in series in the gate driver according to the fourth embodiment of the present disclosure are switched from off operation to on operation. FIG. 4 is a diagram showing simulated waveforms of drain-source voltage and drain-source current when two power semiconductor elements connected in series in the gate driver according to the fifth embodiment of the present disclosure are switched from off operation to on operation. FIG. 5 is a diagram showing simulated waveforms of gate-source voltage when two power semiconductor elements connected in series in the gate driver according to the fifth embodiment of the present disclosure are switched from on operation to off operation.

[0029] The gate driver will be described below with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals. Furthermore, the scale of these drawings has been changed as appropriate to facilitate understanding. The illustrated embodiments are examples for carrying out the present invention, and the present invention is not limited to these embodiments. Furthermore, the numerical values ​​exemplified below are merely examples, and numerical values ​​other than those described herein may be used.

[0030] In the following description, a "power semiconductor element" refers to a semiconductor switching element. The "on" state of a power semiconductor element means that the electrical circuit in which the power semiconductor element is provided is closed. In other words, when a power semiconductor element is turned on, the electrical circuit in which the power semiconductor element is provided is connected and closed. The "off" state of a power semiconductor element means that the electrical circuit in which the power semiconductor element is provided is opened. In other words, when a power semiconductor element is turned off, the electrical circuit in which the power semiconductor element is provided is interrupted and opened. The "on" state of a switch means that the electrical circuit in which the switch is provided is closed. In other words, when a switch is turned on, the electrical circuit in which the switch is provided is connected and closed. The "off" state of a switch means that the electrical circuit in which the switch is provided is opened. In other words, when a switch is turned off, the electrical circuit in which the switch is provided is interrupted and opened.

[0031] A gate driver according to each embodiment of the present disclosure drives on and off a plurality of power semiconductor elements connected in series. Examples of power semiconductor elements include MOSFETs, IGBTs, thyristors, GTOs, and transistors. MOSFETs have gate, drain, and source terminals as their terminals. IGBTs have gate, collector, and emitter terminals as their terminals. Transistors have base, collector, and emitter terminals as their terminals. Thyristors and GTOs have gate, anode, and cathode terminals as their terminals. The "current inflow terminals" of power semiconductor elements correspond to the "drain terminals" of MOSFETs, the "collector terminals" of IGBTs and transistors, and the "anode terminals" of thyristors and GTOs, respectively. The "current outflow terminals" of power semiconductor elements correspond to the "source terminals" of MOSFETs, the "emitter terminals" of IGBTs and transistors, and the "cathode terminals" of thyristors and GTOs, respectively. The "control terminal" of a power semiconductor element corresponds to the "gate terminal" of a MOSFET, IGBT, thyristor, and GTO, and the "base terminal" of a transistor.

[0032] The following description will be given of a case where the power semiconductor element is configured as a MOSFET as an example, but the embodiments of the present disclosure are also applicable to IGBTs, thyristors, GTOs, or transistors. Furthermore, when the power semiconductor element is configured as an IGBT, the "drain" as a current inflow terminal is replaced with the "collector," and the "source" as a current outflow terminal is replaced with the "emitter," and the embodiments of the present disclosure are applicable. Furthermore, when the power semiconductor element is configured as a transistor, the "gate" as a control terminal is replaced with the "base," the "drain" as a current inflow terminal is replaced with the "collector," and the "source" as a current outflow terminal is replaced with the "emitter," and the embodiments of the present disclosure are applicable. Furthermore, when the power semiconductor element is configured as a thyristor or GTO, the "drain" as a current inflow terminal is replaced with the "anode," and the "source" as a current outflow terminal is replaced with the "cathode," and the embodiments of the present disclosure are applicable.

[0033] The gate driver according to the first to seventh embodiments of the present disclosure is configured to turn on and off a plurality of power semiconductor devices connected in series. Here, as an example, an example of turning on and off two or three power semiconductor devices connected in series will be described, but the following description can also be applied to the case of turning on and off four or more power semiconductor devices connected in series.

[0034] <Overall Configuration of First to Third Embodiments>

[0035] 1 is a circuit diagram showing a gate driver for turning on and off two power semiconductor devices connected in series according to the first to third embodiments of the present disclosure. The circuit diagram shown in FIG. 1 is also applicable to the second and third embodiments described below.

[0036] Power semiconductor element Q Ａ The feedback diode D Ａ are connected in antiparallel. Similarly, the power semiconductor element Q Ｂ The feedback diode D Ｂ are connected in antiparallel. Ａ and Q Ｂ When is a MOSFET, the feedback diode D Ａ and DＢ are the power semiconductor elements Q Ａ and Q Ｂ A parasitic diode may be used instead.

[0037] The gate driver 1 according to the first embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B.

[0038] The gate drive voltage supply unit 11-A supplies a power semiconductor element Q Ａ The gate drive voltage supply unit 11-B is provided corresponding to the power semiconductor element Q and outputs a positive gate drive voltage corresponding to an ON signal of the gate signal and a negative gate drive voltage corresponding to an OFF signal of the gate signal. Ｂ and outputs a positive gate drive voltage corresponding to an ON signal of the gate signal and a negative gate drive voltage corresponding to an OFF signal of the gate signal.

[0039] The gate drive voltage supply unit 11-A supplies the positive potential VP of the gate drive voltage. Ａ and a positive potential output section 21P-A that outputs a negative potential VN of the gate drive voltage. Ａ The potential VR at an intermediate terminal 22-A, which is a connection point between the positive potential output portion 21P-A and the negative potential output portion 21N-A, is Ａ and the power semiconductor element Q corresponding to the gate drive voltage supply unit 11-A. Ａ The potential VQ at the source terminal, which is the output terminal of Ａ When the positive-side switch 23P-A is turned on in accordance with the gate signal output from the power conversion control unit 3, the positive-side potential VP output from the positive-side potential output unit 21P-A is Ａ However, as a positive gate drive voltage, the power semiconductor element Q ＡWhen the negative-side switch 23N-A is turned on in accordance with the gate signal output from the power conversion control unit 3, the negative-side potential VN output from the negative-side potential output unit 21N-A Ａ However, as a negative gate drive voltage, the power semiconductor element Q Ａ is output to the

[0040] The gate drive voltage supply unit 11-B supplies the positive potential VP of the gate drive voltage Ｂ and a positive potential output section 21P-B that outputs a negative potential VN of the gate drive voltage. Ｂ The potential VR at an intermediate terminal 22-B, which is a connection point between the positive potential output portion 21P-B and the negative potential output portion 21N-B, is set to VR. Ｂ and the power semiconductor element Q corresponding to the gate drive voltage supply unit 11-B. Ｂ The potential VQ at the source terminal, which is the output terminal of Ｂ When the positive-side switch 23P-B is turned on in accordance with the gate signal output from the power conversion control unit 3, the positive-side potential VP output from the positive-side potential output unit 21P-B is Ｂ However, as a positive gate drive voltage, the power semiconductor element Q Ｂ When the negative-side switch 23N-B is turned on in accordance with the gate signal output from the power conversion control unit 3, the negative-side potential VN output from the negative-side potential output unit 21N-B Ｂ However, as a negative gate drive voltage, the power semiconductor element Q Ｂ is output to the

[0041] The positive terminal of the gate drive voltage supply unit 11-A is connected to a positive gate resistor R ｇｏｎ -A is connected, and the negative terminal is connected to the negative gate resistor R ｇｏｆｆ Similarly, a positive gate resistor R ｇｏｎ -B is connected, and the negative terminal is connected to the negative gate resistor R ｇｏｆｆ -B is connected.

[0042] The gate line 12-A is connected to the gate drive voltage supply unit 11-A and the power semiconductor element Q ＡThe gate line 12-A supplies the gate drive voltage output from the gate drive voltage supply unit 11-A to the corresponding power semiconductor element Q Ａ The power semiconductor element Q is supplied with a voltage from the gate terminal of the power semiconductor element Q. Ａ When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ａ is turned on, and the power semiconductor element Q Ａ When a negative gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ａ is turned off.

[0043] The gate line 12-B is connected to the gate drive voltage supply unit 11-B and the power semiconductor element Q Ｂ The gate line 12-B supplies the gate drive voltage output from the gate drive voltage supply unit 11-B to the corresponding power semiconductor element Q Ｂ The power semiconductor element Q is supplied with a voltage from the gate terminal of the power semiconductor element Q. Ｂ When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ｂ is turned on, and the power semiconductor element Q Ｂ When a negative gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ｂ is turned off.

[0044] The magnetic coupling unit 13 magnetically couples the gate line 12-A and the gate line 12-B. FIG. 2 is a diagram illustrating a magnetic coupling unit in the gate drive device according to the first to seventh embodiments of the present disclosure. FIG. 2 is also applicable to the second to seventh embodiments described later. The magnetic coupling unit 13 has a magnetic body 30. The gate lines 12-A and 12-B are wound around the magnetic body 30. For example, as shown in FIG. 2, the gate current Ig １ When the gate current Ig flows, a magnetic flux Φ1 is generated in the magnetic body 30 and crosses the gate line 12-B. ２ When a current flows, a magnetic flux Φ2 is generated in the magnetic body 30 and crosses the gate line 12-A. This magnetically couples the gate line 12-A and the gate line 12-B. The number of turns N of the gate line 12-A around the magnetic body 30 is １ and the number of turns N of the gate line 12-B around the magnetic body 30. ２ The gate current Ig １ and gate current Ig２ When |Φ1|=|Φ2|, the gate current Ig １ and gate current Ig ２ When Φ1 and Φ2 have opposite polarities, Φ2 and Φ3 have opposite polarities.

[0045] For example, a power semiconductor element Q Ａ and power semiconductor element Q Ｂ The timing of the power semiconductor element Q Ａ is the power semiconductor element Q Ｂ If the off operation is performed before the gate current Ig １ is the gate current Ig ２ Since the magnetic flux Φ1 and the magnetic flux Φ2 are not equal when they flow out before the gate line 12-A, a magnetic flux of |Φ1-Φ2| is generated in the magnetic body 30, and they are magnetically coupled. １ The gate line 12-B has an inductance L ２ These inductances L １ and L ２ is proportional to |Φ1-Φ2|. Gate current Ig １ and gate current Ig ２ The greater the imbalance with １ and L ２ Also, the inductance L １ and L ２ As the impedance of the gate lines 12-A and 12-B increases, the gate current Ig １ and Ig ２ This makes it difficult for the gate current Ig １ and gate current Ig ２ The impedance of the gate lines 12-A and 12-B changes depending on the imbalance between the １ and gate current Ig ２ It can be operated so that the

[0046] In this way, the magnetic coupling portion 13 has a power semiconductor element Q Ａ and power semiconductor element Q Ｂ Even if the timing of the off operation is not synchronized with the gate current Ig １ and gate current Ig２ There is a function that makes it work so that it roughly matches the

[0047] FIG. 3 is a diagram showing a power conversion device including a gate driver according to the first to seventh embodiments of the present disclosure. FIG. 4 is a circuit diagram showing an arm provided in the power conversion device shown in FIG. 3. FIGS. 3 and 4 are also applicable to the second to seventh embodiments described later. Here, as an example, two power semiconductor elements Q connected in series are shown. Ａ and Q Ｂ An example of the configuration of the arm 50 will be described.

[0048] The power conversion device 100 according to the first to seventh embodiments of the present disclosure includes a gate drive device 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3 ) each having a plurality of power semiconductor elements connected in series and performing power conversion operations in response to the on / off operations of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2.

[0049] In the example shown in FIGS. 3 and 4, the upper and lower arms 50 each include, for example, two power semiconductor elements Q Ａ and Q Ｂ However, it may be configured with three or more power semiconductor elements connected in series. Ａ The drain terminal of １ is drawn out, and the power semiconductor element Q Ｂ The source terminal of ２ The power conversion circuit unit 2 is connected to the terminal P ２ is the terminal P of the lower arm 50 １ The connection point is connected to one terminal of the load 300. The power semiconductor element Q in the upper arm 50, which is arranged on the highest potential side, Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 located on the lowest potential side. Ｂ3 and 4, two arms 50 are connected in series to form one leg 60, and the two legs 60 form the power conversion circuit unit 2.

[0050] A DC power supply 200 is connected to a leg 60 formed of the arms 50 connected in series. １ and the negative terminal T between the series-connected arms 50 in the other leg 60. ２ A load 300 is connected between the two.

[0051] The gate driver 1 is provided corresponding to each arm 50. Ａ and power semiconductor element Q Ｂ are turned on and off by the corresponding gate drive devices 1. That is, the gate drive voltage supply units 11-A and 11-B generate the gate drive voltages as described above, and then turn on and off the positive side switches 23P-A and 23P-B and the negative side switches 23N-A and 23N-B, thereby controlling the power semiconductor elements Q Ａ and Q Ｂ The voltage applied to the gate terminal of the transistor is controlled.

[0052] The power conversion control unit 3 outputs gate signals for controlling the on and off operations of the positive-side switches 23P-A and 23P-B and the negative-side switches 23N-A and 23N-B in each gate drive device 1. That is, the power conversion control unit 3 controls the on and off operations of the positive-side switches 23P-A and 23P-B and the negative-side switches 23N-A and 23N-B in each gate drive device 1 using gate signals, thereby controlling the power semiconductor element Q Ａ and Q Ｂ , and thereby controlling the voltage applied to the gate terminal of the power semiconductor element Q Ａ and Q Ｂ The power conversion circuit section 2 turns on and off the power semiconductor element Q in accordance with the gate signal. Ａand Q Ｂ By turning on and off the power supply 200, the power conversion control unit 3 converts the DC power supplied from the DC power supply 200 into a desired power and supplies it to the load 300. １ The detected value i of the current flowing from the load 300 to the load 300 is compared with the current command i which is the control target value. ＊ Gate signals are generated to control the on and off operations of the positive-side switches 23P-A and 23P-B and the negative-side switches 23N-A and 23N-B in each gate driver 1 so as to eliminate any deviation from the reference voltage.

[0053] Although not shown here, the power line for supplying power to the power conversion control unit 3 is a system separate from the power line for supplying power from the DC power supply 200 to the arm 50. In other words, even before power is supplied from the DC power supply 200 to the arm 50, power is supplied to drive the power conversion control unit 3 in preparation for operation when power is supplied to the arm 50.

[0054] <Principle of Occurrence of Voltage Imbalance> Next, a description will be given of voltage imbalance during ON and OFF operations caused by a time difference between the switching timings of ON and OFF operations of power semiconductor elements.

[0055] 5 is a circuit diagram illustrating a voltage imbalance caused by a time difference between the switching timings of the power semiconductor elements when they are turned on and off, and the power conversion control unit 3 is not shown in FIG.

[0056] Power semiconductor element Q Ａ The drain-source parasitic capacitance of ｄｓ -A, drain-gate parasitic capacitance is C ｄｇ -A, gate-source parasitic capacitance is C ｇｓ -A. Power semiconductor element Q Ｂ The drain-source parasitic capacitance of ｄｓ -B, drain-gate parasitic capacitance is C ｄｇ -B, gate-source parasitic capacitance is C ｇｓ The parasitic capacitance of the magnetic coupling portion 13 is C ｔｒ -1 and C ｔｒ -2. Power semiconductor element Q Ａand the drain terminal of the power semiconductor element Q Ｂ The magnitude of the voltage of the DC power supply 200 connected to the source terminal of is assumed to be E [V].

[0057] Power semiconductor element Q Ａ and Q Ｂ When the switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-gate parasitic capacitance C ｄｇ -A is charged to E / 2 [V], and the power semiconductor element Q Ｂ The drain-gate parasitic capacitance C ｄｇ -B is charged to E / 2 [V]. These voltage changes are Ａ The drain-gate parasitic capacitance C ｄｇ -A to the parasitic capacitance C of the magnetic coupling portion 13 ｔｒ Power semiconductor element Q via -1 Ｂ The gate-source parasitic capacitance C ｇｓ This generates a displacement current (indicated by the dotted arrow in the figure) that flows through a path leading to -B. This displacement current reduces the parasitic capacitance C ｔｒ -1 is charged to E / 2 [V]. As shown in FIG. Ｂ The gate-source parasitic capacitance C ｇｓ A displacement current flows through -B, but the power semiconductor element Q Ａ The gate-source parasitic capacitance C ｇｓ No displacement current flows through -A. Power semiconductor element Q Ａ and Q Ｂ When switching from on to off, the gate-source parasitic capacitance C ｇｓ -A and C ｇｓ The charge of -B is drawn out and the gate-source voltage decreases, but the power semiconductor element Q Ｂ The gate-source parasitic capacitance C ｇｓ Since a displacement current flows into -B, the power semiconductor element Q Ｂ Therefore, even if the gate signal is output from the power conversion control unit 3 at the same timing, the speed at which the gate-source voltage of the power semiconductor element Q decreases becomes slower. Ａ and power semiconductor element Q ＢA time difference occurs between the ON and OFF timings, and the power semiconductor element Q Ａ and power semiconductor element Q Ｂ An imbalance occurs in the drain-source voltages applied to each of the transistors.

[0058] 6A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two serially connected power semiconductor elements are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A). FIG. 6B is a diagram showing simulated waveforms of the gate-source voltage when two serially connected power semiconductor elements are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A).

[0059] In the simulation, the power semiconductor element Q Ａ and Q Ｂ is a SiC-MOSFET with a breakdown voltage of 3.3 kV / 750 A, and the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q Ｂ It is assumed that a load current of 750 A flows when the voltage of the DC power supply 200 connected between the source terminal of the positive side potential output section 21P-A and the source terminal of the positive side potential output section 21P-A is 3600 V. The load is an inductive load of 10 mH. The inductances of the main circuit wiring connected to the load are 22 nH and 23 nH. Ａ and the positive potential VP of the positive potential output section 21P-B Ｂ is set to 17 V. The negative potential VN of the negative potential output section 21N-A Ａ and the negative potential VN of the negative potential output section 21N-B Ｂ is set to -11V. Power semiconductor element Q Ａ and Q Ｂ The internal resistance of each of the power semiconductor elements Q is 2.1Ω. Ａ and Q Ｂ The gate-source parasitic capacitance is 210 nF. The positive gate resistance R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆThe winding ratio of the magnetic coupling portion 13 is set to "1:1", the self-inductance is set to 70 μH, and the coupling coefficient is set to 0.97. The parasitic capacitance C of the magnetic coupling portion 13 ｔｒ -1 and C ｔｒ -2 is set to 40 pF each.

[0060] As shown in FIGS. 6A and 6B, the power semiconductor element Q Ａ The gate-source voltage V ｇｓ Looking at the waveform of -A, the power semiconductor element Q Ａ The drain-source voltage V ｄｓ When -A rises, the power semiconductor element Q Ｂ The gate-source voltage V ｇｓ -B rises, and power semiconductor element Q Ｂ The timing at which the power semiconductor element Q switches from ON to OFF is Ａ As a result, the power semiconductor element Q after the switching from the ON operation to the OFF operation is delayed. Ａ The drain-source voltage V ｄｓ -A is a power semiconductor element Q Ｂ The drain-source voltage V ｄｓ It can be seen that the power semiconductor device Q Ａ and Q Ｂ An imbalance state in which a large voltage is applied to one of the power semiconductor elements Q Ａ and Q Ｂ Power semiconductor element Q due to overheating caused by failure or deterioration of Ａ and Q Ｂ As described with reference to FIG. 5, the power semiconductor elements Q connected in series may fail or deteriorate. Ａ and Q Ｂ A displacement current is generated by a change in the voltage applied to the ｔｒ -1 causes a voltage imbalance. Ａ and Q ＢThe larger the voltage change applied to the power semiconductor element Q, the larger the displacement current. Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ The voltage difference and imbalance with -B becomes larger.

[0061] 7A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two serially connected power semiconductor elements are switched from off operation to on operation in the invention described in Patent Document 1 (JP 2002-204578 A). FIG. 7B is a diagram showing simulated waveforms of the gate-source voltage when two serially connected power semiconductor elements are switched from off operation to on operation in the invention described in Patent Document 1 (JP 2002-204578 A).

[0062] The simulation conditions for FIGS. 7A and 7B are the same as those for FIGS. 6A and 6B.

[0063] Power semiconductor element Q Ａ and Q Ｂ When switching from the OFF operation to the ON operation, the power semiconductor element Q Ａ and Q Ｂ Similarly, when switching from ON to OFF, the series-connected power semiconductor element Q Ａ and Q Ｂ The displacement current caused by a change in the voltage applied to the power semiconductor device Q (i.e., a change in the drain-source voltage) Ｂ The gate-source parasitic capacitance C ｇｓ -B, but in the opposite direction to when switching from ON to OFF. Ｂ The gate-source parasitic capacitance C ｇｓ As a result, during the period when the drain-source voltage is changing, Ａ The gate-source voltage V ｇｓ -A is a power semiconductor element Q Ｂ The gate-source voltage Vｇｓ -B, and the power semiconductor element Q Ｂ The timing at which the power semiconductor element Q switches from OFF to ON Ａ There is a difference in timing between when the switch is switched from OFF to ON.

[0064] As shown in FIGS. 7A and 7B, the power semiconductor device Q Ａ and Q Ｂ The drain-source voltage V ｄｓ -A and V ｄｓ During the period when −B is changing, the power semiconductor element Q Ａ The gate-source voltage V ｇｓ -A is a power semiconductor element Q Ｂ The gate-source voltage V ｇｓ -B, and the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A is a power semiconductor element Q Ｂ The drain-source voltage V ｄｓ It can be seen that the voltage falls earlier than -B. However, there is no imbalance in which a large voltage is applied to one of the power semiconductor elements, as occurs when switching from on operation to off operation as shown in Figures 6A and 6B. Therefore, rather than focusing on the timing when the power semiconductor elements switch from off operation to on operation, it is necessary to take measures to address the imbalance by focusing on the timing when the power semiconductor elements switch from on operation to off operation.

[0065] As described above, when the power semiconductor element is switched from an ON state to an OFF state, the parasitic capacitance C ｔｒ A voltage imbalance occurs because the displacement current flowing through -1 raises the gate-source voltage of the lower series-connected power semiconductor device. This voltage imbalance is determined by the magnitude of the displacement current and is Ａ and Q Ｂ The parasitic capacitance C of the magnetic coupling portion 13 changes depending on the magnitude of the change in the voltage applied to the ｔｒ -1 and power semiconductor element Q Ａand Q Ｂ The magnitude of the voltage imbalance is determined by the magnitude of the voltage change applied to the power semiconductor element. Therefore, in the first to seventh embodiments of the present disclosure, the voltage imbalance is eliminated by adjusting the timing at which the power semiconductor element switches from an ON operation to an OFF operation.

[0066] In a first embodiment of the present disclosure, in order to eliminate imbalances that occur when power semiconductor elements are switched from an on state to an off state, the gate drive voltage output by a gate drive voltage supply unit provided corresponding to a power semiconductor element arranged on the highest potential side among a plurality of power semiconductor elements connected in series is set to be higher than the gate drive voltages output by gate drive voltage supplies provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side, thereby delaying the timing of switching from an on state to an off state of the power semiconductor element arranged on the highest potential side to coincide with the timing of switching from an on state to an off state of the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

[0067] In the example shown in FIG. 1, two power semiconductor elements Q Ａ and Q Ｂ Among these, the power semiconductor element Q is placed on the highest potential side. Ａ In the first embodiment of the present disclosure, the power semiconductor element Q Ａ The gate drive voltage output from the gate drive voltage supply unit 11-A provided corresponding to the power semiconductor element Q Ｂ The gate drive voltage is set to be larger than the gate drive voltage output by the gate drive voltage supply unit 11-B provided corresponding to the power semiconductor element Q Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ The delay is made to coincide with the timing of switching from ON to OFF.

[0068] Here, several modes for setting the gate drive voltage output from the gate drive voltage supply unit 11-A to be higher than the gate drive voltage output from the gate drive voltage supply unit 11-B will be listed.

[0069] In the first embodiment, the power semiconductor element Q Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ As an example of the numerical value, the positive side potential VP outputted by the positive side potential output section 21P-A in the gate drive voltage supply section 11-A is set to be larger than Ａ is set to 17.5 V, and the positive potential VP output from the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B is Ｂ is set to 17 V. The negative potential VN output from the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A is set to 17 V. Ａ and the negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B. Ｂ are both set to −11 V. Note that the values ​​given here are merely examples, and other values ​​may be used.

[0070] 8A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements in the gate drive device according to the first embodiment of the present disclosure are switched from on operation to off operation, and FIG. 8B is a diagram showing simulated waveforms of the gate-source voltage when two series-connected power semiconductor elements in the gate drive device according to the first embodiment of the present disclosure are switched from on operation to off operation.

[0071] In the simulations of FIGS. 8A and 8B, the positive potential VP output from the positive potential output section 21P-A Ａ is set to 17.5 V, and the positive potential VP output from the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B is Ｂ was set to 17 V. The other simulation conditions for Figures 8A and 8B were the same as those for Figures 6A and 6B.

[0072] As shown in FIGS. 8A and 8B, the positive potential VP output from the positive potential output section 21P-A Ａ The positive potential VP output by the positive potential output unit 21P-B Ｂ By setting it to 0.5 V higher than Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B almost coincides with each other, and it can be seen that the voltage imbalance is suppressed.

[0073] In the second mode, in which the gate drive voltage output by the gate drive voltage supply unit 11-A is set to be larger than the gate drive voltage output by the gate drive voltage supply unit 11-B, the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side is set to be larger than the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the other power semiconductor elements. In the example shown in FIG. Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ Set it to be larger than

[0074] In the third form, in which the gate drive voltage output by the gate drive voltage supply unit 11-A is set to be larger than the gate drive voltage output by the gate drive voltage supply unit 11-B, the positive side potential output by the positive side potential output unit and the negative side potential output by the negative side potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side are set to be larger than the positive side potential output by the positive side potential output unit and the negative side potential output by the negative side potential output unit in the gate drive voltage supply units provided corresponding to the other power semiconductor elements. In the example shown in FIG. Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ and the power semiconductor element Q Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ Set it to be larger than

[0075] FIG. 9 is a diagram illustrating the relationship between the power supply voltage and the differential voltage of the gate drive voltages output by the gate drive voltage supply units in the gate drive device according to the first embodiment of the present disclosure.

[0076] As described above, the power semiconductor element Q Ａ and Q Ｂ The voltage imbalance is determined by the magnitude of the displacement current, and the power semiconductor element Q Ａ and Q Ｂ The power semiconductor element Q changes depending on the magnitude of the voltage change applied to the power semiconductor element Q (i.e., the change in the drain-source voltage). Ａ and the drain terminal of the power semiconductor element Q Ｂ9, the difference between the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply units provided corresponding to the other power semiconductor elements is proportional to the magnitude of the voltage of the DC power supply. Therefore, by setting the difference between the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply units provided corresponding to the other power semiconductor elements in accordance with the magnitude of the power supply voltage output by the DC power supply 200, the parasitic capacitance C ｔｒ It is possible to suppress the occurrence of voltage imbalance caused by −1.

[0077] The above is a power semiconductor element Q connected in series. Ａ and Q Ｂ However, in the first embodiment, it is also possible to turn on and off three or more power semiconductor elements connected in series.

[0078] 10 is a circuit diagram showing a gate driver for turning on and off three serially connected power semiconductor elements according to the first to third embodiments of the present disclosure. As an example, three serially connected power semiconductor elements Q Ａ , Q Ｂ and Q Ｃ 10 is also applicable to the second and third embodiments described later.

[0079] Power semiconductor element Q Ａ Diode D Ａ are connected in antiparallel. Similarly, the power semiconductor element Q Ｂ Diode D Ｂ are connected in antiparallel, and the power semiconductor element Q Ｃ Diode D Ｃ are connected in antiparallel. Ａ , Q Ｂ and Q Ｃ When is a MOSFET, the feedback diode DＡ , D Ｂ and D Ｃ are the power semiconductor elements Q Ａ , Q Ｂ and Q Ｃ A parasitic diode may be used instead.

[0080] The gate driver 1 for driving three serially connected power semiconductor elements on and off according to the first embodiment of the present disclosure includes gate drive voltage supply units 11-A, 11-B, and 11-C, gate lines 12-A, 12-B, and 12-C, a magnetic coupling unit 13, and a positive gate resistor R ｇｏｎ -A, R ｇｏｎ -B and R ｇｏｎ -C and negative gate resistance R ｇｏｆｆ -A, R ｇｏｆｆ -B and R ｇｏｆｆ -C.

[0081] The gate drive voltage supply unit 11-A supplies a power semiconductor element Q Ａ The gate drive voltage supply unit 11-B is provided corresponding to the power semiconductor element Q and outputs a positive gate drive voltage corresponding to an ON signal of the gate signal and a negative gate drive voltage corresponding to an OFF signal of the gate signal. Ｂ The gate drive voltage supply unit 11-C is provided corresponding to the power semiconductor element Q and outputs a positive gate drive voltage corresponding to an ON signal of the gate signal and a negative gate drive voltage corresponding to an OFF signal of the gate signal. Ｃ and outputs a positive gate drive voltage corresponding to an ON signal of the gate signal and a negative gate drive voltage corresponding to an OFF signal of the gate signal.

[0082] The gate drive voltage supply unit 11-A supplies the positive potential VP of the gate drive voltage. Ａ and a positive potential output section 21P-A that outputs a negative potential VN of the gate drive voltage. Ａ The potential VR at an intermediate terminal 22-A, which is a connection point between the positive potential output portion 21P-A and the negative potential output portion 21N-A, is Ａand the power semiconductor element Q corresponding to the gate drive voltage supply unit 11-A. Ａ The potential VQ at the source terminal, which is the output terminal of Ａ When the positive-side switch 23P-A is turned on in accordance with the gate signal output from the power conversion control unit 3, the positive-side potential VP output from the positive-side potential output unit 21P-A is Ａ However, as a positive gate drive voltage, the power semiconductor element Q Ａ When the negative-side switch 23N-A is turned on in accordance with the gate signal output from the power conversion control unit 3, the negative-side potential VN output from the negative-side potential output unit 21N-A Ａ However, as a negative gate drive voltage, the power semiconductor element Q Ａ is output to the

[0083] The gate drive voltage supply unit 11-B supplies the positive potential VP of the gate drive voltage Ｂ and a positive potential output section 21P-B that outputs a negative potential VN of the gate drive voltage. Ｂ The potential VR at an intermediate terminal 22-B, which is a connection point between the positive potential output portion 21P-B and the negative potential output portion 21N-B, is set to VR. Ｂ and the power semiconductor element Q corresponding to the gate drive voltage supply unit 11-B. Ｂ The potential VQ at the source terminal, which is the output terminal of Ｂ When the positive-side switch 23P-B is turned on in accordance with the gate signal output from the power conversion control unit 3, the positive-side potential VP output from the positive-side potential output unit 21P-B is Ｂ However, as a positive gate drive voltage, the power semiconductor element Q Ｂ When the negative-side switch 23N-B is turned on in accordance with the gate signal output from the power conversion control unit 3, the negative-side potential VN output from the negative-side potential output unit 21N-B Ｂ However, as a negative gate drive voltage, the power semiconductor element Q Ｂ is output to the

[0084] The gate drive voltage supply unit 11-C supplies the positive potential VP of the gate drive voltage. Ｃand a positive potential output section 21P-C that outputs a negative potential VN of the gate drive voltage. Ｃ The potential VR at an intermediate terminal 22-C, which is a connection point between the positive potential output portion 21P-C and the negative potential output portion 21N-C, is set to VR. Ｃ and the power semiconductor element Q corresponding to the gate drive voltage supply unit 11-C. Ｃ The potential VQ at the source terminal, which is the output terminal of Ｃ When the positive-side switch 23P-C is turned on in accordance with the gate signal output from the power conversion control unit 3, the positive-side potential VP output from the positive-side potential output unit 21P-C is Ｃ However, as a positive gate drive voltage, the power semiconductor element Q Ｃ When the negative-side switch 23N-C is turned on in accordance with the gate signal output from the power conversion control unit 3, the negative-side potential VN output from the negative-side potential output unit 21N-C Ｃ However, as a negative gate drive voltage, the power semiconductor element Q Ｃ is output to the

[0085] The positive terminal of the gate drive voltage supply unit 11-A is connected to a positive gate resistor R ｇｏｎ -A is connected, and the negative terminal is connected to the negative gate resistor R ｇｏｆｆ Similarly, a positive gate resistor R ｇｏｎ -B is connected, and the negative terminal is connected to the negative gate resistor R ｇｏｆｆ -B is connected to the positive terminal of the gate drive voltage supply unit 11-C. ｇｏｎ -C is connected, and the negative terminal is connected to the negative gate resistor R ｇｏｆｆ -C is connected.

[0086] The gate line 12-A is connected to the gate drive voltage supply unit 11-A and the power semiconductor element Q Ａ The gate line 12-A supplies the gate drive voltage output from the gate drive voltage supply unit 11-A to the corresponding power semiconductor element Q Ａ The power semiconductor element Q is supplied with a voltage from the gate terminal of the power semiconductor element Q. ＡWhen a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ａ is turned on, and the power semiconductor element Q Ａ When a negative gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ａ is turned off.

[0087] The gate line 12-B is connected to the gate drive voltage supply unit 11-B and the power semiconductor element Q Ｂ The gate line 12-B supplies the gate drive voltage output from the gate drive voltage supply unit 11-B to the corresponding power semiconductor element Q Ｂ The power semiconductor element Q is supplied with a voltage from the gate terminal of the power semiconductor element Q. Ｂ When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ｂ is turned on, and the power semiconductor element Q Ｂ When a negative gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ｂ is turned off.

[0088] The gate line 12-C is connected to the gate drive voltage supply unit 11-C and the power semiconductor element Q Ｃ The gate line 12-C supplies the gate drive voltage output from the gate drive voltage supply unit 11-C to the corresponding power semiconductor element Q Ｃ The power semiconductor element Q is supplied with a voltage from the gate terminal of the power semiconductor element Q. Ｃ When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ｃ is turned on, and the power semiconductor element Q Ｃ When a negative gate drive voltage is applied to the gate terminal of the power semiconductor element Q Ｃ is turned off.

[0089] The magnetic coupling portion 13 magnetically couples the gate line 12-A to the gate line 12-B, and magnetically couples the gate line 12-B to the gate line 12-C. The magnetic coupling portion 13 is as described with reference to FIG.

[0090] When three or more power semiconductor devices connected in series are turned on and off, the problem of voltage imbalance described with reference to FIG. 5 also occurs.

[0091] 11A is a diagram showing simulated waveforms of drain-source voltage and drain-source current when three serially connected power semiconductor elements are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A). FIG. 11B is a diagram showing simulated waveforms of gate-source voltage when three serially connected power semiconductor elements are switched from on operation to off operation in the invention described in Patent Document 1 (JP 2002-204578 A).

[0092] In the simulation, the power semiconductor element Q Ａ , Q Ｂ and Q Ｃ is a SiC-MOSFET with a breakdown voltage of 3.3 kV / 750 A, and the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q Ｃ It is assumed that a load current of 750 A flows when the voltage of the DC power supply 200 connected between the source terminal of the positive side potential output section 21P-A and the source terminal of the positive side potential output section 21P-A is 5400 V. The load is an inductive load of 10 mH. The inductances of the main circuit wiring connected to the load are 22 nH and 23 nH. Ａ , the positive potential VP of the positive potential output section 21P-B Ｂ and the positive potential VP of the positive potential output section 21P-C Ｃ is set to 17 V. The negative potential VN of the negative potential output section 21N-A Ａ , the negative potential VN of the negative potential output section 21N-B Ｂ and the negative potential VN of the negative potential output section 21N-C Ｃ is set to -11V. Power semiconductor element Q Ａ , Q Ｂ and Q Ｃ The internal resistance of each of the positive gate resistors R ｇｏｎ -A, R ｇｏｎ -B and R ｇｏｎ -C and negative gate resistance R ｇｏｆｆ -A, R ｇｏｆｆ -B and R ｇｏｆｆ The winding ratio of the magnetic coupling portion 13 is set to "1:1", the self-inductance is set to 70 μH, and the coupling coefficient is set to 0.97. The parasitic capacitance C of the magnetic coupling portion 13ｔｒ -1 and C ｔｒ -2 is set to 40 pF each.

[0093] As shown in FIGS. 11A and 11B, the power semiconductor element Q Ａ The gate-source voltage V ｇｓ Looking at the waveform of -A, the power semiconductor element Q Ａ The drain-source voltage V ｄｓ When -A rises, the power semiconductor element Q Ｂ The gate-source voltage V ｇｓ -B and power semiconductor element Q Ｃ The gate-source voltage V ｇｓ -C rises, and power semiconductor element Q Ｂ and Q Ｃ The timing at which the power semiconductor element Q switches from ON to OFF is Ａ As a result, the power semiconductor element Q after the switching from the ON operation to the OFF operation is delayed. Ａ The drain-source voltage V ｄｓ -A is a power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B and power semiconductor element Q Ｃ The drain-source voltage V ｄｓ It can be seen that the power semiconductor element Q Ｂ Since two transformers of the magnetic coupling unit 13 are connected in series to the gate line 12-B of the power semiconductor element Q Ｂ The timing at which the power semiconductor element Q switches from ON to OFF is Ｃ is delayed from the timing at which the power semiconductor element Q is switched from the ON operation to the OFF operation, and after the switching from the ON operation to the OFF operation is completed, Ｂ The drain-source voltage V ｄｓ -B is the power semiconductor element Q Ｃ The drain-source voltage V ｄｓ It can be seen that it is slightly lower than -C.

[0094] In the example shown in FIG. 10, three power semiconductor elements Q Ａ , Q Ｂ and Q Ｃ Among these, the power semiconductor element Q is arranged on the highest potential side. Ａ The gate drive voltage output from the gate drive voltage supply unit 11-A provided corresponding to the power semiconductor element Q Ｂ The gate drive voltage output by the gate drive voltage supply unit 11-B provided corresponding to the power semiconductor element Q Ｃ The gate drive voltage is set to be larger than the gate drive voltage output by the gate drive voltage supply unit 11-C provided corresponding to the power semiconductor element Q Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ and Q Ｃ The delay is made to coincide with the timing of switching from ON to OFF.

[0095] There are three ways to set the gate drive voltage output by the gate drive voltage supply unit 11-A to be higher than the gate drive voltages output by the gate drive voltage supply units 11-B and 11-C.

[0096] In the first mode, the gate drive voltage output from the gate drive voltage supply unit 11-A is set to be larger than the gate drive voltages output from the gate drive voltage supply units 11-B and 11-C. Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ and power semiconductor element Q Ｃ The positive potential VP output by the positive potential output unit 21P-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ Set it to be larger than

[0097] 12A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when three series-connected power semiconductor elements in the gate drive device according to the first embodiment of the present disclosure are switched from on operation to off operation, and FIG. 12B is a diagram showing simulated waveforms of the gate-source voltage when three series-connected power semiconductor elements in the gate drive device according to the first embodiment of the present disclosure are switched from on operation to off operation.

[0098] In the simulations of FIGS. 12A and 12B, the positive potential VP output by the positive potential output section 21P-A Ａ is set to 17.5 V, and the positive potential VP output from the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B is Ｂ and the positive potential VP output by the positive potential output unit 21P-C in the gate drive voltage supply unit 11-B. Ｃ was set to 17 V. The other simulation conditions for Figures 12A and 12B were the same as those for Figures 11A and 11B.

[0099] As shown in FIGS. 12A and 12B, the positive potential VP output from the positive potential output section 21P-A Ａ is the positive potential VP output by the positive potential output section 21P-B. Ｂ and the positive potential VP output by the positive potential output section 21P-C Ｃ By setting it to 0.5 V higher than Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ and Q Ｃ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B and power semiconductor element Q Ｃ The drain-source voltage V ｄｓ -C almost coincides with each other, and it can be seen that the voltage imbalance is suppressed.

[0100] In a second embodiment, the gate drive voltage output from the gate drive voltage supply unit 11-A is set to be larger than the gate drive voltages output from the gate drive voltage supply units 11-B and 11-C. Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ and power semiconductor element Q Ｃ The negative potential VN output by the negative potential output unit 21N-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ Set it to be larger than

[0101] In a third embodiment, the gate drive voltage output from the gate drive voltage supply unit 11-A is set to be larger than the gate drive voltages output from the gate drive voltage supply units 11-B and 11-C. Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ and power semiconductor element Q Ｃ The positive potential VP output by the positive potential output unit 21P-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ The power semiconductor element Q Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ and power semiconductor element Q Ｃ The negative potential VN output by the negative potential output unit 21N-C in the gate drive voltage supply unit 11-C provided corresponding to ＣSet it to be larger than

[0102] In the first to third embodiments described above, three power semiconductor elements Q connected in series Ａ , Q Ｂ and Q Ｃ Even when the power semiconductor element Q is turned on and off, the power semiconductor element Q disposed on the highest potential side is turned on and off depending on the magnitude of the power supply voltage output by the DC power supply 200. Ａ The gate drive voltage output by the gate drive voltage supply unit 11-A provided corresponding to the power semiconductor element Q Ｂ and Q Ｃ By setting the difference between the gate drive voltages output by the gate drive voltage supply units 11-B and 11-C provided corresponding to the parasitic capacitance C ｔｒ It is possible to suppress the occurrence of voltage imbalance caused by −1.

[0103] <Second Embodiment> In a second embodiment of the present disclosure, the output timing of a gate signal that switches on to off a power semiconductor element that is arranged on the highest potential side among a plurality of power semiconductor elements connected in series is set to be later than the output timing of gate signals that switch on to off other power semiconductor elements other than the power semiconductor element arranged on the highest potential side. This allows the timing of switching from on operation to off operation of the power semiconductor element arranged on the highest potential side to coincide with the timing of switching from on operation to off operation of the other power semiconductor elements, thereby reducing the parasitic capacitance C of the magnetic coupling portion 13. ｔｒ It is possible to suppress the occurrence of voltage imbalance caused by −1.

[0104] As shown in FIG. 1, the gate driver 1 according to the second embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B. The gate driving voltage supply units 11-A and 11-B, the gate lines 12-A and 12-B, the magnetic coupling unit 13, and the positive gate resistance R ｇｏｎ -A and R ｇｏｎ-B, and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B is as described with reference to FIGS.

[0105] 3 and 4, a power conversion device 100 including a gate driver 1 according to a second embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3) each provided with a plurality of power semiconductor elements connected in series and performing power conversion operation in response to the on / off operation of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2. The arms 50 and the power conversion circuit unit 2 are as described with reference to FIGS. 3 and 4.

[0106] As described above, the voltage imbalance among the plurality of power semiconductor elements connected in series is determined by the magnitude of the displacement current and varies depending on the magnitude of the voltage change applied to the plurality of power semiconductor elements connected in series (i.e., the voltage change between the drain terminal of the power semiconductor element arranged on the highest potential side and the source terminal of the power semiconductor element arranged on the lowest potential side). The voltage between the drain terminal of the power semiconductor element arranged on the highest potential side and the source terminal of the power semiconductor element arranged on the lowest potential side corresponds to the power supply voltage output by the DC power supply 200. In the second embodiment of the present disclosure, the power conversion control unit 3 outputs each gate signal so that the output timing of the gate signal that switches the power semiconductor element arranged on the highest potential side from on to off is delayed compared to the output timing of the gate signals that switch the power semiconductor elements other than the power semiconductor element arranged on the highest potential side from on to off. The time difference between the output timing of the gate signal that switches the power semiconductor element located on the highest potential side from on to off and the output timing of the gate signal that switches the other power semiconductor elements from on to off is set according to the magnitude of the voltage of the DC power supply connected to one of the two terminals of a set consisting of multiple power semiconductor elements connected in series.

[0107] 1, the power conversion control unit 3 outputs gate signals for controlling the on and off operations of the positive side switches 23P-A and 23P-B and the negative side switches 23N-A and 23N-B in each gate drive device 1. Ａ The timing of outputting the gate signal that turns the power semiconductor element Q from ON to OFF is determined by the timing of outputting the gate signal that turns the power semiconductor element Q from the power conversion control unit 3. Ｂ The power conversion control unit 3 controls the on and off operations of the positive side switches 23P-A and 23P-B and the negative side switches 23N-A and 23N-B in each gate drive device 1 using the gate signals, thereby controlling the power semiconductor element Q Ａ and Q Ｂ , and thereby controlling the voltage applied to the gate terminal of the power semiconductor element Q Ａ and Q Ｂ performs an ON / OFF operation.

[0108] FIG. 13 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two power semiconductor elements connected in series in the gate drive device according to the second embodiment of the present disclosure are switched from an on operation to an off operation.

[0109] In the simulation of FIG. 13, the power semiconductor element Q Ａ The output timing of the gate signal that turns the power semiconductor element Q Ｂ The output timing of the gate signal that changes the gate from on to off was set to 550 ns (550 nanoseconds). The other simulation conditions for Fig. 13 were the same as those for Figs. 6A and 6B.

[0110] As shown in FIG. 13, the power semiconductor element Q Ａ The output timing of the gate signal that turns the power semiconductor element Q Ｂ By setting the timing 550 ns later than the output timing of the gate signal that turns the power semiconductor element Q ＡThe timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B almost coincides with each other, and it can be seen that the voltage imbalance is suppressed.

[0111] The second embodiment of the present disclosure can also be applied to a gate driver that turns on and off three or more power semiconductor elements connected in series. For example, as shown in FIG. 10, Ａ , Q Ｂ and Q Ｃ When the power semiconductor element Q is driven on and off, the power semiconductor element Q is placed on the highest potential side. Ａ The output timing of the gate signal that turns the power semiconductor element Q from ON to OFF is Ｂ and Q Ｃ The timing is set to be slower than the output timing of the gate signal that turns the power semiconductor element Q from on to off. Ａ The output timing of the gate signal that turns the power semiconductor element Q from ON to OFF Ｂ and Q Ｃ The time difference between the output timing of the gate signal that turns on and off the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q Ｃ The value is set in accordance with the magnitude of the voltage of the DC power supply 200 applied between the source terminal of the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 in FIG. 3, which is located on the lowest potential side. Ｃ A DC power supply 200 is connected between the source terminal of the power semiconductor element Q Ｃ and the source terminal of the power semiconductor element Q in the lower arm 50. Ａ The drain terminal of the transistor is connected to a load 300 .

[0112] <Third Embodiment> In a third embodiment of the present disclosure, the resistance value of a gate resistor provided corresponding to a power semiconductor element arranged on the highest potential side among a plurality of power semiconductor elements connected in series is set to be larger than the resistance values ​​of gate resistors provided corresponding to other power semiconductor elements other than the power semiconductor element arranged on the highest potential side. By setting the resistance values ​​of the gate resistors in this manner, the timing of switching from on to off of the power semiconductor element arranged on the highest potential side is made to coincide with the timing of switching from on to off of the other power semiconductor elements. This reduces the parasitic capacitance C of the magnetic coupling portion 13. ｔｒ It is possible to suppress the occurrence of voltage imbalance caused by −1.

[0113] As shown in FIG. 1, the gate driver 1 according to the third embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B. The gate drive voltage supply units 11-A and 11-B, the gate lines 12-A and 12-B, the magnetic coupling unit 13, and the positive gate resistance R ｇｏｎ -A and R ｇｏｎ -B is as described with reference to FIGS.

[0114] 3 and 4, a power conversion device 100 including a gate driver 1 according to a third embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3) each provided with a plurality of power semiconductor elements connected in series and performing power conversion operation in response to the on / off operation of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2. The arms 50, the power conversion circuit unit 2, and the power conversion control unit 3 are as described with reference to FIGS. 3 and 4.

[0115] In the example shown in FIG. 1, two power semiconductor elements Q Ａ and Q ＢAmong these, the power semiconductor element Q is arranged on the highest potential side. Ａ A negative gate resistor R ｇｏｆｆ The resistance value of -A is Ｂ A negative gate resistor R ｇｏｆｆ Set to a value greater than the resistance value of -B.

[0116] As described above, the voltage imbalance among the plurality of power semiconductor elements connected in series is determined by the magnitude of the displacement current and varies according to the magnitude of the voltage change applied to the plurality of power semiconductor elements connected in series (i.e., the voltage change between the drain terminal of the power semiconductor element arranged on the highest potential side and the source terminal of the power semiconductor element arranged on the lowest potential side). The voltage between the drain terminal of the power semiconductor element arranged on the highest potential side and the source terminal of the power semiconductor element arranged on the lowest potential side corresponds to the power supply voltage output by DC power supply 200. In a third embodiment of the present disclosure, the resistance value of the negative-side gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side is made larger than the resistance values ​​of the negative-side gate resistors provided corresponding to the power semiconductor elements other than the power semiconductor element arranged on the highest potential side. The difference between the resistance value of the negative-side gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side and the resistance values ​​of the negative-side gate resistors provided corresponding to the other power semiconductor elements is set according to the magnitude of the voltage of the DC power supply connected to one of the two terminals of a set consisting of multiple power semiconductor elements connected in series.

[0117] FIG. 14 is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two power semiconductor elements connected in series in the gate drive device according to the third embodiment of the present disclosure are switched from an on operation to an off operation.

[0118] In the simulation of FIG. 14, the power semiconductor element Q Ａ A negative gate resistor R ｇｏｆｆ -A is set to 8 Ω, and the power semiconductor element Q Ｂ A negative gate resistor R ｇｏｆｆ-B was set to 0 Ω. The other simulation conditions for FIG. 14 were the same as those for FIGS. 6A and 6B. ｇｏｆｆ The 0 Ω of -B is only a setting in the simulation. In an actual circuit, for example, the negative gate resistance R ｇｏｆｆ This corresponds to the resistance value of −B being a very small value near 0.

[0119] As shown in FIG. 14, the power semiconductor element Q Ａ A negative gate resistor R ｇｏｆｆ The resistance value of -A is set to 8 Ω, and the power semiconductor element Q Ｂ A negative gate resistor R ｇｏｆｆ By setting the resistance value of -B to 0Ω, the power semiconductor element Q Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B almost coincides with each other, and it can be seen that the voltage imbalance is suppressed.

[0120] The third embodiment of the present disclosure can also be applied to a gate driver that turns on and off three or more power semiconductor elements connected in series. For example, as shown in FIG. 10, Ａ , Q Ｂ and Q Ｃ When the power semiconductor element Q is driven on and off, the power semiconductor element Q is placed on the highest potential side. Ａ A negative gate resistor R ｇｏｆｆ The resistance value of -A is Ｂ and Q Ｃ A negative gate resistor R ｇｏｆｆ -B and R ｇｏｆｆ - Set the resistance value to be larger than the resistance value of C. Power semiconductor element Q Ａ A negative gate resistor R ｇｏｆｆResistance value of -A and power semiconductor element Q Ｂ and Q Ｃ A negative gate resistor R ｇｏｆｆ -B and R ｇｏｆｆ The difference between the resistance value of -C and the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q Ｃ The value is set in accordance with the magnitude of the voltage of the DC power supply 200 applied between the source terminal of the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 in FIG. 3, which is located on the lowest potential side. Ｃ A DC power supply 200 is connected between the source terminal of the power semiconductor element Q Ｃ and the source terminal of the power semiconductor element Q in the lower arm 50. Ａ The drain terminal of the transistor is connected to a load 300 .

[0121] <Overall Configuration of Fourth to Seventh Embodiments> In the fourth to seventh embodiments of the present disclosure, a capacitor is further provided between the current outflow terminal (source terminal) and the control terminal (gate terminal) of the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series in the gate drive device 1 according to the first embodiment. By providing such a capacitor, the timing of switching from on to off of the power semiconductor element arranged on the highest potential side is made to coincide with the timing of switching from on to off of the other power semiconductor elements. As a result, the parasitic capacitance C of the magnetic coupling portion 13 ｔｒ It is possible to suppress the occurrence of voltage imbalance caused by −1.

[0122] 15 is a circuit diagram showing a gate driver for driving two serially connected power semiconductor elements Q1 and Q2 according to the fourth to seventh embodiments of the present disclosure. FIG. 15 is also applicable to the fifth to seventh embodiments of the present disclosure, which will be described later. Here, as an example, two serially connected power semiconductor elements Q1 and Q2 are shown. Ａ and Q ＢHowever, the following description is also applicable to the case where three or more power semiconductor elements connected in series are turned on and off.

[0123] Power semiconductor element Q Ａ The feedback diode D Ａ are connected in antiparallel. Similarly, the power semiconductor element Q Ｂ The feedback diode D Ｂ are connected in antiparallel. Ａ and Q Ｂ When is a MOSFET, the feedback diode D Ａ and D Ｂ are the power semiconductor elements Q Ａ and Q Ｂ The parasitic diode may be used instead.

[0124] As shown in FIG. 15, the gate driver 1 according to the fourth embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B and capacitor C ｇｓｐｌｕｓ The gate driving voltage supply units 11-A and 11-B, the gate lines 12-A and 12-B, the magnetic coupling unit 13, the positive gate resistance R ｇｏｎ -A and R ｇｏｎ -B, and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B is as described with reference to FIGS.

[0125] 3 and 4, a power conversion device 100 including a gate driver 1 according to a fourth embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3) each having a plurality of power semiconductor elements connected in series and performing power conversion operation in response to the on / off operation of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2. The arms 50, the power conversion circuit unit 2, and the power conversion control unit 3 are as described with reference to FIGS. 3 and 4.

[0126] Capacitor C ｇｓｐｌｕｓ is two power semiconductor elements Q connected in series. Ａ and Q Ｂ The power semiconductor element Q is arranged on the highest potential side of the Ａ The transistor is connected between a source terminal, which is a current output terminal, and a gate terminal, which is a control terminal, of the transistor.

[0127] As described above, the voltage imbalance among a plurality of power semiconductor elements connected in series is determined by the magnitude of the displacement current, and varies according to the magnitude of the voltage change applied to the plurality of power semiconductor elements connected in series (i.e., the voltage change between the drain terminal of the power semiconductor element arranged on the highest potential side and the source terminal of the power semiconductor element arranged on the lowest potential side). The voltage between the drain terminal of the power semiconductor element arranged on the highest potential side and the source terminal of the power semiconductor element arranged on the lowest potential side corresponds to the power supply voltage output by the DC power supply 200. In the fourth embodiment of the present disclosure, a capacitor C is provided between the gate terminal and source terminal of the power semiconductor element arranged on the highest potential side. ｇｓｐｌｕｓ is connected to the capacitor C ｇｓｐｌｕｓ The capacitance is set according to the magnitude of the voltage of the DC power supply 200 connected to one of the two terminals of the set made up of a plurality of power semiconductor elements connected in series.

[0128] 16A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements in the gate driver according to the fourth embodiment of the present disclosure are switched from on operation to off operation, and Fig. 16B is a diagram showing simulated waveforms of the gate-source voltage when two series-connected power semiconductor elements in the gate driver according to the fourth embodiment of the present disclosure are switched from on operation to off operation.

[0129] In the simulations of FIGS. 16A and 16B, the capacitor C ｇｓｐｌｕｓThe capacitance of the power semiconductor device Q used in the simulation was set to 8.4 nF. The other simulation conditions for Figs. 16A and 16B were the same as those for Figs. 6A and 6B. Ａ and Q Ｂ Since it is a SiC-MOSFET with a breakdown voltage of 3.3 kV / 750 A, the power semiconductor element Q Ａ and Q Ｂ The gate-source parasitic capacitance of is 210 nF. Therefore, the 8.4 nF capacitor C ｇｓｐｌｕｓ By adding the power semiconductor element Q Ａ The parasitic capacitance between the gate and source of the power semiconductor element Q Ｂ This is about 4% larger than the gate-source parasitic capacitance of

[0130] As shown in FIGS. 16A and 16B, the power semiconductor element Q Ａ A capacitor C of 8.4 nF is placed between the gate terminal and the source of ｇｓｐｌｕｓ By adding Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B almost coincides with each other, and it can be seen that the voltage imbalance is suppressed.

[0131] The above is a power semiconductor element Q connected in series. Ａ and Q Ｂ However, in the fourth embodiment, it is also possible to turn on and off three or more power semiconductor elements connected in series.

[0132] 17 is a circuit diagram showing a gate driver for turning on and off three power semiconductor elements connected in series according to the fourth to seventh embodiments of the present disclosure. FIG. 17 is also applicable to the fifth to seventh embodiments of the present disclosure, which will be described later. As an example, a gate driver for turning on and off three power semiconductor elements Q connected in series according to the fourth to seventh embodiments of the present disclosure. Ａ , QＢ and Q Ｃ An example of on / off driving will be described.

[0133] Power semiconductor element Q Ａ Diode D Ａ are connected in antiparallel. Similarly, the power semiconductor element Q Ｂ Diode D Ｂ are connected in antiparallel, and the power semiconductor element Q Ｃ Diode D Ｃ are connected in antiparallel. Ａ , Q Ｂ and Q Ｃ When is a MOSFET, the feedback diode D Ａ , D Ｂ and D Ｃ are the power semiconductor elements Q Ａ , Q Ｂ and Q Ｃ A parasitic diode may be used instead.

[0134] As shown in FIG. 17 , a gate driver 1 for driving three serially connected power semiconductor elements on and off according to the fourth embodiment of the present disclosure includes gate drive voltage supply units 11-A, 11-B, and 11-C, gate lines 12-A, 12-B, and 12-C, a magnetic coupling unit 13, and a positive gate resistor R ｇｏｎ -A, R ｇｏｎ -B and R ｇｏｎ -C and negative gate resistance R ｇｏｆｆ -A, R ｇｏｆｆ -B and R ｇｏｆｆ -C and capacitor C ｇｓｐｌｕｓ The gate driving voltage supply units 11-A, 11-B, and 11-C, the gate lines 12-A, 12-B, and 12-C, the magnetic coupling unit 13, and the positive gate resistance R ｇｏｎ -A, R ｇｏｎ -B and R ｇｏｎ -C, and negative gate resistance R ｇｏｆｆ -A, R ｇｏｆｆ -B and R ｇｏｆｆ -C has been described with reference to FIGS.

[0135] 3 and 4, a power conversion device 100 including a gate driver 1 according to a fourth embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3) each provided with a plurality of power semiconductor elements connected in series and performing power conversion operation in response to the on / off operation of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2. The arms 50, the power conversion circuit unit 2, and the power conversion control unit 3 are as described with reference to FIGS. 3 and 4.

[0136] Capacitor C ｇｓｐｌｕｓ is three power semiconductor elements Q connected in series. Ａ , Q Ｂ and Q Ｃ The power semiconductor element Q is arranged on the highest potential side of the Ａ The capacitor C is connected between the source terminal, which is the current output terminal, and the gate terminal, which is the control terminal. ｇｓｐｌｕｓ The capacitance of the power semiconductor element Q Ａ The drain terminal of the power semiconductor element Q Ｃ The value is set in accordance with the magnitude of the voltage of the DC power supply 200 connected between the source terminal of the inverter and the DC power supply 200.

[0137] <Switching of power semiconductor elements from off operation to on operation in first to fourth embodiments> In the first embodiment of the present disclosure, as shown in Figures 7A and 7B, when multiple power semiconductor elements connected in series are switched from off operation to on operation, no imbalance occurs in which a large voltage is applied to one of the power semiconductor elements, as occurs when multiple power semiconductor elements connected in series are switched from on operation to off operation as shown in Figures 6A and 6B.

[0138] In addition, in the second embodiment of the present disclosure, the output timing of the gate signal that switches the power semiconductor element that is located on the highest potential side among the multiple power semiconductor elements connected in series from on to off is set to be later than the output timing of the gate signals that switch the other power semiconductor elements other than the power semiconductor element located on the highest potential side from on to off. Similarly, by aligning the output timing of the gate signal that switches the power semiconductor element located on the highest potential side from off to on and the output timing of the gate signals that switch the other power semiconductor elements other than the power semiconductor element located on the highest potential side from off to on, an imbalance such as a large voltage being applied to one of the power semiconductor elements when switching the power semiconductor elements from off to on will not occur, as shown in Figures 7A and 7B.

[0139] Furthermore, in the third embodiment of the present disclosure, there is no difference in the resistance values ​​of the positive-side gate resistors that affect the behavior of the power semiconductor element when it switches from off operation to on operation, and therefore, as shown in Figures 7A and 7B, no imbalance occurs in which a large voltage is applied to one of the power semiconductor elements when the power semiconductor element switches from off operation to on operation.

[0140] On the other hand, in the fourth embodiment of the present disclosure, the capacitor C ｇｓｐｌｕｓ By adding this, when multiple serially connected power semiconductor devices are switched from OFF to ON, the drain-source voltage of the power semiconductor device arranged on the highest potential side increases instantaneously. This will be explained below.

[0141] 18A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements in the gate driver according to the fourth embodiment of the present disclosure are switched from off operation to on operation, and Fig. 18B is a diagram showing simulated waveforms of the gate-source voltage when two series-connected power semiconductor elements in the gate driver according to the fourth embodiment of the present disclosure are switched from off operation to on operation.

[0142] The simulation conditions for FIGS. 18A and 18B are the same as those for FIGS. 16A and 16B.

[0143] As shown in FIGS. 18A and 18B, the power semiconductor element Q Ａ A capacitor C of 8.4 nF is placed between the gate terminal and the source of ｇｓｐｌｕｓ By adding the power semiconductor element Q Ａ The gate-source voltage V ｇｓ The timing of the rise of -A is Ｂ The gate-source voltage V ｇｓ As a result, the timing of the rise of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A momentarily increases to 2125V. Such an overvoltage occurs in the power semiconductor device Q Ａ Power semiconductor element Q due to overheating caused by failure or deterioration of Ａ and Q Ｂ This may cause malfunction or deterioration of the product.

[0144] Therefore, as in the fourth embodiment, the capacitor C ｇｓｐｌｕｓ In the case where the capacitor C is added, it is preferable to suppress the overvoltage that occurs when the power semiconductor element is switched from an OFF state to an ON state. ｇｓｐｌｕｓ When the power semiconductor element is switched from OFF to ON, an overvoltage that may occur is suppressed.

[0145] Fifth Embodiment

[0146] As shown in FIG. 15, the gate driver 1 according to the fifth embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B and capacitor C ｇｓｐｌｕｓ3 and 4 , a power conversion device 100 including a gate driver 1 according to a fifth embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3 ) each provided with a plurality of power semiconductor elements connected in series and performing power conversion operation in response to on / off operations of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2.

[0147] Gate lines 12-A and 12-B, magnetic coupling portion 13, positive gate resistance R ｇｏｎ -A and R ｇｏｎ -B, negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B, and capacitor C ｇｓｐｌｕｓ 2 and 15. The arm 50, the power conversion circuit unit 2, and the power conversion control unit 3 are as described with reference to FIGS. 3 and 4.

[0148] In the fifth embodiment, in order to eliminate imbalances that occur when power semiconductor elements are switched from off to on, the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged at the highest potential among a plurality of power semiconductor elements connected in series is set to be higher than the gate drive voltages output by the gate drive voltage supplies provided corresponding to the power semiconductor elements other than the power semiconductor element arranged at the highest potential. This advances the timing of the switching from off to on of the power semiconductor element arranged at the highest potential so as to coincide with the timing of the switching from off to on of the power semiconductor elements other than the power semiconductor element arranged at the highest potential. As a result, it is possible to suppress overvoltages when the power semiconductor elements are switched from off to on.

[0149] In the fifth embodiment, as in the fourth embodiment, the capacitor C ｇｓｐｌｕｓ Two power semiconductor elements Q are connected in series. Ａ and Q Ｂ The power semiconductor element Q is arranged on the highest potential side of the ＡThe power semiconductor element Q is connected between the source terminal, which is the current output terminal, and the gate terminal, which is the control terminal. Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B are almost the same, so that the voltage imbalance can be suppressed.

[0150] There are three ways to set the gate drive voltage output by the gate drive voltage supply unit 11-A to be larger than the gate drive voltage output by the gate drive voltage supply unit 11-B, as explained in the first embodiment.

[0151] In the first mode, the gate drive voltage output from the gate drive voltage supply unit 11-A is set to be higher than the gate drive voltage output from the gate drive voltage supply unit 11-B. Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ As an example of the numerical value, the positive side potential VP outputted by the positive side potential output section 21P-A in the gate drive voltage supply section 11-A is set to be larger than Ａ is set to 17.5 V, and the positive potential VP output from the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B is Ｂ is set to 17 V. The negative potential VN output from the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A is set to 17 V. Ａ and the negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B. Ｂare both set to −11 V. Note that the values ​​given here are merely examples, and other values ​​may be used.

[0152] In the case of a gate driver 1 that turns on and off three power semiconductor elements connected in series as shown in FIG. 17, the three power semiconductor elements Q Ａ , Q Ｂ and Q Ｃ Among these, the power semiconductor element Q is arranged on the highest potential side. Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ and power semiconductor element Q Ｃ The positive potential VP output by the positive potential output unit 21P-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ This sets the power semiconductor element Q Ａ The timing of switching from the OFF operation to the ON operation of the power semiconductor element Q Ｂ and Q Ｃ The timing is advanced so as to coincide with the timing of switching from OFF to ON.

[0153] In the second mode, in which the gate drive voltage output by the gate drive voltage supply unit 11-A is set to be larger than the gate drive voltage output by the gate drive voltage supply unit 11-B, the negative side potential output by the negative side potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side is set to be larger than the negative side potential output by the negative side potential output unit in the gate drive voltage supply unit provided corresponding to the other power semiconductor elements. In the example shown in FIG. 15, two power semiconductor elements Q connected in series are Ａ and Q Ｂ Among these, the power semiconductor element Q is arranged on the highest potential side. Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element QＢ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ Set it to be larger than

[0154] 19A is a diagram showing simulated waveforms of the drain-source voltage and the drain-source current when two series-connected power semiconductor elements in the gate driver according to the fifth embodiment of the present disclosure are switched from off operation to on operation, and Fig. 19B is a diagram showing simulated waveforms of the gate-source voltage when two series-connected power semiconductor elements in the gate driver according to the fifth embodiment of the present disclosure are switched from on operation to off operation.

[0155] 19A and 19B are simulated under the same conditions as those for Fig. 16A and 16B, except that the negative potential VN output from the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A is Ａ -10.5V, and the negative potential VN output from the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B Ｂ is set to -11V.

[0156] As shown in FIGS. 19A and 19B, the negative potential VN output from the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A Ａ is converted into the negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B. Ｂ By setting the switching voltage to be greater than , the timing of switching from OFF to ON of the power semiconductor element arranged on the highest potential side is synchronized with the timing of switching from OFF to ON of the power semiconductor elements other than the power semiconductor element arranged on the highest potential side, thereby making it possible to suppress the occurrence of overvoltage when the power semiconductor elements are switched from OFF to ON.

[0157] In the case of a gate driver 1 that turns on and off three power semiconductor elements connected in series as shown in FIG. 17, the three power semiconductor elements Q Ａ , Q Ｂ and QＣ Among these, the power semiconductor element Q is arranged on the highest potential side. Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ and power semiconductor element Q Ｃ The negative potential VN output by the negative potential output unit 21N-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ For example, the negative potential VN output from the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A is set to be larger than Ａ -10.5V, and the negative potential VN output from the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B Ｂ and the negative potential VN output by the negative potential output unit 21N-C in the gate drive voltage supply unit 11-C. Ｃ is set to -11V.

[0158] In a third embodiment, the gate drive voltage output from the gate drive voltage supply unit 11-A is set to be higher than the gate drive voltage output from the gate drive voltage supply unit 11-B. Ａ The positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ and the negative potential VN output by the negative potential output section 21N-A. Ａ Each of these is a power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ and the negative potential VN output by the negative potential output section 21N-B Ｂ Set it to be larger than

[0159] As shown in FIG. 17, in the gate driver 1 that drives three power semiconductor elements connected in series to turn on and off, ＡThe positive potential VP output by the positive potential output unit 21P-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The positive potential VP output by the positive potential output unit 21P-B in the gate drive voltage supply unit 11-B provided corresponding to Ｂ and power semiconductor element Q Ｃ The positive potential VP output by the positive potential output unit 21P-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ The power semiconductor element Q Ａ The negative potential VN output by the negative potential output unit 21N-A in the gate drive voltage supply unit 11-A provided corresponding to Ａ power semiconductor element Q Ｂ The negative potential VN output by the negative potential output unit 21N-B in the gate drive voltage supply unit 11-B is provided corresponding to Ｂ and power semiconductor element Q Ｃ The negative potential VN output by the negative potential output unit 21N-C in the gate drive voltage supply unit 11-C provided corresponding to Ｃ Set it to be larger than

[0160] In the first to third forms, the difference between the gate drive voltage output by the gate drive voltage supply unit 11-A provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element is set according to the magnitude of the power supply voltage output by the DC power supply 200.

[0161] Sixth Embodiment

[0162] As shown in FIG. 15, the gate driver 1 according to the sixth embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B and capacitor C ｇｓｐｌｕｓThe gate driving voltage supply units 11-A and 11-B, the gate lines 12-A and 12-B, the magnetic coupling unit 13, the positive gate resistance R ｇｏｎ -A and R ｇｏｎ -B, negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B, and capacitor C ｇｓｐｌｕｓ This has been described with reference to FIGS.

[0163] 3 and 4, a power conversion device 100 including a gate driver 1 according to a sixth embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3) each provided with a plurality of power semiconductor elements connected in series and performing power conversion operation in response to the on / off operation of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2. The arms 50 and the power conversion circuit unit 2 are as described with reference to FIGS. 3 and 4.

[0164] In a sixth embodiment of the present disclosure, the output timing of a gate signal that switches the power semiconductor element positioned on the highest potential side from off to on among a plurality of power semiconductor elements connected in series is set to be earlier than the output timing of gate signals that switch the other power semiconductor elements other than the power semiconductor element positioned on the highest potential side from off to on. This allows the timing of switching the power semiconductor element positioned on the highest potential side from off to on to be advanced so as to coincide with the timing of switching the other power semiconductor elements other than the power semiconductor element positioned on the highest potential side from off to on. As a result, it is possible to suppress the occurrence of overvoltage when the power semiconductor elements switch from off to on. The time difference between the output timing of the gate signal that switches the power semiconductor element positioned on the highest potential side from off to on and the output timing of the gate signals that switches the other power semiconductor elements from off to on among the plurality of power semiconductor elements connected in series is set according to the magnitude of the voltage of the DC power supply 200 applied between the drain terminal of the power semiconductor element positioned on the highest potential side and the source terminal of the power semiconductor element positioned on the lowest potential side among the plurality of power semiconductor elements connected in series. The power semiconductor element Q in the upper arm 50 in FIG. 3, which is located on the highest potential side, Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 in FIG. 3, which is located on the lowest potential side. Ｂ A DC power supply 200 is connected between the source terminal of the power semiconductor element Q Ｂ and the source terminal of the power semiconductor element Q in the lower arm 50. Ａ The drain terminal of the transistor is connected to a load 300 .

[0165] In the sixth embodiment, as in the fourth embodiment, the capacitor C ｇｓｐｌｕｓ Two power semiconductor elements Q are connected in series. Ａ and Q Ｂ The power semiconductor element Q is arranged on the highest potential side of the Ａ The power semiconductor element Q is connected between the source terminal, which is the current output terminal, and the gate terminal, which is the control terminal. ＡThe timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B are almost the same, so that the voltage imbalance can be suppressed.

[0166] The sixth embodiment of the present disclosure can also be applied to a gate driver that turns on and off three or more power semiconductor elements connected in series. For example, as shown in FIG. 17 , Ａ , Q Ｂ and Q Ｃ When the power semiconductor element Q is driven on and off, the power semiconductor element Q is placed on the highest potential side. Ａ The output timing of the gate signal that changes the power semiconductor element Q from OFF to ON is Ｂ and Q Ｃ The power semiconductor element Q, which is located on the highest potential side, is set to be earlier than the output timing of the gate signal that turns the power semiconductor element Q from off to on. Ａ The output timing of the gate signal that turns the power semiconductor element Q from OFF to ON Ｂ and Q Ｃ The time difference between the output timing of the gate signal that turns the power semiconductor element Q1 from OFF to ON and the output timing of the gate signal that turns the power semiconductor element Q2 from OFF to ON is Ａ and the drain terminal of the power semiconductor element Q Ｃ The value is set in accordance with the magnitude of the voltage of the DC power supply 200 applied between the source terminal of the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 in FIG. 3, which is located on the lowest potential side. Ｃ A DC power supply 200 is connected between the source terminal of the power semiconductor element Q Ｃ and the source terminal of the power semiconductor element Q in the lower arm 50. Ａ The drain terminal of the transistor is connected to a load 300 .

[0167] Seventh Embodiment

[0168] As shown in FIG. 15, the gate driver 1 according to the seventh embodiment of the present disclosure includes gate drive voltage supply units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, and a positive-side gate resistor R ｇｏｎ -A and R ｇｏｎ -B and negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B and capacitor C ｇｓｐｌｕｓ The gate driving voltage supply units 11-A and 11-B, the gate lines 12-A and 12-B, the magnetic coupling unit 13, the negative gate resistance R ｇｏｆｆ -A and R ｇｏｆｆ -B, and capacitor C ｇｓｐｌｕｓ This has been described with reference to FIGS.

[0169] 3 and 4, a power conversion device 100 including a gate driver 1 according to a seventh embodiment of the present disclosure includes the gate driver 1, a power conversion circuit unit 2 having a plurality of arms 50 (four in FIG. 3) each provided with a plurality of power semiconductor elements connected in series and performing power conversion operation in response to the on / off operation of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2. The arms 50, the power conversion circuit unit 2, and the power conversion control unit 3 are as described with reference to FIGS. 3 and 4.

[0170] In the seventh embodiment, the power semiconductor element Q Ａ A positive gate resistor R ｇｏｎ The resistance value of -A is Ｂ A positive gate resistor R ｇｏｎ -B. This makes it smaller than the resistance value of the capacitor C. ｇｓｐｌｕｓ is connected between a source terminal which is a current outflow terminal and a gate terminal which is a control terminal. Ａ is a power semiconductor element Q Ｂ The timing of turning from off to on is synchronized. The power semiconductor element Q, which is located on the highest potential side ＡA positive gate resistor R ｇｏｎ Resistance value of -A and power semiconductor element Q Ｂ A positive gate resistor R ｇｏｎ The difference between the resistance value of -B and the resistance value of the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q Ｂ The value is set in accordance with the magnitude of the voltage of the DC power supply 200 applied between the source terminal of the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 in FIG. 3, which is located on the lowest potential side. Ｂ A DC power supply 200 is connected between the source terminal of the power semiconductor element Q Ｂ and the source terminal of the power semiconductor element Q in the lower arm 50. Ａ The drain terminal of the transistor is connected to a load 300 .

[0171] In the seventh embodiment, as in the fourth embodiment, the capacitor C ｇｓｐｌｕｓ Two power semiconductor elements Q are connected in series. Ａ and Q Ｂ The power semiconductor element Q is arranged on the highest potential side of the Ａ The power semiconductor element Q is connected between the source terminal, which is the current output terminal, and the gate terminal, which is the control terminal. Ａ The timing of switching from ON operation to OFF operation of the power semiconductor element Q Ｂ As a result, the timing of switching from ON operation to OFF operation of the power semiconductor element Q Ａ The drain-source voltage V ｄｓ -A and power semiconductor element Q Ｂ The drain-source voltage V ｄｓ -B are almost the same, so that the voltage imbalance can be suppressed.

[0172] The seventh embodiment of the present disclosure can also be applied to a gate driver that turns on and off three or more power semiconductor elements connected in series. For example, as shown in FIG. 17, Ａ , Q Ｂ and Q Ｃ When the power semiconductor element Q is driven on and off, the power semiconductor element Q is placed on the highest potential side. Ａ A positive gate resistor R ｇｏｎ The resistance value of -A is Ｂ and Q Ｃ A positive gate resistor R ｇｏｎ -B and R ｇｏｎ The resistance value of the power semiconductor element Q is set to be smaller than that of the power semiconductor element Q. Ａ A positive gate resistor R ｇｏｎ Resistance value of -A and power semiconductor element Q Ｂ and Q Ｃ A positive gate resistor R ｇｏｎ -B and R ｇｏｎ The difference between the resistance value of -C and the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q Ｃ The value is set in accordance with the magnitude of the voltage of the DC power supply 200 applied between the source terminal of the power semiconductor element Q Ａ and the drain terminal of the power semiconductor element Q in the lower arm 50 in FIG. 3, which is located on the lowest potential side. Ｃ A DC power supply 200 is connected between the source terminal of the power semiconductor element Q Ｃ and the source terminal of the power semiconductor element Q in the lower arm 50. Ａ The drain terminal of the transistor is connected to a load 300 .

[0173] <Processor and Memory> The power conversion device 100 includes at least one processor, which is an arithmetic processing device. Examples of the arithmetic processing device include an IC, an LSI, a CPU, an MPU, and a DSP. The arithmetic processing device includes a power conversion control unit 3 and other processing units. Each of these units in the arithmetic processing device is a functional module implemented by a program executed on the processor. For example, if the power conversion control unit 3 and other processing units are implemented in a program format, the functions of each unit can be realized by operating the arithmetic processing device in accordance with the program. The programs for executing each process in the power conversion control unit 3 and other processing units may be provided in a form recorded on a computer-readable recording medium such as a semiconductor memory, a magnetic recording medium, or an optical recording medium. Alternatively, the power conversion control unit 3 and other processing units may be implemented as a semiconductor integrated circuit in which a program implementing the function of each unit is written.

[0174] The power conversion device 100 is also provided with at least one memory serving as a storage device. The memory includes various storage units within the power conversion control unit 3 and other processing units. The memory may be, for example, an electrically erasable and recordable non-volatile memory such as an EEPROM (registered trademark), or a high-speed read / write random access memory such as a DRAM or an SRAM. The storage unit may also have a configuration such as an HDD (hard disk drive) or an SSD (solid state drive). The memory stores programs for operating the power conversion control unit 3 and other processing units. The memory also stores a gate signal generated by the power conversion control unit 3. The memory also stores a detected value i of the current flowing through the load 300. The memory also stores a current command i ＊ The memory also stores various programs and data related to the power conversion control unit 3. The memory also stores various programs and data related to the power conversion device 100.

[0175] Although the present disclosure has been described in detail above, the present disclosure is not limited to the individual embodiments and individual variations described above. Various additions, substitutions, modifications, partial deletions, etc. are possible for these embodiments and variations within the scope of the gist of the present disclosure, or within the scope of the gist of the present disclosure derived from the content of the claims and their equivalents. These embodiments and variations can also be implemented in combination. For example, in the above-described embodiments and variations, the order of each operation and the order of each process are shown as examples and are not limited to these. The same applies when numerical values ​​or mathematical formulas are used in the description of the above-described embodiments and variations.

[0176] REFERENCE SIGNS LIST 1 Gate drive device 2 Power conversion circuit section 3 Power conversion control section 11-A, 11-B, 11-C Gate drive voltage supply section 12-A, 12-B, 12-C Gate line 13 Magnetic coupling section 21N-A, 21N-B, 21N-C Negative side potential output section 21P-A, 21P-B, 21P-C Positive side potential output section 22-A, 22-B, 22-C Intermediate terminal 23P-A, 23P-B, 23P-C Positive side switch 23N-A, 23N-B, 23N-C Negative side switch 30 Magnetic body 50 Arm 60 Leg 100 Power conversion device 200 DC power supply 300 Load C ｇｓｐｌｕｓ Capacitor D Ａ , D Ｂ , D Ｃ Feedback diode P １ , P ２ Terminal Q Ａ , Q Ｂ , Q Ｃ Power semiconductor device R ｇｏｎ -A, R ｇｏｎ -B, R ｇｏｎ -C Positive gate resistance R ｇｏｆｆ -A, R ｇｏｆｆ -B, R ｇｏｆｆ -C Negative gate resistance T １ Terminal T ２ Terminals

Claims

1. A gate drive device for a plurality of power semiconductor elements connected in series, comprising: a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; gate lines that supply the gate drive voltage output from the gate drive voltage supply unit to the control terminals of each of the corresponding power semiconductor elements; and a magnetic coupling unit that magnetically couples each of the gate lines to each other, wherein the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element located on the highest potential side of the plurality of power semiconductor elements connected in series is set to be higher than the gate drive voltages output by gate drive voltage supply units provided corresponding to power semiconductor elements other than the power semiconductor element located on the highest potential side.

2. The gate drive device according to claim 1, wherein each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and wherein the positive potential output by the positive potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side is set to be higher than the positive potential output by the positive potential output unit in the gate drive voltage supply unit provided corresponding to the other power semiconductor elements.

3. The gate drive device according to claim 1, wherein each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and wherein the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side is set to be higher than the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the other power semiconductor elements.

4. The gate drive device according to claim 1, wherein each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and wherein the positive potential output by the positive potential output unit and the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side are set higher than the positive potential output by the positive potential output unit and the negative potential output by the negative potential output unit in the gate drive voltage supply units provided corresponding to the other power semiconductor elements, respectively.

5. A gate drive device according to any one of claims 1 to 4, wherein the difference between the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the other power semiconductor element is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of power semiconductor elements connected in series.

6. A gate drive device for a plurality of power semiconductor elements connected in series, comprising: a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; a gate line supplying the gate drive voltage output from the gate drive voltage supply unit to a control terminal of each of the corresponding power semiconductor elements; and a magnetic coupling unit magnetically coupling each of the gate lines to each other, wherein the output timing of a gate signal that switches on to off the power semiconductor element located on the highest potential side among the plurality of power semiconductor elements connected in series is set later than the output timing of a gate signal that switches on to off the other power semiconductor elements other than the power semiconductor element located on the highest potential side.

7. The gate drive device according to claim 6, wherein the time difference between the output timing of the gate signal that switches the power semiconductor element arranged on the highest potential side from on to off and the output timing of the gate signal that switches the other power semiconductor elements from on to off is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of power semiconductor elements connected in series.

8. A gate drive device for a plurality of power semiconductor elements connected in series, comprising: a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; gate lines supplying the gate drive voltage output from the gate drive voltage supply unit to the control terminals of each of the corresponding power semiconductor elements; a magnetic coupling unit magnetically coupling each of the gate lines to each other; and gate resistors provided corresponding to each of the power semiconductor elements and provided on a current path between the gate drive voltage supply unit and the gate line corresponding to the gate drive voltage supply unit, wherein the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series is set to be larger than the resistance values ​​of the gate resistors provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

9. The gate drive device according to claim 8, wherein a difference between the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side and the resistance value of the gate resistor provided corresponding to the other power semiconductor element is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of the power semiconductor elements connected in series.

10. A gate drive device for a plurality of power semiconductor elements connected in series, comprising: a gate drive voltage supply unit provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; gate lines supplying the gate drive voltage output from the gate drive voltage supply unit to the control terminals of the corresponding power semiconductor elements; a magnetic coupling unit magnetically coupling each of the gate lines to each other; and a capacitor connected between the current output terminal and the control terminal of the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series.

11. The gate drive device according to claim 10, wherein the capacitance of the capacitor is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of the power semiconductor elements connected in series.

12. A gate drive device as described in claim 10, wherein the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series is set to be higher than the gate drive voltage output by the gate drive voltage supply units provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

13. The gate drive device according to claim 12, wherein each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and wherein the positive potential output by the positive potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side is set to be higher than the positive potential output by the positive potential output unit in the gate drive voltage supply unit provided corresponding to the other power semiconductor element.

14. The gate drive device according to claim 12, wherein each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and wherein the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side is set to be higher than the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the other power semiconductor element.

15. The gate drive device according to claim 12, wherein each of the gate drive voltage supply units has a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and wherein the positive potential output by the positive potential output unit and the negative potential output by the negative potential output unit in the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side are set higher than the positive potential output by the positive potential output unit and the negative potential output by the negative potential output unit in the gate drive voltage supply units provided corresponding to the other power semiconductor elements, respectively.

16. A gate drive device as claimed in any one of claims 13 to 15, wherein the difference between the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the power semiconductor element arranged on the highest potential side and the gate drive voltage output by the gate drive voltage supply unit provided corresponding to the other power semiconductor element is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of power semiconductor elements connected in series.

17. A gate drive device as described in claim 10, wherein the output timing of a gate signal that switches from OFF to ON the power semiconductor element that is located on the highest potential side among the plurality of power semiconductor elements connected in series is set earlier than the output timing of gate signals that switch from OFF to ON the other power semiconductor elements other than the power semiconductor element that is located on the highest potential side.

18. The gate drive device of claim 17, wherein the time difference between the output timing of the gate signal that switches the power semiconductor element arranged on the highest potential side from off to on and the output timing of the gate signal that switches the other power semiconductor elements from off to on is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of power semiconductor elements connected in series.

19. The gate drive device according to claim 10, further comprising gate resistors provided corresponding to each of the power semiconductor elements and arranged on a path of current flowing from the gate drive voltage supply unit to the gate line corresponding to that gate drive voltage supply unit, wherein the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side among the plurality of power semiconductor elements connected in series is set to be smaller than the resistance values ​​of the gate resistors provided corresponding to the other power semiconductor elements other than the power semiconductor element arranged on the highest potential side.

20. The gate drive device according to claim 19, wherein a difference between the resistance value of the gate resistor provided corresponding to the power semiconductor element arranged on the highest potential side and the resistance value of the gate resistor provided corresponding to the other power semiconductor element is set according to the magnitude of the voltage of a DC power supply connected to one of two terminals of a set consisting of a plurality of the power semiconductor elements connected in series.

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