Imaging element and imaging device

Abstract

This imaging element comprises: a first photoelectric conversion unit that performs photoelectric conversion; a second photoelectric conversion unit that is arranged side by side with the first photoelectric conversion unit in a row direction and performs photoelectric conversion; a first accumulation unit to which charge converted by the first photoelectric conversion unit is transferred; a second accumulation unit to which charge converted by the first photoelectric conversion unit is transferred; a third accumulation unit to which charge converted by the second photoelectric conversion unit is transferred; a fourth accumulation unit to which charge converted by the second photoelectric conversion unit is transferred; a first transfer unit that has a plurality of transistors for transferring the charge converted by the first photoelectric conversion unit and transfers the charge in order of the first accumulation unit and the second accumulation unit; a second transfer unit that has a plurality of transistors for transferring the charge converted by the second photoelectric conversion unit and transfers the charge in order of the third accumulation unit and the fourth accumulation unit; and a drive unit that performs control such that a first timing, at which the charge converted by the first photoelectric conversion unit is transferred to the second accumulation unit by the first transfer unit, and a second timing, at which the charge converted by the second photoelectric conversion unit is transferred to the fourth accumulation unit by the second transfer unit, are different.

Description

Image sensor and image pickup device Incorporation by Reference

[0001] This application claims priority from Japanese Patent Application No. 2024-100351, filed on June 21, 2024, the contents of which are incorporated herein by reference.

[0002] The present invention relates to an imaging element and an imaging device.

[0003] 2. Description of the Related Art Image sensors having a pixel array in which a plurality of pixels are arranged in a matrix are known (see, for example, Japanese Patent Application Laid-Open No. 2003-122999). Improved frame rates of image sensors have been desired for some time.

[0004] JP 2014-60697 A

[0005] The imaging element of the disclosed technique includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in the row direction, a first accumulation unit to which the electric charges converted by the first photoelectric conversion unit are transferred, a second accumulation unit to which the electric charges converted by the first photoelectric conversion unit are transferred, a third accumulation unit to which the electric charges converted by the second photoelectric conversion unit are transferred, a fourth accumulation unit to which the electric charges converted by the second photoelectric conversion unit are transferred, and a transistor for transferring the electric charges converted by the first photoelectric conversion unit. a first transfer section having a plurality of transistors for transferring the charges converted by the second photoelectric conversion section and transferring the charges in the order of the first accumulation section and the second accumulation section; a second transfer section having a plurality of transistors for transferring the charges converted by the second photoelectric conversion section and transferring the charges in the order of the third accumulation section and the fourth accumulation section; and a drive section that controls so that a first timing at which the charges converted by the first photoelectric conversion section are transferred to the second accumulation section by the first transfer section and a second timing at which the charges converted by the second photoelectric conversion section are transferred to the fourth accumulation section by the second transfer section are different timings.

[0006] FIG. 1 is an explanatory diagram illustrating the basic principle of a ToF sensor. FIG. 2 is an exploded perspective view illustrating an example of an image sensor. FIG. 3 is an explanatory diagram illustrating an example of a specific configuration of a pixel unit. FIG. 4 is a circuit diagram illustrating an example of a circuit configuration of a pixel according to Example 1. FIG. 5 is an explanatory diagram illustrating an example of a specific configuration of a control circuit unit. FIG. 6 is an explanatory diagram illustrating an example of an internal configuration of a control block. FIG. 7 is a timing chart illustrating an example of exposure timing control of a pixel according to Example 1. FIG. 8 is an explanatory diagram illustrating an example of a block configuration of an image sensor according to Example 1. FIG. 9 is an explanatory diagram illustrating an example of a circuit configuration of an image sensor according to Example 1. FIG. 10 is an explanatory diagram illustrating an example of a conversion table according to Example 1. FIG. 11 is an explanatory diagram illustrating a correspondence relationship between a ratio and a time of flight. FIG. 12 is an explanatory diagram illustrating a modified example of the circuit configuration of the image sensor illustrated in FIG. 8. FIG. 13 is an explanatory diagram illustrating a detailed circuit configuration example 1 of an image sensor according to Example 1. FIG. 14 is an explanatory diagram illustrating a detailed circuit configuration example 2 of an image sensor according to Example 1. FIG. 15 is an explanatory diagram illustrating a detailed circuit configuration example 3 of an image sensor according to Example 1. FIG. 16 is an explanatory diagram showing a selection process of the S&H selection circuit according to the first embodiment. FIG. 17 is a graph showing an example of generation of a digital signal according to the first embodiment. FIG. 18 is an explanatory diagram showing an example of a first conversion table. FIG. 19 is an explanatory diagram showing an example of a second conversion table. FIG. 20 is an explanatory diagram showing another configuration example of the exposure control unit. FIG. 21 is a truth table showing the correspondence relationship between the resistance value of a variable resistor, a control signal, and a ratio. FIG. 22 is an explanatory diagram showing another configuration example of the exposure control unit. FIG. 23 is a timing chart of the exposure control unit. FIG. 24 is an explanatory diagram showing a first calculation example of the time of flight. FIG. 25 is an explanatory diagram showing a second calculation example of the time of flight. FIG. 26 is a schematic partial cross-sectional side view showing a first layout variation. FIG. 27 is a schematic partial cross-sectional side view showing a second layout variation. FIG. 28 is a schematic partial cross-sectional side view showing a third layout variation. FIG. 29 is an explanatory diagram showing a modification of exposure timing control according to the first embodiment. FIG. 30 is a circuit diagram showing an example of a circuit configuration of a pixel according to the second embodiment. Fig. 31 is a timing chart showing an example of exposure timing control of a pixel according to Example 2. Fig. 32 is an explanatory diagram showing an example of a block configuration of an image sensor according to Example 2.FIG. 33 is a diagram illustrating an example of a circuit configuration of an image sensor according to Example 2. FIG. 34 is a diagram illustrating an example of a conversion table according to Example 2. FIG. 35 is a diagram illustrating a detailed circuit configuration example 1 of an image sensor according to Example 2. FIG. 36 is a diagram illustrating a detailed circuit configuration example 2 of an image sensor according to Example 2. FIG. 37 is a diagram illustrating a detailed circuit configuration example 3 of an image sensor according to Example 2. FIG. 38 is a diagram illustrating a selection process of an S&H selection circuit according to Example 2. FIG. 39 is a graph illustrating an example of generation of a digital signal according to Example 2. FIG. 40 is a diagram illustrating a modified example of exposure timing control according to Example 2.

[0007] <Figure 1: Basic Principle of a ToF (Time of Flight) Sensor> Figure 1 is an explanatory diagram showing the basic principle of a ToF sensor. (A) An electronic device 100, such as an image capture device or a rangefinder, and a subject 110 are placed at a distance L apart. The electronic device 100 has a light source 101, an image sensor 102, a control unit 103, a calculation unit 104, a recording unit 105, a display unit 106, and a bus 107.

[0008] Light source 101 irradiates light onto subject 110. Image sensor 102 receives the light reflected from subject 110 and performs photoelectric conversion. Electronic device 100 measures the time of flight Td of light from when the light is irradiated onto subject 110 until the reflected light returns. If the speed of light is c, then distance L is calculated by the following formula (1):

[0009] L=(c×Td) / 2...(1)

[0010] There are two methods for calculating the above formula (1): a direct ToF method and an indirect ToF method. The direct ToF method is a measurement method that uses a TDC (Time to Digital Converter) to convert the difference between the time of irradiation of light from the electronic device 100 and the time of reception of reflected light into a digital value indicating the distance L. The indirect ToF method is a measurement method that calculates the distance L based on the phase difference between the irradiated light and the reflected light. The indirect ToF method does not require a TDC, so it is easier to achieve a higher number of pixels than the direct ToF method. Although the examples shown in (B) and (C) are described using the indirect ToF method, the direct ToF method may also be used.

[0011] The control unit 103 controls the light source 101 and the image sensor 102. Specifically, for example, the control unit 103 controls a pulse width (T0 in FIG. 7 , which will be described later) that indicates the projection time of light emitted from the light source 101 and the light reception time during which the image sensor 102 receives light reflected from the subject 110. The calculation unit 104 corrects image data from the image sensor 102, measures the time of flight Td, and calculates the distance L. At least one of the control unit 103 and the calculation unit 104 may be implemented inside the image sensor 102.

[0012] The recording unit 105 is configured with a recording device such as an SSD (Solid State Drive) or an HDD (Hard Disk Drive), and records image data from the image sensor 102 and calculation results by the calculation unit 104. The display unit 106 is configured with a display device such as an organic EL display, and displays the image data and calculation results. The bus 107 connects the light source 101, the image sensor 102, the control unit 103, the calculation unit 104, the recording unit 105, and the display unit 106 so that they can communicate with each other.

[0013] The electronic device 100 may be connected to an upstream control system (not shown). The control system performs automatic driving of a moving object such as an automobile (control of the steering wheel, brake, and accelerator), generates data by inputting it to a 3D printer, and controls a machine tool based on the calculation results (for example, flight time Td and distance L) by the calculation unit 104.

[0014] 1B and 1C are explanatory diagrams showing an example of the layout of a charge distribution element in a ToF sensor. 1B shows a two-tap charge distribution element 121. 1C shows a three-tap charge distribution element 122. In 1B and 1C, PPD is a buried photodiode, and FD1 to FD3 (when not distinguished, simply referred to as FD) are buried storages that accumulate charge photoelectrically converted by the PPD.

[0015] TGD is a transistor that controls the discharge of electric charge. TG1 to TG3 (when not distinguished, simply referred to as TG) are transistors that accumulate electric charge in FD1 to FD3. TGD is a transistor that controls the discharge of electric charge in PPD. TGD constitutes a discharge unit and resets the electric charge in PPD.

[0016] In the following Example 1, an image sensor 102 equipped with a two-tap charge distribution element 121 will be described, and in Example 2, an image sensor 102 equipped with a three-tap charge distribution element 122 will be described. The three-tap charge distribution element 122 can remove background light using TG3 and FD3.

[0017] In this specification, the X-axis and Y-axis are orthogonal to each other, and the Z-axis is orthogonal to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the image sensor 102. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as a "row" and the arrangement in the Y-axis direction will be described as a "column," but the matrix direction is not limited to this.

[0018] 2 to 29 , the configuration of the image sensor 102 equipped with the two-tap charge distribution element 121 will be described. The structure of the image sensor 102 may be either a back-illuminated type or a front-illuminated type.

[0019] [Figure 2 Image Sensor 102] Figure 2 is an exploded perspective view showing an example of the image sensor 102. The image sensor 102 is provided in the electronic device 100 and captures an image of the subject 110. The image sensor 102 generates image data of the captured image of the subject 110. The image sensor 102 includes a first semiconductor substrate 210, a second semiconductor substrate 220, and a third semiconductor substrate 230. As shown in Figure 2, the first semiconductor substrate 210 is stacked on the second semiconductor substrate 220, and the second semiconductor substrate 220 is stacked on the third semiconductor substrate 230.

[0020] The first semiconductor substrate 210 has a pixel unit 201. The pixel unit 201 outputs a pixel signal based on incident light. Specifically, for example, the pixel unit 201 outputs a pixel signal based on light that is irradiated from the electronic device 100 and reflected by the subject 110.

[0021] The second semiconductor substrate 220 has a control circuit section 202 and a peripheral circuit section 221 .

[0022] The control circuit unit 202 receives the pixel signals output from the first semiconductor substrate 210. The control circuit unit 202 processes the received pixel signals. The control circuit unit 202 is disposed on the second semiconductor substrate 220 at a position facing the pixel unit 201. For example, the control circuit unit 202 is disposed so as to overlap with the pixel unit 201 in the direction in which the first semiconductor substrate 210 and the second semiconductor substrate 220 are stacked. The control circuit unit 202 may output a control signal to the pixel unit 201 for controlling the driving of the pixel unit 201.

[0023] The peripheral circuit unit 221 controls the driving of the control circuit unit 202. The peripheral circuit unit 221 is arranged around the control circuit unit 202 on the second semiconductor substrate 220. Specifically, the peripheral circuit unit 221 is arranged in an area of ​​the second semiconductor substrate 220 that is arranged outside the area where the control circuit unit 202 is arranged. The peripheral circuit unit 221 may also be electrically connected to the first semiconductor substrate 210 and control the driving of the pixel unit 201. The peripheral circuit unit 221 is arranged along two sides of the second semiconductor substrate 220, but the arrangement of the peripheral circuit unit 221 is not limited to this example.

[0024] The third semiconductor substrate 230 has a data processing unit 203. The data processing unit 203 uses the digital data output from the second semiconductor substrate 220 to perform addition processing, thinning processing, and other image processing.

[0025] [Figure 3 Pixel Unit 201] Figure 3 is an explanatory diagram showing an example of a specific configuration of the pixel unit 201. The pixel unit 201 has a plurality of pixel blocks 300. The plurality of pixel blocks 300 are arranged in the row and column directions in the pixel unit 201. Specifically, the plurality of pixel blocks 300 includes M x N (M and N are natural numbers) pixel blocks 300 arranged in the row and column directions in the pixel unit 201. Although the figure shows a case where M is equal to N, M and N may be different.

[0026] The pixel block 300 has a plurality of pixels 301. The pixels 301 are configured, for example, by the two-tap charge distribution element 121 shown in FIG. 1B . The plurality of pixels 301 are arranged in rows and columns in the pixel block 300. The pixel block 300 has m×n pixels 301 (m and n are natural numbers) arranged in rows and columns. For example, the pixel block 300 has 16×16 pixels 301 arranged in rows and columns. The number of pixels 301 corresponding to the pixel block 300 is not limited to this. Although the illustration shows a case where m is equal to n, m may be different from n.

[0027] The pixel block 300 has a plurality of pixels 301 connected to a common control line (for example, a transfer control line 411 and a discharge control line 412 described later) in the row direction. For example, each pixel 301 in the pixel block 300 is connected to the common control line so that the pixels 301 are set to the same exposure time. Specifically, for example, every n pixels 301 arranged in the row direction are connected by the common control line.

[0028] On the other hand, between different pixel blocks 300, one pixel block 300 may be set to an exposure time different from that of the other pixel block 300. For example, when one pixel block 300 and the other pixel block 300 are arranged side by side in the row direction, the multiple pixels 301 included in one pixel block 300 and the multiple pixels 301 included in the other pixel block 300 are connected by different control lines. The multiple pixels 301 in the mth row of one pixel block 300 are commonly connected by a control line different from the common control line to which the multiple pixels 301 in the mth row of the other pixel block 300 are connected. Furthermore, when one pixel block 300 and the other pixel block 300 are arranged side by side in the column direction, the multiple pixels 301 included in one pixel block 300 and the multiple pixels 301 included in the other pixel block 300 are connected by different control lines. The pixels 301 in the mth row of one pixel block 300 are commonly connected to a control line that is different from the common control line to which the pixels 301 in the mth row of the other pixel block 300 are connected.

[0029] Furthermore, for example, when one pixel block 300 and the other pixel block 300 are arranged side by side in the row direction, the plurality of pixels 301 included in one pixel block 300 and the plurality of pixels 301 included in the other pixel block 300 are connected by different signal lines 302. The plurality of pixels 301 in the nth column of one pixel block 300 are connected in common by a signal line 302 that is different from the common signal line 302 to which the plurality of pixels 301 in the nth column of the other pixel block 300 are connected. Furthermore, when one pixel block 300 and the other pixel block 300 are arranged side by side in the column direction, the plurality of pixels 301 included in one pixel block 300 and the plurality of pixels 301 included in the other pixel block 300 are connected in common by different signal lines 302. The plurality of pixels 301 in the nth column of one pixel block 300 are connected in common by a signal line 302 that is different from the common signal line 302 to which the plurality of pixels 301 in the nth column of the other pixel block 300 are connected.

[0030] The pixel blocks 300 are arranged corresponding to the control blocks 500 described later. That is, one pixel block 300 is arranged for one control block 500.

[0031] Furthermore, multiple pixel blocks 300 may be arranged for one control block 500. Even when multiple pixel blocks 300 are arranged for one control block 500, different exposure times may be set for each pixel block 300. When two pixel blocks 300 arranged in the column direction are arranged for one control block, the control block 500 controls 2m×n pixels 301. Specifically, for example, the control block 500 controls 32×16 pixels 301. The number of pixels 301 corresponding to the control block 500 is not limited to this.

[0032] [Fig. 4 Circuit Configuration of Pixel 301] Fig. 4 is a circuit diagram showing an example of the circuit configuration of the pixel 301 according to Example 1. That is, Fig. 4 shows an equivalent circuit diagram of the two-tap charge distribution element 121 shown in Fig. 1(B). The pixel 301 includes a photoelectric conversion unit 400 and a readout unit 410.

[0033] The readout unit 410 has a transfer unit 401, a discharge unit 402, an FD (floating diffusion) 403, a reset unit 404, and a pixel output unit 405, and reads out pixel signals based on the charges converted by the photoelectric conversion unit 400 to the signal line 302. The pixel output unit 405 has an amplifier unit 451 and a selection unit 452. The transfer unit 401, discharge unit 402, FD 403, reset unit 404, amplifier unit 451, and selection unit 452 are collectively referred to as the readout unit 410. The readout unit 410 will be described as an N-channel FET, but the type of transistor is not limited to this.

[0034] The photoelectric conversion unit 400 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 400 accumulates the electric charges generated by the photoelectric conversion. The photoelectric conversion unit 400 is configured by, for example, a pinned photodiode PPD shown in FIG. 1B.

[0035] The transfer units 401A and 401B (transfer unit 401 when not distinguished) transfer the charges of the photoelectric conversion unit 400 to the FDs 403A and 403B (FD 403 when not distinguished). The transfer unit 401 controls the electrical connection between the photoelectric conversion unit 400 and the FD 403. The transfer units 401A and 401B are configured, for example, by the transistors TG1 and TG2 shown in FIG. 1B.

[0036] The transfer unit 401 may also be an element that has at least a gate terminal and constitutes part of a transistor in which a part of the photoelectric conversion unit 400 serves as a source terminal and a part of the FD 403 serves as a drain terminal. The gate terminals of the transfer units 401A and 401B are connected to transfer control lines 411A and 411B (referred to as transfer control line 411 when no distinction is made between them) for inputting transfer control signals G1 and G2.

[0037] The discharge unit 402 discharges the charge accumulated in the photoelectric conversion unit 400 to a power supply wiring to which a power supply voltage VDD is supplied. The discharge unit 402 controls the connection between the photoelectric conversion unit 400 and the power supply wiring. The discharge unit 402 is configured by, for example, the transistor TGD shown in FIG. 1B.

[0038] Furthermore, the discharge unit 402 may be an element that has at least a gate terminal and constitutes part of a transistor, with a part of the photoelectric conversion unit 400 as the source terminal and a part of the diffusion region connected to the power supply wiring as the drain terminal. The gate terminal of the discharge unit 402 is connected to a discharge control line 412 for inputting a discharge control signal D. Note that although the discharge unit 402 has been described as discharging the charge of the photoelectric conversion unit 400 to the power supply wiring to which the power supply voltage VDD is supplied, it may also be discharged to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0039] The FD 403 receives charges transferred from the photoelectric conversion unit 400 by the transfer unit 401. The FD 403 accumulates the charges transferred from the photoelectric conversion unit 400.

[0040] The reset units 404A and 404B (referred to as the reset unit 404 when no distinction is made between them) discharge the charge accumulated in the FD 403 to the power supply wiring to which the power supply voltage VDD is supplied. The reset unit 404 resets the potential of the FD 403 to the power supply voltage VDD, which is the reference potential. The reset unit 404 controls the electrical connection between the FD 403 and the power supply wiring. The reset unit 404 is configured, for example, by a transistor.

[0041] The reset unit 404 may be an element that has at least a gate terminal and constitutes a part of a transistor whose source terminal is a part of the FD 403 and whose drain terminal is a part of the diffusion region connected to the power supply wiring. The gate terminal of the reset unit 404 is connected to reset control lines 413A and 413B (referred to as reset control line 413 when no distinction is made between them) for inputting a reset control signal R.

[0042] The pixel output units 405A and 405B (or the pixel output unit 405 when they are not distinguished) output pixel signals based on the potential of the FD 403 to the signal line 302. The pixel output unit 405 has amplifiers 451A and 451B (or the amplifier 451 when they are not distinguished) and selectors 452A and 452B (or the selector 452 when they are not distinguished).

[0043] The amplifier 451 is configured with a transistor. The amplifier 451 has a gate terminal connected to the FD 403, a drain terminal connected to a power supply line to which the power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selector 452.

[0044] The selection unit 452 controls the electrical connection between the pixel 301 and the signal line 302. When the selection unit 452 electrically connects the pixel 301 and the signal line 302, a pixel signal is output from the pixel 301 to the signal line 302. The selection unit 452 is configured by a transistor.

[0045] The selection unit 452 may also be an element that has at least a gate terminal and constitutes part of a transistor, with part of the amplifier unit 451 as its source terminal and part of the diffusion region connected to the signal line 302 as its drain terminal. The gate terminal of the selection unit 452 is connected to a selection control line 414 that spans multiple pixel blocks 300 and is used to input selection control signals SEL1 and SEL2. The source terminal of the selection unit 452 is connected to the load current source 406.

[0046] The load current sources 406A and 406B (when not distinguished, referred to as the load current source 406) are connected to the signal line 302 and supply current for reading out pixel signals from the pixels 301. This makes it possible to stabilize the operation of the amplifier unit 451. The load current source 406 is also connected to the signal line 302. The load current source 406 may be provided on the first semiconductor substrate 210 or on the second semiconductor substrate 220.

[0047] The FD 403 and the pixel output unit 405 may be shared with other pixels 301. For example, the FD 403 and the pixel output unit 405 may be shared by a plurality of pixels 301 arranged side by side in the row or column direction. The pixel 301 may also be configured with a plurality of photoelectric conversion units 400 and transfer units 401.

[0048] 5 is an explanatory diagram showing an example of a specific configuration of the control circuit section 202. The control circuit section 202 has a plurality of control blocks 500. The plurality of control blocks 500 are arranged side by side in the row and column directions in the control circuit section 202. Specifically, the control circuit section 202 has M×N control blocks 500.

[0049] When one pixel block 300 is arranged for one control block 500, the control circuit unit 202 has the control block 500 directly below the pixel block 300. One pixel block 300 and one control block 500 have substantially the same shape and size. Furthermore, when multiple pixel blocks 300 arranged in a column direction are arranged for one control block 500, the control circuit unit 202 has one control block 500 directly below the multiple pixel blocks 300 arranged in a column direction.

[0050] The control block 500 is provided corresponding to the pixel block 300. As an example of the correspondence between the control block and the pixel block, for example, the control block 500 is located directly below the pixel block 300 in the direction in which the first semiconductor substrate 210 and the second semiconductor substrate 220 are stacked (stacking direction).

[0051] The control block 500 is also electrically connected to the pixel block 300 via the signal line 302, the transfer control line 411, and the discharge control line 412. Specifically, the control block 500 located directly below the pixel block 300 in the stacking direction is electrically connected to the pixel block 300 (hereinafter referred to as the corresponding pixel block 300) located directly above it in the stacking direction via local control lines such as the transfer control line 411 and the discharge control line 412. The control block 500 also receives pixel signals output from the pixels 301 of the corresponding pixel block 300 via the signal line 302.

[0052] The control block 500 controls the driving of the corresponding pixel block 300. For example, the control block 500 controls the exposure time of the pixels 301 included in the corresponding pixel block 300. The control block 500 also has a signal processing unit 502 that processes input signals, and processes pixel signals output from the pixels 301 included in the corresponding pixel block 300. For example, the control block 500 converts analog pixel signals output from the pixels 301 included in the corresponding pixel block 300 into digital signals.

[0053] The control block 500 has a pixel control unit 501 and a signal processing unit 502. The pixel control unit 501 has an autonomous exposure processing unit 511, an exposure control unit 512, and a pixel driving unit 513, and controls the pixels 301 of the pixel unit 201. The signal processing unit 502 has a signal input unit 521, a signal conversion unit 522, and a signal output unit 523, and converts analog pixel signals from the pixel unit 201 into digital signals and transfers them to the pixel control unit 501 and the data processing unit 203.

[0054] The autonomous exposure processing unit 511 is a circuit that generates a control signal related to the exposure time of the pixel 301 included in the corresponding pixel block 300 based on the pixel signal converted into a digital signal by the signal processing unit 502 .

[0055] The exposure control unit 512 is a circuit that controls the exposure of the pixels 301 included in the corresponding pixel block 300 based on a control signal related to the exposure time calculated by the autonomous exposure processing unit 511. Specifically, the exposure control unit 512 generates an output timing signal for controlling the timing of the exposure time of the pixels 301 included in the corresponding pixel block 300 (the charge accumulation time of the photoelectric conversion unit 400).

[0056] For example, the exposure control unit 512 adjusts the start timing or end timing of exposure of the pixels 301 included in the corresponding pixel block 300, thereby controlling the exposure time for each pixel block 300. The exposure control unit 512 is provided in the control block 500, extending in the row direction.

[0057] The pixel driving unit 513 generates pixel driving signals (transfer control signals G1, G2 and discharge control signal D) based on the output timing signal generated by the exposure control unit 512, and outputs the pixel driving signals to the pixels 301 included in the corresponding pixel block 300. The pixel driving unit 513 is a driving circuit that drives the pixels 301 included in the corresponding pixel block 300 with the pixel driving signals. The pixel driving unit 513 drives the pixels 301 in a pixel row selected from the pixels 301 included in the corresponding pixel block 300.

[0058] The pixel driving units 513 extend in the column direction, and are thus arranged at positions corresponding to the m pixels 301 arranged in the column direction. The autonomous exposure processing units 511, exposure control units 512, and pixel driving units 513 are arranged in an L shape in the control block 500, with the pixel driving units 513 extending in the column direction and the autonomous exposure processing units 511 and exposure control units 512 extending in the row direction.

[0059] The signal input unit 521 receives pixel signals output from pixels 301 included in the corresponding pixel block 300. The signal input unit 521 outputs the received pixel signals to the signal conversion unit 522. The signal input unit 521 may be provided for each of n pixels 301 arranged in the row direction in the corresponding pixel block 300. The signal input unit 521 may include a processing circuit that performs signal processing such as noise removal on the pixel signals output from the first semiconductor substrate 210.

[0060] Furthermore, the signal input unit 521 may have a voltage adjustment circuit that adjusts the voltage of the signal line 302 connected to the pixel 301 included in the corresponding pixel block 300 so that it does not fall below a predetermined value. When the load current source 406 is arranged on the second semiconductor substrate 220, it may be arranged in the signal input unit 521 included in the corresponding control block 500.

[0061] The signal conversion unit 522 converts the pixel signals output from the signal input unit 521 into digital signals. The signal conversion unit 522 sequentially converts into digital signals the pixel signals output from m pixels 301 arranged in the column direction in the corresponding pixel block 300. The signal conversion unit 522 converts into parallel digital signals the pixel signals output from the pixels 301 arranged in n columns in the row direction in the corresponding pixel block 300.

[0062] The signal output unit 523 stores the pixel signals converted into digital signals by the signal conversion unit 522. The signal output unit 523 may have a latch circuit for storing the digital signals. The signal output unit 523 is arranged between the signal conversion unit 522 and the autonomous exposure processing unit 511 in the column direction. The signal output unit 523 outputs the pixel signals converted into digital signals to the outside of the control circuit unit 202. The signal output unit 523 is provided in the control block 500, extending in the row direction. The signal output unit 523 is arranged between the signal conversion unit 522 and the autonomous exposure processing unit 511 in the column direction.

[0063] [Figure 6 Internal Configuration of Control Block 500] Figure 6 is an explanatory diagram showing an example of the internal configuration of the control block 500. The signal conversion unit 522 includes n comparators 601 and n storage units 602. The exposure control unit 512 includes a pixel block control unit 603 and a level shift unit 604. A combination of one comparator 601 and a storage unit 602 connected to that comparator 601 forms one ADC (Analog-to-Digital Converter) 500.

[0064] The comparators 601 are provided extending in the column direction in the control block 500. The n comparators 601 are arranged side by side in the row direction. A comparator 601 is arranged for every m pixels 301 arranged in the column direction in the corresponding pixel block 300. The comparators 601 sequentially read out pixel signals from the m pixels 301 arranged in the column direction in the corresponding pixel block 300 and convert them into digital signals.

[0065] The storage unit 602 stores the pixel signals converted into digital signals using the comparator 601. The storage unit 602 is provided on the negative side of the comparator 601 in the Y-axis direction in the signal conversion unit 522. For example, the storage unit 602 has a latch circuit. The storage unit 602 may have a memory configured using an SRAM or the like.

[0066] The pixel block control unit 603 controls the operation of the transfer unit 401 and discharge unit 402 of the pixel 301 included in the corresponding pixel block 300. Specifically, the pixel block control unit 603 outputs, as pixel drive signals, transfer control signals G1 and G2 for controlling the transfer unit 401 of the pixel 301 included in the corresponding pixel block 300, and a discharge control signal D for controlling the discharge unit 402 of the pixel 301 included in the corresponding pixel block 300. The pixel block control unit 603 is provided extending in the row direction in the control block 500. The pixel block control unit 603 is arranged between the level shift unit 604 and the autonomous exposure processing unit 511 in the column direction.

[0067] The level shift unit 604 adjusts the voltage level of the pixel drive signal output from the pixel block control unit 603. Specifically, the level shift unit 604 boosts the voltage level of the transfer control signals G1 and G2 output from the pixel block control unit 603. The level shift unit 604 also boosts the voltage level of the discharge control signal D output from the pixel block control unit 603.

[0068] The transfer unit 401 receives the transfer control signals G1 and G2 boosted by the pixel block control unit 603 via a transfer control line 411. The discharge unit 402 receives the discharge control signal D boosted by the pixel block control unit 603 via a discharge control line 412.

[0069] In this way, the pixel block control unit 603 boosts the transfer control signals G1, G2 and the discharge control signal D to voltage levels used in the transfer unit 401 and the discharge unit 402 of the readout unit 410 of the pixel 301. The level shift unit 604 is provided in the control block 500, extending in the row direction.

[0070] The level shift unit 604 is provided closer to the outer periphery of the control block 500 than the pixel block control unit 603. The end of the level shift unit 604 on the positive side in the X-axis direction and the end on the negative side in the Y-axis direction are located at the outermost sides of the control block 500. The end of the level shift unit 604 on the negative side in the X-axis direction is in contact with the pixel driving unit 513.

[0071] The level shift unit 604 and pixel drive unit 513 handle the level-shifted signal. On the other hand, the autonomous exposure processing unit 511, pixel block control unit 603, level shift unit 604, and pixel drive unit 513 handle the pixel signal output from the first semiconductor substrate 210.

[0072] Here, each component of the control block 500 is formed in a well region provided in the second semiconductor substrate 220. The well regions are provided separately according to the voltage level of the signals to be handled. The well regions are separated depending on whether the power supply used is a digital power supply or an analog power supply. Furthermore, even if the signal conversion unit 522 uses the same analog power supply, it may be separated from an area that uses another analog power supply from the perspective of noise. Separating the well regions requires well isolation regions spaced apart according to the manufacturing process rules.

[0073] In the control block 500, well regions for forming the level shift unit 604 and the pixel driving unit 513 are separated from other well regions. For example, the level shift unit 604 and the pixel driving unit 513 can be provided in an L-shape, thereby sharing the well regions of the level shift unit 604 and the pixel driving unit 513. Sharing the well region makes it possible to omit a well isolation region, thereby improving layout efficiency.

[0074] The L-shaped pixel control unit 501 forms part of the outer periphery of the control block 500. This allows the well region to be shared with other control blocks 500 adjacent in the row and column directions.

[0075] 7 is a timing chart showing an example of exposure timing control of the pixel 301 according to the first embodiment. ES is a light projection signal indicating light emitted from the light source of the electronic device 100. RS is a light reception signal indicating light reflected from the subject 110. T0 is the pulse width of the light projection signal ES and the light reception signal RS. Td is the time of flight of light.

[0076] First, the imaging (exposure and readout) of frame F1 will be described. Light is emitted from light source 101 of electronic device 100 as light projection signal ES onto subject 110 in synchronization with the falling edge of discharge control signal D and the rising edge of transfer control signal G2, and pixels 301 of image sensor 102 receive the reflected light from subject 110 as light reception signal RS. The number of pulses of light projection signal ES and light reception signal RS is assumed to be 1000.

[0077] The transfer control signal G2 is turned ON in synchronization with the rising edge of the light projection signal ES, and the transfer control signal G1 is turned ON in synchronization with the falling edge of the transfer control signal G2. The discharge control signal D is turned OFF in synchronization with the rising edge of the light projection signal ES, and is turned ON in synchronization with the falling edge of the transfer control signal G1.

[0078] Therefore, the charge photoelectrically converted by the photoelectric conversion unit 400 is accumulated in FD 403B during the period when the transfer control signal G2 is ON and the discharge control signal D is OFF, and is accumulated in FD 403A during the period when the transfer control signal G1 is ON and the discharge control signal D is OFF.

[0079] When the selection control signals SEL1 and SEL2 are turned ON, the exposure ends and the charge accumulated in the FD 403 is read out.

[0080] After this, a timing value is calculated, and the exposure timing of the next frame F2 is adjusted. This timing value is the signal distribution ratio of the transfer control signals G1 and G2 calculated by the autonomous exposure processor 511, and is the 3-bit control signal CTL shown in FIG. 9, which will be described later. The exposure timing of the next frame (the time from the falling edge of the discharge control signal D and the rising edge of the light-projection signal ES to the rising edge of the transfer control signal G2) is adjusted by the control signal CTL.

[0081] 8 is an explanatory diagram illustrating an example of a block configuration of the image sensor 102 according to the first embodiment. The pixel drive unit 513 outputs transfer control signals G1 and G2 to the pixel 301. The pixel 301 controls the transfer of charges photoelectrically converted by the photoelectric conversion unit 400 to the FD 403 using the transfer control signals G1 and G2. The charges accumulated in the FDs 403A and 403B are converted into voltages, which are output as analog pixel signals P1 and P2 to the signal processing unit 502. The signal processing unit 502 performs AD conversion on the analog pixel signals P1 and P2 to digital pixel signals Q1 and Q2, and outputs the digital pixel signals Q1 and Q2 to the autonomous exposure processing unit 511 and the peripheral circuit unit 221.

[0082] The autonomous exposure processor 511 calculates a control signal related to the exposure time for capturing the next frame based on the digital pixel signals Q1 and Q2. The exposure controller 512 adjusts the output timing of the transfer control signals G1 and G2 and the discharge control signal D based on the control signal related to the exposure time calculated by the autonomous exposure processor 511, and outputs the output timing signal to the pixel driver 513. The pixel driver 513 controls the driving of the pixels 301 using the transfer control signals G1 and G2 and the discharge control signal D whose output timing has been adjusted by the exposure controller 512.

[0083] [Fig. 9: Example of a circuit configuration of the image sensor 102] Fig. 9 is an explanatory diagram illustrating an example of a circuit configuration of the image sensor 102 according to the first embodiment. For convenience of explanation, the signal input unit 521 of the signal processing unit 502 is omitted from Fig. 9. The signal conversion unit 522 has an ADC 522A that performs AD conversion on an analog pixel signal P1 to a digital pixel signal Q1, and an ADC 522B that performs AD conversion on an analog pixel signal P2 to a digital pixel signal Q2. When there is no need to distinguish between the ADCs 522A and 522B, they are simply referred to as ADC 522. The ADC 522 may be a SAR (Successive Approximation Register) type or a SS (Single Slope) type.

[0084] The ADC 522 outputs a 12-bit digital pixel signal Q to the signal output unit 523. The signal output unit 523 outputs the digital pixel signal Q to the calculation unit 104 via the peripheral circuit unit 221. The bit width of the digital pixel signal Q is 12 bits, which is an example, and a bit width other than 12 bits may be used. The ADC 522A outputs a digital pixel signal Q1_MSB, which is the most significant three bits of the 12-bit digital pixel signal Q1, to the autonomous exposure processing unit 511. Similarly, the ADC 522B outputs a digital pixel signal Q2_MSB, which is the most significant three bits of the 12-bit digital pixel signal Q2, to the autonomous exposure processing unit 511. When there is no need to distinguish between the digital pixel signals Q1_MSB and Q2_MSB, they will be referred to as a digital pixel signal Q_MSB. The bit width of the digital pixel signal Q_MSB, which is 3 bits, is an example, and it may be any width as long as it is smaller than the bit width of the digital pixel signal Q.

[0085] The autonomous exposure processing unit 511 refers to the conversion table 900 and outputs a 3-bit control signal CTL based on the digital pixel signal Q_MSB to the exposure control unit 512 and the calculation unit 104. In this example, the autonomous exposure processing unit 511 is a 6-bit input, 3-bit output encoder.

[0086] The control unit 103 sets a pulse width T0 and outputs it to the light source 101, the exposure control unit 512, and the calculation unit 104. The calculation unit 104 calculates an adjustment time Tc that indicates the phase shift between the transfer control signals G2 and G1 based on the control signal CTL. The calculation of the adjustment time Tc is also performed inside the exposure control unit 512.

[0087] 10 is an explanatory diagram showing an example of the conversion table 900 according to Example 1. The autonomous exposure processing unit 511 refers to the conversion table 900, and identifies the ratio Q2:Q1 of the digital pixel signals Q1 and Q2 as comparison data based on the combination of the digital pixel signals Q1_MSB and Q2_MSB, and generates a 3-bit control signal CTL corresponding to the ratio Q2:Q1 as a control signal related to the exposure time.

[0088] [Figure 11: Correspondence between ratio Q2:Q1 and time of flight Td] Figure 11 is an explanatory diagram showing the correspondence between ratio Q2:Q1 and time of flight Td. As shown in Figure 10, the ratio Q2:Q1 is nine types of comparison data ranging from 7:<1 to <1:7. The ratio Q2:Q1 is determined by the timing indicating the falling edge of transfer control signal G2 and the rising edge of transfer control signal G1.

[0089] (A) shows the flight time Td at the control timing CTa when the ratio Q2:Q1 is 7:1. (B) shows the flight time Td at the control timing CTb when the ratio Q2:Q1 is 4:4. (C) shows the flight time Td at the control timing CTc when the ratio Q2:Q1 is 1:7. In the ratio Q2:Q1, the larger Q2 is, the shorter the flight time Td is, and the smaller Q2 is, the longer the flight time Td is.

[0090] When the control signal CTL of (A) is input, the exposure control unit 512 adjusts the timing of the transfer control signals G1 and G2 so that the control timing CTa becomes the control timing CTb. Similarly, when the control signal CTL of (C) is input, the exposure control unit 512 adjusts the timing of the transfer control signals G1 and G2 so that the control timing CTc becomes the control timing CTb.

[0091] [Fig. 12: Modified Example of Circuit Configuration of Image Sensor 102] Fig. 12 is an explanatory diagram showing a modified example of the circuit configuration of the image sensor 102 shown in Fig. 9. Fig. 12 shows an example in which a signal conversion unit 522D is added. A reference signal ref having a ramp waveform is input to signal conversion units 522A and 522B constituting the signal processing unit 502. The signal conversion unit 522A outputs a digital pixel signal Q1 corresponding to the difference between an analog pixel signal P1 and the reference signal ref, and the signal conversion unit 522B outputs a digital pixel signal Q2 corresponding to the difference between an analog pixel signal P2 and the reference signal ref.

[0092] The signal converter 522D compares the analog pixel signals P1 and P2 and outputs a differential signal def12 to the autonomous exposure processor 511. The autonomous exposure processor 511 includes a conversion table 900. However, in the example of FIG. 12, the digital pixel signals Q1_MSB and Q2_MSB are not input to the autonomous exposure processor 511, so the columns for the digital pixel signals Q1_MSB and Q2_MSB are unnecessary. The ratio Q2:Q1 corresponds to the differential signal def12 obtained by comparing the analog pixel signals P1 and P2. Therefore, the autonomous exposure processor 511 outputs a control signal CTL corresponding to the differential signal def12 to the exposure controller 512. The exposure controller 512 uses the control signal CTL to calculate the time of flight Td. In the configuration of FIG. 12, the signal converter 522D directly compares the analog pixel signals P1 and P2, thereby enabling faster exposure control.

[0093] [Fig. 13: Detailed Circuit Configuration Example 1 of Image Sensor 102] Fig. 13 is an explanatory diagram illustrating a detailed circuit configuration example 1 of the image sensor 102 according to the first embodiment. Fig. 13 illustrates a circuit configuration example in which the signal conversion unit 522 is of SS type. The signal conversion unit 522A has a comparator 1301A and a latch circuit 1302A. The signal conversion unit 522B has a comparator 1301B and a latch circuit 1302B. When the comparators 1301A and 1301B are not distinguished from each other, they are referred to as comparators 1301. When the latch circuits 1302A and 1302B are not distinguished from each other, they are referred to as latch circuits 1302.

[0094] A reference signal ref is input to comparators 1301A and 1301B. The comparator 1301A outputs a digital value (High (1) or Low (0)) indicating the result of comparison between an analog pixel signal P1 and the reference signal ref. The comparator 1301B outputs a digital value indicating the result of comparison between an analog pixel signal P2 and the reference signal ref.

[0095] The latch circuits 1302 are circuits that hold digital values ​​of 0 or 1, and exist for each bit. Each latch circuit 1302 holds the analog pixel signal P as a digital value. A count value is input to the latch circuit 1302. The count value increases by 1 over time. Because the signal conversion unit 522 is of the SS type, the values ​​of all bits are determined as the digital pixel signal Q at the time (count value) when the input analog pixel signal P and the reference signal ref match.

[0096] [Fig. 14: Detailed Circuit Configuration Example 2 of Image Sensor 102] Fig. 14 is an explanatory diagram illustrating a detailed circuit configuration example 2 of the image sensor 102 according to the first embodiment. Fig. 14 illustrates a circuit configuration example in which the signal conversion unit 522 is an SAR type. The signal conversion unit 522A includes an S&H (Sample & Hold) circuit 1401A, a comparator 1301A, an n-bit DAC (Digital-Analog Converter) 1402A, an n-bit register 1403A, and a control circuit 1404A. The signal conversion unit 522B includes an S&H circuit 1401B, a comparator 1301B, an n-bit DAC 1402B, an n-bit register 1403B, and a control circuit 1404B.

[0097] When there is no need to distinguish between the S&H circuits 1401A and 1401B, they are referred to as S&H circuits 1401. When there is no need to distinguish between the n-bit DACs 1402A and 1402B, they are referred to as n-bit DACs 1402. When there is no need to distinguish between the n-bit registers 1403A and 1403B, they are referred to as n-bit registers 1403. When there is no need to distinguish between the control circuits 1404A and 1404B, they are referred to as control circuits 1404.

[0098] The S&H circuit 1401 samples and holds the analog pixel signal P and outputs it to the comparators 1301A and 1301B as voltage signals VinA and VinB. When the voltage signals VinA and VinB are not distinguished, they are referred to as a voltage signal Vin. The n-bit DAC 1402 converts the n-bit digital pixel signals Q1 and Q2 into analog signals VdacA and VdacB (voltage). When the analog signals VdacA and VdacB are not distinguished, they are referred to as an analog signal Vdac.

[0099] The comparator 1301 compares the voltage signal Vin of the analog pixel signal P sampled and held by the S&H circuit 1401 with the analog signal Vdac from the n-bit DAC 1402. The comparator 1301 outputs High (1) if Vin≧Vdac, and outputs Low (0) if Vin<Vdac.

[0100] Since the SAR ADC is a method of determining data from the most significant bit, the analog signal Vdac from the n-bit DAC 1402 is set to a voltage value that is half the upper limit value of the input to the comparator 1301 .

[0101] The n-bit register 1403 is a latch circuit that stores the output value (High (1) or Low (0)) of the comparator 1301 .

[0102] The control circuit 1404 generates a DAC voltage for determining the next lower bit based on the value stored in the n-bit register 1403. For example, when DAC (MSB) = 1 / 2 [V] and P > Vdac, the control circuit 1404 causes DAC (MSB-1) to generate a voltage of 1 / 2 + 1 / 4. By repeating this cycle, the digital pixel signal Q is determined starting from the higher bits, and the bit resolution increases according to the number of cycles.

[0103] The SAR type ADC 522 shown in Fig. 14 can operate at a higher speed than the SS type ADC 522 shown in Fig. 13. The SS type ADC 522 shown in Fig. 13 can achieve a smaller circuit scale than the SAR type ADC 522 shown in Fig. 14.

[0104] [Fig. 15 Detailed Circuit Configuration Example 3 of Image Sensor 102] Fig. 15 is an explanatory diagram illustrating a detailed circuit configuration example 3 of the image sensor 102 according to the first embodiment. Fig. 15 illustrates a circuit configuration example in which the signal conversion unit 522 is of the SS type and the SAR type. In Fig. 15, an SAR type ADC 1501 functions as the autonomous exposure processing unit 511. An SS type ADC 1502 has the same configuration as that illustrated in Fig. 13.

[0105] The SAR ADC 1501 includes an S&H selection circuit 1511 , a comparator 1512 , a 3-bit DAC 1513 , an n-bit register 1514 , and a control circuit 1515 .

[0106] The S&H selection circuit 1511 samples and holds the analog pixel signal P. Based on a selection signal SEL from an n-bit register 1514, the S&H selection circuit 1511 selects the output destination (comparator 1512 or 3-bit DAC) of each of the sampled and held analog pixel signals P1 and P2.

[0107] 16 is an explanatory diagram showing the selection process of the S&H selection circuit 1511 according to the first embodiment. When the value of the selection signal SEL is "0", the S&H selection circuit 1511 sets the output destination of the sampled and held analog pixel signal P1 to the comparator 1512, and sets the output destination of the sampled and held analog pixel signal P2 to the 3-bit DAC 1513. When the value of the selection signal SEL is "1", the S&H selection circuit 1511 sets the output destination of the sampled and held analog pixel signal P1 to the 3-bit DAC 1513, and sets the output destination of the sampled and held analog pixel signal P2 to the comparator 1512.

[0108] 15 , the comparator 1512 receives the analog pixel signal P from the S&H selection circuit 1511 as a voltage signal Vin, and receives the analog signal Vdac from the 3-bit DAC 1513. The comparator 1512 compares the voltage signal Vin with the analog signal Vdac. The comparator 1512 outputs High (1) to the n-bit register 1514 if Vin≧Vdac, and outputs Low (0) if Vin<Vdac.

[0109] The n-bit register 1514 holds the comparison result from the comparator 1512. The n-bit register 1514 outputs a 1-bit selection signal SEL to the S&H selection circuit 1511 and the exposure control unit 512.

[0110] The control circuit 1515 controls the voltage value of the analog signal Vdac based on the comparison result (High (1) or Low (0)) from the comparator 1512 held in the n-bit register 1514. Specifically, for example, the control circuit 1515 does not adjust the voltage to 1 / 2, 1 / 4, etc. based on the upper input limit value of the comparator 1512, but rather directly compares the analog pixel signals P1 and P2 by using the reference signal REF (analog pixel signal P1 or P2) from the S&H selection circuit 1511 as a reference. The control circuit 1515 outputs a 3-bit digital signal REG, which is the comparison result of the analog pixel signals P1 and P2, to the 3-bit DAC 1513 and the exposure control unit 512.

[0111] 17 is a graph showing an example of generation of the digital signal REG according to Example 1. Graph 1700 illustrates an example in which the analog pixel signal P1 is input to the comparator 1512 as the voltage signal Vin (selection signal SEL=0). When the selection signal SEL=1, P1 and P2 in graph 1700 are swapped.

[0112] For REG[2], the most significant bit of the digital signal REG, the analog signal Vdac from the 3-bit DAC 1513 is higher than the voltage signal Vin, so the value of REG[2] is "0". For REG[1] of the digital signal REG, the analog signal Vdac from the 3-bit DAC 1513 is lower than the voltage signal Vin, so the value of REG[1] is "1". For REG[0], the least significant bit of the digital signal REG, the analog signal Vdac from the 3-bit DAC 1513 is higher than the voltage signal Vin, so the value of REG[0] is "0". Therefore, the digital signal REG has a value of "010".

[0113] Returning to FIG. 15, the exposure control unit 512 controls exposure based on a 3-bit digital signal from the control circuit 1515 and a 1-bit selection signal SEL from an n-bit register.

[0114] 18 is an explanatory diagram showing an example of a first conversion table 1800. The first conversion table 1800 is applied when the selection signal SEL is “0”, that is, when the analog pixel signal P1 is output to the comparator 1512.

[0115] 19 is an explanatory diagram showing an example of the second conversion table 1900. The second conversion table 1900 is applied when the selection signal SEL is “1”, that is, when the analog pixel signal P2 is output to the comparator 1512.

[0116] The exposure control unit 512 determines the ratio Q2:Q1 based on either the first conversion table 1800 or the second conversion table 1900 and the 3-bit digital signal REG from the control circuit 1515. The exposure control unit 512 generates a 3-bit control signal CTL corresponding to the ratio Q2:Q1 as a control signal related to the exposure time, and outputs it to the pixel driving unit 513. In the example of the first conversion table 1800 in FIG. 18 , the selection signal SEL=0 and the digital signal REG is “010”, so the ratio Q2:Q1 is “2:8”.

[0117] The pixel driving unit 513 controls driving of the pixels 301 using the transfer control signals G1 and G2 and the discharge control signal D whose output timing is adjusted by the exposure control unit 512. In the above example, the exposure control unit 512 adjusts the timing of the transfer control signals G1 and G2 so that the ratio Q2:Q1 changes from "2:8" to "8:8."

[0118] [Fig. 20 Alternative Configuration Example 1 of Exposure Control Unit 512] Fig. 20 is an explanatory diagram showing Alternative Configuration Example 1 of the exposure control unit 512. In Fig. 20, the exposure control unit 512 is configured with an analog circuit. An RC circuit 2000 is configured with a variable resistor 2001 and a capacitor 2002. When a control signal CTL from the autonomous exposure processing unit 511 is input to the variable resistor 2001, the output of a timing pulse 2010 input to the variable resistor 2001 is adjusted.

[0119] Specifically, for example, the smaller the resistance value R of variable resistor 2001, the earlier the timing pulse 2010 is output from variable resistor 2001, and the larger the value of variable resistor 2001, the later the timing pulse 2010 is output from variable resistor 2001. Note that the capacitance C of capacitor 2002 is fixed. That is, the delay time T of the output of this timing pulse 2010 is calculated as T=RC, which is the time it takes for the transient phenomenon before timing pulse 2010 goes high or low to end.

[0120] 21 is a truth table 2100 showing the correspondence between the resistance value R of the variable resistor 2001, the control signal CTL, and the ratio Q2:Q1. The resistance value R of the variable resistor 2001 varies depending on the combination of the bit strings of the control signal CTL. For example, when the control signal CTL is "001," the resistance value R of the variable resistor 2001 is set to 2.5 Ω.

[0121] [Fig. 22: Alternative Configuration Example 2 of Exposure Control Unit 512] Fig. 22 is an explanatory diagram showing Alternative Configuration Example 2 of the exposure control unit 512. In Fig. 22, the exposure control unit 512 is configured with digital circuits. The exposure control unit 512 has counters 2201A and 2201B, counter control circuits 2202A and 2202B, FFs 2203A and 2203B, and an AND circuit 2204.

[0122] Counters 2201A and 2201B calculate count values ​​and output the count values ​​to counter control circuits 2202A and 2202B.

[0123] The counter control circuits 2202A and 2202B receive the count values ​​from the counters 2201A and 2201B and the control signal CTL from the autonomous exposure processing unit 511. The counter control circuits 2202A and 2202B output latch signals latch to the FFs 2203A and 2203B at the timing when the received count values ​​match the control signal CTL.

[0124] The FFs 2203A and 2203B receive the clock signal Clk and the latch signal latch. The FF 2203A outputs an assert signal assert when the latch signal latch is received from the counter control circuit 2202A. The FF 2203B outputs a negate signal negate when the latch signal latch is received from the counter control circuit 2202B.

[0125] The AND circuit 2204 outputs an AND signal based on the assert signal assert and the negate signal negate to the pixel driving unit 513 as a control signal for adjusting the output timing of the transfer control signals G1, G2 and the discharge control signal D.

[0126] 23 is a timing chart of the exposure control unit 512. The AND circuit 2204 generates an AND signal that is ON during the period from the rising edge of the assert signal assert to the falling edge of the negate signal negate.

[0127] [Fig. 24 Calculation Example 1 of Flight Time Td] Fig. 24 is an explanatory diagram showing calculation example 1 of flight time Td. The flight time Td is calculated by the following formula (2).

[0128]

[0129] In Fig. 24, (A) is the same timing chart as (A) in Fig. 11, and (B) is the same timing chart as (B) in Fig. 11. In Fig. 24, (A) is the timing before adjustment, and (B) is the timing after adjustment. Tc is the adjustment time indicating the phase difference between the transfer control signals G2 and G1.

[0130] The ratio Q2:Q1 is changed from 7:1 in (A) to 4:4 in (B), so the time of flight Td increases. This increase is the adjustment time Tc, and the transfer control signals G2 and G1 are adjusted by the exposure control unit 512 so that they rise earlier by the adjustment time Tc.

[0131] [Figure 25: Calculation Example 2 of Time-of-Flight Td] Figure 25 is an explanatory diagram showing calculation example 2 of time-of-flight Td. In Figure 25, (A) is the same timing chart as (C) of Figure 11, and (B) is the same timing chart as (B) of Figure 11. In Figure 25, (A) is the timing before adjustment, and (B) is the timing after adjustment.

[0132] The ratio Q2:Q1 is changed from 1:7 in (A) to 4:4 in (B), so the time of flight Td is reduced. This reduction is the adjustment time Tc, and the transfer control signals G2 and G1 are adjusted by the exposure control unit 512 so that they rise with a delay of the adjustment time Tc.

[0133] [Modifications of the layout shown in FIGS. 26 to 28] Next, modifications of the layout shown in FIGS. 5 and 6 will be described.

[0134] (FIG. 26 : Layout Variation 1) FIG. 26 is a schematic partial side cross-sectional view showing layout variation 1. In FIG. 26 , the description focuses on an insulating wiring layer stacked between the first semiconductor substrate 210 and the second semiconductor substrate 220. A first wiring layer 2601 and a second wiring layer 2602 are provided between the first semiconductor substrate 210 and the second semiconductor substrate 220. The first wiring layer 2601 is provided between the first semiconductor substrate 210 and the second wiring layer 2602. The second wiring layer 2602 is provided between the first wiring layer 2601 and the second semiconductor substrate 220.

[0135] The first wiring layer 2601 is provided with a first connection portion 2610. The second wiring layer 2602 is provided with a second connection portion 2620.

[0136] The first connection portion 2610 has a first connection pad 2611, a second connection pad 2612, and a first timing circuit 2613. The second connection portion 2620 has a first connection pad 2621, a second connection pad 2622, and a second timing circuit 2623. The first timing circuit 2613 and the second timing circuit 2623 are configured, for example, by an RC circuit. The second timing circuit 2623 may be configured as a part of the exposure control portion 512.

[0137] First, the wiring connection between the pixel block 300 on the first semiconductor substrate 210 and the control block 500 on the second semiconductor substrate 220 will be described.

[0138] In the first wiring layer 2601, the first connection pads 2611 are connected to the first connection pads 2621. The first timing circuits 2613 are provided between each pixel 301 in the pixel block 300 and the first connection pads 2611, and serve as wiring that connects each pixel 301 in the pixel block 300 to the first connection pads 2611. An analog pixel signal from the pixel 301 is output to the first connection pads 2621 in the second wiring layer 2602 via wiring formed by the first timing circuit 2613 and the first connection pads 2611.

[0139] In the second wiring layer 2602, the first connection pad 2621 is connected to the first connection pad 2611. The second timing circuit 2623 is provided between the first connection pad 2621 and the signal processing unit 502 of the control block 500, and serves as wiring that connects the signal processing unit 502 of the control block 500 to the first connection pad 2621. The analog pixel signal from the pixel 301 is output to the signal processing unit 502 via wiring formed by the first connection pad 2621 and the second timing circuit 2623.

[0140] In the second wiring layer 2602, the second connection pads 2622 are connected to the second connection pads 2612. The second timing circuit 2623 is provided between the pixel driving unit 513 of the control block 500 and the first connection pads 2621, and serves as wiring that connects the pixel driving unit 513 of the control block 500 and the first connection pads 2621. The pixel driving signals (transfer control signals G1, G2 and discharge control signal D) from the pixel driving unit 513 are output to the second connection pads 2612 of the first wiring layer 2601 via wiring formed by the second timing circuit 2623 and the second connection pads 2622.

[0141] Furthermore, in the first wiring layer 2601, the second connection pads 2612 are connected to the second connection pads 2622. The first timing circuits 2613 are also provided between each pixel 301 in the pixel block 300 and the second connection pads 2612, and serve as wiring that connects each pixel 301 in the pixel block 300 to the second connection pads 2612. The pixel drive signals from the pixel drive unit 513 are output to the pixels 301 via wiring formed by the second connection pads 2612 and the first timing circuits 2613.

[0142] Next, a description will be given of the wiring connection between the control blocks 500 on the second semiconductor substrate 220. The wiring connection between the control blocks 500 is performed using the free space in the first wiring layer 2601 and the second wiring layer 2602. In Fig. 26, the wiring connection between the control blocks 500a and 500b will be described as an example.

[0143] Of the first connection parts 2610 and the second connection parts 2620, at least the second connection part 2620 is used for the wiring connection between the control blocks 500a and 500b. In the example of FIG. 26, the control blocks 500a and 500b are wired and connected using two first connection parts 2610 and three second connection parts 2620. By configuring a delay circuit based on the wiring path lengths of the control blocks 500a and 500b, timing control by signal delay using wiring resistance becomes possible. Furthermore, by providing multiple wiring paths with different wiring path lengths, a variable resistor made up of multiple different wiring resistances can be constructed in an empty space, making timing control easier.

[0144] 26 has described the wiring connection between the first semiconductor substrate 210 and the second semiconductor substrate 220, but the wiring connection between the second semiconductor substrate 220 and the third semiconductor substrate 230 may be configured in a similar manner. In particular, the wiring connection between the control blocks 500a and 500b may use the wiring layer between the second semiconductor substrate 220 and the third semiconductor substrate 230 without passing through the first wiring layer 2601 and the second wiring layer 2602.

[0145] (FIG. 27 Layout Modification 2) FIG. 27 is a schematic partial side cross-sectional view showing layout modification 2. In FIG. 27 , a control block 500 is disposed across the second semiconductor substrate 220 and the third semiconductor substrate 230. Specifically, for example, a signal processing unit 502 and a pixel driving unit 513 are provided on the second semiconductor substrate 220, and an autonomous exposure processing unit 511 and an exposure control unit 512 are provided on the third semiconductor substrate 230.

[0146] The autonomous exposure processing unit 511 and the exposure control unit 512 are configured by logic circuits and are driven by the same driving voltage.

[0147] Furthermore, the signal processing unit 502 and the pixel driving unit 513 are configured using different types of transistors, and the driving voltages in the signal processing unit 502 and the pixel driving unit 513 are higher than the driving voltages applied in the autonomous exposure processing unit 511 and the exposure control unit 512.

[0148] Therefore, by providing the autonomous exposure processing unit 511 and the exposure control unit 512 on the same semiconductor substrate, the third semiconductor substrate 230, and providing the signal processing unit 502 and the pixel driving unit 513 on the second semiconductor substrate 220, which is different from the semiconductor substrate on which the autonomous exposure processing unit 511 and the exposure control unit 512 are implemented, the integration degree of the autonomous exposure processing unit 511 and the exposure control unit 512 is improved.

[0149] The wiring connection between the first semiconductor substrate 210 and the second semiconductor substrate 220 may be configured as shown in Fig. 26. Similarly, the wiring connection between the second semiconductor substrate 220 and the third semiconductor substrate 230 may also be configured as shown in Fig. 26.

[0150] (FIG. 28: Layout Variation 3) FIG. 28 is a schematic partial cross-sectional side view showing layout variation 3. FIG. 28 shows a layout variation relating to the orientation of adjacent control blocks 500. FIG. 28 shows a layout of 3×3 control blocks 500 as an example.

[0151] Specifically, for example, between adjacent control blocks 500 in the X direction, the control blocks 500 are arranged so that the pixel driving units 513 are adjacent, or so that the signal processing units 502, autonomous exposure processing units 511, and exposure control units 512 are adjacent.

[0152] Furthermore, between adjacent control blocks 500 in the Y direction, the control blocks 500 are arranged so that the signal input section 521 and the pixel driving section 513 are adjacent to each other, or so that the exposure control section 512 and the pixel driving section 513 are adjacent to each other.

[0153] In this way, by arranging the same components adjacent to each other between adjacent control blocks 500, it is possible to make the components smaller than in a configuration in which the same components are arranged separately.

[0154] [Fig. 29: Modified Example of Exposure Timing Control] Fig. 29 is an explanatory diagram showing a modified example of exposure timing control according to Example 1. In Fig. 7, frame F1 is exposed at default timing, and the timing value (control signal CTR) for frame F1 is used to update the exposure timing for the subsequent frame F2. In contrast, in Fig. 29, calibration related to exposure control is performed at default timing for frame F1 before actual shooting, and the exposure timing is updated using the timing value (control signal CTR) from that calibration during the actual shooting of frame F1. For subsequent frames F2 and onward, the same processing as in Fig. 7 is performed.

[0155] The number of pulses of the light projection signal ES and the light reception signal RS in the calibration is adjusted to be smaller than the number of pulses of the light projection signal ES and the light reception signal RS in the actual photographing. In this example, the number of pulses of the light projection signal ES and the light reception signal RS in the actual photographing is 1000, whereas the number of pulses of the light projection signal ES and the light reception signal RS in the calibration is 10.

[0156] In this way, by performing calibration before the actual shooting of frame F1, it is possible to optimize the exposure for frame F1. Furthermore, by performing such calibration with fewer pulses of the light projection signal ES and the light reception signal RS than in the actual shooting, it is possible to speed up the calibration.

[0157] 30 to 40: Configuration of the image sensor 102 First, the configuration of the image sensor 102 on which the three-tap charge distribution element 122 having the discharge portion TGD shown in FIG. 1C is mounted will be described using FIGS. 30 to 40. The structure of the image sensor 102 may be either a back-illuminated type or a front-illuminated type. Note that, in Example 2, differences from Example 1 will be mainly described, and therefore a description of the configuration common to Example 1 will be omitted.

[0158] [Fig. 30 Circuit Configuration of Pixel 301] Fig. 30 is a circuit diagram showing an example of the circuit configuration of the pixel 301 according to Example 2. That is, Fig. 30 shows an equivalent circuit diagram of the three-tap charge distribution element 122 having the discharge portion TGD shown in Fig. 1(C).

[0159] 30, the pixel 301 has, in addition to the configuration shown in FIG. 4, a transfer unit 401C, a discharge unit 402C, an FD 403C, a reset unit 404C, a pixel output unit 405C, and a load current source 406C in the readout unit 410.

[0160] The transfer unit 401C (transfer unit 401 when the transfer units 401A, 401B, and 401C are not distinguished) transfers the charge of the photoelectric conversion unit 400 to the FD 403C (FD 403 when the FDs 403A, 403B, and 403C are not distinguished). The transfer unit 401C controls the electrical connection between the photoelectric conversion unit 400 and the FD 403C. The transfer unit 401C is configured, for example, by the transistor TG3 shown in FIG. 1C.

[0161] The transfer unit 401C may be an element that has at least a gate terminal and constitutes part of a transistor in which a part of the photoelectric conversion unit 400 serves as a source terminal and a part of the FD 403C serves as a drain terminal. The gate terminal of the transfer unit 401C is connected to a transfer control line 411C (transfer control line 411 when the transfer control lines 411A, 411B, and 411C are not distinguished) for inputting a transfer control signal G3.

[0162] The discharge unit 402C (referred to as the discharge unit 402 when the discharge units 402A, 402B, and 402C are not distinguished from one another) discharges the charges accumulated in the photoelectric conversion unit 400 to a power supply wiring to which a power supply voltage VDD is supplied. The discharge unit 402C controls the connection between the photoelectric conversion unit 400 and the power supply wiring. The discharge unit 402C is configured, for example, by the transistor TGD shown in FIG. 1C.

[0163] Furthermore, the discharge unit 402C may be an element that has at least a gate terminal and constitutes part of a transistor, with a part of the photoelectric conversion unit 400 as the source terminal and a part of the diffusion region connected to the power supply wiring as the drain terminal. The gate terminal of the discharge unit 402C is connected to a discharge control line 412 for inputting a discharge control signal D. Note that although the discharge unit 402 has been described as discharging the charge of the photoelectric conversion unit 400 to the power supply wiring to which the power supply voltage VDD is supplied, the discharge unit 402 may also be discharged to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0164] The FD 403C receives charges transferred from the photoelectric conversion unit 400 by the transfer unit 401C. The FD 403C accumulates the charges transferred from the photoelectric conversion unit 400.

[0165] The reset unit 404C (referred to as the reset unit 404 when the reset units 404A, 404B, and 404C are not distinguished) discharges the charge accumulated in the FD 403C to the power supply wiring to which the power supply voltage VDD is supplied. The reset unit 404C resets the potential of the FD 403C to the power supply voltage VDD, which is the reference potential. The reset unit 404C controls the electrical connection between the FD 403C and the power supply wiring. The reset unit 404C is configured, for example, by a transistor.

[0166] The reset unit 404C may be an element that has at least a gate terminal and constitutes a part of a transistor, with a part of the FD 403C as a source terminal and a part of the diffusion region connected to the power supply wiring as a drain terminal. The gate terminal of the reset unit 404C is connected to a reset control line 413C (referred to as the reset control line 413 when the reset control lines 413A, 413B, and 413C are not distinguished) for inputting a reset control signal R.

[0167] The pixel output unit 405C (pixel output unit 405 when the pixel output units 405A, 405B, and 405C are not distinguished) outputs a pixel signal based on the potential of the FD 403C to the signal line 302. The pixel output unit 405C has an amplifier 451C (amplifier 451 when the amplifiers 451A, 451B, and 451C are not distinguished) and a selector 452C (selector 452 when the selector 452A, 452B, and 452C are not distinguished).

[0168] The amplifier 451C is configured with a transistor. The amplifier 451C has a gate terminal connected to the FD 403C, a drain terminal connected to a power supply line that supplies the power supply voltage VDD, and a source terminal connected to the drain terminal of the selector 452C.

[0169] The selection unit 452C controls the electrical connection between the pixel 301 and the signal line 302. When the selection unit 452C electrically connects the pixel 301 and the signal line 302, a pixel signal is output from the pixel 301 to the signal line 302. The selection unit 452C is configured by a transistor.

[0170] The selection unit 452C may also be an element that has at least a gate terminal and constitutes part of a transistor, with part of the amplifier unit 451C as its source terminal and part of the diffusion region connected to the signal line 302 as its drain terminal. The gate terminal of the selection unit 452C is connected to a selection control line 414C that spans multiple pixel blocks 300 and is used to input a selection control signal SEL3 (or the selection control signal SEL when the selection control signals SEL1, SEL2, and SEL3 are not distinguished). The source terminal of the selection unit 452C is connected to the load current source 406.

[0171] The load current source 406C (when the load current sources 406A, 406B, and 406C are not distinguished from one another, the load current source 406 is referred to as the load current source 406) is connected to the signal line 302 and supplies a current for reading out pixel signals from the pixels 301. This makes it possible to stabilize the operation of the amplifier unit 451C. The load current source 406C is also connected to the signal line 302. The load current source 406C may be provided on the first semiconductor substrate 210 or on the second semiconductor substrate 220.

[0172] The FD 403 and the pixel output unit 405 may be shared with other pixels 301. For example, the FD 403 and the pixel output unit 405 may be shared by a plurality of pixels 301 arranged side by side in the row or column direction. The pixel 301 may also be configured with a plurality of photoelectric conversion units 400 and transfer units 401.

[0173] 31 is a timing chart showing an example of exposure timing control of the pixel 301 according to Example 2. The difference from Fig. 7 is that a transfer control signal G3 and a selection control signal SEL3 are added.

[0174] First, the imaging (exposure and readout) of frame F1 will be described. Light is emitted from the light source of electronic device 100 as a light projection signal ES onto subject 110 in synchronization with the falling edge of discharge control signal D and the rising edges of transfer control signals G2 and G3, and pixel 301 receives the light reflected from subject 110 as a light reception signal RS. The number of pulses of light projection signal ES and light reception signal RS is set to 1000.

[0175] The transfer control signals G2 and G3 turn ON in synchronization with the rising edge of the light projection signal ES, and the transfer control signal G1 turns ON in synchronization with the falling edge of the transfer control signal G2. The transfer control signal G3 turns OFF in synchronization with the falling edge of the transfer control signal G1. The discharge control signal D turns OFF in synchronization with the rising edge of the light projection signal ES, and turns ON in synchronization with the falling edge of the transfer control signal G1.

[0176] Therefore, the charge photoelectrically converted by the photoelectric conversion unit 400 is accumulated in FD 403B during the period when the transfer control signal G2 is ON and the discharge control signal D is OFF, accumulated in FD 403A during the period when the transfer control signal G1 is ON and the discharge control signal D is OFF, and accumulated in FD 403C during the period when the transfer control signal G3 is ON and the discharge control signal D is OFF.

[0177] When the selection control signals SEL1, SEL2, and SEL3 are turned ON, the exposure ends and the charge accumulated in the FD 403 is read out.

[0178] Thereafter, the timing value (control signal CTR) is calculated, and the exposure timing of the next frame F2, that is, the output timing of the transfer control signals G1, G2, G3 and the discharge control signal D, is adjusted.

[0179] 32 is an explanatory diagram illustrating an example of a block configuration of the image sensor 102 according to Example 2. The pixel driving unit 513 outputs transfer control signals G1, G2, and G3 to the pixel 301. The pixel 301 controls the transfer of charges photoelectrically converted by the photoelectric conversion unit 400 to the FD 403 using the transfer control signals G1, G2, and G3.

[0180] The charges accumulated in the FDs 403A, 403B, and 403C are converted into voltages and output as analog pixel signals P1, P2, and P3 to the signal processing unit 502. The signal processing unit 502 performs AD conversion on the analog pixel signals P1, P2, and P3 to convert them into digital pixel signals Q1, Q2, and Q3, and outputs the digital pixel signals Q1, Q2, and Q3 to the autonomous exposure processing unit 511 and the peripheral circuit unit 221. The digital pixel signal Q3 is a signal that indicates the luminance of the background.

[0181] The autonomous exposure processor 511 calculates a control signal related to the exposure time for capturing the next frame based on the digital pixel signals Q1, Q2, and Q3. The exposure controller 512 adjusts the output timing of the transfer control signals G1, G2, and G3 and the discharge control signal D so that the exposure time corresponds to the control signal related to the exposure time calculated by the autonomous exposure processor 511, and outputs the output timing signal to the pixel driver 513. The pixel driver 513 controls the driving of the pixels 301 using the transfer control signals G1, G2, and G3 and the discharge control signal D whose output timing has been adjusted by the exposure controller 512.

[0182] [Fig. 33: Example of a circuit configuration of an image sensor 102] Fig. 33 is an explanatory diagram illustrating an example of a circuit configuration of an image sensor 102 according to a second embodiment. Differences from Fig. 9 will be described. The signal conversion unit 522 includes an ADC 5223 that performs AD conversion of an analog pixel signal P3 into a digital pixel signal Q3, in addition to an ADC 522A and an ADC 522B. When the ADCs 522A, 522B, and 522C are not to be distinguished from one another, they will be simply referred to as ADC 522. The ADC 522C may be an SAR type or an SS type.

[0183] The ADC 522C outputs a 12-bit digital pixel signal Q3 to the signal output unit 523. When the digital pixel signals Q1, Q2, and Q3 are not distinguished from one another, they are referred to as a digital pixel signal Q. The 12-bit bit width of the digital pixel signal Q is an example, and a bit width other than 12 bits may be used. The ADC 522C also outputs a digital pixel signal Q3_MSB, which is the most significant three bits of the 12-bit digital pixel signal Q3, to the autonomous exposure processing unit 511. When the digital pixel signals Q1_MSB, Q2_MSB, and Q3_MSB are not distinguished from one another, they are referred to as a digital pixel signal Q_MSB. The 3-bit bit width of the digital pixel signal Q_MSB is an example, and it is sufficient if it is smaller than the bit width of the digital pixel signal Q.

[0184] The autonomous exposure processing unit 511 has a first subtraction unit 3301, a second subtraction unit 3302, and an encoder 3303. The first subtraction unit 3301 is connected to the ADC 522A, the ADC 522C, and the encoder 3303. The first subtraction unit 3301 subtracts the digital pixel signal Q3_MSB from the digital pixel signal Q1_MSB, and outputs a first subtraction result SR1 to the encoder 3303.

[0185] The second subtraction unit 3302 is connected to the ADC 522B, the ADC 522C, and the encoder 3303. The second subtraction unit 3302 subtracts the digital pixel signal Q3_MSB from the digital pixel signal Q2_MSB, and outputs the second subtraction result SR2 to the encoder 3303.

[0186] The encoder 3303 refers to the conversion table 900 and outputs a 3-bit control signal CTL to the exposure control unit 512 based on the first subtraction result SR1 and the second subtraction result SR2. In this example, the encoder 3303 is a 6-bit input / 3-bit output encoder. The control signal CTL is also used in the exposure control unit 512 to calculate the time of flight Td.

[0187] 34 is an explanatory diagram showing an example of a conversion table 3300 according to Example 2. The autonomous exposure processing unit 511 refers to the conversion table 3300, and determines the ratio Q2:Q1 of the digital pixel signals Q1, Q2 based on the combination of the first subtraction result SR1 and the second subtraction result SR2, and generates a 3-bit control signal CTL corresponding to the ratio Q2:Q1. Note that the correspondence relationship between the ratio Q2:Q1 and the time of flight Td is the same as in Example 1.

[0188] [Fig. 35 Detailed Circuit Configuration Example 1 of Image Sensor 102] Fig. 35 is an explanatory diagram showing a detailed circuit configuration example 1 of the image sensor 102 according to Example 2. Fig. 35 shows a circuit configuration example in which the signal conversion unit 522 is of SS type. The difference from Fig. 13 is that a signal conversion unit 522C is added, and the autonomous exposure processing unit 511 is configured with a first subtraction unit 3301, a second subtraction unit 3302, and an encoder 3303.

[0189] The signal conversion unit 522C has a comparator 1301C and a latch circuit 1302C. The signal conversion unit 522B has a comparator 1301B and a latch circuit 1302B. When the comparators 1301A to 1301C are not distinguished from each other, they are referred to as comparators 1301. When the latch circuits 1302A to 1302C are not distinguished from each other, they are referred to as latch circuits 1302.

[0190] The reference signal ref is input to the comparator 1301C. The comparator 1301C outputs a digital value (High (1) or Low (0)) indicating the result of comparison between the analog pixel signal P3 and the reference signal ref.

[0191] The latch circuits 1302C are circuits that hold digital values ​​of 0 or 1, and exist for each bit. Each latch circuit 1302C holds the analog pixel signal P as a digital value. A count value is input to the latch circuit 1302C. The count value increases by 1 over time. Because the signal conversion unit 522C is of the SS type, the values ​​of all bits are determined as the digital pixel signal Q3 at the time (count value) when the input analog pixel signal P3 and the reference signal ref match.

[0192] [Fig. 36: Detailed Circuit Configuration Example 2 of Image Sensor 102] Fig. 36 is an explanatory diagram showing a detailed circuit configuration example 2 of the image sensor 102 according to Example 2. Fig. 36 shows a circuit configuration example when the signal conversion unit 522 is of an SAR type. The difference from Fig. 14 is that a signal conversion unit 522C is added, and the autonomous exposure processing unit 511 is configured with a first subtraction unit 3301, a second subtraction unit 3302, and an encoder 3303.

[0193] The signal conversion unit 522C has an S&H circuit 1401C, a comparator 1301C, an n-bit DAC 1402C, an n-bit register 1403C, and a control circuit 1404C.

[0194] When there is no need to distinguish between the S&H circuits 1401A to 1401C, they are referred to as S&H circuits 1401. When there is no need to distinguish between the n-bit DACs 1402A to 1402C, they are referred to as n-bit DACs 1402. When there is no need to distinguish between the n-bit registers 1403A to 1403C, they are referred to as n-bit registers 1403. When there is no need to distinguish between the control circuits 1404A to 1404C, they are referred to as control circuits 1404.

[0195] The S&H circuit 1401C samples and holds the analog pixel signal P and outputs it to the comparator 1301C as a voltage signal VinC. When the voltage signals VinA to VinC are not distinguished, they are referred to as a voltage signal Vin. The n-bit DAC 1402C converts the n-bit digital pixel signal Q3 into an analog signal VdacC (voltage). When the analog signals VdacA to VdacC are not distinguished, they are referred to as an analog signal Vdac.

[0196] The comparator 1301C compares the voltage signal VinC of the analog pixel signal P sampled and held by the S&H circuit 1401C with the analog signal VdacC from the n-bit DAC 1402C. The comparator 1301C outputs High (1) if VinC≧VdacC, and outputs Low (0) if VinC<VdacC.

[0197] Since the SAR ADC is a method of determining data from the most significant bit, the analog signal VdacC from the n-bit DAC 1402C is set to a voltage value that is half the upper limit value of the input to the comparator 1301C.

[0198] The n-bit register 1403C is a latch circuit that stores the output value (High (1) or Low (0)) of the comparator 1301C.

[0199] The control circuit 1404C generates a DAC voltage for determining the next lower bit based on the value stored in the n-bit register 1403C. For example, when DAC (MSB) = 1 / 2 [V] and P3 > VdacC, the control circuit 1404C causes DAC (MSB-1) to generate a voltage of 1 / 2 + 1 / 4. By repeating this cycle, the digital pixel signal Q3 is determined starting from the higher bits, and the bit resolution increases according to the number of cycles.

[0200] The SAR type ADC 522 shown in Fig. 36 can operate at a higher speed than the SS type ADC 522 shown in Fig. 35. The SS type ADC 522 shown in Fig. 35 can achieve a smaller circuit scale than the SAR type ADC 522 shown in Fig. 36.

[0201] [Fig. 37 Detailed Circuit Configuration Example 3 of Image Sensor 102] Fig. 37 is an explanatory diagram showing a detailed circuit configuration example 3 of the image sensor 102 according to Example 2. Fig. 37 shows a circuit configuration example when the signal conversion unit 522 is of SS type and SAR type. In Fig. 37, an SAR type ADC 1501 functions as the autonomous exposure processing unit 511. The SS type ADC 1502 has the same configuration as that shown in Fig. 35.

[0202] The SAR ADC 1501 has an S&H selection circuit 1511, a comparator 1512, a 3-bit DAC 1513, an n-bit register 1514, and a control circuit 1515. The difference from FIG. 15 is that an analog pixel signal P3 indicating the luminance of the background is input from the pixel 301 to the S&H selection circuit 1511.

[0203] The S&H selection circuit 1511 subtracts the analog pixel signal P3 from the analog pixel signal P1 and samples and holds the subtraction result P10. The S&H selection circuit 1511 subtracts the analog pixel signal P3 from the analog pixel signal P2 and samples and holds the subtraction result P20. The S&H selection circuit 1511 selects the output destination (the comparator 1512 or the 3-bit DAC) of each of the sampled and held subtraction results P10 and P20 based on a selection signal SEL from an n-bit register 1514. When there is no need to distinguish between the subtraction results P10 and P20, they are referred to as subtraction result P00.

[0204] 38 is an explanatory diagram showing the selection process of the S&H selection circuit 1511 according to the second embodiment. When the value of the selection signal SEL is “0”, the S&H selection circuit 1511 sets the output destination of the sampled and held subtraction result P10 to the comparator 1512, and sets the output destination of the sampled and held subtraction result P20 to the 3-bit DAC 1513. When the value of the selection signal SEL is “1”, the S&H selection circuit 1511 sets the output destination of the sampled and held subtraction result P10 to the 3-bit DAC 1513, and sets the output destination of the sampled and held subtraction result P20 to the comparator 1512.

[0205] 37 , the comparator 1512 receives the subtraction result P00 from the S&H selection circuit 1511 as the voltage signal Vin, and also receives the analog signal Vdac from the 3-bit DAC 1513. The comparator 1512 compares the voltage signal Vin with the analog signal Vdac. The comparator 1512 outputs High (1) to the n-bit register 1514 if Vin≧Vdac, and Low (0) if Vin<Vdac.

[0206] The n-bit register 1514 holds the comparison result from the comparator 1512. The n-bit register 1514 outputs a 1-bit selection signal SEL to the S&H selection circuit 1511 and the exposure control unit 512.

[0207] The control circuit 1515 controls the voltage value of the analog signal Vdac based on the comparison result (High (1) or Low (0)) from the comparator 1512 held in the n-bit register 1514. Specifically, for example, the control circuit 1515 does not adjust the voltage to 1 / 2, 1 / 4, etc. based on the upper input limit value of the comparator 1512, but directly compares the analog pixel signals P1 and P2 by using the reference signal REF (P1 or P2) from the S&H selection circuit 1511 as a reference. The control circuit 1515 outputs a 3-bit digital signal REG, which is the comparison result of the analog pixel signals P1 and P2, to the 3-bit DAC 1513 and the exposure control unit 512.

[0208] 39 is a graph showing an example of generation of the digital signal REG according to the second embodiment. The graph 3900 shows an example in which the subtraction result P10 is input to the comparator 1512 as the voltage signal Vin (selection signal SEL=0). When the selection signal SEL=1, P10 and P20 in the graph 3900 are swapped.

[0209] For REG[2], the most significant bit of the digital signal REG, the analog signal Vdac from the 3-bit DAC 1513 is higher than the voltage signal Vin, so the value of REG[2] is "0". For REG[1] of the digital signal REG, the analog signal Vdac from the 3-bit DAC 1513 is lower than the voltage signal Vin, so the value of REG[1] is "1". For REG[0], the least significant bit of the digital signal REG, the analog signal Vdac from the 3-bit DAC 1513 is higher than the voltage signal Vin, so the value of REG[0] is "0". Therefore, the digital signal REG has a value of "010".

[0210] Returning to FIG. 37, the exposure control unit 512 controls exposure based on a 3-bit digital signal from the control circuit 1515 and a 1-bit selection signal SEL from an n-bit register.

[0211] The first conversion table 1800 shown in FIG. 18 is applied when the selection signal SEL is “0”, that is, when the subtraction result P 10 is output to the comparator 1512 .

[0212] The second conversion table 1900 shown in FIG. 19 is applied when the selection signal SEL is “1”, that is, when the subtraction result P 20 is output to the comparator 1512 .

[0213] The exposure control unit 512 determines the ratio Q2:Q1 based on either the first conversion table 1800 or the second conversion table 1900 and the 3-bit digital signal REG from the control circuit 1515. The exposure control unit 512 generates a 3-bit control signal CTL corresponding to the ratio Q2:Q1 as a control signal related to the exposure time, and outputs it to the pixel driving unit 513. In the first conversion table 1800 of FIG. 18, the selection signal SEL=0 and the digital signal REG shown in FIG. 39 is "010", so the ratio Q2:Q1 is "2:8".

[0214] The pixel drive unit 513 controls the driving of the pixels 301 using the transfer control signals G1 and G2 and the discharge control signal D whose output timing is adjusted by the exposure control unit 512. In the above example, the exposure control unit 512 adjusts the timing of the transfer control signals G1 and G2 so that the ratio Q2:Q1 is 8:8. Note that the transfer control signal G3 may be adjusted forward or backward by the same amount as the timing adjustment amount of the transfer control signals G1 and G2. Because background light generally has low frequency dependency, there is little impact even if the timing of the transfer control signals G1 and G2 is slightly off. However, the timing of the discharge control signal D is adjusted so that it is the inverse of the OR signal of the transfer control signals G1 to G3.

[0215] The exposure control unit 5412 is the same as that in the first embodiment. The difference from the first embodiment is the calculation formula for the flight time Td. The calculation formula for the flight time Td in the second embodiment is shown in the following formula (3).

[0216]

[0217] <Modification of Exposure Timing Control> Fig. 40 is an explanatory diagram showing a modification of exposure timing control according to Example 2. In Fig. 31 , frame F1 is exposed at default timing, and the timing value for frame F1 is used to update the exposure timing for the subsequent frame F2. In contrast, in Fig. 40 , calibration related to exposure control is performed at default timing for frame F1 before actual shooting, and the exposure timing for the actual shooting of frame F1 is updated using the timing value from that calibration. For subsequent frames F2 and onwards, the same processing as in Fig. 31 is performed.

[0218] The number of pulses of the light projection signal ES and the light reception signal RS in the calibration is adjusted to be smaller than the number of pulses of the light projection signal ES and the light reception signal RS in the actual photographing. In this example, the number of pulses of the light projection signal ES and the light reception signal RS in the actual photographing is 1000, whereas the number of pulses of the light projection signal ES and the light reception signal RS in the calibration is 10.

[0219] In this way, by performing calibration before the actual shooting of frame F1, it is possible to optimize the exposure for frame F1. Furthermore, by performing such calibration with fewer pulses of the light projection signal ES and the light reception signal RS than in the actual shooting, it is possible to speed up the calibration.

[0220] As described above, according to the first and second embodiments, it is possible to improve the distance measurement accuracy.

[0221] The electronic device described above can also be configured as follows (1) to (29).

[0222] (1) An electronic device having: an irradiation unit that irradiates light; a light receiving unit having a first accumulation unit and a second accumulation unit that can accumulate electric charges by photoelectrically converting light reflected from a subject that is incident as a result of irradiating the subject with light from the irradiation unit; a generation unit that generates comparison data that compares a first accumulation amount of electric charge in the first accumulation unit with a second accumulation amount of electric charge in the second accumulation unit; a control unit that controls the timing of switching from accumulation by the first accumulation unit to accumulation by the second accumulation unit based on the comparison data from the generation unit; and a calculation unit that calculates a distance to the subject based on the irradiation time of light from the irradiation unit, the first accumulation amount and the second accumulation amount after the timing has been controlled by the control unit, and the comparison data before the timing has been controlled by the control unit.

[0223] (2) The electronic device according to (1), wherein the control unit controls the timing so that a difference between the first accumulation amount and the second accumulation amount becomes small.

[0224] (3) The electronic device according to (1) above, comprising: a first conversion unit that converts the first accumulation amount into a first digital signal; and a second conversion unit that converts the second accumulation amount into a second digital signal, wherein the generation unit calculates the comparison data based on the first digital signal and the second digital signal.

[0225] (4) The electronic device according to (3), wherein the generation unit calculates the comparison data based on bit strings at specific bit positions that are part of the first digital signal and the second digital signal.

[0226] (5) The electronic device according to (4), wherein the specific bit position is a bit position of a higher-order bit that is located higher than a bit position of a lower-order bit in each bit string of the first digital signal and the second digital signal.

[0227] (6) The electronic device according to (3), wherein the generating unit compares the first accumulation amount with the second accumulation amount to generate the comparison data in digital form.

[0228] (7) The electronic device described in (1) above, wherein the light receiving unit has a third accumulation unit capable of photoelectrically converting the reflected light and accumulating electric charge, and compares a first difference between the first accumulation amount and a third accumulation amount of electric charge in the third accumulation unit with a second difference between the second accumulation amount and the third accumulation amount to output the comparison data, and the calculation unit further calculates the distance to the subject based on the third accumulation amount.

[0229] (8) The electronic device according to (7), wherein the control unit controls the timing so that a difference between the first difference amount and the second difference amount becomes small.

[0230] (9) The electronic device according to (7) above, comprising: a first conversion unit that converts the first difference amount into a first digital signal; and a second conversion unit that converts the second difference amount into a second digital signal, wherein the generation unit calculates the comparison data based on the first digital signal and the second digital signal.

[0231] (10) The electronic device according to (9), wherein the generation unit calculates the comparison data based on bit strings at specific bit positions that are part of the first digital signal and the second digital signal.

[0232] (11) The electronic device according to (10), wherein the specific bit position is a bit position of a higher-order bit that is located higher than a bit position of a lower-order bit in each bit string of the first digital signal and the second digital signal.

[0233] (12) The electronic device according to (8), wherein the generation unit compares the first difference amount with the second difference amount to generate the digital comparison data.

[0234] (13) The electronic device according to any one of (1) to (11), wherein the control unit has a resistor and a capacitor, adjusts one of the resistor and the capacitor based on the comparison data, and controls the timing based on the adjusted time constant of the one of the elements.

[0235] (14) The electronic device according to (12), wherein the one of the elements is an element whose value is variable based on the comparison data.

[0236] (15) The electronic device according to (12), wherein the one element is a plurality of elements having different values, and the control unit selects one of the plurality of elements.

[0237] (16) The electronic device described in (1) above, wherein the control unit has an assert circuit that outputs an assert signal, a negate circuit that outputs a negate signal, and a generation circuit that generates a control signal in which the assert signal and the negate signal overlap, and controls the timing based on the control signal, wherein the assert circuit controls the rising timing of the assert signal based on a clock signal and the comparison data, and the negate circuit controls the falling timing of the negate signal based on the clock signal and the comparison data.

[0238] (17) An electronic device according to (1) above, comprising a first substrate and a second substrate stacked together, the first substrate having a plurality of the light receiving elements, and the second substrate having, for each light receiving element, a conversion unit that converts analog signals of the first accumulation amount and the second accumulation amount from the light receiving elements into digital signals, a generation unit to which the digital signals are input, the control unit, and the calculation unit, all of which are positioned opposite the light receiving elements.

[0239] (18) An electronic device as described in (17) above, comprising the first substrate, first wiring layer, second wiring layer and second substrate stacked together, wherein the first wiring layer comprises: a first output wiring for outputting the analog signal; and a first input wiring for inputting a timing control signal indicating the timing from the control unit to the light receiving unit, and the second wiring layer comprises: a second input wiring connected to the first output wiring for inputting the analog signal to the conversion unit, and a second output wiring connected to the first input wiring for outputting the timing control signal to the first input wiring.

[0240] (19) The electronic device according to (12) above, comprising a first substrate, a first wiring layer, a second wiring layer and a second substrate which are stacked together, the first substrate comprising a plurality of the light receiving portions, the second substrate comprising a conversion unit which converts analog signals of the first accumulation amount and the second accumulation amount from the light receiving portions into digital signals, the generation unit to which the digital signals are input, the control unit and the calculation unit, which are located for each of the light receiving portions, facing the light receiving portions, the first wiring layer comprising: a first output wiring which outputs analog signals of the first accumulation amount and the second accumulation amount from the light receiving portions; and a first input wiring which inputs a timing control signal indicating the timing from the control unit to the light receiving portions, the second wiring layer comprising: a second input wiring which is connected to the first output wiring and which inputs the analog signal to the generation unit; and a second output wiring which is connected to the first input wiring and which outputs the timing control signal to the first input wiring, a wiring having the one of the elements of the control unit is arranged in the second wiring layer and the first wiring layer.

[0241] (20) The electronic device described in (1) above, comprising a first substrate, a second substrate and a third substrate stacked together, wherein the first substrate comprises a plurality of the light receiving units, the second substrate comprises a conversion unit that converts analog signals of the first accumulation amount and the second accumulation amount from the light receiving units into digital signals, a readout unit that reads out the digital signals to the outside of the electronic device and to the generation unit, and a set of a driver that drives the first accumulation unit and the second accumulation unit at the timing, positioned opposite the light receiving units for each of the light receiving units, and the third substrate comprises a set of the generator, the control unit and the calculation unit, positioned opposite the set of the converter, the readout unit and the driver for each set of the converter, the readout unit and the driver.

[0242] (21) The electronic device described in (17) above, wherein the second substrate has a first set of a first conversion unit, a first generation unit, a first control unit, and a first calculation unit facing a first light receiving unit among the plurality of light receiving units, and a second set of a second conversion unit, a second generation unit, a second control unit, and a second calculation unit facing a second light receiving unit among the plurality of light receiving units that is arranged next to the first light receiving unit, and the first conversion unit of the first set and the second conversion unit of the second set are arranged adjacent to each other.

[0243] (22) The electronic device described in (17) above, wherein the second substrate has a first set of a first conversion unit, a first generation unit, a first control unit, and a first calculation unit facing a first light receiving unit among the plurality of light receiving units, and a second set of a second conversion unit, a second generation unit, a second control unit, and a second calculation unit facing a second light receiving unit among the plurality of light receiving units that is arranged next to the first light receiving unit, and the first generation unit of the first set and the second generation unit of the second set are arranged adjacent to each other.

[0244] (23) The electronic device described in (17) above, wherein the second substrate has a first set of a first conversion unit, a first generation unit, a first control unit, and a first calculation unit facing a first light receiving unit among the plurality of light receiving units, and a second set of a second conversion unit, a second generation unit, a second control unit, and a second calculation unit facing a second light receiving unit among the plurality of light receiving units that is arranged next to the first light receiving unit, and the first control unit of the first set and the second control unit of the second set are arranged adjacent to each other.

[0245] (24) The electronic device described in (1) above, wherein the light receiving unit accumulates the first accumulation amount and the second accumulation amount multiple times during a first accumulation period, and accumulates the first accumulation amount and the second accumulation amount multiple times during a second accumulation period after the first accumulation period has elapsed; the generation unit compares the first accumulation amount and the second accumulation amount accumulated after the multiple executions during the first accumulation period and outputs the comparison data; and the control unit controls the timing during the second accumulation period after the first accumulation period has elapsed.

[0246] (25) An electronic device according to (23) above, comprising: a first conversion unit that converts the first accumulation amount into a first digital signal; a second conversion unit that converts the second accumulation amount into a second digital signal; and a readout unit that reads out the first digital signal and the second digital signal to a readout destination, wherein the readout unit reads out the first digital signal and the second digital signal to the readout destination after the first accumulation period has elapsed and before the second accumulation period begins.

[0247] (26) The electronic device described in (23) above, comprising: a first conversion unit that converts the first accumulation amount into a first digital signal; a second conversion unit that converts the second accumulation amount into a second digital signal; and a readout unit that reads out the first digital signal and the second digital signal to a readout destination, wherein the readout unit reads out the first digital signal and the second digital signal to the readout destination before the start of the first accumulation period and the second accumulation period.

[0248] (27) The electronic device according to (25) above, wherein the number of times the first accumulation amount and the second accumulation amount are accumulated during the first accumulation period is less than the number of times the first accumulation amount and the second accumulation amount are accumulated during the second accumulation period.

[0249] (28) The electronic device according to (1) above, wherein the irradiation unit repeatedly irradiates light, and the control unit controls the irradiation timing at which the irradiation unit irradiates light based on the first accumulation amount and the second accumulation amount.

[0250] (29) The electronic device according to (27) above, wherein the control unit controls the irradiating unit to irradiate light at intervals that are increased when the first accumulation amount is equal to or less than a first threshold value and the second accumulation amount is equal to or less than a second threshold value.

[0251] The present invention is not limited to the above-described contents, and may be implemented by any combination thereof. Furthermore, other embodiments conceivable within the scope of the technical concept of the present invention are also included in the scope of the present invention.

[0252] 100 Electronic device, 101 Light source, 102 Image sensor, 110 Subject, 121 2-tap charge distribution element, 122 3-tap charge distribution element, 201 Pixel unit, 202 Control circuit unit, 203 Data processing unit, 210 First semiconductor substrate, 220 Second semiconductor substrate, 221 Peripheral circuit unit, 230 Third semiconductor substrate, 300 Pixel block, 301 Pixel, 400 Photoelectric conversion unit, 401 Transfer unit, 402 Discharge unit, 403 FD, 404 Reset unit, 405 Pixel output unit, 406 Load current source, 410 Readout unit, 451 Amplification unit, 452 Selection unit, 500 Control block, 501 Pixel control unit, 502 Signal processing unit, 511 Autonomous exposure processing unit, 512 Exposure control unit, 513 Pixel drive unit, 521 Signal input unit, 522 Signal conversion unit, 523 signal output unit, 601 comparator, 602 memory unit, 603 pixel block control unit, 604 level shift unit, 900 conversion table, 1301 comparator, 1302 latch circuit, 1401 S&H (Sample & Hold) circuit, 1403 n-bit register, 1404 control circuit, 1511 selection circuit, 1512 comparator, 1514 n-bit register, 1515 control circuit, 1800 first conversion table, 1900 second conversion table, 2000 RC circuit, 2001 variable resistor, 2002 capacitor, 2203 FF 2204 AND circuit, 2601 first wiring layer, 2602 second wiring layer, 2610 first connection unit, 2611 first connection pad, 2612 second connection pad, 2613 First timing circuit, 2620: Second connection section, 2621: First connection pad, 2622: Second connection pad, 2623: Second timing circuit, 3301: First subtraction section, 3302: Second subtraction section, 3303: Encoder, 3300: Conversion table

Claims

a first photoelectric conversion unit that converts light into electric charges; a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in the row direction; a first accumulation unit to which the charges converted by the first photoelectric conversion unit are transferred; a second accumulation unit to which the charges converted by the first photoelectric conversion unit are transferred; a third accumulation unit to which the charges converted by the second photoelectric conversion unit are transferred; a fourth accumulation unit to which the charges converted by the second photoelectric conversion unit are transferred; a first transfer unit including a plurality of transistors for transferring the charges converted by the first photoelectric conversion unit, and transferring the charges to the first accumulation unit and then to the second accumulation unit; a second transfer unit including a plurality of transistors for transferring the charges converted by the second photoelectric conversion unit, and transferring the charges to the third accumulation unit and then to the fourth accumulation unit; a drive unit that controls so that a first timing at which the first transfer unit transfers the electric charges converted in the first photoelectric conversion unit to the second accumulation unit and a second timing at which the second transfer unit transfers the electric charges converted in the second photoelectric conversion unit to the fourth accumulation unit are different from each other; An imaging element comprising:

2. The imaging device according to claim 1, the driving section outputs driving signals to the first transfer section and the second transfer section so that the first timing and the second timing are different from each other. Image sensor.

3. The imaging device according to claim 2, the first transfer unit includes a first transfer transistor that transfers the charges converted by the first photoelectric conversion unit to the first accumulation unit, and a second transfer transistor that transfers the charges converted by the first photoelectric conversion unit to the second accumulation unit; the second transfer unit includes a third transfer transistor that transfers the charges converted by the second photoelectric conversion unit to the third accumulation unit, and a fourth transfer transistor that transfers the charges converted by the second photoelectric conversion unit to the fourth accumulation unit, the drive unit outputs drive signals to the second transfer transistor and the fourth transfer transistor so that the first timing at which the charges converted in the first photoelectric conversion unit are transferred to the second accumulation unit by the second transfer transistor and the second timing at which the charges converted in the second photoelectric conversion unit are transferred to the fourth accumulation unit by the fourth transfer transistor are different timings. Image sensor.

3. The imaging device according to claim 2, The imaging element includes a control unit that controls a timing at which the drive signal is output from the drive unit.

5. The imaging device according to claim 4, An imaging element comprising a generation unit that generates first comparison data by comparing a first signal value of a signal based on the charge of the first storage unit with a second signal value of a signal based on the charge of the second storage unit, and second comparison data by comparing a third signal value of a signal based on the charge of the third storage unit with a fourth signal value of a signal based on the charge of the fourth storage unit.

6. The imaging device according to claim 5, the control unit controls the first timing based on the first comparison data, and controls the second timing based on the second comparison data. Image sensor.

7. The imaging device according to claim 6, The driving section includes a first driving circuit section that outputs a driving signal to the first transfer section, and a second driving circuit section that outputs a driving signal to the second transfer section.

8. The imaging device according to claim 7, The control unit includes a first control circuit that controls the first drive circuit, and a second control circuit that controls the second drive circuit.

9. The imaging device according to claim 8, The generation unit includes a first generation circuit unit that generates the first comparison data and a second generation circuit unit that generates the second comparison data.

10. The imaging device according to claim 9, an imaging element including a calculation unit for calculating a distance to a subject based on the first comparison data and the first signal value and the second signal value after the first timing is controlled, and a distance to the subject based on the second comparison data and the third signal value and the fourth signal value after the second timing is controlled. 　 The imaging device according to claim 10, the first control circuit controls the first timing so that a difference between the first signal value and the second signal value becomes small; the second control circuit controls the second timing so that a difference between the third signal value and the fourth signal value becomes small. Image sensor. 　 The imaging device according to claim 10, a first conversion unit that converts the first signal value into a first digital signal; a second conversion unit that converts the second signal value into a second digital signal value; a third conversion unit that converts the third signal value into a third digital signal value; a fourth conversion unit that converts the fourth signal value into a fourth digital signal value, the first generation circuit calculates the first comparison data based on the first digital signal value and the second digital signal value; the second generation circuit unit calculates the second comparison data based on the third digital signal value and the fourth digital signal value. Image sensor. The imaging device according to claim 12, the first generation circuit unit calculates the first comparison data based on bit strings at first bit positions that are part of the first digital signal value and the second digital signal value; the second generation circuit unit calculates the second comparison data based on bit strings at second bit positions that are part of the third digital signal value and the fourth digital signal value; Image sensor. 　 The imaging device according to claim 13, the first bit position is a bit position of a more significant bit located higher than a bit position of a less significant bit in the bit strings of each of the first digital signal value and the second digital signal value, and the second bit position is a bit position of a more significant bit located higher than a bit position of a less significant bit in the bit strings of each of the third digital signal value and the fourth digital signal value. Image sensor. 　 The imaging device according to claim 12, the first generation circuit unit compares the first signal value with the second signal value to generate the first comparison data, which is digital; the second generation circuit unit compares the third signal value with the fourth signal value to generate the second comparison data, which is digital; Image sensor. 　 The imaging device according to claim 11, a fifth accumulation unit to which charges are transferred from the first photoelectric conversion unit; a sixth accumulation unit to which charges are transferred from the second photoelectric conversion unit, the first generation circuit unit compares a first differential signal value of a first differential signal between the first signal value and a fifth signal value of a signal based on the charge of the fifth storage unit with a second differential signal value of a second differential signal between the second signal value and the fifth signal value, and outputs the first comparison data; the second generation circuit unit compares a third differential signal value of a third differential signal between the third signal value and a sixth signal value of a signal based on the charge of the sixth storage unit with a fourth differential signal value of a fourth differential signal between the fourth signal value and the sixth signal value, and outputs the second comparison data; the calculation unit calculates a distance to the subject based on the first comparison data, the fifth signal value, and the first signal value and the second signal value after the first timing has been controlled, and a distance to the subject based on the second comparison data, the sixth signal value, and the third signal value and the fourth signal value after the second timing has been controlled. Image sensor.

17. The imaging device according to claim 16, the first control circuit controls the first timing so that a difference between the first differential signal value and the second differential signal value becomes small; the second control circuit controls the second timing so that a difference between the third differential signal value and the fourth differential signal value becomes small. Image sensor.

17. The imaging device according to claim 16, a first conversion unit that converts the first differential signal into a first digital signal value; a second conversion unit that converts the second differential signal into a second digital signal value; a third conversion unit that converts the third differential signal into a third digital signal value; a fourth conversion unit that converts the fourth differential signal into a fourth digital signal value, the first generation circuit calculates the first comparison data based on the first digital signal value and the second digital signal value; the second generation circuit unit calculates the second comparison data based on the third digital signal value and the fourth digital signal value. Image sensor.

19. The imaging device according to claim 18, the first generation circuit unit calculates the first comparison data based on bit strings at first bit positions that are part of the first digital signal value and the second digital signal value; the second generation circuit unit calculates the second comparison data based on bit strings at second bit positions that are part of the third digital signal value and the fourth digital signal value; Image sensor.

20. The imaging device according to claim 19, the first bit position is a bit position of a more significant bit located higher than a bit position of a less significant bit in the bit strings of each of the first digital signal value and the second digital signal value, and the second bit position is a bit position of a more significant bit located higher than a bit position of a less significant bit in the bit strings of each of the third digital signal value and the fourth digital signal value. Image sensor.

19. The imaging device according to claim 18, the first generation circuit unit compares the first differential signal value with the second differential signal value to generate the first comparison data, which is digital; the second generation circuit unit compares the third difference signal value with the fourth difference signal value to generate the second comparison data, which is digital; Image sensor.

22. The imaging device according to claim 1, the control unit has a resistor and a capacitor, adjusts one of the resistor and the capacitor based on the first comparison data and the second comparison data, and controls the timing based on the adjusted time constant of the one of the resistor and the capacitor. Image sensor.

23. The imaging device according to claim 22, the value of either one of the elements is variable based on the first comparison data and the second comparison data; Image sensor.

23. The imaging device according to claim 22, the one element is a plurality of elements having different values, The control unit selects one of the plurality of elements. Image sensor. 　 The imaging device according to claim 10, the control unit has an assertion circuit that outputs an assertion signal, a negation circuit that outputs a negation signal, and a generation circuit that generates a control signal in which the assertion signal and the negation signal overlap, and controls the first timing and the second timing based on the control signal; the assert circuit controls the rising timing of the assert signal based on a clock signal, the first comparison data, and the second comparison data; the negate circuit controls the falling timing of the negate signal based on the clock signal and the comparison data; Image sensor. 　 The imaging device according to claim 10, a first substrate and a second substrate that are stacked together; the first substrate includes the first photoelectric conversion unit and the second photoelectric conversion unit, the second substrate includes a first conversion unit that converts the first signal value and the second signal value into digital signal values, and a second conversion unit that converts the third signal value and the fourth signal value into digital signal values, the first conversion unit is disposed at a position facing the first photoelectric conversion unit, and the second conversion unit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

27. The imaging device according to claim 26, the second substrate has the first drive circuit unit and the second drive circuit unit, the first drive circuit unit is disposed at a position facing the first photoelectric conversion unit, and the second drive circuit unit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

28. The imaging device according to claim 27, the second substrate has a first control circuit unit and the second control circuit unit, the first control circuit is disposed at a position facing the first photoelectric conversion unit, and the second control circuit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

29. The imaging device according to claim 28, the second substrate has a first generating circuit unit and the second generating circuit unit; the first generation circuit unit is disposed at a position facing the first photoelectric conversion unit, and the second generation circuit unit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

25. The imaging device according to claim 24, a first substrate, a first wiring layer, a second wiring layer, and a second substrate that are stacked together; the first substrate includes the first photoelectric conversion unit and the second photoelectric conversion unit, the second substrate includes the first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit; the first conversion unit and the second conversion unit are disposed at positions facing the first photoelectric conversion unit, and the third conversion unit and the fourth conversion unit are disposed at positions facing the second photoelectric conversion unit. Image sensor.

31. The imaging device according to claim 30, the second substrate has the first drive circuit unit and the second drive circuit unit, the first drive circuit unit is disposed at a position facing the first photoelectric conversion unit, and the second drive circuit unit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

32. The imaging device according to claim 31, the second substrate has a first control circuit unit and the second control circuit unit, the first control circuit is disposed at a position facing the first photoelectric conversion unit, and the second control circuit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

33. The imaging device according to claim 32, the second substrate has a first generating circuit unit and the second generating circuit unit; the first generation circuit unit is disposed at a position facing the first photoelectric conversion unit, and the second generation circuit unit is disposed at a position facing the second photoelectric conversion unit; Image sensor.

34. The imaging device according to claim 33, the wiring layer has a first output wiring that outputs analog signals of the first signal value and the second signal value from the first photoelectric conversion unit, a second output wiring that outputs analog signals of the third signal value and the fourth signal value from the second photoelectric conversion unit, a first input wiring that inputs a first timing control signal indicating the first timing from the first control circuit unit to the first transfer unit, and a second input wiring that inputs a second timing control signal indicating the second timing from the second control circuit unit to the second transfer unit; the second wiring layer has a third input wiring connected to the first output wiring and inputting the analog signal to the first generation circuit unit, a fourth input wiring connected to the second output wiring and inputting the analog signal to the second generation circuit unit, a third output wiring connected to the first input wiring and outputting the first timing control signal to the first input wiring, and a fourth output wiring connected to the second input wiring and outputting the second timing control signal to the second input wiring; a wiring having the one of the elements of the control unit is arranged in the second wiring layer and the first wiring layer; Image sensor. 　 The imaging device according to claim 10, the first photoelectric conversion unit accumulates the first signal value and the second signal value a plurality of times during a first accumulation period, and accumulates the first signal value and the second signal value a plurality of times during a second accumulation period after the first accumulation period has elapsed; the first generation circuit compares the first signal value and the second signal value accumulated after a plurality of executions during the first accumulation period, and outputs the first comparison data; the first control circuit controls the first timing during a second accumulation period after the first accumulation period has elapsed; Image sensor.

36. The imaging device according to claim 35, the second photoelectric conversion unit accumulates the third signal value and the fourth signal value a plurality of times during a third accumulation period, and accumulates the third signal value and the fourth signal value a plurality of times during a fourth accumulation period after the third accumulation period has elapsed; the second generation circuit compares the third signal value and the fourth signal value accumulated after a plurality of executions during the third accumulation period, and outputs the second comparison data; the second control circuit controls the second timing during a fourth accumulation period after the third accumulation period has elapsed; Image sensor.

37. The imaging device according to claim 36, a first conversion unit that converts the first signal value into a first digital signal value; a second conversion unit that converts the second signal value into a second digital signal value; a third conversion unit that converts the third signal value into a third digital signal value; a fourth conversion unit that converts the fourth signal value into a fourth digital signal value; a reading unit that reads the first digital signal value, the second digital signal value, the third digital signal value, and the fourth digital signal value to a reading destination; the readout unit reads out the first digital signal value and the second digital signal value to the readout destination after the first accumulation period has elapsed and before the second accumulation period has started, and reads out the third digital signal value and the fourth digital signal value to the readout destination after the third accumulation period has elapsed and before the fourth accumulation period has started. Image sensor.

37. The imaging device according to claim 36, a first conversion unit that converts the first signal value into a first digital signal value; a second conversion unit that converts the second signal value into a second digital signal value; a third conversion unit that converts the third signal value into a third digital signal value; a fourth conversion unit that converts the fourth signal value into a fourth digital signal value; a reading unit that reads the first digital signal value, the second digital signal value, the third digital signal value, and the fourth digital signal value to a reading destination; the readout unit reads out the first digital signal value and the second digital signal value to the readout destination before the start of the first accumulation period and the second accumulation period, and reads out the third digital signal value and the fourth digital signal value to the readout destination before the start of the third accumulation period and the fourth accumulation period. Image sensor.

39. The imaging device according to claim 38, an imaging element in which the number of times the first signal value and the second signal value are accumulated during the first accumulation period is less than the number of times the first signal value and the second signal value are accumulated during the second accumulation period, and the number of times the third signal value and the fourth signal value are accumulated during the third accumulation period is less than the number of times the third signal value and the fourth signal value are accumulated during the fourth accumulation period.

40. The imaging device according to claim 1, An imaging device comprising the imaging element.

Images