Power amplifier bias circuit

Abstract

Power amplifier bias circuits are disclosed. In one aspect, a bias circuit is provided that provides temperature compensation based on temperatures in a power amplifier (118) while at the same time having a relatively low voltage overhead, allowing for use in low voltage devices. In further particulars, the bias circuit uses a feedback amplifier (404) to synthesize an equivalent bias resistance without needing a physical series resistance in an output of the bias circuit. With appropriate switches, the bias circuit can be configured to provide a positive temperature coefficient or a negative temperature coefficient. By providing a desired temperature-compensated bias signal while also operating at low voltages, power amplifier (118) operation may be improved.

Description

POWER AMPLIFIER BIAS CIRCUITPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 662,049, filed on June 20, 2024, and entitled “POWER AMPLIFIER BIAS CIRCUIT,” the contents of which are incorporated herein by reference in their entirety.BACKGROUNDI. Field of the Disclosure

[0002] The technology of the disclosure relates generally to power amplifiers and, more particularly, to temperature-compensating bias circuits for power amplifiers.II. Background

[0003] Computing and communication devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile computing and entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to increase the bandwidth available for data transmission to and from these devices to support the myriad functions. The desire for increased bandwidth has led to the use of higher frequencies and larger frequency bands that require sophisticated amplifier operation over large frequency bands. Pressure to reduce component size and power consumption remains a commercial reality for power amplifier designers. Balancing power consumption with desired operation provides room for innovation.SUMMARY

[0004] Aspects disclosed in the detailed description include systems and methods for providing a power amplifier bias circuit. In particular, a bias circuit is provided that provides temperature compensation based on temperatures in the power amplifier while at the same time having a relatively low voltage overhead, allowing for use in low voltagedevices. In further particulars, the bias circuit uses a feedback amplifier to synthesize an equivalent bias resistance without needing a physical series resistance in an output of the bias circuit. With appropriate switches, the bias circuit can be configured to provide a positive temperature coefficient or a negative temperature coefficient. By providing a desired temperature-compensated bias signal while also operating at low voltages, power amplifier operation may be improved.

[0005] In this regard, in one aspect, an amplifier chain is disclosed. The amplifier chain includes an amplifier transistor, a bias stage coupled to the amplifier transistor, the bias stage comprising a bias voltage drop and a bias circuit. The bias circuit of the amplifier chain comprising a virtual synthesized resistance in series with the bias voltage drop while keeping an actual series resistance out of a series path with the bias voltage drop and a current feedback loop comprising a current mirror to provide a loop gain to a bias signal passing through the series path.

[0006] In another aspect, a wireless communication device is disclosed. The wireless communication device includes a baseband processor (BBP) and a front-end module (FEM) coupled to the BBP comprising an amplifier chain. The amplifier chain of the wireless communication devices comprising an amplifier transistor, a bias stage coupled to the amplifier transistor, the bias stage comprising a bias voltage drop, and a bias circuit. The bias circuit comprising a virtual synthesized resistance in series with the bias voltage drop while keeping an actual series resistance out of a series path with the bias voltage drop and a current feedback loop comprising a current mirror to provide a loop gain to a bias signal passing through the series path.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a circuit diagram of a conventional bias circuit that suffers from headroom issues in low- voltage conditions;

[0008] Figure IB is a circuit diagram of an alternate bias stage replacing diodes with diode-connected transistors;

[0009] Figure 1C is a circuit diagram of an alternate bias stage that provides fractional diode voltages;

[0010] Figure ID is a circuit diagram of a closed loop bias stage that may be used in place of the diodes of Figure 1 A;

[0011] Figure 2 is a circuit diagram of an exemplary bias circuit with an abstracted synthesized resistance that allows operation at low voltage conditions;

[0012] Figure 3 is a block diagram of the bias circuit of Figure 2 with multiple feedback loops to assist in providing a desired synthesized resistance;

[0013] Figure 4 is a block diagram of the bias circuit of Figure 2 with additional details about the shunt synthesized resistance;

[0014] Figure 5 is a block diagram of the bias circuit of Figure 2 with additional switching details to switch temperature coefficient operation;

[0015] Figure 6 is a block diagram of the bias circuit of Figure 2 with cascoded current mirrors for more accurate mirroring ratio;

[0016] Figure 7 is a circuit diagram of the bias circuit of Figure 6 with an additional operational amplifier to balance the current mirror; and

[0017] Figure 8 is a block diagram of a wireless communication device, which may include the power amplifier bias circuits of Figures 2-7 according to the present disclosure.DETAILED DESCRIPTION

[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein, ft should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0019] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on orextend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0021] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] In keeping with the above admonition about definitions, the present disclosure uses transceiver in a broad manner. Current industry literature uses “transceiver” in twoways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuit as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0025] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0026] Aspects disclosed in the detailed description include systems and methods for providing a power amplifier bias circuit. In particular, a bias circuit is provided that provides temperature compensation based on temperatures in the power amplifier while at the same time having a relatively low voltage overhead, allowing for use in low voltage devices. In further particulars, the bias circuit uses a feedback amplifier to synthesize an equivalent bias resistance without needing a physical series resistance in an output of the bias circuit. With appropriate switches, the bias circuit can be configured to provide a positive temperature coefficient or a negative temperature coefficient. By providing a desired temperature-compensated bias signal while also operating at low voltages, power amplifier operation may be improved.

[0027] Before addressing aspects of the present disclosure, a brief overview of conventional bias circuits is discussed with reference to Figures 1A-1D. Against this backdrop, a discussion of aspects of the present disclosure begins below with reference to Figure 2.

[0028] In this regard, various bias circuits may be employed in conjunction with amplifier chains. In practice, the bias circuit adds or subtracts current or voltage to an input signal for the amplifier chain (e.g., at a base or gate of a transistor), thereby changing the input signal to offset non-linearities (e.g., compression) that may occur in the transistor. While there are current-bias circuits, most such circuits suffer from an inability to consider temperature in the bias signal. That is, a current-bias circuit may not be aware of instantaneous temperature swings in the transistors of the power amplifier and may notcorrect for temperature induced non-linearities. More recently, the assignee of the present disclosure has introduced voltage-bias circuits that do have the ability to consider temperature, but the configuration of such voltage-bias circuits requires battery voltages that are no longer commercially practical.

[0029] Figure 1A illustrates such a conventional voltage-bias circuit 100 to assist in understanding where the voltage demands are generated and why relatively high voltage demands leave no headroom when using contemporary battery levels. The bias circuit 100 includes a battery 102 providing a battery voltage (i.e., Vbatt). There is a first voltage drop across a transistor 104 (i.e., VDS (voltage from drain to source)) and a second voltage drop across a bias resistor (Rbias) 106 (generally at least 300 millivolts). Further, there is another voltage drop in the bias stage 107 and, more specifically, across diodes 108, 110 (2*Vd). Typical diodes have a Vd of approximately 1.2-1.25 V, so 2*Vd may be approximately 2.4-2.5 V (and sometimes higher). The current through the diodes 108, 110 is dependent on temperature variation of the diodes 108, 110. Because the diodes 108, 110 are in the same die as the amplifying transistor 118, the diodes 108, 110 are tightly thermally coupled to the amplifying transistor 118 and changes in the temperature caused by power use of the amplifying transistor 118. Unlike the current bias circuits, this thermal coupling allows the bias circuit 100 to compensate for changes in temperature.

[0030] However, as noted, battery voltages (or sometimes an equivalent supply voltage) are becoming increasingly constrained (e.g., approximately 2.8 V). Some designers are now requesting even lower battery voltages, which, given the 2*Vd requirements, leaves no headroom for VDS and the voltage drop across Rbias to vary. The voltage at node 112 turns on an emitter-follower transistor 114 and a second bias resistor 116, which adds to an input signal for an amplifying transistor 118 at node 120. The node 120 couples to an input node 122 through a blocking capacitor 124. Thus, if the node 112 cannot vary, the voltage at the node 120 cannot vary and the bias for the amplifying transistor 118 is not able to compensate for all needed non-linearities of the amplifying transistor 118.

[0031] It should be appreciated that the bias stage 107 need not be two diodes (more (or fewer) may be present). Further, the diodes may be replaced by other devices, as seen in Figures IB- ID. Thus, a bias stage 107B, seen in Figure IB, may be formed from one or more diode-connected transistors 130(1)- 130(N). Still further, Figure 1C illustrates abias stage 107C that allows a fractional value for Vd may be formed by a resistance divider network 134 where the values of resistors 136, 138 may be chosen to divide the voltage drop between the collector and emitter of the transistor 140. A closed-loop bias stage 107D is illustrated in Figure ID. The closed-loop bias stage 107D includes transistors 150, 152, 154, where the transistor 152 is diode connected. Transistor 154 mirrors the transistor 152 and feeds back to the transistor 150. Regardless of the structure used in the bias stage, there is a voltage drop that will consume some portion of the supply voltage. If the bias stage is formed inside a gallium arsenide (GaAs) die, this voltage drop for the bias stage may be in excess of two volts and leave little headroom.

[0032] Exemplary aspects of the present disclosure allow for operation at lower supply voltages by using an active feedback amplifier that synthesizes an equivalent series resistance without having a physical resistance in series with the voltage headroom budget. There are several ways in which the feedback amplifier may be implemented. The feedback amplifier may be a voltage amplifier, a transconductance amplifier, or even a current amplifier. While a physical resistance may be present in the structure of the feedback amplifier, this resistance is not in series with the bias path. Thus, the arrangement avoids the need for a relatively large supply voltage (e.g., Vbatt) for the circuit to operate. The feedback amplifier that synthesizes the bias resistor can be implemented in bulk complementary metal oxide semiconductor (CMOS), silicon on insulator (SOI) CMOS, other MOS processes, or bipolar processes (e.g., silicon germanium (SiGe) BiCMOS) or the like.

[0033] Figure 2 illustrates a bias circuit 200 that has an exemplary active feedback voltage bias that synthesizes the equivalent resistance 202. More specifically, a supply voltage source 204, which may be Vbatt, provides a supply voltage to a transistor 206, which may be a P-type field effect transistor (FET) analogous to transistor 104 of Figure 1A. However, instead of resistor 106, a feedback amplifier 208 and resistor 210 synthesize the equivalent resistance 202. The feedback amplifier 208 is also coupled to a reference voltage source 212 that provides a reference voltage (e.g., Vbg).

[0034] As noted, shifting the resistor out of the series path allows a desired headroom budget. However, to achieve a desired temperature coefficient based on the amplifier die, a current component based on the voltage drop of the bias is needed. As shown in Figure 2, the current Ir through the resistor 210 is:

[0035] The current Ibias through the diodes 108, 110 may be defined as:

[0036] Where the negative second term indicates a positive temperature coefficient. A negative temperature coefficient is also possible as discussed in greater detail below.

[0037] More generally, the bias circuit 200 may be represented as shown by bias circuit 300 in Figure 3. The bias circuit 300 couples to an amplifier 302 (also referred to as a power cell in Figure 3) through a bias stage 304. The bias stage 304 can be any of the bias stages 107, 107B-107D, or the like. The resistor 210 couples the node 112 to a shared node 306 that provides the basis for a first feedback loop 308, which may keep the node 306 at a fixed voltage and a second feedback loop 310, which provides the synthesized resistance for the bias. The first feedback loop 308, may be a voltage feedback loop (series-output feedback) and the second feedback loop 310, may be a current feedback loop (shunt output feedback). Other combinations are possible and within the scope of the present disclosure.

[0038] The resistor 210 remains coupled with the node 112 having a potential equal to the voltage drop across the bias stage 304 (e.g., N*Vd). The first feedback loop 308 keeps the left side of the resistor 210 at a voltage that is independent of temperature (e.g., using a bandgap voltage or the like). The second feedback loop 310 is the loop that, with the resistor 210, provides the equivalent bias resistance without having the physical resistance in series with the bias path. While shown as being independent, the loops 308, 310 could be nested (i.e., having a common branch).

[0039] Figure 4 provides some additional details about this possible implementation. Specifically, the bias circuit 200 shows additional elements of the feedback loops 308, 310. More specifically, the second feedback loop 310 where the node 306 couples to a first transistor 400, which may be a P-type FET (PFET) to a variable PFET 402 (analogous to FET 206, and which may be controlled by a digital to analog converter (DAC) and thus may be referred to as Mdac). As noted, this creates the shunt resistance such that the equivalent resistance is equal to the shunt feedback resistance divided by the loop gain (Req = R / Loop gain). The transistors 400, 402 act as a current mirror with a multiplication factor M, which, as noted can be set with a DAC. Reflecting on the equation for Ibias set forth above, there is a positive temperature coefficient for Ibias. The M+l factor allows for digital control of the positive temperature coefficient and can,with proper sizing of M be proportional to absolute temperature (PTAT), super-PTAT (x*PTAT) or sub-PTAT (PTAT / x).

[0040] For the first feedback loop 308, the node 306 is also coupled to a positive input of an operational amplifier 404. A negative input of the op-amp 404 may be coupled to a reference voltage (Vref), which may be a bandgap (Vbg) voltage source. The node 306 is also coupled to a variable current source 406, which may also be controlled by a DAC. Other elements remain as previously described.

[0041] There may be situations where a negative temperature coefficient is desired. Appropriate use of switches may allow such possibilities. In this regard, Figure 5 illustrates the bias circuit 200 with switching network 500 therein. More specifically, the switching network 500 may include a first portion 500A having switch 502, which connects the negative input of the op-amp 404 to either a reference voltage (e.g., Vbg) in a positive PTAT mode or to the node 112 in a negative PTAT (NT AT) mode. The switching network 500 further includes a second portion 500B, with switches 504, 506, and 508.

[0042] In the NTAT mode, the switches 504 and 508 are closed such that the node 510 adjacent the resistor 210 is coupled to ground in parallel with the current source 406. The predominant feedback is negative since the impedance of the two series diodes 108, 110 is many orders of magnitude smaller than the resistor 210. Switch 506 is open in this mode. The bias through the diodes 108, 110 becomes Ibias = M*(Idac+ 2Vd / R) and thus gets a negative temperature coefficient from the 2Vd / R term.

[0043] Conversely in PTAT mode, the switch 508 is open and switches 504, 506 are closed. The math for this situation is explained above.

[0044] When the switch 504 is open and switch 506 is closed, the bias circuit 200 may operate as a standard current-bias circuit similar to current-bias circuit 100. The DAC associated with the transistor 402 may set M to be two (2) and Vref may be set to be 2*Vd, thereby keeping the good accuracy for mirroring gain. This approach may be appropriate if the mode of operation (e.g., 2G versus 5G) has different requirements.

[0045] In the figures above, simple current mirrors have been used. This approach may result in relatively small output impedances and thus may be vulnerable to large errors. Cascode current mirrors (not shown) may be used to achieve larger output impedances and thus higher accuracy transfer functions. Note also that there may be other ways to implement the feedback amplifier using different amplifier configurations. Thepower supply rejection of the circuit may be used to consider whether a particular configuration is appropriate (e.g., noisy environments may have a larger ripple and it may be desirable to have the bias current have little to no ripple).

[0046] Figures 6 and 7 provide alternate bias circuits that have cascoded current mirrors. In this regard, Figure 6 illustrates a bias circuit 600 with cascoded current mirrors 602, 604 replacing 400 / 406 and op-amp 404 respectively.

[0047] Relevantly, the Mdac current mirror has an accurate mirroring ratio over a wide range of Vbatt supply voltage values. If the Mdac varies with Vbatt, the synthesized impedance R / (M+1) also varies, resulting in offsets in the bias generator. In this regard, Figure 7 illustrates a bias circuit 700 that keeps the Mdac ratio approximately constant by matching the PFETs 702, 704 and adding a local feedback loop with an op-amp 706 that keeps the two Vds equal to ensure a good match.

[0048] There are many ways in which the bias circuit can be implemented using NFETs, PFETs, or complementary structures. Further, calibration and correction circuits (not shown) can be added to the circuit. Ensuring a relatively orthogonal current level and temperature coefficient setting may also require adding other analog blocks to the bias generator.

[0049] Note that while it is possible to keep a single value for the temperature coefficient for the entire operating temperature range using the present disclosure, it is also possible to have a piecewise linear function where the temperature coefficient changes based on operating temperature. One possible way to implement this is the use of a power amplifier temperature sensor (not shown) that generates a signal that controls the bias temperature coefficient in digital or analog fashion (e.g., changing switching configuration or changing the value of M). Alternatively, multiple bias circuits with different temperature coefficients may be summed or subtracted to get a desired temperature coefficient.

[0050] The bias circuits for power amplifiers according to aspects disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch,a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0051] Figure 8 is a schematic diagram of an exemplary communication device 800 wherein the bias circuits can be provided. Herein, the communication device 800 can be any type of communication device, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications.

[0052] More particularly, the communication device 800 will generally include a control system 802, a baseband processor 804, transmit circuitry 806, receive circuitry 808, antenna switching circuitry 810, multiple antennas 812, and user interface circuitry 814. In a non-limiting example, the control system 802 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 802 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 808 receives radio frequency signals via the antennas 812 and through the antenna switching circuitry 810 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 808 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog- to-digital converter(s) (ADC).

[0053] The baseband processor 804 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 804 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0054] For transmission, the baseband processor 804 receives digitized data, which may represent voice, data, or control information, from the control system 802, which it encodes for transmission. The encoded data is output to the transmit circuitry 806, wherea digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier that may be biased using bias circuits of the present disclosure will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 812 through the antenna switching circuitry 810 to the antennas 812. The multiple antennas 812 and the replicated transmit and receive circuitries 806, 808 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0055] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0056] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMS received by the International Bureau on 09 December 2025 (09.12.2025)What is claimed is:

1. (Cunently Amended) An amplifier chain comprising: an amplifier transistor; a bias stage coupled to a base of the amplifier transistor, wherein the amplifier transistor comprises a bipolar junction transistor, BIT, the bias stage comprising a bias voltage drop; and a bias circuit comprising: a virtual synthesized resistance in series with the bias voltage drop while keeping an actual series resistance out of a series path with the bias voltage drop; and a cunent feedback loop comprising a current minor to provide a loop gain to a bias signal passing through the series path.

2. (Original) The amplifier chain of claim 1, wherein the cunent minor comprises a field effect transistor, FET.

3. Canceled.

4. (Original) The amplifier chain of claim 1, wherein the cunent feedback loop comprises a resistor coupled to a first node in the series path and a second node outside the series path.

5. (Original) The amplifier chain of claim 4, further comprising a voltage feedback loop, the voltage feedback loop coupled to the second node.

6. (Original) The amplifier chain of claim 5, wherein the voltage feedback loop is configured to keep the second node at a fixed voltage.

7. (Original) The amplifier chain of claim 5, wherein the voltage feedback loop comprises an operational amplifier coupled to a reference voltage.

8. (Original) The amplifier chain of claim 4, further comprising a variable current source coupled to the second node.

9. (Original) The amplifier chain of claim 8, wherein the variable cunent source is configured to be controlled by a digital-to-analog converter, DAC.

10. (Original) The amplifier chain of claim 4, further comprising a switching network associated with the resistor.

11. (Original) The amplifier chain of claim 10, wherein the switching network comprises a first switch between the resistor and the series path.

12. (Original) The amplifier chain of claim 10, wherein the switching network comprises a second switch between the resistor and ground.

13. (Original) The amplifier chain of claim 10, wherein the switching network is configured to switch operation of the bias circuit between a positive temperature coefficient and a negative temperature coefficient.

14. (Original) The amplifier chain of claim 1, wherein the loop gain is configured to be adjusted by a digital-to-analog converter, DAC, associated with a field effect transistor, FET, in the cunent minor.

15. (Currently Amended) A wireless communication device comprising: a baseband processor, BBP; and a front-end module coupled to the BBP comprising an amplifier chain comprising: an amplifier transistor; a bias stage coupled to a base of the amplifier transistor, wherein the amplifier transistor comprises a bipolar junction transistor, BIT, the bias stage comprising a bias voltage drop; anda bias circuit comprising: a virtual synthesized resistance in series with the bias voltage dropAwhile keeping an actual series resistance out of a series path with the bias voltage drop; and a cunent feedback loop comprising a cunent minor to provide a loop gain to a bias signal passing through the series path.

16. (Original) The wireless communication device of claim 15, wherein the current minor comprises a field effect transistor, FET.

17. Canceled.

18. (Original) The wireless communication device of claim 15, wherein the current feedback loop comprises a resistor coupled to a first node in the series path and a second node outside the series path.

19. (Original) The wireless communication device of claim 18, further comprising a voltage feedback loop, the voltage feedback loop coupled to the second node.

20. (Original) The wireless communication device of claim 19, wherein the voltage feedback loop is configured to keep the second node at a fixed voltage.STATEMENT UNDER ARTICLE 19 (1)Claims 1 and 15 are amended.Claims 3 and 17 are canceled.Support for the amendments to claims 1 and 15 can be found in claims 3 and 17, as well asFigure 3.The remaining claims are unchanged.

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