Chip design processing method and apparatus

Abstract

Disclosed in the present application are a chip design processing method and apparatus. The method comprises: verifying the metal density of a top layer of a chip, so as to make the metal density fall within the range of a first density threshold value to a second density threshold value, wherein the first density threshold value is less than the second density threshold value; and using a polysilicon cap layer for blocking, such that the preset range around a through-silicon via (TSV) is a keep-out zone.

Description

A chip design processing method and device TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, integrated circuit technology, and in particular to a chip design processing method and device. BACKGROUND

[0002] The goal of improving the bonding yield of three-dimensional integrated circuits (3D ICs) is to improve the reliability of bonding during manufacturing and assembly processes, thereby increasing the quality and performance of the products. Bonding refers to the process of securely connecting two or more components (usually chips, devices, or other electronic elements) together through a connection method. The purpose of this connection is to establish an electrical connection so that signals, currents, or power can flow between these components. Bonding usually involves connecting conductive materials (such as metal wires) to the connection points (usually metal pins or other connection structures) of electronic devices. This process requires a high degree of precision and reliability, as it directly affects the performance and reliability of electronic equipment.

[0003] Warpage refers to the degree of curvature or bending of the surface of a wafer. During the manufacturing process, wafers may be affected by various factors such as temperature, mechanical stress, etc., causing the wafer surface to bend. 3D IC technology involves vertically stacking chips between different layers, usually connected together through bonding technology. Therefore, the warpage of the wafer directly affects the quality and success rate of bonding, that is, in 3D IC manufacturing, the warpage of the wafer is crucial to the bonding process.

[0004] If the warpage of the wafer is too large, it may cause difficulty in achieving good contact and connection during the bonding process. Inhomogeneous warpage can also cause uneven gaps between stacked layers, affecting electrical performance and reliability.

[0005] How to minimize the impact of warpage on bonding and improve the bonding yield of 3D ICs is a technical problem that needs to be solved.

[0006] SUMMARY

[0007] The present application provides a chip design processing method and device, which can solve any of the above technical problems.

[0008] The present application provides a chip design processing method, comprising:

[0009] checking the metal density of the top layer of the chip so that the metal density is within the range of a first density threshold and a second density threshold, wherein the first density threshold is less than the second density threshold; and,

[0010] The polysilicon cover layer is used to block the TSV peripheral preset range to be a clearance area.

[0011] In an exemplary embodiment, the metal density of the top layer of the chip is checked, including:

[0012] A check window is defined and the metal density requirement that the check window needs to meet is defined.

[0013] The metal density of the top layer of the chip is checked according to the check window, so that the metal density is within the range of the first density threshold and the second density threshold of the metal density requirement; and the metal density of the top layer of the chip is checked using a place and route (PR) tool.

[0014] In an exemplary embodiment, the physical layout information of the chip is obtained and the checking of the metal density is performed by a design rule check (DRC) rule.

[0015] In an exemplary embodiment, the polysilicon cover layer is used to block the TSV peripheral preset range to be a clearance area, including:

[0016] During the TSV design, the polysilicon cover layer (Poly OD) is added according to a preset rule within the TSV peripheral preset range.

[0017] In an exemplary embodiment, the method further includes:

[0018] After the physical layout information of the chip is obtained, the TSV layer and the distance between the TSV layer and each layer in the chip design defined in the DRC rule are used to pass the DRC rule check so that the TSV peripheral preset range is a clearance area.

[0019] In an exemplary embodiment, the passing of the DRC rule check so that the TSV peripheral preset range is a clearance area can include:

[0020] When the TSV is selected to fall on a first metal layer, the distance between the TSV and each layer of the Poly OD is kept greater than or equal to the distance between the TSV layer and each layer of the Poly OD defined in the DRC rule.

[0021] When the TSV is selected to fall on an Nth metal layer, the first metal layer to the (N-1)th metal layer is further included to be not placed within the TSV peripheral preset range.

[0022] In an exemplary embodiment, the method further includes:

[0023] The HB is used as a bonding standard, and an HB bonding alignment mark is performed to ensure that the bonding of different wafers occurs at the correct position.

[0024] The embodiment of the present application further provides a computer readable storage medium storing computer executable instructions for executing the chip design processing method.

[0025] The embodiment of the present application further provides a chip design processing device, comprising a first processing module and a second processing module.

[0026] The first processing module is configured to check the metal density of the top layer of the chip so that the metal density is within a range of a first density threshold and a second density threshold, wherein the first density threshold is smaller than the second density threshold.

[0027] The second processing module is configured to use a polysilicon cover layer to block so that a preset range of the periphery of the TSV is a clearance area.

[0028] In an exemplary example, the third processing module is further configured to use the HB as a bonding standard to perform HB bonding alignment marking to ensure that the bonding of different wafers occurs at the correct position.

[0029] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be learned from the practice of the present application. The objectives and other advantages of the present application can be achieved and obtained by the structure particularly pointed out in the description, claims and drawings.

[0030] SUMMARY

[0031] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0032] Fig. 1 is a flow diagram of the chip design processing method according to the embodiment of the present application;

[0033] Fig. 2 is a schematic diagram of the composition structure of the chip design processing device according to the embodiment of the present application.

[0034] DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in any way without conflict.

[0036] For the purposes of promoting an understanding of the principles of the application, reference will now be made to the embodiments illustrated in the drawings. It is expressly understood that the drawings are for illustration purposes only and are not a limitation on the scope of the application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0038] To meet the requirements of 3D IC bonding factory, back-end design needs to consider multiple factors, including process, automation, quality control and scalability. To meet the requirements of 3D IC bonding factory in the design of the back-end, the embodiments of the application provide a chip design processing method, which can maximize the requirements of 3D IC bonding factory in the design of the back-end to minimize the impact of warpage on bonding, thereby improving the 3D IC bonding yield.

[0039] FIG. 1 is a chip design processing method according to an embodiment of the application. As shown in FIG. 1, the method can include:

[0040] Step 100: Check the metal density of the chip top layer to make the metal density within the range of a first density threshold and a second density threshold, wherein the first density threshold is less than the second density threshold.

[0041] In the embodiments of the application, when designing a chip, a back-end engineer needs to consider the layout optimization of the chip top, which includes checking the metal density to make the metal density within the range of a first density threshold and a second density threshold. The metal density refers to the distribution density of metal between electrical elements and electrical connection lines in the metal layer of the chip top. In this way, when designing a chip, the back-end engineer checks the chip top metal density when optimizing the layout of the chip top design, which effectively avoids the problem of repeated iteration in the later inspection process.

[0042] In an exemplary example, the metal density of the chip top layer can be checked using a place and route (PR) tool. The PR tool is a software tool for chip layout and routing. Through the PR tool, the back-end engineer can check the metal density of the chip top layer to ensure that the metal is evenly distributed and meets the design specifications, so that the metal density of the chip top layer is within the range of the first density threshold and the second density threshold.

[0043] In one example, the density verification is performed according to the physical layout information of the chip and by the Design Rule Check (DRC) rules. In one embodiment, the physical layout information of the chip can be obtained by exporting the Graphic Data System (GDS) file of the top metal layer of the chip. The GDS file is a standard chip design file format, which contains the physical layout information of the chip, including detailed metal patterns and layout information, which can be used to calculate the coverage of the metal in each region, and thus the metal density. In this embodiment, the back-end engineers can export the GDS file of the top metal layer of the chip, and then use the DRC tool to verify the metal density. By using the DRC tool, the design rules can be applied to check whether the layout of the metal meets the requirements, including density limits, spacing, line width, etc.

[0044] In one embodiment, the metal layer is first defined to specify the metal layer to be checked, the check window, and the metal density requirement to be met by the check window, i.e. the metal density in the check window is within the first density threshold and the second density threshold. The metal density of the top layer of the chip is checked according to the check window, so that the metal density is within the first density threshold and the second density threshold of the metal density requirement. Taking the check window of 200 μm x 200 μm, the first density threshold of 30%, and the second density threshold of 70% as an example, the check is performed on the wafer according to the check window of 200 μm x 200 μm each time. Assuming that the check is performed on the check window according to the step of 100 μm each time, through the check, it is ensured that the metal density of the metal layer in the check window of 200 μm x 200 μm is not less than the first density threshold of 30%, so as to avoid the wafer from being concave due to too little metal. At the same time, it is ensured that the metal density of the metal layer in the check window of 200 μm x 200 μm is not higher than the second density threshold of 70%, so as to avoid the wafer from being too high and convex, thereby keeping the wafer flat. Through step 100, the back-end engineers have evaluated the distribution density of the metal in each 200 μm x 200 μm region on the wafer, and ensured that the metal density of the metal layer therein is not less than the first density threshold of 30% and not higher than the second density threshold of 70%, so that the metal density in different regions of the chip is uniform and meets the design specification.

[0045] Through step 100, the check of the metal density directly affecting the warping degree is added during the back-end design, which ensures that the warping degree of the wafer is not too large, and also ensures that the warping degree of the wafer is uniform.

[0046] Step 101: Using the polysilicon cover layer blockage to make the TSV peripheral preset range be a clearance area.

[0047] In the embodiment of the present application, when designing a chip, a back-end engineer needs to consider that the TSV peripheral preset range is a clearance area, that is, there is no polysilicon cover layer (Poly OD, Poly Over Diffusion) and required metal layer in the TSV peripheral preset range. The through-silicon via (TSV) is a vertical connection technology that penetrates the silicon layer, and is usually used in 3D integrated circuits.

[0048] In one embodiment, when designing a TSV, Poly OD blockage is added in the TSV peripheral preset range according to a pre-set rule to prevent dummy fill or other elements from being placed around the TSV, thereby creating a clearance area around the TSV. In the embodiment, the rule of adding Poly OD blockage in the TSV peripheral preset range set in the pre-set rule ensures that there is enough clearance area in the TSV peripheral preset range. By adding blockage around the TSV according to the pre-set rule, dummy fill is effectively prevented from entering the TSV peripheral preset range area.

[0049] Through step 101, it is ensured that the logic IMD film penetrated by the TSV does not contain metal elements, so that there is no problem with wafer perforation during bonding, thereby ensuring that the packaging after bonding can be performed normally.

[0050] It should be noted that the execution order of step 100 and step 101 has no specific sequence, that is, step 100 can be executed first and then step 101 can be executed, or step 101 can be executed first and then step 100 can be executed.

[0051] The chip design processing method provided by the embodiments of the present application, on the one hand, in the back-end design of the chip design, by limiting the metal density of the top layer of the chip within the range of the first density threshold value and the second density threshold value, the wafer is prevented from being concave, and the wafer is also prevented from being too high and convex upward, so that the flatness of the wafer is maintained, so that the warpage of the wafer is ensured not to be too large, and the warpage of the wafer is ensured to be uniform; on the other hand, in the back-end design of the chip design, the polysilicon cover layer is used to block, so that the preset range around the TSV is a clearance area, so that there is no any Poly OD and required metal layer in the preset range around the TSV, and the dummy fill is effectively prevented from entering the preset range area around the TSV. Through the chip design processing method provided by the embodiments of the present application, the influence of the warpage on the bonding is maximally reduced, and the 3D IC bonding yield is improved.

[0052] In an exemplary instance, for some metal parts with higher permissions, such as metal lines, such as power and ground stripes, there may be no blocking and being placed around the TSV. In order to avoid the high permission metal being placed in the preset range around the TSV, the chip design processing method provided by the embodiments of the present application can further include:

[0053] After obtaining the physical layout information of the chip, such as after generating the GDS file, the TSV layer and the distance between the TSV layer and each layer in the chip design are further defined in the DRC rule, so that the preset range around the TSV is a clearance area through the DRC rule check.

[0054] In an embodiment, the preset range around the TSV is a clearance area through the DRC rule check, which can include:

[0055] When the TSV is selected to fall on the first metal layer, the distance between the TSV and each layer of the Poly OD is kept greater than or equal to the distance between the TSV layer and each layer of the Poly OD defined in the DRC rule, such as 0.46 μm, so that there is no Poly OD in the preset range around the TSV. The each layer of the Poly OD includes an OD injection layer and a dummy fill of the OD.

[0056] In an embodiment, the dummy fill of the OD can also be divided into various patterns, and the dummy fill in the same layer has different shapes in size and thickness, and some have twice illumination process. In order to identify different illuminations, a process manufacturer adopts a pattern for the first illumination, and another pattern for the second illumination.

[0057] Similarly, when the selected TSV falls in the Nth metal layer, in addition to ensuring that there is no Poly OD within the preset range around the TSV, it is also necessary to ensure that the first metal layer to the (N-1)th metal layer is not placed within the preset range around the TSV, and thus, for all patterns of different word illumination, the space needs to be kept as 0.46, taking the pattern of dummy fill of OD as an example.

[0058] In an exemplary instance, the processing method for chip design provided in the embodiments of the present application still cannot completely avoid the warping degree of the wafer, and there will always be high and low positions, even if chemical mechanical polishing (CMP) is used, especially in the case of an aluminum (AL) metal layer as the top metal layer, since the AL metal is prone to deformation in the manufacturing process of the wafer, the processing method for chip design provided in the embodiments of the present application can further include:

[0059] A hybrid bonding (HB) technology is used as a bonding standard, and in the back-end design, HB bonding alignment marks are made to ensure that the bonding of different wafers occurs at the correct position. Hb bonding is the bonding of the entire wafer, and if one of the wafers has a high warping degree during production, there will be bonding deviation and failure, which affects the normal function of the chip. Since the HB is produced by first processing different wafers separately and then combining them, using HB as a bonding standard can ensure complete alignment and thus there is no need to worry about the problem of misalignment of two wafers due to the severe AL warping, thereby ensuring the bonding yield.

[0060] In the embodiments of the present application, in order to ensure the alignment of the bonding of two different wafers under the condition of warping, HB layers are used as the process alignment marks for bonding, and the alignment of the HB layers during bonding reduces the error.

[0061] The embodiments of the present application also provide a computer-readable storage medium storing computer-executable instructions for executing the processing method for chip design of any of the above.

[0062] The embodiments of the present application further provide a computer device including a memory and a processor, wherein the memory stores instructions executable by the processor, and the instructions are used to execute the steps of the processing method for chip design of any of the above.

[0063] FIG. 2 is a schematic diagram of the composition structure of the processing device for chip design in the embodiments of the present application, as shown in FIG. 2, which can include a first processing module and a second processing module; wherein,

[0064] The first processing module is configured to check the metal density of the top layer of the chip so that the metal density is within a range of a first density threshold and a second density threshold, where the first density threshold is less than the second density threshold.

[0065] The second processing module is configured to use a polysilicon cover layer to block so that a preset range around the TSV is a clearance area.

[0066] The processing device for chip design provided by the embodiments of the present application, on one hand, in the back-end design of the chip design, by limiting the metal density of the top layer of the chip within a range of a first density threshold and a second density threshold, avoids the wafer from being concave, and also avoids the wafer from being too high and convex upward, thereby keeping the wafer flat, so that the warpage of the wafer is guaranteed not to be too large, and the warpage of the wafer is guaranteed to be uniform; on the other hand, in the back-end design of the chip design, using a polysilicon cover layer to block so that a preset range around the TSV is a clearance area, so that there is no any Poly OD and required metal layer in the preset range around the TSV, effectively preventing the dummy fill from entering the preset range around the TSV. Through the processing device for chip design provided by the embodiments of the present application, the influence of the warpage on the bonding is maximally reduced, and the 3D IC bonding yield is improved.

[0067] In an exemplary instance, the first processing module can be further configured to:

[0068] After the GDS file is generated, the TSV layer and the space between the TSV layer and each layer in the chip design are further defined in the DRC rule, so that the preset range around the TSV is a clearance area through the check of the DRC rule. In this way, some metal parts with relatively high permissions are avoided from being placed in the preset range around the TSV.

[0069] In an exemplary instance, a third processing module can be further included, configured to use HB as a bonding standard to perform HB bonding alignment marking to ensure that the bonding occurs at the correct position. In this way, the problem of the warpage of the wafer that cannot be completely avoided due to the deformation of the AL metal in the wafer manufacturing process is avoided, especially for the case that the top metal layer is an AL metal layer.

[0070] Although the present application has been described with reference to the above embodiments, the contents described are merely employed embodiments for facilitating the understanding of the present application, and are not intended to limit the present application. Any modification and change in the form and details can be made by any person skilled in the art without departing from the spirit and scope of the present application, and the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A processing method of chip design, comprising: checking metal density of a top layer of a chip so that the metal density is within a range of a first density threshold and a second density threshold, wherein the first density threshold is less than the second density threshold; and using a polysilicon overlay barrier to make a preset range of a through silicon via (TSV) periphery an empty area.

2. The treatment method of claim 1, wherein, The checking of the metal density of the top layer of the chip comprises: defining a checking window and a metal density requirement that the checking window needs to meet; checking the metal density of the top layer of the chip according to the checking window so that the metal density is within the range of the first density threshold and the second density threshold of the metal density requirement; and 3. The treatment method of claim 2, wherein, checking the metal density of the top layer of the chip using a place and route (PR) tool.

4. The treatment method of claim 1, wherein, The checking of the metal density of the top layer of the chip is performed by obtaining physical layout information of the chip and checking the metal density by a design rule checking (DRC) rule. The using of the polysilicon overlay barrier to make the preset range of the TSV periphery an empty area comprises: when the TSV is designed, adding a polysilicon overlay (Poly OD) barrier in the preset range of the TSV periphery according to a preset rule. 5.The processing method of claim 1, further comprising:

6. The treatment method of claim 5, wherein, after obtaining the physical layout information of the chip, making the preset range of the TSV periphery an empty area by checking a TSV layer and a distance between the TSV layer and each layer in the chip design defined in the DRC rule. The making of the preset range of the TSV periphery an empty area by checking the DRC rule can comprise: when the TSV falls on a first metal layer, keeping a distance between the TSV and each layer of the Poly OD greater than or equal to a distance between the TSV layer and each layer of the Poly OD defined in the DRC rule; when the TSV falls on an Nth metal layer, further comprising making the first metal layer to an (N-1) th metal layer not be placed in the preset range of the TSV periphery. 7.The processing method of claim 1 or 5, further comprising: using HB as a bonding standard to perform HB bonding alignment marking to ensure that bonding of different wafers occurs at a correct position. 8.A computer readable storage medium storing computer executable instructions for performing the processing method of chip design of any one of claims 1-7.

9. A processing device for chip design, comprising: a first processing module and a second processing module; wherein the first processing module is configured to check metal density of a top layer of a chip so that the metal density is within a range of a first density threshold and a second density threshold, wherein the first density threshold is less than the second density threshold; and the second processing module is configured to use a polysilicon overlay barrier to make a preset range of a through silicon via (TSV) periphery an empty area. 10.The processing apparatus of claim 9, further comprising a third processing module configured to use HB as a bonding standard to perform HB bonding alignment marking to ensure that bonding of different wafers occurs at a correct position.

Images