Light-emitting unit and manufacturing method therefor, and light-emitting diode chip

Abstract

A light-emitting unit and a manufacturing method therefor, and a light-emitting diode chip. The light-emitting unit comprises a plurality of sub-light-emitting units (SP); at least one of the plurality of sub-light-emitting units (SP) comprises an epitaxial layer (EPI) and at least one first electrode (F1); the epitaxial layer (EPI) is arranged on a base substrate (BS), and comprises a first semiconductor layer (S1), a light-emitting layer (E) and a second semiconductor layer (S2) which are sequentially arranged in a direction away from the base substrate (BS); one of the first semiconductor layer (S1) and the second semiconductor layer (S2) is a P-type semiconductor layer, and the other is an N-type semiconductor layer; the first electrode (F1) is arranged on the side of the epitaxial layer (EPI) away from the base substrate (BS) and is electrically connected to the second semiconductor layer (S2); and the at least one first electrode (F1) is dot-shaped. The light-emitting unit has higher reliability and can be used in high-voltage light-emitting devices.

Description

Light emitting unit and preparation method, light emitting diode chip TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a light emitting unit and preparation method, and a light emitting diode chip. BACKGROUND

[0002] Light Emitting Diode (LED) has many advantages such as small volume, low energy consumption, firm structure, strong impact and shock resistance, long service life, and has become an important light source technology in the display field. Under the demand of large-size backlight such as television and spliced screen, the difference in cost between LED and OELD has become the key to their competition. How to improve the reliability of LED and reduce the preparation cost of LED is a problem that technicians in the field are constantly researching.

[0003] SUMMARY

[0004] At least one embodiment of the present disclosure provides a light emitting unit, which comprises a plurality of sub-light emitting units, wherein at least one of the plurality of sub-light emitting units comprises an epitaxial layer and at least one first electrode; the epitaxial layer is arranged on a substrate, and comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer arranged in sequence in a direction away from the substrate, wherein one of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer; at least one first electrode is arranged on a side of the epitaxial layer away from the substrate and is electrically connected with the second semiconductor layer, wherein the at least one first electrode is in a dot shape.

[0005] For example, in the light emitting unit provided by at least one embodiment of the present disclosure, the first semiconductor layer comprises a first part overlapping the light emitting layer in a direction perpendicular to the substrate and a second part not overlapping the light emitting layer in the direction perpendicular to the substrate, and at least one sub-light emitting unit of the plurality of light emitting units further comprises: at least one second electrode arranged on a side of the second part away from the substrate and electrically connected with the second part, wherein the at least one second electrode is in a dot shape.

[0006] For example, in the light emitting unit provided by at least one embodiment of the present disclosure, the plurality of sub-light emitting units comprise adjacent first sub-light emitting units and second sub-light emitting units, and the first electrode of the first sub-light emitting unit is electrically connected with the second electrode of the second sub-light emitting unit.

[0007] For example, in the light emitting unit provided by at least one embodiment of the present disclosure, the aspect ratio of the dot shape is less than 2.

[0008] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the point shape includes a circle, a ring, or a regular polygon.

[0009] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the epitaxial layer further includes a third semiconductor layer disposed on a side of the first semiconductor layer close to the substrate, and the third semiconductor layer is an undoped semiconductor layer.

[0010] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, at least one sub-light emitting unit of the plurality of light emitting units further includes a current blocking layer disposed on a side of the second semiconductor layer away from the substrate, and a current spreading layer disposed on a side of the current blocking layer away from the substrate, and the at least one first electrode is disposed on a side of the current spreading layer away from the substrate.

[0011] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, at least one sub-light emitting unit of the plurality of light emitting units further includes a first connecting electrode disposed on a side of the at least one first electrode away from the substrate, and electrically connected to the at least one first electrode through at least one first via.

[0012] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, at least one sub-light emitting unit of the plurality of light emitting units further includes a second connecting electrode disposed on a side of the at least one second electrode away from the substrate, and electrically connected to the at least one second electrode through at least one second via, and the first connecting electrode and the second connecting electrode are disposed in the same layer.

[0013] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, in the at least one sub-light emitting unit, the total number N of the at least one first via and the at least one second via is 2-10.

[0014] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the at least one first via and the at least one second via include a first sub-via having a first projection area and a second sub-via having a second projection area, the area of the orthographic projection of the first sub-via on the substrate is less than the area of the orthographic projection of the second sub-via on the substrate, the number of the first sub-via is N1, the number of the second sub-via is N2, N1≥N2, and N1+N2=N.

[0015] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the at least one second via includes the second sub-via, and the at least one first via includes the first sub-via.

[0016] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the at least one first via hole and the at least one second via hole are arranged in a linear, triangular, cross or ring shape.

[0017] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, at least one sub light emitting unit of the plurality of light emitting units further comprises a first protective layer and a second protective layer; the first protective layer is arranged at least on the sidewall of the epitaxial layer, and the second protective layer is arranged at least on the side of the first protective layer away from the epitaxial layer; wherein the orthographic projection of the first protective layer and the second protective layer on the substrate is at least partially overlapped with the orthographic projection of the sidewall of the epitaxial layer on the substrate.

[0018] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the first via hole and the second via hole penetrate the first protective layer and the second protective layer.

[0019] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the at least one first electrode comprises a first bottom surface close to the substrate and a first side surface connected to the first bottom surface, and a first included angle formed by the first bottom surface and the first side surface is 40-50°.

[0020] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the at least one second electrode comprises a second bottom surface close to the substrate and a second side surface connected to the second bottom surface, and a second included angle formed by the second bottom surface and the second side surface is 40-50°.

[0021] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, at least one sub light emitting unit of the plurality of light emitting units further comprises: a first reflective layer, which is arranged at least between adjacent first electrodes and second electrodes, and comprises first reflective sub-layers and second reflective sub-layers arranged alternately in a direction away from the substrate, wherein the materials of the first reflective sub-layers and the second reflective sub-layers are different.

[0022] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the array substrate further comprises: a second reflective layer, which is arranged on the side of the substrate away from the epitaxial layer, and comprises third reflective sub-layers and fourth reflective sub-layers arranged alternately in a direction away from the epitaxial layer, wherein the materials of the third reflective sub-layers and the fourth reflective sub-layers are different, and the total number of layers of the third reflective sub-layers and the fourth reflective sub-layers is 10-70.

[0023] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the light emitting unit comprises a plurality of sub light emitting units and a non-electric region arranged between adjacent sub light emitting units, and the non-electric region is insulated from the plurality of sub light emitting units.

[0024] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, at least one of the plurality of light emitting units further comprises: a first contact pad and a second contact pad; the first insulating layer is arranged on a side of the first connecting electrode and the second connecting electrode away from the substrate, and comprises a third via hole exposing the first connecting electrode and a fourth via hole exposing the second connecting electrode, the first contact pad is electrically connected to the first connecting electrode through the third via hole, and the second contact pad is electrically connected to the first connecting electrode through the fourth via hole.

[0025] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the shape or area of the orthographic projection of the first contact pad on the substrate is different from that of the orthographic projection of the second contact pad on the substrate; the area of the orthographic projection of the second contact pad on the substrate is smaller than that of the orthographic projection of the first contact pad on the substrate, or the orthographic projection of the second contact pad on the substrate has a notch.

[0026] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the plurality of light emitting units are arranged in multiple rows and multiple columns, the first contact pad and the second contact pad extend along the column direction and overlap with at least two of the at least one first electrode and the at least one second electrode in a direction perpendicular to the substrate.

[0027] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the plurality of first electrodes and the plurality of second electrodes included in two adjacent columns of light emitting units are collectively center-symmetric.

[0028] For example, in the light emitting unit provided by at least one of the embodiments of the present disclosure, the planar shapes of the third via hole and the fourth via hole are respectively elliptical.

[0029] At least one of the embodiments of the present disclosure further provides a preparation method of a light emitting unit, the preparation method comprising: forming a plurality of light emitting units on a substrate, wherein at least one of the plurality of light emitting units comprises an epitaxial layer and at least one first electrode; the epitaxial layer is formed on the substrate and comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer arranged in sequence away from the substrate, wherein one of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer; the at least one first electrode is formed on a side of the epitaxial layer away from the substrate and is electrically connected to the second semiconductor layer, wherein the at least one first electrode is in a dot shape.

[0030] At least one of the embodiments of the present disclosure further provides a light emitting diode chip, which comprises a plurality of light emitting units provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0032] FIGS. 1A-1F are schematic plan views of light emitting diodes including different numbers of unit cells;

[0033] FIG. 2 is a schematic cross-sectional view of a light emitting unit according to at least one embodiment of the present disclosure;

[0034] FIG. 3 is a schematic view of a film layer of the light emitting unit of FIG. 2;

[0035] FIG. 4A is a partial plan view scanning electron microscope (SEM) image of a plurality of unit cells in a light emitting unit according to at least one embodiment of the present disclosure;

[0036] FIG. 4B is a cross-sectional SEM image of a portion of the light emitting unit of FIG. 4A;

[0037] FIG. 5A is another partial plan view SEM image of a plurality of unit cells in a light emitting unit according to at least one embodiment of the present disclosure;

[0038] FIG. 5B is a cross-sectional SEM image of a portion of the light emitting unit of FIG. 5A;

[0039] FIGS. 6A-6D are SEM images of an epitaxial layer in a light emitting unit according to at least one embodiment of the present disclosure in different situations;

[0040] FIG. 7B is a partial plan view SEM image of a first electrode in a light emitting unit according to at least one embodiment of the present disclosure;

[0041] FIGS. 7A and 7C are schematic cross-sectional views of the portion of the first electrode of FIG. 7B circled by the dashed lines, respectively;

[0042] FIG. 8 is a schematic plan view of a light emitting unit according to at least one embodiment of the present disclosure;

[0043] FIG. 9 is a schematic cross-sectional view of a light emitting unit according to at least one embodiment of the present disclosure;

[0044] FIGS. 10-14 are schematic views of arrangements of first and second vias in a light emitting unit according to at least one embodiment of the present disclosure;

[0045] FIG. 15A is a schematic cross-sectional view of a first electrode in a light emitting unit according to at least one embodiment of the present disclosure;

[0046] FIG. 15B is a schematic cross-sectional view of a first electrode in a light emitting unit according to at least one embodiment of the present disclosure;

[0047] FIG. 16 is a schematic cross-sectional view of a first reflective layer in a light emitting unit according to at least one embodiment of the present disclosure;

[0048] FIG. 17 is a schematic cross-sectional view of a second reflective layer in a light emitting unit according to at least one embodiment of the present disclosure;

[0049] FIG. 18 is a schematic plan view of a first contact pad and a second contact pad in a light emitting unit according to at least one embodiment of the present disclosure;

[0050] FIG. 19 is a schematic plan view of a light emitting unit according to at least one embodiment of the present disclosure;

[0051] FIG. 20 is a schematic plan view of another light emitting unit according to at least one embodiment of the present disclosure; and

[0052] FIGS. 21A-21G are schematic cross-sectional views of a light emitting unit during fabrication according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] So that the purposes, technical solutions and superiorities of the embodiments of the present disclosure can be more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of the present disclosure.

[0054] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this present disclosure belongs. The terms “first”, “second”, and similar terms used in the present disclosure do not necessarily denote any order, quantity, or importance, but are used to distinguish different components. The terms “include”, “comprise”, and similar terms are intended to mean that the elements or objects listed after the terms encompass the elements or objects recited after the terms, and equivalents thereof, without excluding other elements or objects. The terms “connected” or “coupled” and similar terms are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and similar terms are used only to indicate relative positions when the absolute positions of the described objects are changed.

[0055] For optimizing light emitting diode (LED) products, such as medium-large size Mini LED products, structural optimization and cost reduction can be performed from the perspectives of circuit board (e.g., PCB) substrate design, optical design, and Mini LED chip design.

[0056] For example, in the design of Mini LED chips, by dividing the control of multiple LEDs into multiple zones, for example, by dividing multiple LEDs into multiple zones, and by simplifying a zone with multiple lights (LEDs) into a zone with one light, not only can the number of series connections of LEDs be reduced, but the wiring of the PCB substrate can also be further simplified. After simplifying a zone with multiple lights into a zone with one light, in order to achieve the required brightness of the product, a larger size area Mini LED chip needs to be used; at the same time, in order to reduce the use of LED current, solve the problem of LED current exceeding the specification in the low partition scheme, and make the driving current of the LED device smaller and closer to the best efficiency point, thereby improving the luminous efficiency of the LED device, a higher voltage 6V, 9V, 12V, 18V, 24V, etc. Polycell (cell) high-voltage Mini LED is often used.

[0057] For example, FIGS. 1A-1F show schematic diagrams of LEDs including different numbers of cells, FIG. 1A shows a case where the LED includes a single cell, at this time, the driving voltage of the LED is 3V; FIG. 1B shows a case where the LED includes two cells, at this time, the two cells are connected in series, and the driving voltage of the LED is 6V; FIG. 1C shows a case where the LED includes three cells, at this time, the three cells are connected in series, and the driving voltage of the LED is 9V; FIG. 1D shows a case where the LED includes four cells, at this time, the four cells are connected in series, and the driving voltage of the LED is 12V; FIG. 1E shows a case where the LED includes six cells, at this time, the six cells are connected in series, and the driving voltage of the LED is 18V; FIG. 1F shows a case where the LED includes eight cells, at this time, the eight cells are connected in series, and the driving voltage of the LED is 24V.

[0058] FIG. 2 shows a cross-sectional schematic diagram of an array substrate provided by at least one embodiment of the present disclosure, and FIG. 3 shows a film layer schematic diagram of the array substrate. As shown in FIGS. 2 and 3, the array substrate includes a substrate BS, a buffer layer BF, an epitaxial layer EPI, a current blocking layer E1, a current spreading layer E2, a first electrode F1, a second electrode F2, an insulating layer PV, a first reflective layer DB1, a first contact pad P1, and a second contact pad P2, and has a connection relationship as shown.

[0059] For example, the epitaxial layer EPI includes a first semiconductor layer S1, a second semiconductor layer S2, and a light-emitting layer E between the first semiconductor layer S1 and the second semiconductor layer S2, and further includes a third semiconductor layer S0, one of the first semiconductor layer S1 and the second semiconductor layer S2 is a P-type semiconductor layer, that is, it has been P-doped, and the other is an N-type semiconductor layer, that is, it has been N-doped, and the third semiconductor layer S0 is an intrinsic semiconductor layer, that is, it has not been doped.

[0060] The first electrode F1 is electrically connected to the second semiconductor layer S2 through the current blocking layer E1 and the current spreading layer E2, and the second electrode F2 is electrically connected to the first semiconductor layer S1, so that the light emitting layer E can emit light under the voltage applied by the first electrode F1 and the second electrode F2. In the case where each LED includes a poly-cell, the first electrode F1 and the second electrode F2 are usually in a strip shape to facilitate electrical connection.

[0061] However, in the case where each LED includes a poly-cell, FIG. 4A shows a partial planar scanning electron microscope image of the poly-cell, FIG. 4B shows a cross-sectional scanning electron microscope image near the dotted line circle in FIG. 4A, and FIG. 5A shows another partial planar scanning electron microscope image of the poly-cell, and FIG. 5B shows a cross-sectional scanning electron microscope image near the dotted line circle in FIG. 5A. In combination with FIG. 4A and FIG. 5A, in the case where each LED includes a poly-cell, the first electrode F1 on the right side of the trench G between adjacent cells is about 2 μm higher than the rest of the position, so as to have a protruding part of about 2 μm, and in the production process such as die bonding, assembly, etc., the position of the protruding part is prone to Peeling damage of the first reflective layer DB1, as shown by the arrows in FIG. 4B and FIG. 5B, so that impurities such as water vapor are prone to enter the inside of the substrate along the damaged part, for example, into the epitaxial layer EPI, causing problems such as dead lamp assembly and the like.

[0062] In addition, in the case where the semiconductor layer of the poly-cell high-voltage Mini LED adopts GaN material, under the harsh environment of high temperature and high humidity such as 85°C and 85% RH or 60°C and 90% RH, impurities such as water vapor will enter the inside of the epitaxial layer EPI along the defect holes and cracks of the insulating layer PV, and then the GaN will undergo redox reaction with hydrogen ions and hydroxyl ions, so as to cause burn of the epitaxial layer EPI and the insulating layer PV, resulting in reliability dead lamp problem of the LED. For example, FIG. 6A shows a scanning electron microscope image of the epitaxial layer EPI with normal morphology, and FIG. 6B-FIG. 6D show scanning electron microscope images of the epitaxial layer EPI when the epitaxial layer EPI is burned. As shown in the dotted line box part of FIG. 6B-FIG. 6D, in the case where the epitaxial layer EPI is burned, the structure of the epitaxial layer EPI is destroyed, thereby seriously affecting the normal light emission of the LED.

[0063] In addition, FIG. 7B shows a partial planar scanning electron microscope image of the first electrode F1, and FIG. 7A and FIG. 7C respectively show partial cross-sectional schematic diagrams of the first electrode F1 in the portion circled by the dashed line in FIG. 7B. Since the first electrode F1 and the second electrode F2 are in the form of a long strip, the side wall slope angle is 60°-70°, 63.1° in FIG. 7A, and 72.4° in FIG. 7C. The angle value of the slope angle is designed to be too large, which causes the side wall to be not smooth enough and relatively steep, and wrinkles or even cracks are easily generated in the first reflective layer DB1 and the insulating layer PV adjacent to the side wall, thereby causing electrode short circuit and further causing problems such as lamp leakage and lamp death.

[0064] The above-mentioned problems of assembly lamp death, reliability lamp death, and lamp leakage lamp death will affect the product quality and production yield, and the higher the voltage and the more the number of sub-light emitting units, the higher the failure probability.

[0065] To this end, embodiments of the present disclosure provide a light emitting unit and a preparation method thereof, and a light emitting diode chip. The light emitting unit includes a plurality of sub-light emitting units, at least one of the plurality of sub-light emitting units including an epitaxial layer and at least one first electrode. The epitaxial layer is disposed on a substrate and includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer disposed in sequence in a direction away from the substrate. One of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer. The at least one first electrode is disposed on a side of the epitaxial layer away from the substrate and is electrically connected to the second semiconductor layer. The at least one first electrode is in a dot shape.

[0066] In embodiments of the present disclosure, by designing the at least one first electrode in a dot shape, in the case where the plurality of sub-light emitting units included in the light emitting unit are divided in structure by a trench, a convex electrode can be avoided near the trench, and in the production process such as die bonding and assembly, damage such as peeling of the reflective layer or the insulating layer can be avoided, thereby improving the product quality and production yield. The higher the voltage and the more the number of sub-light emitting units, the more obvious the improvement effect, and thus the light emitting unit can be used in a high-voltage light emitting device.

[0067] Hereinafter, the light emitting unit and the preparation method thereof, and the light emitting diode chip provided by embodiments of the present disclosure will be described in detail through specific embodiments.

[0068] Embodiments of the present disclosure provide a light emitting unit. FIG. 8 shows a planar schematic diagram of the light emitting unit, and FIG. 9 shows a cross-sectional schematic diagram of the light emitting unit. As shown in FIG. 8, the light emitting unit includes a plurality of sub-light emitting units SP, and four sub-light emitting units SP are shown as an example in the figure. For example, the sub-light emitting unit SP can be implemented as a unit cell described above or in another suitable form.

[0069] As shown in FIG. 9, at least one (for example, each) of the plurality of sub-light emitting units includes an epitaxial layer EPI and at least one first electrode F1; the epitaxial layer EPI is disposed on a substrate BS and includes a first semiconductor layer S1, a light emitting layer E, and a second semiconductor layer S2 disposed in sequence in a direction away from the substrate BS, one of the first semiconductor layer S1 and the second semiconductor layer S2 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.

[0070] The P-type semiconductor layer includes a hole-type semiconductor and is mainly electrically conductive with positive holes, for example, formed by doping a trivalent element; the N-type semiconductor layer includes an electron-type semiconductor and is mainly electrically conductive with negative free electrons, for example, formed by doping a pentavalent element. For example, in some embodiments, the first semiconductor layer S1 can be an N-type semiconductor layer, and the second semiconductor layer S2 can be a P-type semiconductor layer; or, in other embodiments, the first semiconductor layer S1 can be a P-type semiconductor layer, and the second semiconductor layer S2 can be an N-type semiconductor layer. Embodiments of the present disclosure are described by taking the first semiconductor layer S1 as an N-type semiconductor layer and the second semiconductor layer S2 as a P-type semiconductor layer as an example.

[0071] As shown in FIG. 9, the first electrode F1 is disposed on a side of the epitaxial layer EPI away from the substrate BS and is electrically connected to the second semiconductor layer S2. For example, in the embodiments of FIGS. 8 and 9, two first electrodes F1 are shown as an example, and in other embodiments, the number of first electrodes F1 can also be more or less, which will be described in detail later.

[0072] For example, in some embodiments, the first electrode F1 is in a dot shape.

[0073] In embodiments of the present disclosure, the aspect ratio of the dot shape is less than 2. That is, the ratio of the length occupied by the dot shape in a certain direction (hereinafter referred to as the first direction) to the length occupied by the dot shape in another direction (for example, a direction perpendicular to the first direction) is less than 2. For example, in some embodiments, the dot shape can include a circular shape, a ring shape, a regular polygonal shape, or a deformed shape thereof. For example, in products and preparation processes, due to preparation errors and the like, the above-mentioned dot shape can deviate from the designed shape, thereby forming the above-mentioned deformed shape.

[0074] Therefore, in embodiments of the present disclosure, by designing at least one first electrode in a dot shape, in the case where the plurality of sub-light emitting units included in the light emitting unit are divided by the trench into sub-light emitting unit structures, the protruding electrode near the trench can be avoided, and in the production process such as die bonding and assembly, the peeling of the reflective layer and the insulating layer and the like can be avoided, thereby improving the quality and production yield of the product, and the higher the voltage and the more the number of sub-light emitting units, the more obvious the improvement effect is, and therefore, the light emitting unit provided by the embodiments of the present disclosure can be used in high-voltage light emitting devices.

[0075] For example, in some embodiments, as shown in FIG. 9, the first semiconductor layer S1 includes a first portion S11 overlapping the light-emitting layer E in a direction perpendicular to the substrate substrate BS and a second portion S12 not overlapping the light-emitting layer E in the direction perpendicular to the substrate substrate BS, at least one sub-light-emitting unit of the plurality of light-emitting units further includes at least one second electrode F2, the second electrode F2 is disposed on a side of the second portion S12 away from the substrate substrate BS and is electrically connected with the second portion S12, for example, the at least one second electrode F2 is in a dot shape.

[0076] Similarly, the aspect ratio of the dot shape is less than 2, which can be referred to the above description. In this way, the design of the second electrode F2 can also avoid the protruding electrode near the groove, and can avoid the damage such as peeling of the reflective layer and the insulating layer in the production process such as die bonding and assembly, thereby improving the product quality and production yield.

[0077] For example, in some embodiments, the substrate substrate BS can be a patterned substrate substrate, for example, a sapphire substrate, and the main material is aluminum oxide. For example, in the vertical direction in FIG. 9, the maximum thickness of the substrate substrate BS is between 50 μm and 300 μm. For example, the substrate substrate BS includes a plurality of conical protrusions arranged in an array on the surface close to the epitaxial layer EPI, the base width of each conical protrusion can be 2.4 μm to 3.0 μm, the maximum height in the vertical direction in FIG. 9 can be 1.4 μm to 2.0 μm, and the pitch of the center axes of the adjacent two conical protrusions can be 1.0 μm to 4.0 μm. The substrate substrate BS can play a certain debugging role for the light emitted by the light-emitting unit, and improve the light-emitting efficiency of the light-emitting unit.

[0078] For example, in some embodiments, as shown in FIG. 9, the epitaxial layer EPI can further include a third semiconductor layer S0 disposed on the side of the first semiconductor layer S1 close to the substrate substrate BS, and the third semiconductor layer S0 is an undoped semiconductor layer, which can be referred to as an intrinsic semiconductor layer. For example, in some embodiments, the epitaxial layer EPI can further include a buffer layer BF disposed on the side of the third semiconductor layer S0 close to the substrate substrate BS, and the buffer layer BF can provide a flat surface, and the third semiconductor layer S0 can increase the adhesion of the first semiconductor layer S1 on the buffer layer BF, thereby improving the stability of the whole light-emitting unit.

[0079] For example, in some embodiments, the third semiconductor layer S0 can employ a semiconductor material such as gallium nitride, and the thickness in the vertical direction in FIG. 9 is 0.5 μm to 1.5 μm. At this time, one of the first semiconductor layer S1 and the second semiconductor layer S2 can be P-type gallium nitride, and the other can be N-type gallium nitride. For example, the light emitting layer E is a multi-quantum well layer (MQW), which is a main light emitting layer of the light emitting unit.

[0080] For example, the N-type gallium nitride is doped with Si, and the thickness in the vertical direction in FIG. 9 is 2 μm to 4 μm, which provides negative electrons for the stimulated emission process; the P-type gallium nitride is doped with Mg, and the thickness in the vertical direction in FIG. 9 is 1000 angstroms to 5000 angstroms, which provides positive holes for the stimulated emission process. The multi-quantum well layer can include a stack of InGaN and GaN, and the thickness in the vertical direction in FIG. 9 is 500 angstroms to 300 angstroms.

[0081] For example, in some embodiments, the entire thickness of the epitaxial layer EPI including the buffer layer BF, the third semiconductor layer S0, the first semiconductor layer S1, the light emitting layer E, and the second semiconductor layer S2 in the vertical direction in FIG. 9 is 3 μm to 7 μm. For example, the material of the buffer layer BF can employ a material such as aluminum nitride, and the thickness in the vertical direction in FIG. 9 is 200 angstroms to 300 angstroms, which can improve the lattice matching of the substrate base plate BS and the third semiconductor layer S0.

[0082] For example, in some embodiments, as shown in FIG. 9, the sub light emitting unit can further include a current blocking layer E1 disposed on the side of the second semiconductor layer S2 away from the substrate base plate BS, and a current spreading layer E2 disposed on the side of the current blocking layer E1 away from the substrate base plate BS, and the first electrode F1 is disposed on the side of the current spreading layer E2 away from the substrate base plate BS.

[0083] For example, in some embodiments, the first semiconductor layer S1 is an N-type semiconductor layer, and the second semiconductor layer S2 is a P-type semiconductor layer, at this time, the main material of the current blocking layer E1 can employ a material such as gallium aluminum nitride, and the thickness in the vertical direction in FIG. 9 is 180 angstroms to 280 angstroms, which is used for negative electron blocking. The main material of the current spreading layer can employ a material such as indium tin oxide (ITO), and the thickness in the vertical direction in FIG. 9 is 500 angstroms to 1500 angstroms, which is used for positive current spreading. The arrangement of the current blocking layer E1 and the current spreading layer E2 can improve the light emitting efficiency of the light emitting layer E.

[0084] For example, in some embodiments, as shown in FIG. 8, the plurality of sub light emitting units SP include adjacent first sub light emitting unit SP1 and second sub light emitting unit SP2, and the first electrode F1 of the first sub light emitting unit SP1 is electrically connected to the second electrode F2 of the second sub light emitting unit SP2, thereby realizing the series connection between the sub light emitting units SP.

[0085] For example, in the embodiment of FIG. 8, the plurality of sub-light emitting units SP further include a third sub-light emitting unit SP3 and a fourth sub-light emitting unit SP4, the first electrode F1 of the second sub-light emitting unit SP2 is electrically connected to the second electrode F2 of the third sub-light emitting unit SP3, and the first electrode F1 of the third sub-light emitting unit SP3 is electrically connected to the second electrode F2 of the fourth sub-light emitting unit SP4, thereby realizing the series connection of the first sub-light emitting unit SP1 to the fourth sub-light emitting unit SP4 in sequence. For example, in some examples, the working voltage of each sub-light emitting unit is 3V, and at this time, the working voltage of the light emitting unit including the first sub-light emitting unit SP1 to the fourth sub-light emitting unit SP4 is 12V.

[0086] For example, in some embodiments, as shown in FIG. 9, at least one sub-light emitting unit in the plurality of light emitting units further includes a first connection electrode C1, the first connection electrode C1 is disposed on the side of at least one first electrode F1 away from the substrate base plate BS and is electrically connected to at least one first electrode F1 through at least one first via V1.

[0087] For example, in some embodiments, as shown in FIG. 9, at least one sub-light emitting unit in the plurality of light emitting units further includes a second connection electrode C2, the second connection electrode C2 is disposed on the side of at least one second electrode F2 away from the substrate base plate BS and is electrically connected to at least one second electrode F2 through at least one second via V2, for example, the first connection electrode C1 and the second connection electrode C2 are disposed in the same layer.

[0088] It should be noted that in the embodiments of the present disclosure, “disposed in the same layer” means that two functional layers or structural layers are formed in the same layer and with the same material in the layer structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process.

[0089] For example, in some embodiments, the first connection electrode C1 and the second connection electrode C2 can adopt metal materials or alloy materials such as Al, Ti, Ni, Cr, Ti, Pt, etc., and the thickness in the vertical direction in FIG. 9 can be 0.5 μm-2.5 μm, which is used for the electrical connection of the epitaxial layer EPI and other circuits.

[0090] For example, in some embodiments, the first electrode F1 and the second electrode F2 can be disposed in the same layer to simplify the preparation process. For example, the materials of the first electrode F1 and the second electrode F2 can adopt metal materials or alloy materials such as Au, Ag, Cu, Cr, Al, Ni, Pt, Ti, Pt, etc., and the thickness in the vertical direction in FIG. 9 can be 0.5 μm-2.5 μm, which is used for the electrical connection of the epitaxial layer EPI and other circuits and current expansion.

[0091] For example, in some examples, the first electrode F1 and the second electrode F2 comprise a multi-layer metal material, for example a multi-layer metal comprising Cr / Al / Ni / Pt / Ti / Pt / Au, with the thickness of each layer being 200 angstroms, 1200 angstroms, 1100 angstroms, 600 angstroms, 800 angstroms, 500 angstroms, and 15100 angstroms, respectively; the first connecting electrode C1 and the second connecting electrode C2 also comprise a multi-layer metal material, for example a multi-layer metal comprising Cr / Al / Ti / Ni / Al / Ti / Pt, with the thickness of each layer being 200 angstroms, 1000 angstroms, 3500 angstroms, 1000 angstroms, 10000 angstroms, 1000 angstroms, and 2000 angstroms, respectively.

[0092] For example, in some embodiments, as shown in FIG. 8, the first connecting electrode C1 and the second connecting electrode C2 can be used to realize series connection between multiple sub-light emitting units SP. For example, as shown in FIG. 9, the first connecting electrode C1 of the first sub-light emitting unit SP1 is electrically connected to the second connecting electrode C2 of the second sub-light emitting unit SP2, for example in an integrated structure, thereby realizing series connection. Similarly, the first connecting electrode C1 of the second sub-light emitting unit SP2 is electrically connected to the second connecting electrode C2 of the third sub-light emitting unit SP3, for example in an integrated structure; the first connecting electrode C1 of the third sub-light emitting unit SP3 is electrically connected to the second connecting electrode C2 of the fourth sub-light emitting unit SP4, for example in an integrated structure, thereby realizing series connection of the first sub-light emitting unit SP1 to the fourth sub-light emitting unit SP4 in sequence.

[0093] For example, in some embodiments, in at least one sub-light emitting unit SP, for example in each sub-light emitting unit SP, the total number N of vias of the at least one first via V1 and the at least one second via V2 is 2-10. In the embodiments of FIGS. 8 and 9, the total number of the first via V1 and the second via V2 is three as an example.

[0094] For example, FIGS. 10-14 show various arrangement diagrams of the first via V1 and the second via V2. In some embodiments, as shown in FIG. 10, the total number N of the first via V1 and the second via V2 included in each sub-light emitting unit SP is 2, and the total number of the first electrode F1 and the second electrode F2 is 2; as shown in FIGS. 11A and 11B, the total number N of the first via V1 and the second via V2 included in each sub-light emitting unit SP is 3, and the total number of the first electrode F1 and the second electrode F2 is 3; as shown in FIG. 12, the total number N of the first via V1 and the second via V2 included in each sub-light emitting unit SP is 4, and the total number of the first electrode F1 and the second electrode F2 is 4; as shown in FIG. 13, the total number N of the first via V1 and the second via V2 included in each sub-light emitting unit SP is 5, and the total number of the first electrode F1 and the second electrode F2 is 5; as shown in FIG. 14, the total number N of the first via V1 and the second via V2 included in each sub-light emitting unit SP is 7, and the total number of the first electrode F1 and the second electrode F2 is 7.

[0095] For example, in some embodiments, as shown in FIGS. 10-14, the first via V1 and the second via V2 include first sub-vias V11 having a first projected area and second sub-vias V12 having a second projected area, the area of the orthographic projection of the first sub-vias V11 on the substrate BS is less than the area of the orthographic projection of the second sub-vias V12 on the substrate BS, the number of the first sub-vias V11 is N1, the number of the second sub-vias V12 is N2, N1≥N2, and N1+N2=N. In this way, some of the first via V1 and the second via V2 are large vias, and some are small vias, and the number of small vias is less than or equal to the number of large vias, thereby achieving different electrical connection modes of the first electrode F1 and the second electrode F2 and improving the electrical connection effect.

[0096] For example, in some embodiments, the second via V2 includes the second sub-via V12, i.e., the second via V2 includes a large via, and the first via V1 includes the first sub-via V11, i.e., the first via V1 includes a small via. Since the second via V2 penetrates more film layers (to be described in detail later), the second via V2 including a large via can make the electrical connection effect of the second via V2 better, for example, the electrical connection effect between the second electrode F2 and the second connection electrode C2 is better and more stable.

[0097] For example, in the embodiments of FIGS. 10-14, the second via V2 can include the second sub-via V12, and the first via V1 includes all the first sub-vias V11; or the second via V2 can include the second sub-via V12 and part of the first sub-vias V11, and the first via V1 includes the other first sub-vias V11; or in other embodiments, the first via V1 can include the second sub-via V12, and the second via V2 includes all the first sub-vias V11; or the first via V1 can include the second sub-via V12 and part of the first sub-vias V11, and the second via V2 includes the other first sub-vias V11, which are not limited in the embodiments of the present disclosure.

[0098] For example, in some embodiments, as shown in FIGS. 10-14, the first via V1 and the second via V2 can have various arrangements, such as a linear arrangement (as shown in FIGS. 10 and 11B), a triangular arrangement (as shown in FIGS. 11A and 12), a cross-shaped arrangement (as shown in FIG. 13), or a ring-shaped arrangement (as shown in FIG. 14), and the like. Thus, the overall arrangement of the first via V1 and the second via V2 is more orderly, which is helpful for circuit design and arrangement.

[0099] For example, in some embodiments, as shown in FIG. 9, at least one sub-light emitting unit of the plurality of light emitting units further includes a first protective layer PR1 and a second protective layer PR2; the first protective layer PR1 is disposed at least on the sidewall EP1 of the epitaxial layer EPI, for example, also disposed on the sidewall of the structures such as the first electrode F1 and the second electrode F2, and the second protective layer PR2 is disposed at least on the side of the first protective layer PR1 away from the epitaxial layer EPI; the orthographic projection of the first protective layer PR1 and the second protective layer PR2 on the substrate BS at least partially overlaps with the orthographic projection of the sidewall EP1 of the epitaxial layer EPI on the substrate BS. For example, the orthographic projection of the sidewall EP1 of the epitaxial layer EPI on the substrate BS is located inside the orthographic projection of the first protective layer PR1 and the second protective layer PR2 on the substrate BS.

[0100] The first protective layer PR1 and the second protective layer PR2 can protect the epitaxial layer EPI, and also can protect the structures such as the first electrode F1 and the second electrode F2, to avoid the epitaxial layer EPI and other structures from being eroded by external impurities such as water and oxygen, thereby ensuring the stability of the epitaxial layer EPI structure and avoiding the occurrence of reliability dead light and other adverse problems.

[0101] In the embodiments of the present disclosure, as shown in FIG. 9, the sidewall EP1 of the epitaxial layer EPI is the sidewall between the surface close to the substrate BS and the surface away from the substrate BS of the epitaxial layer EPI. Since the epitaxial layer EPI has multiple film layers, the sidewall of the epitaxial layer EPI can have a structure inclined relative to the substrate BS or a stepped structure.

[0102] For example, in some embodiments, the first protective layer PR1 can be a protective layer made by an atomic layer deposition (ALD) process, and the material of the first protective layer PR1 can be aluminum trioxide with a thickness of 500 angstroms to 2500 angstroms. The second protective layer PR2 can be a protective layer formed by a physical vapor deposition (PECVD) process, and the material of the second protective layer PR2 can be silicon dioxide with a thickness of 0.8 μm to 1.4 μm. In this way, the first protective layer PR1 and the second protective layer PR2 formed above have fewer defect holes, higher density, and better coverage of the steps (for example, the coverage of the epitaxial layer EPI sidewall), which can effectively improve the water vapor corrosion resistance of the sub-light emitting unit SP and avoid problems such as reliability dead light caused by oxidation and burn of the epitaxial layer EPI in harsh environments such as high temperature and high humidity.

[0103] For example, in some embodiments, as shown in FIG. 9, the first via V1 and the second via V2 penetrate the first protective layer PR1 and the second protective layer PR2.

[0104] For example, in some embodiments, as shown in FIG. 15A, the first electrode F1 includes a first bottom surface F11 close to the substrate substrate BS and a first side surface F12 connected to the first bottom surface F11. The first angle a formed by the first bottom surface F11 and the first side surface F12 is 40°-50°, for example, 42°, 43°, 45°, 47°, or 49°, etc.

[0105] For example, in some embodiments, as shown in FIG. 15B, the second electrode F2 includes a second bottom surface F21 close to the substrate substrate BS and a second side surface F22 connected to the second bottom surface F21. The second angle b formed by the second bottom surface F21 and the second side surface F22 is 40°-50°, for example, 42°, 43°, 45°, 47°, or 49°, etc.

[0106] By designing the first angle a and the second angle b to be in the above range, the structural stability of the film layers (for example, the first protective layer PR1, the second protective layer PR2, and the first reflective layer DB1, which will be described in detail later) formed thereon can be improved, and peeling or wrinkles of these film layers at the first side surface F12 and the second side surface F22 can be avoided, thereby avoiding problems such as electrical leakage and dead light.

[0107] For example, in some embodiments, as shown in FIG. 9, at least one of the plurality of light emitting units further comprises a first reflective layer DB1, which at least fills between the adjacent first electrode F1 and the second electrode F2. For example, FIG. 16 shows a schematic cross-sectional view of the first reflective layer DB1, as shown in FIG. 16, the first reflective layer DB1 comprises first reflective sub-layers DB11 and second reflective sub-layers DB12 arranged alternately in a direction away from the substrate substrate BS, the materials of the first reflective sub-layers DB11 and the second reflective sub-layers DB12 are different.

[0108] For example, in some embodiments, the first reflective sub-layers DB11 and the second reflective sub-layers DB12 can respectively adopt SiO2 and TiO2, the thicknesses in the vertical direction in FIG. 16 are respectively 3 μm-5 μm, the first reflective sub-layers DB11 and the second reflective sub-layers DB12 are alternately stacked, and the light emitted by the light emitting layer E can be reflected to the substrate substrate BS, thereby improving the light extraction efficiency of the light emitting unit. For example, the total number of layers of the first reflective sub-layers DB11 and the second reflective sub-layers DB12 can be 20-40, for example, 20-30. Due to the large number of layers of the first reflective sub-layers DB11 and the second reflective sub-layers DB12, by designing the first angle a and the second angle b to be in the above-mentioned angle range, wrinkles or cracks of the first reflective sub-layers DB11 and the second reflective sub-layers DB12 at the first side surface F12 and the second side surface F22 can be avoided, thereby improving the structural integrity and stability.

[0109] For example, as shown in FIG. 9, the first via V1 and the second via V2 also penetrate the first reflective layer DB1.

[0110] For example, in some embodiments, as shown in FIG. 9, the array substrate can further comprise a second reflective layer DB2, which is arranged on a side of the substrate substrate BS away from the epitaxial layer EPI. For example, FIG. 17 shows a schematic cross-sectional view of the second reflective layer DB2, as shown in FIG. 17, the second reflective layer DB2 comprises third reflective sub-layers DB21 and fourth reflective sub-layers DB22 arranged alternately in a direction away from the epitaxial layer EPI, the materials of the third reflective sub-layers DB21 and the fourth reflective sub-layers DB22 are different, and the total number of layers of the third reflective sub-layers DB21 and the fourth reflective sub-layers DB22 is 10-70, for example, 20-60, for example, 30-50, for example, 35-45, etc. The second reflective layer DB2 can be used to control the light emitting pattern and the light emitting angle of the light emitting unit.

[0111] For example, in some embodiments, the third reflective sub-layers DB21 and the fourth reflective sub-layers DB22 can respectively adopt SiO2 and TiO2, the thicknesses in the vertical direction in FIG. 17 are respectively 1 μm-4 μm, and the light emitting pattern and the light emitting angle of the light emitting unit can be controlled.

[0112] For example, in some embodiments, as shown in FIG. 9, the sub-light emitting unit SP can further include a first insulating layer B1, a first contact pad P1 and a second contact pad P2; the first insulating layer B1 is arranged on the side of the first connecting electrode C1 and the second connecting electrode C2 away from the substrate base plate BS, includes a third via V3 exposing the first connecting electrode C1 and a fourth via V4 exposing the second connecting electrode C2, the first contact pad P1 is electrically connected with the first connecting electrode C1 through the third via V3, and the second contact pad P2 is electrically connected with the second connecting electrode C2 through the fourth via V4.

[0113] For example, the material of the first insulating layer B1 can be SiO2 or TiO2, and the thickness in the vertical direction in FIG. 9 is 1-2 μm, which can realize the functions of insulation and protection.

[0114] For example, in some embodiments, as shown in FIG. 8, the first contact pad P1 and the second contact pad P2 can be in the shape of a strip, such as a rectangle, etc.

[0115] For example, the first contact pad P1 and the second contact pad P2 can be solder electrodes, which can be divided into two types of non-preformed and preformed. For example, the non-preformed contact pad is made of Al / Ti / Pt / Au, with a thickness of about 2 μm, and the main material is Au. The preformed contact pad is made of Al / Ti / Pt / Au / Sn / Ag / Cu, with a thickness of 8-35 μm, and the main material is Sn / Ag / Cu.

[0116] For example, FIG. 18 shows a plan view of the first contact pad P1 and the second contact pad P2 in at least one embodiment of the present disclosure. As shown in FIG. 18, the shape or area of the orthographic projection of the first contact pad P1 on the substrate base plate BS is different from that of the orthographic projection of the second contact pad P2 on the substrate base plate BS; the area of the orthographic projection of the second contact pad P2 on the substrate base plate BS is smaller than that of the orthographic projection of the first contact pad P1 on the substrate base plate BS, or the orthographic projection of the second contact pad P2 on the substrate base plate BS has a notch P21.

[0117] For example, as shown in FIG. 18, in some embodiments, the light emitting unit includes eight sub-light emitting units (which can be referred to FIGS. 19 and 20 later), at this time, the length L1 of the substrate base plate BS corresponding to the light emitting unit is 865-965 μm; the width L2 of the substrate base plate BS corresponding to each light emitting unit is 400-500 μm; the length L3 of the first contact pad P1 is 370-430 μm; the width L4 of the first contact pad P1 is 285-345 μm; the length of the second contact pad P2 can be equal to the length L3 of the first contact pad P1, and the width of the second contact pad P2 can be equal to the width L4 of the first contact pad P1; the minimum distance L5 between the first contact pad P1 and the second contact pad P2 can be 170-270 μm.

[0118] For example, in some embodiments, the plurality of sub-light emitting units SP are arranged in multiple rows and multiple columns, the first contact pad P1 and the second contact pad P2 extend along the column direction, and the first contact pad P1 and the second contact pad P2 respectively overlap with at least two of the at least one first electrode F1 and the at least one second electrode F2 in a direction perpendicular to the substrate base plate BS; for example, in the embodiment of FIG. 8, the first contact pad P1 covers one first electrode F1 and one second electrode F2 of the second sub-light emitting unit SP2, and also covers one first electrode F1 and one second electrode F2 of a third sub-light emitting unit SP3; the second contact pad P2 covers one first electrode F1 and one second electrode F2 of the first sub-light emitting unit SP1, and also covers one first electrode F1 and one second electrode F2 of a fourth sub-light emitting unit SP4.

[0119] For example, in some embodiments, as shown in FIG. 8, the overall of the plurality of first electrodes F1 and the plurality of second electrodes F2 included in the two adjacent columns of sub-light emitting units is centrally symmetrical. This is conducive to improving the uniformity of the structure, thereby improving the light emitting uniformity of the light emitting unit.

[0120] For example, in some embodiments, as shown in FIG. 8, the planar shapes of the third via V3 and the fourth via V4 are respectively elliptical. In the embodiment of FIG. 8, the third via V3 is disposed in the third sub-light emitting unit SP3, and the long axis direction of the third via V3 is along the column direction; the fourth via V4 is disposed in the fourth sub-light emitting unit SP4, and the long axis direction of the fourth via V4 is along the row direction.

[0121] For example, FIG. 19 shows a plan view of another light emitting unit provided by at least one embodiment of the present disclosure. As shown in FIG. 19, the light emitting unit includes a plurality of sub-light emitting units SP and a non-electric region N disposed between adjacent sub-light emitting units SP, and the non-electric region N is insulated from the plurality of sub-light emitting units SP. For example, the non-electric region N has no circuit structure and can be referred to as an island, which can be a pushing region of the light emitting unit. When the light emitting unit is disposed in a certain device or region, the non-electric region N can be used as a pushing tool (or other pushing tool) to dispose the light emitting unit on the required interval or region. The design of the island can avoid damage to the light emitting unit during the setting process.

[0122] For example, in the case where the light emitting unit includes eight sub-light emitting units, the working voltage of each sub-light emitting unit can be 3V, and the working voltage of the light emitting unit formed by series connection is 24V. For example, in other embodiments, the light emitting unit can also include other numbers of sub-light emitting units, such as two, three, four, five, six, seven, nine, or ten, etc., and the embodiments of the present disclosure do not make specific limitations in this regard.

[0123] For example, in some embodiments, the non-electricity region N can be a circular region as shown in FIG. 19, in which case the diameter of the circular region can be 30 μm to 50 μm; or the non-electricity region N can be a rectangular region as shown in FIG. 20, in which case the diagonal of the rectangular region can be 30 μm to 50 μm, so as to be sufficient to accommodate the needle or other pushing tool.

[0124] In summary, in the light emitting unit provided by the embodiments of the present disclosure, the first electrode F1 and the second electrode F2 are in a dot shape, so that the protrusions near the grooves between the sub light emitting units can be avoided, and further, the damage such as peeling of the reflective layer or the insulating layer can be avoided, and further, the quality and the production yield of the product can be improved; in addition, the first protective layer PR1 and the second protective layer PR2 have higher compactness, fewer defect holes, and better coverage effect on the steps, so that the water vapor corrosion resistance of the sub light emitting unit SP can be effectively improved; in addition, the sidewall angle of the first electrode F1 and the second electrode F2 is designed to be 40° to 50°, so that the structural stability of the film layer formed thereon can be improved, and the peeling or the wrinkle of these film layers at the sidewall of the first electrode F1 and the second electrode F2 can be avoided; thus, the reliability of the light emitting unit and the production yield of the product can be effectively improved.

[0125] The at least one embodiment of the present disclosure further provides a preparation method of a light emitting unit, the preparation method comprising: forming a plurality of sub light emitting units on a substrate BS, wherein at least one of the plurality of sub light emitting units comprises an epitaxial layer EPI and at least one first electrode F1; the epitaxial layer EPI is formed on the substrate BS and comprises a first semiconductor layer S1, a light emitting layer E and a second semiconductor layer S2 arranged in sequence in a direction away from the substrate BS, one of the first semiconductor layer S1 and the second semiconductor layer S2 is a P-type semiconductor layer, and the other is an N-type semiconductor layer; the at least one first electrode F1 is formed on a side of the epitaxial layer EPI away from the substrate BS and is electrically connected with the second semiconductor layer S2, wherein the at least one first electrode F1 is in a dot shape.

[0126] FIGS. 21A-21G show cross-sectional schematic views of a light emitting unit in a preparation process according to at least one embodiment of the present disclosure, and the preparation method of the light emitting unit according to the embodiments of the present disclosure will be described in detail below with reference to FIGS. 21A-21G. For example, the method comprises a front-end process, a middle-end process and a back-end process.

[0127] For example, as shown in FIG. 21A, in the front-end process, first, a substrate BS is provided, which can be a patterned sapphire substrate with a thickness of 500-650 μm (for details, refer to the above embodiment), and then a material layer EPI0 of an epitaxial layer EPI is formed on the substrate BS by a process such as metal organic chemical vapor deposition (MOCVD). The material layer EPI0 of the epitaxial layer EPI is formed on the substrate BS as a whole, including multiple film layers for forming a buffer layer BF, a third semiconductor layer S0, a first semiconductor layer S1, a light-emitting layer E, and a second semiconductor layer S1.

[0128] For example, in the above step, the main process can further include processes such as sapphire substrate quality inspection, quality inspection test using an ellipsometer, thickness and appearance test of each film layer, and the like. For details, refer to the related art, which will not be described here.

[0129] As shown in FIG. 21B, in the middle-end process, the material layer EPI0 is patterned to form a patterned buffer layer BF, a third semiconductor layer S0, a first semiconductor layer S1, a light-emitting layer E, and a second semiconductor layer S1. For example, a first mask plate can be used to pattern the film layers for forming the light-emitting layer E and the second semiconductor layer S1, for example, etching, to form the pattern of the light-emitting layer E and the second semiconductor layer S1, and then a second mask plate can be used to pattern the film layers for forming the buffer layer BF, the third semiconductor layer S0, and the first semiconductor layer S1, for example, etching, to form the buffer layer BF, the third semiconductor layer S0, and the first semiconductor layer S1.

[0130] For example, the patterning process can include coating photoresist, exposure, development, spin-drying, film fixing, etching, and the like. For details, refer to the related art, which will not be described here.

[0131] For example, as shown in FIG. 21C, the current blocking layer E1 can be formed by a patterning process using a third mask plate, the current spreading layer E2 can be formed by a patterning process using a fourth mask plate, and the first electrode F1 and the second electrode F2 can be formed by a patterning process using a fifth mask plate.

[0132] For example, when the first electrode F1 and the second electrode F2 are formed, the design of the first angle a and the second angle b as shown in FIGS. 15A and 15B can be achieved by optimizing the parameters of the evaporation process, so that when the first protective layer PR1, the second protective layer PR2, and the first reflective layer DB1 are subsequently formed, the stress concentration of the first protective layer PR1, the second protective layer PR2, and the first reflective layer DB1 at the slope position can be improved, the first protective layer PR1, the second protective layer PR2, and the first reflective layer DB1 can more completely cover the first electrode F1 and the second electrode F2, and the risk of film layer peeling can be reduced.

[0133] For example, as shown in FIG. 21D, the first protective layer PR1 is formed by a method such as atomic layer deposition (ALD), and the second protective layer PR2 is formed by a method such as physical vapor deposition (PECVD). At this time, the first protective layer PR1 and the second protective layer PR2 can be formed on the surface of each structure that has been formed on the substrate BS.

[0134] For example, as shown in FIG. 21E, the first reflective layer DB1 can be formed by a process such as deposition. In the case where the first reflective layer DB1 includes first reflective sub-layers DB11 and second reflective sub-layers DB12 arranged alternately in a direction away from the substrate BS, the materials of the first reflective sub-layers DB11 and the second reflective sub-layers DB12 can be deposited alternately on the surfaces of the first protective layer PR1 and the second protective layer PR2, in sequence, to form the first reflective layer DB1.

[0135] For example, as shown in FIG. 21F, the first via V1 exposing the first electrode F1 and the second via V2 exposing the second electrode F2 are formed by a patterning process using a sixth mask plate, and the materials of the first protective layer PR1 and the second protective layer PR2 are filled in the vias. Then, the first connecting electrode C1 and the second connecting electrode C2 are formed by a patterning process using a seventh mask plate, the first connecting electrode C1 is electrically connected to the first electrode F1 through the first via, and the second connecting electrode C2 is electrically connected to the second electrode F2 through the second via.

[0136] For example, as shown in FIG. 21G, the first insulating layer B1 having the third via V1 exposing the first connecting electrode C1 and the fourth via V4 exposing the second connecting electrode C2 is formed by a patterning process using an eighth mask plate, and then the first contact pad P1 and the second contact pad P2 are formed by a patterning process using a ninth mask plate, the first contact pad P1 is electrically connected to the first connecting electrode C1 through the third via V1, and the second contact pad P2 is electrically connected to the second connecting electrode C2 through the fourth via V4.

[0137] For example, the material of the first insulating layer B1 can be formed first by a process such as deposition, and then the pattern of the first insulating layer B1 is formed by a patterning process using the eighth mask plate. For example, during the deposition process, the ratio of SiH4 and N2O used in the process can be optimized, and the one-time deposition can be modified to multiple-cycle deposition, that is, by multiple deposition, each deposition with a thinner thickness, to avoid the growth of holes in the film layer, improve the density of the first insulating layer B1, and further improve the insulation and protection functions of the first insulating layer B1.

[0138] In summary, the preparation of the main structure of the sub-light emitting unit is completed by using nine mask plates, a total of 9 mask processes.

[0139] For example, in some embodiments, when the light emitting unit includes the second reflective layer DB2, the second reflective layer DB2 can be formed by a deposition process or the like on the side of the substrate BS away from the epitaxial layer EPI. For example, the third reflective sub-layer DB21 and the fourth reflective sub-layer DB22 are sequentially and alternately deposited in the direction away from the substrate BS to form the second reflective layer DB2.

[0140] For example, in some embodiments, a plurality of light emitting units arranged in an array are formed on a substrate, which can be used to form a plurality of devices. Therefore, in the subsequent process, the plurality of light emitting units can be divided by grinding, cutting, cleaving, electrical testing, and the like to form a plurality of devices, such as light emitting diode chips.

[0141] The light emitting unit produced by the above process can be used to form a high-voltage Mini LED, which utilizes a 9-mask process to realize the preparation of the structure. Through the design of the point structure of the first electrode F1 and the second electrode F2, the design of the first protective layer PR1 and the second protective layer PR2 with higher density, and the design of the side wall angle of the first electrode F1 and the second electrode F2, the occurrence of dead lights and other defects of high-voltage Mini LED can be avoided, and the reliability of high-voltage devices can be greatly improved, thereby effectively improving the quality and yield of Mini LED products.

[0142] At least one embodiment of the present disclosure also provides a light emitting diode chip, which includes a plurality of light emitting units provided by the embodiments of the present disclosure, for example, a plurality of light emitting units arranged in an array, for example, can be formed into a high-voltage Mini LED chip.

[0143] The light emitting diode chip provided by the embodiments of the present disclosure has higher reliability, and the preparation process is simple, low in cost, and high in yield. For example, for medium and large size Mini LED products, the light emitting diode chip provided by the embodiments of the present disclosure can greatly reduce the production cost, thereby further improving the competitiveness of Mini LED products and OELD products.

[0144] For example, the light emitting diode chip provided by the embodiments of the present disclosure can not only be used in small and medium-sized wearable products, notebook computers, and the like, but also can be applied to medium and large-sized displays and television sets and the like, and can also be used in Mini LED display products using high-voltage Mini LED, such as Mini LED direct display products including commercial display screens, cinemas, and all-in-one machines, and the like, and has a wide range of applications.

[0145] The following points need to be explained:

[0146] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the usual design.

[0147] (2) For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, the drawings are not drawn in accordance with the actual scale. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intermediate element can be present.

[0148] (3) The embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments without conflict.

[0149] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A light-emitting unit, comprising multiple sub-light-emitting units, in, At least one of the plurality of sub-light-emitting units includes: An epitaxial layer, disposed on a substrate, includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed along a direction away from the substrate, wherein one of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer. At least one first electrode is disposed on the side of the epitaxial layer away from the substrate and is electrically connected to the second semiconductor layer. The at least one first electrode is in the form of a dot.

2. The light-emitting unit according to claim 1, wherein, The first semiconductor layer includes a first portion that overlaps with the light-emitting layer in a direction perpendicular to the substrate, and a second portion that does not overlap with the light-emitting layer in a direction perpendicular to the substrate. At least one sub-light-emitting unit among the plurality of light-emitting units further includes: At least one second electrode is disposed on the side of the second portion away from the substrate and is electrically connected to the second portion. The at least one second electrode is in the form of a dot.

3. The light-emitting unit according to claim 1 or 2, wherein, The plurality of sub-light-emitting units include adjacent first sub-light-emitting units and second sub-light-emitting units. The first electrode of the first sub-light-emitting unit is electrically connected to the second electrode of the second sub-light-emitting unit.

4. The light-emitting unit according to any one of claims 1-3, wherein, The aspect ratio of the dots is less than 2.

5. The light-emitting unit according to claim 4, wherein, The dots include circles, rings, or regular polygons.

6. The light-emitting unit according to any one of claims 1-5, wherein, The epitaxial layer further includes a third semiconductor layer disposed on the side of the first semiconductor layer near the substrate, wherein the third semiconductor layer is an undoped semiconductor layer.

7. The light-emitting unit according to any one of claims 1-6, wherein, At least one of the plurality of light-emitting units further includes a current blocking layer disposed on the side of the second semiconductor layer away from the substrate and a current spreading layer disposed on the side of the current blocking layer away from the substrate. The at least one first electrode is disposed on the side of the current spreading layer away from the substrate.

8. The light-emitting unit according to claim 2, wherein, At least one sub-light-emitting unit among the plurality of light-emitting units further includes: A first connecting electrode is disposed on the side of the at least one first electrode away from the substrate, and is electrically connected to the at least one first electrode through at least one first via.

9. The light-emitting unit according to claim 8, wherein, At least one sub-light-emitting unit among the plurality of light-emitting units further includes: A second connecting electrode is disposed on the side of the at least one second electrode away from the substrate, and is electrically connected to the at least one second electrode through at least one second via. The first connecting electrode and the second connecting electrode are disposed in the same layer.

10. The light-emitting unit according to claim 9, wherein, In at least one sub-light-emitting unit, the total number N of the at least one first via and the at least one second via is 2 to 10.

11. The light-emitting unit according to claim 10, wherein, The at least one first via and the at least one second via include a first sub-via with a first projected area and a second via with a second projected area. The area of ​​the first sub-via's orthographic projection on the substrate is smaller than the area of ​​the second sub-via's orthographic projection on the substrate. The number of the first sub-via is N1, and the number of the second sub-via is N2. N1≥N2, N1+N2=N.

12. The light-emitting unit according to claim 11, wherein, The at least one second via includes the second sub-via, and the at least one first via includes the first sub-via.

13. The light-emitting unit according to claim 11, wherein, The at least one first via and the at least one second via are arranged in a straight line, triangle, cross, or ring shape.

14. The light-emitting unit according to any one of claims 9-13, wherein, At least one sub-light-emitting unit among the plurality of light-emitting units further includes: A first protective layer is provided at least on the sidewall of the epitaxial layer, and A second protective layer is disposed at least on the side of the first protective layer away from the epitaxial layer; Wherein, the orthographic projections of the first protective layer and the second protective layer on the substrate at least partially overlap with the orthographic projections of the sidewalls of the epitaxial layer on the substrate.

15. The light-emitting unit according to claim 14, wherein, The first via and the second via penetrate the first protective layer and the second protective layer.

16. The light-emitting unit according to any one of claims 1-15, wherein, The at least one first electrode includes a first bottom surface near the substrate and a first side surface connected to the first bottom surface, wherein the first bottom surface and the first side surface form a first angle of 40°-50°.

17. The light-emitting unit according to claim 2, wherein, The at least one second electrode includes a second bottom surface near the substrate and a second side surface connected to the second bottom surface, wherein the second included angle formed by the second bottom surface and the second side surface is 40°-50°.

18. The light-emitting unit according to any one of claims 1-17, wherein, At least one sub-light-emitting unit among the plurality of light-emitting units further includes: The first reflective layer, at least filling the space between adjacent first and second electrodes, comprises alternating first and second reflective sublayers arranged in a direction away from the substrate. The first reflective sublayer and the second reflective sublayer are made of different materials.

19. The light-emitting unit according to any one of claims 1-18, wherein, The array substrate further includes: The second reflective layer is disposed on the side of the substrate away from the epitaxial layer, and includes a third reflective sublayer and a fourth reflective sublayer arranged alternately in a direction away from the epitaxial layer. The third and fourth reflective sub-layers are made of different materials, and the total number of the third and fourth reflective sub-layers is 10 to 70.

20. The light-emitting unit according to any one of claims 1-18, wherein, The light-emitting unit includes a plurality of sub-light-emitting units and a non-electric region disposed between adjacent sub-light-emitting units, the non-electric region being insulated from the plurality of sub-light-emitting units.

21. The light-emitting unit according to any one of claims 9-15, wherein, At least one sub-light-emitting unit among the plurality of light-emitting units further includes: A first insulating layer is disposed on the side of the first and second connecting electrodes away from the substrate, and includes a third via exposing the first connecting electrode and a fourth via exposing the second connecting electrode. The first contact pad is electrically connected to the first connecting electrode through the third through-hole, and The second contact pad is electrically connected to the first connecting electrode through the fourth through hole.

22. The light-emitting unit according to claim 21, wherein, The orthographic projection of the first contact pad on the substrate is different in shape or area from the orthographic projection of the second contact pad on the substrate; The area of ​​the orthographic projection of the second contact pad on the substrate is smaller than the area of ​​the orthographic projection of the first contact pad on the substrate, or The second contact pad has a notch in its orthogonal projection onto the substrate.

23. The light-emitting unit according to claim 21, wherein, The multiple sub-light-emitting units are arranged in multiple rows and columns. The first contact pad and the second contact pad extend along the column direction and overlap with at least two of the at least one first electrode and the at least one second electrode in a direction perpendicular to the substrate.

24. The light-emitting unit according to claim 23, wherein, The two adjacent rows of sub-light-emitting units, including multiple first electrodes and multiple second electrodes, are centrally symmetrical.

25. The light-emitting unit according to any one of claims 21-24, wherein, The planar shapes of the third and fourth vias are elliptical.

26. A method for fabricating a light-emitting unit, comprising forming a plurality of sub-light-emitting units on a substrate. in, At least one of the plurality of sub-light-emitting units includes: An epitaxial layer is formed on a substrate and includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed along a direction away from the substrate. The first semiconductor layer and the second semiconductor layer are either P-type or N-type semiconductor layers. At least one first electrode is formed on the side of the epitaxial layer away from the substrate and is electrically connected to the second semiconductor layer. The at least one first electrode is in the form of a dot.

27. A light-emitting diode chip, comprising a plurality of light-emitting units as described in any one of claims 1-25.

Images