Low-latency GPIO communication system and communication method

Abstract

A low-latency GPIO communication system and a communication method. The low-latency GPIO communication system comprises a plurality of connected nodes, wherein each node comprises one or more GPIO ports for connecting to a peripheral device; each node is used for converting GPIO data on its own one or more GPIO ports into local GPIO data; and an upstream node of any two nodes is used for acknowledging its own local GPIO data with local GPIO data or GPIO acknowledgment data of a downstream node, so as to generate current GPIO acknowledgment data. On the basis of the low-latency GPIO communication system and the communication method, low-latency GPIO communication is formed by means of performing level-by-level acknowledgment in each node, and thus the excessive participation of a master node and a peripheral device is not required, the system communication latency is reduced, and the complexity of system design is reduced; the low-latency GPIO communication system has a low cost, can be easily implemented, and only requires the establishment of some basic gate-level circuits, thereby consuming less resources and having a low implementation cost; and the degree of controllability is high and the configuration is flexible.

Description

Low-latency GPIO communication system and communication method

[0001] The present application claims priority to the Chinese patent application No. 202410855568.5, filed on June 27, 2024, and entitled "Low-latency GPIO communication system and communication method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the technical field of integrated circuits, and particularly relates to a low-latency GPIO communication system and communication method. BACKGROUND

[0003] General-purpose input / output (GPIO) can be configured as input or output function, and is usually used for communication with external devices, which has the characteristics of low cost and easy implementation, and has huge application demand for signal control and acquisition. However, in a multi-node system, such as a network system formed by a daisy chain, the GPIO-to-GPIO communication between different nodes has higher complexity. In the traditional method, the GPIO communication based on interrupt generally maps the GPIO input of the slave node to the interrupt pin (IRQ) of the master node, but cannot immediately parse the specific communication content. This method needs the controller to additionally parse the meaning of GPIO behavior and then execute the next operation, which has great delay.

[0004] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present application and should not be taken as admitting that such information in the prior art in any form. SUMMARY

[0005] The purpose of the present application is to provide a low-latency GPIO communication system and communication method, which can greatly improve the flexibility of application and can complete the operation function without complicated setting and clearing instructions.

[0006] In order to achieve the above purpose, a specific embodiment of the present application provides a low-latency GPIO communication system, comprising: a plurality of connected nodes, each node comprising: one or more GPIO ports for connecting with peripheral devices, and the node communicates with the peripheral devices through the GPIO ports;

[0007] Each node is configured to convert the GPIO data on one or more GPIO ports of the node into local GPIO data, and an upstream node in any two nodes is configured to generate current GPIO confirmation data by confirming the local GPIO data of the upstream node with the local GPIO data or GPIO confirmation data of a downstream node.

[0008] In one or more embodiments of the present application, each of the nodes is configured to output initial GPIO data to un-enabled GPIO ports and output GPIO data to enabled GPIO ports to output local GPIO data.

[0009] In one or more embodiments of the present application, the upstream node in any two nodes comprises one or more confirmation modules configured to output current GPIO confirmation data based on local GPIO data of the current node and local GPIO data or GPIO confirmation data of the downstream node.

[0010] In one or more embodiments of the present application, the node comprises:

[0011] one or more local mapping output circuits configured to output GPIO data when the GPIO port in the current node is enabled based on control of the input enable signal and output corresponding initial GPIO data when the GPIO port in the current node is not enabled based on configuration of the conversion control signal at the same time, to output local GPIO data.

[0012] In one or more embodiments of the present application, the local mapping output circuit comprises a first logical AND gate, a second logical AND gate, a first logical NOT gate and a first logical OR gate, a first input end of the first logical AND gate is configured to receive the conversion control signal, a second input end of the first logical AND gate is connected with an output end of the first logical NOT gate, an input end of the first logical NOT gate is connected with a first input end of the second logical AND gate configured to receive the input enable signal, a second input end of the second logical AND gate is connected with a function bit corresponding to the GPIO port, a first input end of the first logical OR gate is connected with an output end of the first logical AND gate, a second input end of the first logical OR gate is connected with an output end of the second logical AND gate, and an output end of the first logical OR gate is configured to output the local GPIO data.

[0013] In one or more embodiments of the present application, the confirmation module comprises a fifth logical OR gate, one input end of the fifth logical OR gate is configured to receive the local GPIO data or the GPIO confirmation data of the downstream node, another input end of the fifth logical OR gate is configured to receive the local GPIO data of the current node, and an output end of the fifth logical OR gate outputs the current GPIO confirmation data.

[0014] In one or more embodiments of the present application, the confirmation module further comprises a ninth logic AND gate, a tenth logic AND gate, an eleventh logic AND gate and a fifth logic NOT gate, a first input terminal of the ninth logic AND gate and a second input terminal of the tenth logic AND gate are connected to an output terminal of the fifth logic NOT gate, an input terminal of the fifth logic NOT gate is configured to receive a conversion control signal, a second input terminal of the ninth logic AND gate and a second input terminal of the eleventh logic AND gate are configured to receive local GPIO data or GPIO confirmation data of a downstream node, a first input terminal of the tenth logic AND gate and a first input terminal of the eleventh logic AND gate are configured to receive local GPIO data of a current node, an output terminal of the ninth logic AND gate is connected to a first input terminal of a fifth logic OR gate, an output terminal of the tenth logic AND gate is connected to a second input terminal of the fifth logic OR gate, an output terminal of the eleventh logic AND gate is connected to a second input terminal of the fifth logic OR gate, and an output terminal of the fifth logic OR gate outputs current GPIO confirmation data.

[0015] The present application further discloses a GPIO communication method based on the low-latency GPIO communication system, the GPIO communication method comprising:

[0016] converting, by each of the nodes, GPIO data on one or more GPIO ports of the node into local GPIO data;

[0017] confirming, by an upstream node of any two nodes, the local GPIO data of the upstream node with local GPIO data or GPIO confirmation data of a downstream node to generate current GPIO confirmation data.

[0018] In one or more embodiments of the present application, each of the nodes performs initial GPIO data configuration output on a GPIO port that is not turned on and GPIO data output on a GPIO port that is turned on to output local GPIO data.

[0019] In one or more embodiments of the present application, one or more confirmation modules of an upstream node of any two nodes output current GPIO confirmation data based on local GPIO data of a current node and local GPIO data or GPIO confirmation data of a downstream node.

[0020] Compared with the prior art, the low-latency GPIO communication system and the communication method of the present application form low-latency GPIO communication through step-by-step confirmation in each node, thereby reducing the communication delay of the system and the complexity of system design without excessive participation of a master node and peripheral devices. The scheme has low cost, is easy to implement, consumes less resources, has low implementation cost, and has high controllability and flexible configuration. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0022] Fig. 1 is a system diagram of a low-latency GPIO communication system in an embodiment of the present application.

[0023] Fig. 2 is a circuit schematic diagram of a single node of a low-latency GPIO communication system in an embodiment of the present application.

[0024] Fig. 3 is a circuit schematic diagram of a local mapping output circuit in an embodiment of the present application.

[0025] Fig. 4 is a circuit schematic diagram of a confirmation module in an embodiment of the present application.

[0026] Fig. 5 is a flowchart of a GPIO communication method in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0028] In the specification, "coupling" or "connection" or "connection" includes both direct connection and indirect connection. Indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have parasitic inductance or parasitic capacitance; indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through circuits or components such as switches, follower circuits, etc. In addition, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0029] In the detailed description of the application, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various embodiments by which the subject matter described herein can be practiced. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, as the scope of the present disclosure is defined by the appended claims.

[0030] Various operations can be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations can not be performed in the order of presentation. Operations described can be performed in a different order than the described embodiment. Various additional operations can be performed and / or described operations can be omitted in additional embodiments.

[0031] For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0032] Various components, devices, etc. can be referred to herein in singular form, but this is not intended to exclude plural arrangements unless specifically stated otherwise. For example, a single component can be used in place of a plurality of components, or a plurality of components can be used in place of a single component.

[0033] The specification describes using the phrases "in one embodiment" or "in other embodiments" or "in some embodiments," which can each refer to one or more embodiments with the same or different embodiments, individually or collectively. Also, the use of the term "including", "containing", "having" and the like with respect to the disclosure are synonymous.

[0034] A low latency GPIO communication system in one embodiment of the present disclosure is capable of mapping GPIO data on GPIO ports of any node to GPIO ports of any node, and GPIO ports of multiple nodes can be collectively mapped to GPIO ports of one node, and such mapping can be configured to be logical OR or logical AND.

[0035] The low latency GPIO communication system includes a plurality of nodes connected via a bus. In one embodiment, the plurality of nodes are connected to form a multi-node daisy chain system as shown in FIG. 1, where the first node at the head of the system can be considered as a master node, the last node at the end of the system can be considered as a slave node, and each node in the middle section between the head and the end of the system can be considered as a slave node, and the number of nodes can be set as needed.

[0036] The data transmission from the master node to the end node is called down bus transmission, and the data transmission from the end node to the master node is called up bus transmission. The GPIO data collected from the peripheral device and input to the GPIO port is transmitted to the master node through up bus transmission, and then the down bus transmission updates the GPIO data output to the peripheral device by all GPIO ports.

[0037] Each node can convert the GPIO data on one or more GPIO ports of the node into local GPIO data, and an upstream node in any two nodes can confirm the local GPIO data of the upstream node with the local GPIO data or GPIO confirmation data of a downstream node to generate current GPIO confirmation data. In an embodiment, the conversion of the local GPIO data is implemented by performing initial GPIO data configuration output on the GPIO ports that are not turned on and performing GPIO data output on the GPIO ports that are turned on.

[0038] In an embodiment, it is noted that, since the end node has no downstream node, the end node outputs the local GPIO data of the end node to the upstream node, the slave node adjacent to the end node receives the local GPIO data output by the end node and confirms the local GPIO data output by the end node with the local GPIO data of the slave node to generate current GPIO confirmation data, and the master node and all other slave nodes confirm the local GPIO data of the nodes with the GPIO confirmation data of the downstream nodes to generate current GPIO confirmation data. The current GPIO confirmation data generated by the master node is a broadcast signal that can be used for down transmission.

[0039] In the embodiment shown in FIG. 2, each node includes at least one or more GPIO ports and one or more local mapping output circuits. In another embodiment, the master node and each slave node further include one or more confirmation modules, and the end node is not provided with a confirmation module (or is provided with a confirmation module but is not used). Each node is connected to an external device through a GPIO port. If the GPIO port is configured as an input GPIO port, the external device generates GPIO data which is transmitted to the node through the GPIO port, and if the GPIO port is configured as an output GPIO port, data can be output to the external device.

[0040] In the embodiment, each GPIO port of each node corresponds to a function bit and an enable bit, each function bit and each enable bit corresponds to a local mapping output circuit, and each GPIO port corresponds to a confirmation module.

[0041] The following is an example in which each node has four GPIO ports.

[0042] As shown in FIG. 2 and FIG. 3, four GPIO ports of each node correspond to four function bits Y1, Y2, Y3, Y4 and four enable bits Z1, Z2, Z3, Z4 respectively, and four local mapping output circuits 11, 12, 13, 14 are set, and four confirmation modules 21, 22, 23, 24 are set.

[0043] As to which function bit enables the output of GPIO data or which function bit is not enabled, it can be judged by whether the input enable signal is valid, and the input enable signal is output through an enable bit to enable the corresponding function bit.

[0044] In an embodiment, the local mapping output circuit is used to output the GPIO data when the GPIO port in the current node is enabled based on the control of the input enable signal, and output the corresponding initial GPIO data when the GPIO port in the current node is not enabled in combination with the configuration of the conversion control signal BUSINV, to finally output the local GPIO data.

[0045] When the enable bit and the function bit are enabled, the valid input enable signal output based on the enabled enable bit and the GPIO data output based on the enabled function bit are used to output the GPIO data, and when the enable bit is not enabled and the invalid input enable signal is output, the initial GPIO data is output based on the conversion control signal BUSINV and the invalid input enable signal output based on the disabled enable bit. The conversion control signal BUSINV can be a "1" signal or a "0" signal. In an embodiment, the invalid input enable signal is "0" and the valid input enable signal is "1".

[0046] As shown in FIG. 3, the four local mapping output circuits 11, 12, 13, 14, wherein the local mapping output circuit 11 has three input ends connected with the function bit Y1 and the enable bit Z1 respectively and simultaneously receiving the first conversion control signal BUSINV1, the local mapping output circuit 11 is used to output the first GPIO data based on the valid input enable signal output based on the enable bit Z1 and the GPIO data output based on the function bit Y1 when the enable bit Z1 outputs the valid input enable signal, and output the first initial GPIO data based on the first conversion control signal BUSINV1 and the invalid input enable signal output based on the enable bit Z1 when the enable bit Z1 outputs the invalid input enable signal, and the first GPIO data and the first initial GPIO data are combined to form the first local GPIO data LOCALMAP1.

[0047] The local mapping output circuit 12 has three input terminals connected with the function bit Y2 and the enable bit Z2 respectively and receiving the second conversion control signal BUSINV2 at the same time. The local mapping output circuit 12 is used to output the second GPIO data based on the valid input enable signal output by the enable bit Z2 and the GPIO data output by the function bit Y2 when the enable bit Z2 outputs the valid input enable signal, output the second initial GPIO data based on the second conversion control signal BUSINV2 and the invalid input enable signal output by the enable bit Z2 when the enable bit Z2 outputs the invalid input enable signal, and combine the second GPIO data and the second initial GPIO data to form the second local GPIO data LOCALMAP2.

[0048] The local mapping output circuit 13 has three input terminals connected with the function bit Y3 and the enable bit Z3 respectively and receiving the third conversion control signal BUSINV3 at the same time. The local mapping output circuit 13 is used to output the third GPIO data based on the valid input enable signal output by the enable bit Z3 and the GPIO data output by the function bit Y3 when the enable bit Z3 outputs the valid input enable signal, output the third initial GPIO data based on the third conversion control signal BUSINV3 and the invalid input enable signal output by the enable bit Z3 when the enable bit Z3 outputs the invalid input enable signal, and combine the third GPIO data and the third initial GPIO data to form the third local GPIO data LOCALMAP3.

[0049] The local mapping output circuit 14 has three input terminals connected with the function bit Y4 and the enable bit Z4 respectively and receiving the fourth conversion control signal BUSINV4 at the same time. The local mapping output circuit 14 is used to output the fourth GPIO data based on the valid input enable signal output by the enable bit Z4 and the GPIO data output by the function bit Y4 when the enable bit Z4 outputs the valid input enable signal, output the fourth initial GPIO data based on the fourth conversion control signal BUSINV4 and the invalid input enable signal output by the enable bit Z4 when the enable bit Z4 outputs the invalid input enable signal, and combine the fourth GPIO data and the fourth initial GPIO data to form the fourth local GPIO data LOCALMAP4.

[0050] As shown in FIG. 3, the four local mapping output circuits 11, 12, 13 and 14 have the same structure, and the difference mainly lies in the connected function bits and enable bits. Therefore, the structure of the local mapping output circuit 11 is taken as an example to be described in detail, and the structures of the local mapping output circuits 12, 13 and 14 are not described herein.

[0051] The local mapping output circuit 11 includes a first logic AND gate ND1, a second logic AND gate ND2, a first logic NOT gate AN1 and a first logic OR gate R1.

[0052] The first input end of the first logic AND gate ND1 is the first input end of the local mapping output circuit 11 for receiving the first conversion control signal BUSINV1, the second input end of the first logic AND gate ND1 is connected with the output end of the first logic NOT gate AN1, the input end of the first logic NOT gate AN1 is connected with the first input end of the second logic AND gate ND2 to form the second input end of the local mapping output circuit 11 for receiving the first input enable signal INEN1 on the enable bit Z1, the second input end of the second logic AND gate ND2 is the third input end of the local mapping output circuit 11 connected with the function bit Y1, at this time, the first input enable signal INEN1 output by the enable bit Z1 can be used as the selection enable signal of the function bit Y1 output data. The first input end of the first logic OR gate R1 is connected with the output end of the first logic AND gate ND1, the second input end of the first logic OR gate R1 is connected with the output end of the second logic AND gate ND2, and the output end of the first logic OR gate R1 is the output end of the local mapping output circuit 11 for outputting the first local GPIO data LOCALMAP1. In an embodiment, the first initial GPIO data is "1" or "0".

[0053] The local mapping output circuits 12, 13 and 14 obtain three local GPIO data, and thus a set of local GPIO data of the current node is obtained, and the master node obtains the local GPIO data in the same way as the slave node.

[0054] For the unopened function bit, the initial value needs to be determined to avoid the interference of the signal output by the unopened function bit on the subsequent logic mapping relationship, and the first conversion control signal BUSINV1 is configured through the link conversion register; when the first conversion control signal BUSINV1 is configured as "0", the first logic AND gate ND1 outputs "0", and based on the unopened enable bit Z1, the output of the second logic AND gate ND2 is also "0", and at this time, the output of the first logic OR gate R1 is "0"; when the first conversion control signal BUSINV1 is configured as "1", based on the unopened enable bit Z1, the first logic AND gate ND1 outputs "1", and the output of the first logic OR gate R1 is "1".

[0055] Therefore, when the enable bit Z1 is unopened, the output of the first logic OR gate R1 depends on the configuration value of the first conversion control signal BUSINV1, and by configuring the first conversion control signal BUSINV1 as "0" or "1", the first initial GPIO data of "0" or "1" output by the first logic OR gate R1 is determined to determine the initial value; when the enable bit Z1 is opened, the output of the first logic OR gate R1 depends on the signal on the function bit Y1, that is, the first logic OR gate R1 outputs the first local GPIO data LOCALMAP1, and the principles of the local mapping output circuits 12, 13 and 14 are the same.

[0056] In an embodiment, the confirmation module is configured to perform a logical operation on the local GPIO data output by the local mapping output circuit of the current node and the data output by the downstream node based on the control of the conversion control signal BUSINV to output the current GPIO confirmation data. The data output by the downstream node is the local GPIO data or the GPIO confirmation data of the downstream node.

[0057] As shown in FIG. 4, there are four confirmation modules 21, 22, 23, 24. The confirmation module 21 has three input terminals respectively receiving the first conversion control signal BUSINV1, the first local GPIO data LOCALMAP1 output by the local mapping output circuit 11, and the data DOWNMP1 output by the downstream node. The confirmation module 21 is configured to output the first current GPIO confirmation data UPMAP1 based on the first conversion control signal BUSINV1, the first local GPIO data LOCALMAP1, and the data DOWNMP1 output by the downstream node.

[0058] The confirmation module 22 has three input terminals respectively receiving the second conversion control signal BUSINV2, the second local GPIO data LOCALMAP2 output by the local mapping output circuit 12, and the data DOWNMP2 output by the downstream node. The confirmation module 22 is configured to output the second current GPIO confirmation data UPMAP2 based on the second conversion control signal BUSINV2, the second local GPIO data LOCALMAP2, and the data DOWNMP2 output by the downstream node.

[0059] The confirmation module 23 has three input terminals respectively receiving the third conversion control signal BUSINV3, the third local GPIO data LOCALMAP3 output by the local mapping output circuit 13, and the data DOWNMP3 output by the downstream node. The confirmation module 23 is configured to output the third current GPIO confirmation data UPMAP3 based on the third conversion control signal BUSINV3, the third local GPIO data LOCALMAP3, and the data DOWNMP3 output by the downstream node.

[0060] The confirmation module 24 has three input terminals respectively receiving the fourth conversion control signal BUSINV4, the fourth local GPIO data LOCALMAP4 output by the local mapping output circuit 14, and the data DOWNMP4 output by the downstream node. The confirmation module 24 is configured to output the fourth current GPIO confirmation data UPMAP4 based on the fourth conversion control signal BUSINV4, the fourth local GPIO data LOCALMAP4, and the data DOWNMP4 output by the downstream node.

[0061] As can be seen from Fig. 4, the four confirmation modules 21, 22, 23 and 24 have the same structure, and thus the structure of the confirmation module 21 will be described in detail as an example, and the structures of the confirmation modules 22, 23 and 24 will not be described herein.

[0062] The confirmation module 21 comprises a ninth logical AND gate ND9, a tenth logical AND gate ND10, an eleventh logical AND gate ND11, a fifth logical NOT gate AN5 and a fifth logical OR gate R5. The first input terminal of the ninth logical AND gate ND9 and the second input terminal of the tenth logical AND gate ND10 are connected to the output terminal of the fifth logical NOT gate AN5, and the input terminal of the fifth logical NOT gate AN5 is configured to receive the conversion control signal BUSINV. The second input terminal of the ninth logical AND gate ND9 and the second input terminal of the eleventh logical AND gate ND11 are connected to receive the data DOWNMAP1 output by the downstream node. The first input terminal of the tenth logical AND gate ND10 and the first input terminal of the eleventh logical AND gate ND11 are configured to receive the first local GPIO data LOCALMAP1 output by the first local mapping output circuit 11 of the current node. The output terminal of the ninth logical AND gate ND9 is connected to the first input terminal of the fifth logical OR gate R5, the output terminal of the tenth logical AND gate ND10 is connected to the second input terminal of the fifth logical OR gate R5, and the output terminal of the eleventh logical AND gate ND11 is connected to the third input terminal of the fifth logical OR gate R5. The output terminal of the fifth logical OR gate R5 outputs the first current GPIO confirmation data UPMAP1.

[0063] By configuring the first conversion control signal BUSINV1 to be different values, different first current GPIO confirmation data UPMAP1 can be generated. In the confirmation module 21, when the data DOWNMP1 transmitted by the upstream bus of the downstream node is received, the first local GPIO data LOCALMAP1 output by the local mapping output circuit 11 is controlled by configuring the first conversion control signal BUSINV1 to perform AND logic or OR logic operation with the data DOWNMP1 to generate the first current GPIO confirmation data UPMAP1, so as to confirm the corresponding data finally output by the GPIO port in the current node. The principles of the confirmation modules 22, 23 and 24 are the same, and the confirmation modules 22, 23 and 24 generate a total of three current GPIO confirmation data. Thus, a set of current GPIO confirmation data of the current node is obtained, and the master node obtains the current GPIO confirmation data in the same manner as the slave node, and the current GPIO confirmation data obtained by the master node can be a broadcast signal.

[0064] If the first conversion control signal BUSINV1 is configured as "0", the ninth logical AND gate ND9 outputs the data DOWNMP1, the tenth logical AND gate ND10 outputs the first local GPIO data LOCALMAP1 outputted by the local mapping output circuit 11, the eleventh logical AND gate ND11 outputs the data DOWNMP1 and the first local GPIO data LOCALMAP1 outputted by the local mapping output circuit 11 after logical AND operation, and finally, the fifth logical OR gate R5 outputs the first current GPIO confirmation data UPMAP1 after logical OR operation of the data DOWNMP1, the first local GPIO data LOCALMAP1 outputted by the local mapping output circuit 11 and the data outputted by the eleventh logical AND gate ND11.

[0065] If the first conversion control signal BUSINV1 is configured as "1", the ninth logical AND gate ND9 outputs "0", the tenth logical AND gate ND10 outputs "0", the eleventh logical AND gate ND11 outputs the data DOWNMP1 and the first local GPIO data LOCALMAP1 outputted by the local mapping output circuit 11 after logical AND operation, and the output of the fifth logical OR gate R5 depends on the output of the eleventh logical AND gate ND11.

[0066] The first current GPIO confirmation data UPMAP1 of the current node is the signal transmitted by the upstream bus, i.e. the signal received by the confirmation module of the upstream node. During the upstream bus transmission, each node performs corresponding operation, so that mutual confirmation during the transmission can be ensured. Each node performs the same operation, so that the final output GPIO information can be confirmed at the node.

[0067] In addition, if the next node adjacent to the current node is the end node, the data DOWNMP1 outputted by the end node is the local GPIO data outputted by the corresponding local mapping output circuit in the end node, because the end node has no confirmation module. If the downstream node of the current node is the slave node, the data DOWNMP1 outputted by the downstream node is the signal outputted by the corresponding confirmation module in the downstream node.

[0068] It should be noted that, in order to ensure low delay of the GPIO communication, the data DOWNMP1 received by the uplink bus transmission needs to be temporarily stored in each node in the step-by-step confirmation of the confirmation module. If the data output by the local mapping output circuit of the current node is updated, the temporarily stored data DOWNMP1 will be subjected to AND logic or OR logic, and the result will be output. In this way, no additional repeated confirmation is needed, and only a simple logical operation is needed in the current node to confirm the new output result. In addition, in the local mapping output circuit, the initial value of the data output by the local mapping output circuit needs to be set for the unopened enable bit, that is, for the unopened corresponding GPIO transmission function. When the first conversion control signal BUSINV1 is configured as "0", the initial value is "0"; when the first conversion control signal BUSINV1 is configured as "1", the initial value is "1", so that no interference will occur in the logical operation of the confirmation module.

[0069] In other embodiments, taking the confirmation module 21 as an example, only one fifth logic OR gate with two input ends can be provided, one input end of the fifth logic OR gate is used to receive the local GPIO data or the GPIO confirmation data of the downstream node, and the other input end is used to receive the local GPIO data of the current node, and the output end of the fifth logic OR gate outputs the current GPIO confirmation data corresponding to the current node.

[0070] In an embodiment, the low-delay GPIO communication system further comprises a master control module, as shown in FIG. 2, each node further comprises a control module and a link transceiver. The link transceiver is used for signal transmission between the current node and the upstream and downstream nodes. The control module is used for configuring various selection signals, conversion control signals and enable signals to realize function configuration and ensure normal communication. The control module comprises various registers used for configuration.

[0071] The master control module directly accesses the control module of the master node through an I2C interface or remotely accesses the control modules of the slave nodes and the end nodes through the I2C interface to interact, so as to obtain configuration information or transmit the configuration information to the control module. The interaction of the slave nodes and the end nodes needs to be forwarded and transmitted by the link transceiver. The control module can configure the input and output functions of the GPIO port, confirm the mapping relationship of the GPIO port, and confirm the AND logic or OR logic relationship in the step-by-step confirmation. The I2C interface supports clock extension function.

[0072] As shown in FIG. 5, the application further discloses a GPIO communication method based on the above low-delay GPIO communication system, the GPIO communication method comprising:

[0073] The GPIO data on one or more GPIO ports of each node is converted into local GPIO data. In the conversion process, the un-enabled GPIO ports are configured with initial GPIO data by each node.

[0074] Specifically, the GPIO data is outputted on the GPIO ports in the current node by one or more local mapping output circuits based on the control of the input enable signal when the GPIO ports are enabled, and the corresponding initial GPIO data is outputted on the GPIO ports in the current node by the configuration of the conversion control signal when the GPIO ports are not enabled.

[0075] The local GPIO data of the upstream node in any two nodes is confirmed with the local GPIO data or the GPIO confirmation data of the downstream node to generate the current GPIO confirmation data.

[0076] The GPIO data on one or more GPIO ports of the upstream node in any two nodes is confirmed with the GPIO data or the GPIO confirmation data of the downstream node to generate the current GPIO confirmation data transmitted to the upstream node. Specifically, the current GPIO confirmation data is outputted by one or more confirmation modules in the upstream node in any two nodes based on the GPIO data of the current node and the GPIO data or the GPIO confirmation data of the downstream node.

[0077] In an embodiment, the GPIO data on one or more GPIO ports of the last node is converted to generate the local GPIO data transmitted to the upstream node, and / or the broadcast signal of the upstream node is transmitted to the one or more GPIO ports of the last node.

[0078] The GPIO data on one or more GPIO ports of the slave node is converted to generate the local GPIO data to be confirmed with the local GPIO data of the last node downstream or the GPIO confirmation data of the slave node downstream to generate the current GPIO confirmation data transmitted to the upstream node.

[0079] The GPIO data on one or more GPIO ports of the master node is converted to generate the local GPIO data to be confirmed with the GPIO confirmation data or the GPIO data of the downstream node to generate the current GPIO confirmation data transmitted to the downstream node.

[0080] In the master node, the current GPIO confirmation data (broadcast signal) transmitted to the downstream node is generated by the confirmation module based on the local GPIO data of the current node and the local GPIO data or the GPIO confirmation data of the downstream node.

[0081] In the slave node, the acknowledgment module outputs the current GPIO acknowledgment data based on the local GPIO data of the current node and the local GPIO data or GPIO acknowledgment data of the downstream node.

[0082] During signal uplink transmission, each node can acknowledge the GPIO data or GPIO acknowledgment data of the downstream node, thus forming a step-by-step acknowledgment process.

[0083] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0084] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A low latency GPIO communication system, characterized by, The application relates to a node system comprising a plurality of connected nodes, wherein each node comprises one or more GPIO ports for connecting with peripheral devices, and each node communicates with peripheral devices through the GPIO ports; wherein each node is configured to convert GPIO data on one or more GPIO ports of the node into local GPIO data, and an upstream node in any two nodes is configured to generate current GPIO validation data by validating the local GPIO data of the upstream node with the local GPIO data or GPIO validation data of a downstream node. Each node is configured to perform initial GPIO data configuration output on a non-enabled GPIO port and GPIO data output on an enabled GPIO port to output the local GPIO data. An upstream node in any two nodes comprises one or more validation modules configured to output current GPIO validation data based on the local GPIO data of the current node and the local GPIO data or GPIO validation data of a downstream node.

2. The low-latency GPIO communication system of claim 1, wherein, The node comprises one or more local mapping output circuits configured to output GPIO data when a GPIO port in the current node is enabled based on control of an input enable signal, and output corresponding initial GPIO data when the GPIO port in the current node is not enabled based on configuration of a conversion control signal, so as to output the local GPIO data.

3. The low-latency GPIO communication system of claim 1, wherein, The local mapping output circuit comprises a first logical AND gate, a second logical AND gate, a first logical NOT gate and a first logical OR gate, wherein a first input end of the first logical AND gate is configured to receive the conversion control signal, a second input end of the first logical AND gate is connected with an output end of the first logical NOT gate, an input end of the first logical NOT gate is connected with a first input end of the second logical AND gate for receiving the input enable signal, a second input end of the second logical AND gate is connected with a function bit corresponding to the GPIO port, a first input end of the first logical OR gate is connected with an output end of the first logical AND gate, a second input end of the first logical OR gate is connected with an output end of the second logical AND gate, and an output end of the first logical OR gate is configured to output the local GPIO data.

4. The low-latency GPIO communication system of claim 2, wherein, The validation module comprises a fifth logical OR gate, one input end of the fifth logical OR gate is configured to receive the local GPIO data or GPIO validation data of a downstream node, and the other input end is configured to receive the local GPIO data of the current node, and an output end of the fifth logical OR gate outputs the current GPIO validation data. ​ 5. The low-latency GPIO communication system of claim 4, wherein, ​ 6. The low-latency GPIO communication system of claim 3, wherein, ​ 7. The low-latency GPIO communication system of claim 6, wherein, The confirmation module further comprises a ninth logic AND gate, a tenth logic AND gate, an eleventh logic AND gate and a fifth logic NOT gate, a first input terminal of the ninth logic AND gate and a second input terminal of the tenth logic AND gate are connected with an output terminal of the fifth logic NOT gate, an input terminal of the fifth logic NOT gate is used for receiving a conversion control signal, a second input terminal of the ninth logic AND gate and a second input terminal of the eleventh logic AND gate are used for receiving local GPIO data or GPIO confirmation data of a downstream node, a first input terminal of the tenth logic AND gate and a first input terminal of the eleventh logic AND gate are used for receiving local GPIO data of a current node, an output terminal of the ninth logic AND gate is connected with a first input terminal of a fifth logic OR gate, an output terminal of the tenth logic AND gate is connected with a second input terminal of the fifth logic OR gate, an output terminal of the eleventh logic AND gate is connected with a second input terminal of the fifth logic OR gate, and an output terminal of the fifth logic OR gate outputs current GPIO confirmation data.

8. A GPIO communication method, characterized by, The GPIO communication method based on the low-delay GPIO communication system according to any one of claims 1-7 comprises: converting, by each node, GPIO data on one or more GPIO ports of the node into local GPIO data; confirming, by an upstream node of any two nodes, the local GPIO data of the upstream node with local GPIO data or GPIO confirmation data of a downstream node to generate current GPIO confirmation data.

9. The GPIO communication method of claim 8, wherein, initially configuring and outputting, by each node, GPIO data of a GPIO port that is not turned on and outputting GPIO data of a GPIO port that is turned on to output local GPIO data.

10. The GPIO communication method of claim 8, wherein, outputting, by one or more confirmation modules of an upstream node of any two nodes, current GPIO confirmation data based on local GPIO data of a current node and local GPIO data or GPIO confirmation data of a downstream node. outputting, by one or more confirmation modules of an upstream node of any two nodes, current GPIO confirmation data based on local GPIO data of a current node and local GPIO data or GPIO confirmation data of a downstream node.

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