Semiconductor module

Abstract

Disclosed in the present application is a semiconductor module, comprising: an inverter chip which comprises a first high-side inverter chip and a second high-side inverter chip arranged opposite each other in a first direction; and a first jumper area located between the first high-side inverter chip and the second high-side inverter chip in the first direction, wherein only the first jumper area is provided in an area jointly enclosed by a first edge connection, a second edge connection, a third edge connection and a fourth edge connection. Therefore, an effective area on a first substrate portion for arranging the first high-side inverter chip and the second high-side inverter chip can be increased, such that a large-sized inverter chip can be provided in the semiconductor module, thereby improving the current-carrying capability of the semiconductor module.

Description

Semiconductor module

[0001] The present application refers to the technical field of semiconductor technology, in particular to a semiconductor module. TECHNICAL FIELD

[0002] The present application refers to the technical field of semiconductor technology, in particular to a semiconductor module. BACKGROUND

[0003] With the development of semiconductor chip technology and packaging technology, high-power semiconductor modules are increasingly widely used. A power module PIM (Power Integrated Module) is a product that integrates three-phase inverter circuit, diode bridge circuit and brake circuit into one module, which can design the main circuit compactly.

[0004] In the related art, the structure design in the PIM is not reasonable enough, and the space for arranging internal components is limited, which can result in that a chip with a larger specification cannot be arranged in the PIM, and further result in that the current-carrying capacity of the PIM is limited. In addition, the space inside the semiconductor module is limited, and the inductance of the chip is large, which can easily cause a spike voltage at both ends of the chip and cause the chip to fail. TECHNICAL PROBLEM

[0005] In the related art, the structure design in the PIM is not reasonable enough, and the space for arranging internal components is limited, which can result in that a chip with a larger specification cannot be arranged in the PIM, and further result in that the current-carrying capacity of the PIM is limited. TECHNICAL SOLUTION

[0006] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, one object of the present application is to provide a semiconductor module which can be provided with a larger specification inverter chip.

[0007] The first aspect of the embodiment of the present application provides a semiconductor module, the semiconductor module has a first direction and a second direction and a high side and a low side oppositely arranged in the second direction, and the semiconductor module comprises: a shell; a substrate arranged in the shell, the substrate has a first substrate part and a second substrate part arranged in sequence and spaced apart along the first direction, the first substrate part is provided with a first high-side inverter chip-on-chip area and a first low-side inverter chip-on-chip area arranged in sequence and spaced apart along the second direction, and the first high-side inverter chip-on-chip area is more adjacent to the high side relative to the first low-side inverter chip-on-chip area, and the second substrate part is provided with a second high-side inverter chip-on-chip area, a third low-side inverter chip-on-chip area and a second low-side inverter chip-on-chip area arranged in sequence and spaced apart along the second direction, and the second high-side inverter chip-on-chip area is more adjacent to the high side relative to the second low-side inverter chip-on-chip area; a plurality of inverter chips, each of the inverter chips is a single chip, each of the inverter chips is provided with a control electrode pad, a first load electrode pad and a second load electrode pad, the plurality of inverter chips comprises a first high-side inverter chip, a second high-side inverter chip, a third high-side inverter chip, a first low-side inverter chip, a second low-side inverter chip and a third low-side inverter chip, the first high-side inverter chip and the second high-side inverter chip are arranged in the first high-side inverter chip-on-chip area and spaced apart along the first direction, the first high-side inverter chip is more away from the second substrate part in the first direction than the second high-side inverter chip, the third high-side inverter chip is arranged in the second high-side inverter chip-on-chip area, the first low-side inverter chip is arranged in the first low-side inverter chip-on-chip area, the second low-side inverter chip is arranged in the second low-side inverter chip-on-chip area, and the third low-side inverter chip is arranged in the third low-side inverter chip-on-chip area; wherein the first high-side inverter chip and the second high-side inverter chip are arranged more adjacent to the high side along the second direction in the first high-side inverter chip-on-chip area, the first high-side inverter chip-on-chip area is provided with a avoiding gap, the avoiding gap is provided with a first jumper area extending along the second direction, the first jumper area is arranged in the first high-side inverter chip-on-chip area, at least a part of the first jumper area is located between the first high-side inverter chip and the second high-side inverter chip in the first direction, the edge of the first high-side inverter chip adjacent to the second high-side inverter chip in the first direction is defined as a first edge, the edge of the second high-side inverter chip adjacent to the first high-side inverter chip in the first direction is defined as a second edge, the edge of the first high-side inverter chip adjacent to the low side in the second direction is defined as a third edge, the edge of the first high-side inverter chip adjacent to the high side in the second direction is defined as a fourth edge, the edge of the second high-side inverter chip adjacent to the low side in the second direction is defined as a fifth edge, and the edge of the second high-side inverter chip adjacent to the high side in the second direction is defined as a sixth edge.The one of the third edge and the fifth edge that is closer to the low side is set as a low-side edge, the one of the fourth edge and the sixth edge that is closer to the high side is set as a high-side edge, the extension line of the first edge, the extension line of the second edge, the extension line of the high-side edge and the extension line of the low-side edge together enclose a spacing region, and the first jumper region is arranged only in a portion of the spacing region corresponding to the avoidance gap; the second load electrode pad of the first high-side inverter chip is connected with the first jumper region through a conductive member, the control electrode pad of the first high-side inverter chip is arranged closer to the high side along the second direction on the first high-side inverter chip, and the control electrode pad of the first high-side inverter chip is electrically connected with an external terminal.

[0008] Therefore, by arranging the first jumper region only in the portion of the avoidance gap corresponding to the spacing region, the effective area of the first substrate portion for arranging the first high-side inverter chip and the second high-side inverter chip can be increased, so that a larger specification inverter chip can be arranged in the semiconductor module to improve the current-carrying capacity of the semiconductor module.

[0009] In some examples of the present application, the first substrate portion further comprises a second jumper region arranged in the avoidance gap, the edge of the first high-side inverter chip that is closer to the high side in the second direction is set as a high-side edge, the second jumper region is arranged on the side of the high-side edge in the second direction that faces the high side, the second jumper region is located on the side of the first jumper region that is away from the second substrate portion in the first direction, the control electrode pad of the first high-side inverter chip is connected with the second jumper region through a conductive member, and the second jumper region is connected with an external terminal through a conductive member.

[0010] In some examples of the present application, the first high-side inverter chip and the second high-side inverter chip are arranged opposite to each other in the first direction, and the projections of the first high-side inverter chip and the second high-side inverter chip in the first direction completely overlap.

[0011] In some examples of the present application, the size of the portion of the first jumper region between the first high-side inverter chip and the second high-side inverter chip in the first direction is L1, and L1 satisfies the relationship: 1.7mm≤L1≤3.2mm.

[0012] In some examples of the present application, the first substrate portion has a dimension A1 in the second direction; a distance B1 between the first high-side inverter chip and an edge of the first substrate portion facing the high side, A1 and B1 satisfying a relationship: 0.086A1≤B1≤0.117A1; and a distance C1 between the second high-side inverter chip and the edge of the first substrate portion facing the high side, A1 and C1 satisfying a relationship: 0.086A1≤C1≤0.117A1.

[0013] In some examples of the present application, the control electrode pad of the first high-side inverter chip is disposed more proximate to a side of the first high-side inverter chip distal to the second substrate portion in the first direction on the first high-side inverter chip.

[0014] In some examples of the present application, the first high-side inverter chip has a control electrode flow channel, the second load electrode pad of the first high-side inverter chip includes two sub load electrode pads, the control electrode flow channel is disposed between the two sub load electrode pads, and the control electrode flow channel of the first high-side inverter chip extends in the first direction.

[0015] In some examples of the present application, the first jumper region is located in a middle portion of the first high-side inverter chip in the first direction.

[0016] In some examples of the present application, the first substrate portion further has a third jumper region connected to an end of the first jumper region proximate to the first low-side inverter chip on-chip region, the third jumper region extending from the first jumper region in the first direction toward a direction distal to the second substrate portion, and the third jumper region and the first low-side inverter chip on-chip region being connected by a conductive member.

[0017] In some examples of the present application, the first low-side inverter chip is disposed more proximate to the second substrate portion in the first direction on the first low-side inverter chip on-chip region, and a side of the first low-side inverter chip on-chip region distal to the second substrate portion is connected to the third jumper region by a conductive member.

[0018] In some examples of the present application, the first substrate portion further has a fourth jumper region connected to an end of the first jumper region distal to the first low-side inverter chip on-chip region, the fourth jumper region extending from the first jumper region in the first direction toward the second substrate portion.

[0019] In some examples of the present application, the third high-side inverter chip is located in a middle portion of the second substrate portion in the first direction.

[0020] In some examples of the present application, the control electrode pad of the third high-side inversion chip is disposed more proximate to the high side in the second direction on the third high-side inversion chip; the control electrode pad of the third high-side inversion chip is disposed more proximate to the first substrate portion in the first direction on the third high-side inversion chip.

[0021] In some examples of the present application, the third high-side inversion chip has a control electrode flow channel, the second load electrode pad of the third high-side inversion chip includes two sub load electrode pads, the control electrode flow channel is disposed between the two sub load electrode pads, and the control electrode flow channel of the third high-side inversion chip extends in the first direction.

[0022] In some examples of the present application, a fifth jumper wire area is further disposed on the second substrate portion, the fifth jumper wire area is located on a side of the second high-side inversion chip away from the first substrate portion in the first direction, and a conductive member is connected between the control electrode pad of the third high-side inversion chip and the fifth jumper wire area.

[0023] In some examples of the present application, the substrate includes a first sub substrate and a second sub substrate arranged in sequence and spaced apart in the first direction, the first substrate portion is disposed on the first sub substrate, and the second substrate portion is disposed on the second sub substrate.

[0024] In some examples of the present application, the substrate further has a third substrate portion, the third substrate portion is disposed on a side of the first substrate portion away from the second substrate portion in the first direction, and the third substrate portion is provided with a brake unit upper core area and a rectifier unit upper core area.

[0025] In some examples of the present application, the substrate includes a third sub substrate, the third sub substrate is disposed on a side of the first sub substrate away from the second sub substrate in the first direction, and the third substrate portion is disposed on the third sub substrate.

[0026] The second aspect of the embodiments of the present application further provides a semiconductor module, the semiconductor module having a first direction and a second direction and a high side and a low side oppositely arranged in the second direction, the semiconductor module comprising: a shell; a substrate arranged in the shell, the substrate having a first substrate part, a second substrate part and a third substrate part sequentially and spaced arranged along the first direction, the third substrate part being provided with a brake chip-on-chip area and a rectifier chip-on-chip area, the first substrate part being provided with a first high-side inverter chip-on-chip area and a first low-side inverter chip-on-chip area spaced arranged along the second direction, and the first high-side inverter chip-on-chip area being more adjacent to the high side relative to the first low-side inverter chip-on-chip area, the second substrate part being provided with a second high-side inverter chip-on-chip area, a third low-side inverter chip-on-chip area and a second low-side inverter chip-on-chip area sequentially and spaced arranged along the second direction, and the second high-side inverter chip-on-chip area being more adjacent to the high side relative to the second low-side inverter chip-on-chip area; a plurality of inverter chips, each of the inverter chips being a single chip, each of the inverter chips being provided with a control electrode pad, a first load electrode pad and a second load electrode pad, the plurality of inverter chips including a first high-side inverter chip, a second high-side inverter chip, a third high-side inverter chip, a first low-side inverter chip, a second low-side inverter chip and a third low-side inverter chip, the first high-side inverter chip and the second high-side inverter chip being arranged in the first high-side inverter chip-on-chip area and spaced arranged along the first direction, the first high-side inverter chip being more away from the second substrate part in the first direction relative to the second high-side inverter chip, the third high-side inverter chip being arranged in the second high-side inverter chip-on-chip area, the first low-side inverter chip being arranged in the first low-side inverter chip-on-chip area, the second low-side inverter chip being arranged in the second low-side inverter chip-on-chip area, and the third low-side inverter chip being arranged in the third low-side inverter chip-on-chip area; wherein the first low-side inverter chip-on-chip area includes a wiring part and an upper chip part connected to each other, the wiring part and the upper chip part are arranged along the first direction, and the upper chip part is located on a side of the wiring part facing the second substrate part, the first low-side inverter chip is arranged in the upper chip part, a side of the upper chip part facing the low side protrudes toward the low side relative to a side of the wiring part facing the low side to form a first avoiding gap, a first jumper area is arranged in the first avoiding gap, the first jumper area is arranged adjacent to the upper chip part in the first direction and adjacent to the wiring part in the second direction, and a conductive member is connected between the first jumper area and the control electrode pad of the brake chip; the control electrode pad of the first low-side inverter chip is arranged more adjacent to the low side on the first low-side inverter chip along the second direction, and the control electrode pad of the first low-side inverter chip is arranged more adjacent to the third substrate part on the first low-side inverter chip along the first direction.The sum of the sizes of the upper core portion and the wiring portion in the first direction is A2, and the size of the upper core portion in the first direction is B2, A2 and B2 satisfy the relationship: B2≥0.5A2.

[0027] Therefore, by setting the first low-side inverter chip as a single chip, arranging the upper core portion of the first low-side inverter chip on the upper core region close to the third substrate portion, and making the size of the upper core portion in the first direction at least half of the size of the upper core region of the first low-side inverter chip in the first direction, the effective area of the second substrate portion for setting the first low-side inverter chip can be increased, so that a larger specification inverter chip can be set in the semiconductor module to improve the current-carrying capacity of the semiconductor module.

[0028] In some examples of the present application, B2 satisfies the relationship: B2≥9.27mm.

[0029] In some examples of the present application, the first low-side inverter chip has a control electrode flow channel, the second load electrode pad of the first low-side inverter chip includes two sub-load electrode pads, the control electrode flow channel is arranged between the two sub-load electrode pads, and the control electrode flow channel of the first low-side inverter chip extends along the second direction.

[0030] In some examples of the present application, a conductive member is also connected between the first jumper region and the external terminal, and the size of the first jumper region in the first direction is C2, which satisfies the relationship: C2≥4.4mm.

[0031] In some examples of the present application, the upper core region of the first high-side inverter chip is provided with a second avoiding gap, the second avoiding gap is provided with a second jumper region, the second jumper region includes a first jumper area and a second jumper area, the first jumper area is arranged to extend in the second direction and is located between the first high-side inverter chip and the second high-side inverter chip in the first direction, the second jumper area is connected to one end of the first jumper area that is more adjacent to the low side in the second direction, the second jumper area is arranged to extend towards a side that is more adjacent to the third substrate portion in the first direction, and a conductive member is connected between the first jumper area and the first high-side inverter chip; a conductive member is connected between the wiring portion and the second jumper area.

[0032] In some examples of the present application, the first substrate portion is further provided with a third jumper area, the third jumper area includes a third jumper region, a fourth jumper region and a fifth jumper region, the third jumper region is arranged at a side of the first low-side inversion chip-on-chip region adjacent to the low side in the second direction, the third jumper region is arranged extending in the first direction, the fourth jumper region and the fifth jumper region are respectively connected at two ends of the third jumper region in the first direction, the fourth jumper region and the fifth jumper region are arranged extending towards a side more adjacent to the high side in the second direction, a third avoiding gap is arranged at a side of the first high-side inversion chip-on-chip region adjacent to the second substrate portion in the first direction, the third avoiding gap is located at an end of the first high-side inversion chip-on-chip region more adjacent to the low side in the second direction, and an end of the fifth jumper region adjacent to the high side in the second direction at least partially extends into the third avoiding gap.

[0033] In some examples of the present application, the first high-side inversion chip and the second high-side inversion chip are both arranged more adjacent to the high side in the second direction on the first high-side inversion chip-on-chip region, a conductive member is connected between the second load electrode pad of the first high-side inversion chip and the second jumper area, and the control electrode pad of the first high-side inversion chip is arranged more adjacent to the high side on the first high-side inversion chip in the second direction, and the control electrode pad of the first high-side inversion chip is electrically connected with an external terminal.

[0034] In some examples of the present application, the first substrate portion is further provided with a fourth jumper area, the fourth jumper area is arranged in the second avoiding gap, a high-side edge of the first high-side inversion chip is defined as a high-side edge, the fourth jumper area is arranged at a side of the high-side edge adjacent to the high side in the second direction, the fourth jumper area is arranged at a side of the first jumper region away from the second substrate portion in the first direction, the control electrode pad of the first high-side inversion chip is arranged more adjacent to the high side on the first high-side inversion chip in the second direction, the control electrode pad of the first high-side inversion chip is arranged at a side of the first high-side inversion chip more away from the second substrate portion in the first direction, a conductive member is connected between the control electrode pad of the first high-side inversion chip and the fourth jumper area, and a conductive member is connected between the fourth jumper area and an external terminal.

[0035] In some examples of the present application, the second jumper area further comprises a sixth jumper area connected to one end of the first jumper area adjacent to the high side in the second direction, the sixth jumper area extends towards the side of the first substrate portion adjacent to the high side in the first direction, and a conductive member is connected between the sixth jumper area and an external terminal.

[0036] In some examples of the present application, the first substrate portion has a dimension D2 in the second direction, a distance E2 between the first high side inverter chip and the edge of the first substrate portion facing the high side, and a distance F2 between the second high side inverter chip and the edge of the first substrate portion facing the high side, and D2, E2 and F2 satisfy the relationship: 0.086D2≤E2≤0.117D2 and 0.086D2≤F2≤0.117D2.

[0037] In some examples of the present application, the third high side inverter chip is located in the middle of the second substrate portion in the first direction.

[0038] In some examples of the present application, the control electrode pad in the third high side inverter chip is arranged more adjacent to the high side in the second direction on the third high side inverter chip, and the control electrode pad in the third high side inverter chip is arranged more adjacent to the first substrate portion in the first direction on the third high side inverter chip.

[0039] In some examples of the present application, the third high side inverter chip has a control electrode flow channel, the second load electrode pad of the third high side inverter chip comprises two sub-load electrode pads, the control electrode flow channel is arranged between the two sub-load electrode pads, and the control electrode flow channel of the third high side inverter chip extends in the first direction.

[0040] In some examples of the present application, a fifth jumper area is further arranged on the second substrate portion, the fifth jumper area is arranged apart from the side of the second high side inverter chip farther away from the first substrate portion in the first direction, a conductive member is connected between the control electrode pad of the third high side inverter chip and the fifth jumper area, and a conductive member is connected between the fifth jumper area and an external terminal.

[0041] In some examples of the present application, the substrate comprises a first sub-substrate, a second sub-substrate and a third sub-substrate arranged in sequence and spaced apart in the first direction, the third substrate portion is arranged on the first sub-substrate, the first substrate portion is arranged on the second sub-substrate, and the second substrate portion is arranged on the third sub-substrate.

[0042] A semiconductor module is further provided in the third aspect of the present application, which can reduce inductance.

[0043] The semiconductor module according to the embodiments of the present application has a first direction and a second direction, and a high side and a low side oppositely arranged in the second direction, and comprises: a housing; a substrate arranged in the housing, the substrate having a first substrate portion and a second substrate portion arranged in sequence along the first direction, the first substrate portion being provided with first high-side inverter chip-on-core regions and first low-side inverter chip-on-core regions arranged in sequence along the second direction, and the first high-side inverter chip-on-core regions being closer to the high side than the first low-side inverter chip-on-core regions; a plurality of inverter chips, each of the inverter chips being a single chip, each of the inverter chips being provided with a control electrode pad, a first load electrode pad and a second load electrode pad, the plurality of inverter chips including a first high-side inverter chip, a second high-side inverter chip, a third high-side inverter chip, a first low-side inverter chip, a second low-side inverter chip and a third low-side inverter chip, the first high-side inverter chip and the second high-side inverter chip being arranged in the first high-side inverter chip-on-core region and spaced apart along the first direction, the first high-side inverter chip being farther away from the second substrate portion than the second high-side inverter chip in the first direction, the third high-side inverter chip being arranged in the second high-side inverter chip-on-core region, the first low-side inverter chip being arranged in the first low-side inverter chip-on-core region, the second low-side inverter chip being arranged in the second low-side inverter chip-on-core region, and the third low-side inverter chip being arranged in the third low-side inverter chip-on-core region; and a plurality of wires, each of the wires being arranged between the control electrode pad of one of the inverter chips and the control electrode pad of another one of the inverter chips.The second wiring part is connected to the side of the second upper core part away from the first substrate part in the first direction and is arranged to extend in the second direction, the second wiring part is arranged to be spaced from the side of the third upper core part away from the first substrate part in the first direction, the third wiring part is connected to the side of the third upper core part closer to the low side in the second direction, the third wiring part is arranged to extend in the second direction and at least partially extends between the first wiring part and the second upper core part; the third high-side inverter chip is located in the middle of the second substrate part in the first direction, the control electrode pad in the third high-side inverter chip is located on the side of the third high-side inverter chip closer to the high side in the second direction, and the control electrode pad in the third high-side inverter chip is located on the end of the third high-side inverter chip closer to the first substrate part in the first direction; the first jumper area is further arranged on the second substrate part, the first jumper area is arranged to be spaced from the side of the second high-side inverter chip further away from the first substrate part in the first direction, the first jumper area is arranged to be spaced from the side of the second wiring part closer to the high side in the second direction, and a conductive member is connected between the first jumper area and the control electrode pad of the third high-side inverter chip.

[0044] Therefore, by arranging the third high-side inverter chip in the middle of the second substrate part, the heat dissipation of the third high-side inverter chip is more uniform, and the size of the second wiring part in the first direction can be increased, which can reduce the inductance of the second wiring part, thereby reducing the inductance of the third high-side inverter chip and suppressing the generation of sharp voltage at both ends of the third high-side inverter chip.

[0045] In some examples of the present application, the third low-side inverter chip is located in the middle of the second substrate part in the first direction.

[0046] In some examples of the present application, the control electrode pad in the third low-side inverter chip is located on the side of the third low-side inverter chip closer to the low side in the second direction, and the control electrode pad in the third low-side inverter chip is located on the end of the third low-side inverter chip further away from the first substrate part in the first direction.

[0047] In some examples of the present application, the third low-side inverter chip has a control electrode flow channel, the second load electrode pad of the third low-side inverter chip includes two sub-load electrode pads, the control electrode flow channel is arranged between the two sub-load electrode pads, and the control electrode flow channel of the third low-side inverter chip extends in the first direction.

[0048] In some examples of the present application, the second low-side inverter chip is arranged on the second substrate part closer to the first substrate part in the first direction.

[0049] In some examples of the present application, the control electrode pad of the second low-side inversion chip is located on a side of the second low-side inversion chip further away from the first substrate portion in the first direction, and the control electrode pad of the second low-side inversion chip is located on an end of the second low-side inversion chip closer to the low side in the second direction.

[0050] In some examples of the present application, the second low-side inversion chip has a control electrode flow channel, the second load electrode pad of the second low-side inversion chip includes two sub-load electrode pads, the control electrode flow channel is disposed between the two sub-load electrode pads, and the control electrode flow channel of the second low-side inversion chip extends in the first direction.

[0051] In some examples of the present application, the second substrate portion further has a second jumper area, the second jumper area is disposed between the first wiring portion and the second upper chip portion in the first direction, the second jumper area is disposed between the third wiring portion and the first upper chip portion in the second direction, a first conductive member is connected between the second jumper area and the second load electrode pad of the third low-side inversion chip, a second conductive member is connected between the second jumper area and the first substrate portion, a third conductive member is connected between the third wiring portion and the first substrate portion, and the second conductive member and the third conductive member are disposed parallel to each other.

[0052] In some examples of the present application, the first substrate portion has a third jumper area, the third jumper area includes a first jumper portion, a second jumper portion, and a third jumper portion, the first jumper portion is disposed on a side of the first low-side inversion chip upper chip area closer to the low side in the second direction, the first jumper portion extends in the first direction, the second jumper portion and the third jumper portion are connected to both ends of the first jumper portion in the first direction, and the second jumper portion and the third jumper portion extend toward a side of the high side closer to the second direction; a first avoiding gap is disposed on a side of the first high-side inversion chip upper chip area closer to the second substrate portion in the first direction, the first avoiding gap is located on an end of the first high-side inversion chip upper chip area closer to the low side in the second direction, at least part of the third jumper portion extends into the first avoiding gap adjacent to the end of the first high-side inversion chip, the second high-side inversion chip is closer to the second substrate portion in the first direction than the first high-side inversion chip, the second high-side inversion chip is disposed apart from the first avoiding gap in the second direction, the third conductive member is connected between the third wiring portion and the part of the first high-side inversion chip upper chip area corresponding to the second high-side inversion chip and the first avoiding gap apart, and the second conductive member is connected between the second jumper area and the third jumper portion.

[0053] In some examples of the present application, the first high-side inversion chip and the second high-side inversion chip are both disposed on the first high-side inversion chip in a second direction more proximate to a high side.

[0054] In some examples of the present application, the first substrate portion has a dimension A1 in the second direction; a distance B1 between the first high-side inversion chip and an edge of the first substrate portion facing the high side, A1 and B1 satisfy a relationship: 0.086A1≤B1≤0.117A1; a distance C1 between the second high-side inversion chip and the edge of the first substrate portion facing the high side, A1 and C1 satisfy a relationship: 0.086A1≤C1≤0.117A1.

[0055] In some examples of the present application, the first low-side inversion chip is disposed on the first low-side inversion chip in a first direction more proximate to the second substrate portion.

[0056] In some examples of the present application, the control electrode pad on the first low-side inversion chip is located on the first low-side inversion chip in a first direction more distal to the second substrate portion, and the control electrode pad on the first low-side inversion chip is located on the first low-side inversion chip in a second direction more proximate to a low side.

[0057] In some examples of the present application, the first low-side inversion chip has a control electrode flow channel, the second load electrode pad of the first low-side inversion chip includes two sub-load electrode pads, the control electrode flow channel is disposed between the two sub-load electrode pads, and the control electrode flow channel of the first low-side inversion chip extends in the second direction.

[0058] In some examples of the present application, a second avoiding gap is disposed in the first high-side inversion chip on-chip region, a fourth jumper zone is disposed in the second avoiding gap, the fourth jumper zone includes a fourth jumper portion and a fifth jumper portion, the fourth jumper portion extends in the second direction and is located between the first high-side inversion chip and the second high-side inversion chip in the first direction, the fifth jumper portion is connected to an end of the fourth jumper portion more proximate to the low side in the second direction, the fifth jumper portion extends and is disposed towards a side of the first low-side inversion chip more distal to the second substrate portion in the first direction, and a conductive member is connected between a portion of the first low-side inversion chip on-chip region distal to the first low-side inversion chip in the first direction and the fifth jumper portion.

[0059] In some examples of this application, the substrate includes a first sub-substrate and a second sub-substrate arranged sequentially along the first direction, with the first substrate portion disposed on the first sub-substrate and the second substrate portion disposed on the second sub-substrate.

[0060] In some examples of this application, the substrate further has a third substrate portion, which is disposed on the side of the first substrate portion away from the second substrate portion in a first direction, and the third substrate portion is provided with a brake unit upper core area and a rectifier unit upper core area.

[0061] In some examples of this application, the substrate is further provided with a third sub-substrate, which is spaced apart from the first sub-substrate on the side away from the second sub-substrate in a first direction, and the third sub-substrate portion is provided on the third sub-substrate.

[0062] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Beneficial effects

[0063] The semiconductor module in this application can be equipped with a larger inverter chip. Attached Figure Description

[0064] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0065] Figure 1 is a schematic diagram of a semiconductor module according to the prior art;

[0066] Figure 2 is a schematic diagram of a semiconductor module according to an embodiment of this application;

[0067] Figure 3 is a schematic diagram of a semiconductor module according to an embodiment of this application from another perspective;

[0068] Figure 4 is a cross-sectional view in the GG direction of Figure 3;

[0069] Figure 5 is a schematic diagram of a semiconductor module according to an embodiment of this application;

[0070] Figure 6 is a schematic diagram of a semiconductor module according to an embodiment of this application;

[0071] Figure 7 is a schematic diagram of the dimensions of a semiconductor module according to an embodiment of this application;

[0072] Figure 8 is a schematic diagram of the first substrate portion according to an embodiment of this application;

[0073] Figure 9 is a schematic diagram of the dimensions of the first substrate portion according to an embodiment of this application;

[0074] Fig. 10 is a schematic view of a second substrate portion according to an embodiment of the present application;

[0075] Fig. 11 is a schematic view of dimensions of the second substrate portion according to an embodiment of the present application;

[0076] Fig. 12 is a schematic view of a third substrate portion according to an embodiment of the present application;

[0077] Fig. 13 is a schematic view of dimensions of the third substrate portion according to an embodiment of the present application;

[0078] Fig. 14 is a schematic view of an inverter chip according to an embodiment of the present application.

[0079] Fig. 15 is a schematic view of a semiconductor module according to the prior art;

[0080] Fig. 16 is a schematic view of a semiconductor module according to an embodiment of the present application;

[0081] Fig. 17 is a schematic view of another perspective of a semiconductor module according to an embodiment of the present application;

[0082] Fig. 18 is a sectional view in the direction of G-G in Fig. 17;

[0083] Fig. 19 is a schematic view of a semiconductor module according to an embodiment of the present application;

[0084] Fig. 20 is a schematic view of a semiconductor module according to an embodiment of the present application;

[0085] Fig. 21 is a schematic view of dimensions of a semiconductor module according to an embodiment of the present application;

[0086] Fig. 22 is a schematic view of a first substrate portion according to an embodiment of the present application;

[0087] Fig. 23 is a schematic view of dimensions of the first substrate portion according to an embodiment of the present application;

[0088] Fig. 24 is a schematic view of a second substrate portion according to an embodiment of the present application;

[0089] Fig. 25 is a schematic view of dimensions of the second substrate portion according to an embodiment of the present application;

[0090] Fig. 26 is a schematic view of a third substrate portion according to an embodiment of the present application;

[0091] Fig. 27 is a schematic view of dimensions of the third substrate portion according to an embodiment of the present application;

[0092] Fig. 28 is a schematic view of an inverter chip according to an embodiment of the present application.

[0093] Fig. 29 is a schematic view of a semiconductor module according to the prior art;

[0094] FIG. 30 is a schematic view of a semiconductor module according to an embodiment of the present application;

[0095] FIG. 31 is a schematic view of another perspective of a semiconductor module according to an embodiment of the present application;

[0096] FIG. 32 is a sectional view in the direction of G-G in FIG. 31;

[0097] FIG. 33 is a schematic view of a semiconductor module according to an embodiment of the present application;

[0098] FIG. 34 is a schematic view of a semiconductor module according to an embodiment of the present application;

[0099] FIG. 35 is a schematic view of dimensions of a semiconductor module according to an embodiment of the present application;

[0100] FIG. 36 is a schematic view of a first substrate portion and a second substrate portion according to an embodiment of the present application;

[0101] FIG. 37 is a schematic view of a first substrate portion according to an embodiment of the present application;

[0102] FIG. 38 is a schematic view of dimensions of a first substrate portion according to an embodiment of the present application;

[0103] FIG. 39 is a schematic view of a second substrate portion according to an embodiment of the present application;

[0104] FIG. 40 is a schematic view of dimensions of a second substrate portion according to an embodiment of the present application;

[0105] FIG. 41 is a schematic view of a third substrate portion according to an embodiment of the present application;

[0106] FIG. 42 is a schematic view of dimensions of a third substrate portion according to an embodiment of the present application;

[0107] FIG. 43 is a schematic view of an inverter chip according to an embodiment of the present application;

[0108] FIG. 44 is a schematic view of dimensions of an inverter chip according to an embodiment of the present application;

[0109] FIG. 45 is a schematic view of dimensions of a rectifier chip according to an embodiment of the present application;

[0110] FIG. 46 is a schematic view of dimensions of a brake diode according to an embodiment of the present application;

[0111] FIG. 47 is a schematic view of dimensions of a brake transistor according to an embodiment of the present application.

[0112] Reference signs: 100, semiconductor module; 10001, high side; 10002, low side; 1, housing; 101, external terminal; 1011, first terminal; 1012, second terminal; 1013, third terminal; 1014, fourth terminal; 1015, fifth terminal; 1016, sixth terminal; 1017, seventh terminal; 1018, eighth terminal; 1019, ninth terminal; 10110, tenth terminal; 10111, eleventh terminal; 10112, twelfth terminal; 10113, thirteenth terminal; 10114, fourteenth terminal; 10115, fifteenth terminal; 10116, sixteenth terminal; 10117, seventeenth terminal; 10118, eighteenth terminal; 10119, nineteenth terminal; 10120, twentieth terminal; 10121, twenty-first terminal; 10122, twenty-second terminal; 10123, twenty-third terminal; 102, silicone gel; 103, side wall portion; 104, top wall portion; 2, substrate; 201, first sub-substrate; 2011, third substrate portion; 202, second sub-substrate; 2021, first substrate portion; 203, third sub-substrate; 2031, second substrate portion; 2041, first jumper portion; 2042, second jumper portion; 2043, third jumper portion; 3, braking chip-on-die region; 301, braking chip; 3011, braking diode; 3012, braking transistor; 4, rectifying chip-on-die region; 401, rectifying chip; 4011, first rectifying diode; 4012, second rectifying diode; 5, first high-side inverter chip-on-die region; 500, avoidance notch; 501, first avoidance notch; 502, second avoidance notch; 5021, first jumper region; 5022, second jumper region; 5023, sixth jumper region; 50211, fourth jumper portion; 50212, fifth jumper portion; 6, first low-side inverter chip-on-die region; 601, wiring portion; 602, die portion; 603, third avoidance notch; 604, fourth avoidance notch; 605, fifth avoidance notch; 7, second high-side inverter chip-on-die region; 701, third die portion; 702, third wiring portion; 8, second low-side inverter chip-on-die region; 801, first die portion; 802, first wiring portion; 9, third low-side inverter chip-on-die region; 901, second die portion; 902, second wiring portion; 10, inverter chip; 1001, first and second load electrode pads; 10011, sub load electrode pad; 1002, control electrode pad; 11, first high-side inverter chip; 1101, first edge; 1102, third edge; 1103, fourth edge; 1104, high-side edge; 12, second high-side inverter chip; 1201, second edge; 1202, fifth edge; 1203, sixth edge; 1206, spacing region; 13, third high-side inverter chip; 14, first low-side inverter chip;15, second low-side inverter chip; 16, third low-side inverter chip; 17, first jumper area; 1701, third jumper area; 1702, fourth jumper area; 1703, fifth jumper area; 18, second jumper area; 19, control electrode flow channel; 20, third jumper area; 21, fourth jumper area; 22, fifth jumper area; 2201, sixth jumper area; 2202, seventh jumper area; 2203, eighth jumper area; 2204, ninth jumper area; 2205, tenth jumper area; 2206, eleventh jumper area; 2207, twelfth jumper area; 2208, thirteenth jumper area; 2209, fourteenth jumper area; 2210, fifteenth jumper area; 23, conductive part; 2301, first conductive part; 2302, second conductive part; 2303, third conductive part; 24, fast recovery diode; 25, insulated gate bipolar transistor.

[0113] Embodiments of the present application

[0114] Embodiments of the present application are described in detail below, with reference to the embodiments described with reference to the accompanying drawings, which are exemplary, and embodiments of the present application are described in detail below.

[0115] Embodiments of the present application are described in detail below, with reference to the embodiments described with reference to the accompanying drawings, which are exemplary, and embodiments of the present application are described in detail below.

[0116] As shown in FIGS. 2-6, the semiconductor module 100 according to the present application has a first direction and a second direction, and a high side 10001 and a low side 10002 oppositely arranged in the second direction, which can mainly include: a housing 1, a substrate 2 and a plurality of inverter chips 10.

[0117] Among them, the substrate 2 is arranged in the housing 1, and the substrate 2 has a first substrate part 2021 and a second substrate part 2031 arranged in sequence and spaced apart along the first direction, and a plurality of elements can be arranged on the first substrate part 2021 and the second substrate part 2031 respectively to constitute the basic structure of the semiconductor module 100.

[0118] The first substrate portion 2021 is provided with the first high-side inverter chip-on-die area 5 and the first low-side inverter chip-on-die area 6 arranged along the second direction at intervals, and the first high-side inverter chip-on-die area 5 is closer to the high side 10001 of the semiconductor module 100 than the first low-side inverter chip-on-die area 6, so that the high-voltage power chip can be arranged on the high side 10001 of the first substrate portion 2021. The second substrate portion 2031 is provided with the second high-side inverter chip-on-die area 7, the third low-side inverter chip-on-die area 9, and the second low-side inverter chip-on-die area 8 arranged along the second direction at intervals, and the second high-side inverter chip-on-die area 7 is closer to the high side 10001 of the semiconductor module 100 than the second low-side inverter chip-on-die area 8, so that the high-voltage power chip can be arranged on the high side 10001 of the second substrate portion 2031. It should be noted that the first direction and the second direction are substantially perpendicular to each other, or the first direction and the second direction are perpendicular to each other.

[0119] In the embodiment of the present application, the first high-side inverter chip-on-die area 5, the second high-side inverter chip-on-die area 7, the first low-side inverter chip-on-die area 6, the second low-side inverter chip-on-die area 8, and the third low-side inverter chip-on-die area 9 can all be used to arrange the power chip in the semiconductor module 100.

[0120] The semiconductor module 100 is provided with a plurality of inverter chips 10, each of which is a single chip. Each of the plurality of inverter chips 10 is provided with a control electrode pad 1002, a first load electrode pad, and a second load electrode pad 1001. The control electrode pad 1002 and the second load electrode pad 1001 are applied with a driving voltage, and the first load electrode pad and the second load electrode pad 1001 are controlled to be connected or disconnected. For example, the inverter chip 10 is an inverse-derivative insulated gate bipolar transistor, or a metal oxide semiconductor field effect transistor, etc.

[0121] When the inverter chip 10 is an inverse-derivative insulated gate bipolar transistor, the first load electrode pad is a collector electrode pad, the second load electrode pad 1001 is an emitter electrode pad, and the control electrode pad 1002 is a gate electrode pad.

[0122] When the inverter chip 10 is a metal oxide semiconductor field effect transistor, the first load electrode pad is a drain electrode pad, the second load electrode pad 1001 is a source electrode pad, and the control electrode pad 1002 is a gate electrode pad.

[0123] In the prior art, as shown in FIG. 1, each inverter chip 10 in the semiconductor module 100 includes an insulated gate bipolar transistor 25 and a fast recovery diode 24. For example, when the inverter chip 10 is arranged on the substrate 2, at least one insulated gate bipolar transistor 25 and one fast recovery diode 24 need to be arranged, so that the number of chips in the semiconductor module 100 in the prior art is large.

[0124] In the embodiments of the present application, the inverter chip 10 can integrate the insulated gate bipolar transistor 25 and the fast recovery diode 24 on one chip, so that the number of chips in the semiconductor module 100 of the present application can be reduced, the functions of the integrated chips can be reduced, so that the number of conductive members 23 can be reduced, so that not only the manufacturing efficiency can be improved, but also the inductance can be reduced, so that the performance of the semiconductor module 100 can be improved.

[0125] It should be noted that in some embodiments of the present application, the conductive member 23 can be an electrically connected wire or an electrically connected sheet, etc.

[0126] The plurality of inverter chips 10 includes a first high-side inverter chip 11, a second high-side inverter chip 12, a third high-side inverter chip 13, a first low-side inverter chip 14, a second low-side inverter chip 15, and a third low-side inverter chip 16.

[0127] Further, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged on the first high-side inverter chip upper chip area 5 and are spaced apart in the first direction. In the embodiments of the present application, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged in the first direction of the first high-side inverter chip upper chip area 5, and mainly occupy the arrangement size of the first high-side inverter chip upper chip area 5 in the first direction. The first high-side inverter chip 11 and the second high-side inverter chip 12 are spaced apart, which not only can ensure that the first high-side inverter chip 11 and the second high-side inverter chip 12 are independent of each other, but also can facilitate heat dissipation of the first high-side inverter chip 11 and the second high-side inverter chip 12, so that heat accumulation between the first high-side inverter chip 11 and the second high-side inverter chip 12 can be prevented, so that the first high-side inverter chip 11 and the second high-side inverter chip 12 can be prevented from being overheated and disabled, and the reliability of the first high-side inverter chip 11 and the second high-side inverter chip 12 can be ensured.

[0128] In addition, the first high-side inverter chip 11 is farther away from the second substrate portion 2031 than the second high-side inverter chip 12 in the first direction, so that the arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12 on the first substrate portion 2021 can be facilitated, and the connection of the first high-side inverter chip 11 and the second high-side inverter chip 12 with other structures in the semiconductor module 100 can be facilitated.

[0129] The third high-side inverter chip 13 is arranged on the second high-side inverter chip upper core area 7, so that the third high-side inverter chip 13 is far away from the first high-side inverter chip 11 and the second high-side inverter chip 12, thereby preventing the three inverter chips 10 from being too close to each other and causing thermal failure of the device or the substrate 2.

[0130] The first low-side inverter chip 14 is arranged on the first low-side inverter chip upper core area 6, the second low-side inverter chip 15 is arranged on the second low-side inverter chip upper core area 8, and the third low-side inverter chip 16 is arranged on the third low-side inverter chip upper core area 9. In this way, the first high-side inverter chip 11, the second high-side inverter chip 12, the third high-side inverter chip 13, the third low-side inverter chip 16, the second low-side inverter chip 15, and the third low-side inverter chip 16 in the semiconductor module 100 are arranged separately to form the basic structure of the semiconductor module 100, thereby ensuring normal operation of the semiconductor module 100.

[0131] In some embodiments of the present application, as shown in FIGS. 2-6, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged more adjacent to the high side 10001 along the second direction on the first high-side inverter chip upper core area 5, the first high-side inverter chip upper core area 5 is provided with a clearance notch 500, the clearance notch 500 is provided with a first jumper area 17 extending along the second direction, the first jumper area 17 is arranged spaced apart from the first high-side inverter chip upper core area 5, at least a part of the first jumper area 17 is located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction, the edge of the first high-side inverter chip 11 adjacent to the second high-side inverter chip 12 in the first direction is defined as a first edge 1101, the edge of the second high-side inverter chip 12 adjacent to the first high-side inverter chip 11 in the first direction is defined as a second edge 1201, the edge of the first high-side inverter chip 11 adjacent to the low side 10002 in the second direction is defined as a third edge 1102, the edge of the first high-side inverter chip 11 adjacent to the high side 10001 in the second direction is defined as a fourth edge 1103, the edge of the second high-side inverter chip 12 adjacent to the low side 10002 in the second direction is defined as a fifth edge 1202, and the edge of the second high-side inverter chip 12 adjacent to the high side 10001 in the second direction is defined as a sixth edge 1203.

[0132] The one of the third edge 1102 and the fifth edge 1202 which is more adjacent to the low side 10002 is set as a low side edge, the one of the fourth edge 1103 and the sixth edge 1203 which is more adjacent to the high side 10001 is set as a high side edge, the extension line of the first edge 1101, the extension line of the second edge 1201, the extension line of the high side edge and the extension line of the low side edge together enclose a spacing region 1206, the part of the spacing region 1206 corresponding to the avoidance gap 500 is only provided with the first jumper area 17, the second load electrode pad 1001 of the first high side inverter chip 11 is connected with the first jumper area 17 through the conductive piece 23, the control electrode pad 1002 of the first high side inverter chip 11 is arranged on the first high side inverter chip 11 along the second direction and is more adjacent to the high side 10001, and the control electrode pad 1002 of the first high side inverter chip 11 is electrically connected with the external terminal 101.

[0133] In the prior art, as shown in FIG. 1, the first high-side inverter chip 11 and the second high-side inverter chip 12 are composed of at least one insulated gate bipolar transistor 25 and one fast recovery diode 24. When the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged on the first substrate part 2021, the fast recovery diode 24 and the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 are arranged in the second direction, and the fast recovery diode 24 constituting the first high-side inverter chip 11 is closer to the high side 10001, and the insulated gate bipolar transistor 25 is closer to the low side 10002. The first jumper area 17 connected to the second load electrode pad 1001 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is arranged between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction. In order to ensure the stability of the connection between the second load electrode pad 1001 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 and the first jumper area 17, the control electrode flow channel 19 between the two sub-load electrode pads 10011 in the second load electrode pad 1001 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 needs to be arranged in the first direction. In this case, the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is on the side closer to the low side 10002 in the second direction of the insulated gate bipolar transistor 25, and the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is on the side closer to the second substrate part 2031 in the first direction of the insulated gate bipolar transistor 25. At this time, in order to avoid the excessive length of the conductive part 23 between the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 and the external terminal 101, the prior art needs to arrange the second jumper area 18 to electrically connect with the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11. Due to the limitation of the position of the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11, the second jumper area 18 can only be arranged between the first high-side inverter chip 11 and the second high-side inverter chip 12, so that the connection between the second jumper area 18 and the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is stable, and there is no intersection between other conductive parts 23.

[0134] The prior art is thus arranged, which causes the size of the avoidance gap 500 in the first direction between the first high-side inverter chip 11 and the second high-side inverter chip 12 to be large enough to accommodate the first jumper area 17 and the second jumper area 18, that is, the size of the part of the first high-side inverter chip 11 and the second high-side inverter chip 12 arranged by the first high-side inverter chip upper chip area 5 in the prior art is small in the first direction, when the first high-side inverter chip 11 and the second high-side inverter chip 12 are each composed of at least one insulated gate bipolar transistor 25 and one fast recovery diode 24, and the insulated gate bipolar transistor 25 and the fast recovery diode 24 are spaced apart in the second direction, the arrangement area of the chip can meet the demand, but when the first high-side inverter chip 11 and the second high-side inverter chip 12 are single chips and large in size, the layout of the first substrate part 2021 of the prior art cannot meet the arrangement area of the first high-side inverter chip 11 and the second high-side inverter chip 12.

[0135] In the embodiment of the present application, the second load electrode pad 1001 of the first high-side inverter chip 11 is connected with the first jumper area 17 through the conductive part 23, the control electrode pad 1002 of the first high-side inverter chip 11 is arranged more adjacent to the high side 10001 of the first high-side inverter chip 11 in the second direction, and the control electrode pad 1002 of the first high-side inverter chip 11 is electrically connected with the external terminal 101. It should be noted that the control electrode pad 1002 of the first high-side inverter chip 11 can be directly electrically connected with the external terminal 101; or the control electrode pad 1002 of the first high-side inverter chip 11 can be electrically connected with the jumper pad through the conductive part, and then the jumper pad is electrically connected with the external terminal through the conductive part.

[0136] When the control electrode pad 1002 of the first high-side inverter chip 11 is directly electrically connected with the external terminal 101, since the first high-side inverter chip 11 and the second high-side inverter chip 12 are single chips, and the control electrode pad 1002 of the first high-side inverter chip 11 is arranged more adjacent to the high side 10001 of the first high-side inverter chip 11 in the second direction, the electrical connection path between the control electrode pad 1002 of the first high-side inverter chip 11 and the external terminal 101 can be shorter.

[0137] Further, an edge of the first high-side inverter chip 11 adjacent to the second high-side inverter chip 12 in the first direction is set as a first edge 1101, an edge of the second high-side inverter chip 12 adjacent to the first high-side inverter chip 11 in the first direction is set as a second edge 1201, an edge of the first high-side inverter chip 11 adjacent to the low side 10002 in the second direction is set as a third edge 1102, an edge of the first high-side inverter chip 11 adjacent to the high side 10001 in the second direction is set as a fourth edge 1103, an edge of the second high-side inverter chip 12 adjacent to the low side 10002 in the second direction is set as a fifth edge 1202, an edge of the second high-side inverter chip 12 adjacent to the high side 10001 in the second direction is set as a sixth edge 1203, one of the third edge 1102 and the fifth edge 1202 that is closer to the low side 10002 is set as a low-side edge, one of the fourth edge 1103 and the sixth edge 1203 that is closer to the high side 10001 is set as a high-side edge, and a region surrounded by an extension line of the first edge 1101, an extension line of the second edge 1201, an extension line of the high-side edge, and an extension line of the low-side edge is set as a spacing region 1206. The avoidance gap 500 corresponds to only a part of the spacing region 1206, and only the first jumper area 17 is provided in the part.

[0138] In this way, the avoidance gap 500 in the first direction corresponding to the part between the first high-side inverter chip 11 and the second high-side inverter chip 12 will only have the first jumper area 17 for the second load electrode pad 1001 of the first high-side inverter chip 11 to jump, and there will be no other jumper area in the avoidance gap 500 in the first direction corresponding to the part between the first high-side inverter chip 11 and the second high-side inverter chip 12. Thus, the part of the avoidance gap 500 in the first direction corresponding to the part between the first high-side inverter chip 11 and the second high-side inverter chip 12 can be used only for accommodating the first jumper area 17, the size of the part of the avoidance gap 500 in the first direction corresponding to the part between the first high-side inverter chip 11 and the second high-side inverter chip 12 can be small, and thus the areas of the parts of the first substrate portion 2021 corresponding to the two sides of the avoidance gap 500 in the first direction can be large, and the effective area for arranging the first high-side inverter chip 11 and the second high-side inverter chip 12 can be increased.

[0139] As shown in FIGS. 2-6, the first substrate portion 2021 further has a second jumper area 18. It should be noted that the second jumper area 18 is the jumper pad described above. The second jumper area 18 is arranged in the avoiding gap 500 and is arranged on the side of the fourth edge 1103 facing the high side 10001 in the second direction. The second jumper area 18 is arranged on the side of the first jumper area 17 away from the second substrate portion 2031 in the first direction. The control electrode pad 1002 of the first high-side inverter chip 11 is connected to the second jumper area 18 through a conductive member 23. The second jumper area 18 is connected to the external terminal 101 through a conductive member 23.

[0140] The second jumper area 18 is arranged, the conductive member 23 is arranged between the control electrode pad 1002 of the first high-side inverter chip 11 and the second jumper area 18, and the conductive member 23 is arranged between the second jumper area 18 and the external terminal 101. In this way, the conductive member 23 between the control electrode pad 1002 of the first high-side inverter chip 11 and the second jumper area 18 is short, and the conductive member 23 between the second jumper area 18 and the external terminal 101 is short. In this way, a long conductive member 23 can be prevented from being used when the control electrode pad 1002 of the first high-side inverter chip 11 is electrically connected to the external terminal 101, and the switching stability of the control electrode pad 1002 of the first high-side inverter chip 11 can be improved. In addition, the arrangement of the second jumper area 18 does not occupy the space of the part of the avoiding gap 500 corresponding to the first high-side inverter chip 11 and the second high-side inverter chip 12. In this way, the effective area of the first substrate portion for arranging the first high-side inverter chip and the second high-side inverter chip can be increased.

[0141] In the embodiment of the present application, the fourth terminal 1014 corresponds to the first substrate portion 2021 and is arranged on the side of the first substrate portion 2021 close to the high side 10001. The fourth terminal 1014 is arranged on the side of the first high-side inverter chip 11 away from the second jumper area 18 in the first direction. In this way, the second jumper area 18 can be arranged between the control electrode pad 1002 of the first high-side inverter chip 11 and the fourth terminal 1014.

[0142] In this way, on the one hand, the second jumper area 18 can be arranged close to the first high-side inverter chip 11, the distance between the second jumper area 18 and the first high-side inverter chip 11 and the control electrode pad 1002 can be shortened, which is beneficial to shorten the length of the conductive member 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the second jumper area 18, and the length of the conductive member 23 between the second jumper area 18 and the fourth terminal 1014 can be shortened, thereby preventing the influence of the too long conductive member 23 on the switching speed and stability of the first high-side inverter chip 11, on the other hand, the structure between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction can be reduced, thereby increasing the effective area of the first high-side inverter chip on the chip area 5 where the inverter chip 10 can be arranged.

[0143] As shown in FIGS. 2-7, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged opposite in the first direction, and the projections of the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction coincide with each other. In this way, not only the arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12 can be facilitated, but also the first high-side inverter chip 11 and the second high-side inverter chip 12 can be away from the first low-side inverter chip 14, thereby improving the heat dissipation performance of the semiconductor device 100.

[0144] As shown in FIGS. 5-7, the size of the part of the first jumper area 17 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction is L1, and L1 satisfies the relationship: 1.7mm≤L1≤3.2mm.

[0145] In some embodiments of the present application, the size of the part of the first jumper area 17 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction is L1, and L1≤3.2mm.

[0146] The size of the part of the first jumper area 17 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction cannot be too large, otherwise the first jumper area 17 will occupy too much space in the first direction of the first substrate part 2021, which is not conducive to arranging larger specification inverter chips 10. In order to increase the effective area of the first high-side inverter chip on the chip area 5 where the inverter chip 10 can be arranged, the size L1 of the part of the first jumper area 17 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction is not more than 3.2. For example, L1 can be 3.2mm, 3.1mm, 3.0mm, 2.9mm and 2.8mm, etc. A suitable specific parameter can be selected in specific design.

[0147] In some embodiments of the present application, the portion of the first jumper area 17 between the first high-side inversion chip 11 and the second high-side inversion chip 12 has a dimension in the first direction of L1, and L1≥1.7mm.

[0148] The portion of the first jumper area 17 between the first high-side inversion chip 11 and the second high-side inversion chip 12 cannot have a dimension in the first direction that is too small, as this would result in the inability to wire the first jumper area 17 normally. To ensure that the first jumper area 17 can be wired normally, the portion of the first jumper area 17 between the first high-side inversion chip 11 and the second high-side inversion chip 12 has a dimension in the first direction of L1, and L1≥1.7mm. For example, L1 can be 1.7mm, 1.8mm, 1.9mm, 2.0mm, etc. A suitable specific parameter is selected in the specific design.

[0149] By setting L1 to be between 1.7mm and 3.2mm, not only is the effective area on the first high-side inversion chip 11 for setting the first high-side inversion chip 11 and the second high-side inversion chip 12 ensured to be large, but it is also ensured that the first jumper area 17 can be wired normally, and a reasonable balance between the normal arrangement of the chips and the normal wiring of the first jumper area 17 is achieved, ensuring the performance of the semiconductor module 100.

[0150] In combination with FIGS. 5-7, the first substrate portion 2021 has a dimension in the second direction of A1, the distance between the edge of the first high-side inversion chip 11 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 is B1, and A1 and B1 satisfy the relationship: 0.086A1≤B1≤0.117A1.

[0151] In some embodiments of the present application, B1 / A1 is not more than 0.117. For example, B1 / A1 can be 0.117, 0.116, or 0.115. If B1 / A1 is too large, the first high-side inverter chip 11 will be arranged further away from the high side 10001 on the first substrate portion 2021, which not only makes the distance between the control electrode pad 1002 on the first high-side inverter chip 11 and the external terminal 101 and the second jumper area 18 too large, resulting in the conductive member 23 between the control electrode pad 1002 and the external terminal 101 being too long, or the conductive member 23 between the control electrode pad 1002 and the second jumper area 18 being too long, affecting the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, but also makes the distance between the first high-side inverter chip 11 and the first low-side inverter chip 14 too close, which is not conducive to the heat dissipation of the first high-side inverter chip 11. In order to ensure the heat dissipation of the first high-side inverter chip 11 and the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, and ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0152] In some embodiments of the present application, B1 / A1 is not less than 0.086. For example, B1 / A1 can be 0.086, 0.087, or 0.088. It should be noted that if B1 / A1 is too small, the first high-side inverter chip 11 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, and there will be no space on the first substrate portion 2021 to arrange the second jumper area 18, which will result in the conductive member 23 connecting the control electrode pad 1002 of the first high-side inverter chip 11 directly to the external terminal 101 being too long, and the switch stability of the control electrode pad 1002 of the first high-side inverter chip 11 being poor. In order to ensure the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, and ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0153] In combination with FIGS. 5-7, the size of the first substrate portion 2021 in the second direction is A1, the distance between the edge of the second high-side inverter chip 12 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 is C1, and A1 and C1 satisfy the relationship: 0.086A1≤C1≤0.117A1.

[0154] In some embodiments of the present application, C1 / A1 is not more than 0.117. For example, C1 / A1 can be 0.117, 0.116, or 0.115. If C1 / A1 is too large, the second high-side inversion chip 12 will be arranged further away from the high side 10001 in the second direction of the first substrate portion 2021, which not only makes the length of the conductive member 23 between the control electrode pad 1002 on the second high-side inversion chip 12 and the external terminal 101 too large, affecting the stability of the switch of the second high-side inversion chip 12, but also makes the distance between the second high-side inversion chip 12 and the first low-side inversion chip 14 too close, which is not conducive to the heat dissipation of the second high-side inversion chip 12. In order to ensure the heat dissipation of the second high-side inversion chip 12 and the switching stability of the control electrode pad 1002 on the second high-side inversion chip 12, and to ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0155] In some embodiments of the present application, C1 / A1 is not less than 0.086. For example, the sixth parameter value can be 0.086, 0.087, or 0.088. If C1 / A1 is too small, the second high-side inversion chip 12 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, and there will be no space to set the fourth jumper area 21 on the first substrate portion 2021, which will result in the length of the conductive member 23 between the first jumper area 17 and the external terminal 101 being too large, affecting the working stability of the second load electrode pad 1001 of the first high-side inversion chip 11.

[0156] In combination with FIGS. 5-6, the control electrode pad 1002 of the first high-side inversion chip 11 is arranged on the first high-side inversion chip 11 along the first direction closer to the side of the first high-side inversion chip 11 away from the second substrate portion 2031.

[0157] It should be noted that in the embodiments of the present application, the inversion chips 10 are all chips of the same structure, which can facilitate installation and setting, prevent chips from being installed in the wrong position, and ensure the consistency of the chips. Furthermore, during installation, the position of the control electrode pad 1002, the first load electrode pad, and the second load electrode pad 1001 on the inversion chip 10 on the substrate 2 can be adjusted by rotating the inversion chip 10. Specifically, the control electrode pad 1002 on the first high-side inversion chip 11 is arranged on the first high-side inversion chip 11 along the first direction closer to the side of the first high-side inversion chip 11 closer to the second substrate portion 2031, which can further shorten the length of the conductive member 23 between the control electrode pad 1002 on the first high-side inversion chip 11 and the second jumper area 18, or further shorten the length of the conductive member 23 between the control electrode pad 1002 on the first high-side inversion chip 11 and the external terminal 101, while ensuring the consistency of the chips.

[0158] As shown in FIGS. 1, 5, 6 and 7, compared with the prior art, in the embodiment of the present application, the control electrode pad 1002 on the first high-side inverter chip 11 can be arranged more adjacent to the side of the first high-side inverter chip 11 away from the second substrate portion 2031 in the first direction after the first high-side inverter chip 11 is rotated by a certain angle. In this way, the control electrode pad 1002 on the first high-side inverter chip 11 can be arranged close to the second jumper area 18 after the position of the second jumper area 18 is adjusted.

[0159] It can be understood that in the embodiment of the present application, the second jumper area 18 is located between the control electrode pad 1002 on the first high-side inverter chip 11 and the fourth terminal 1014 on the shell 1, so that the distance between the control electrode pad 1002, the second jumper area 18 and the fourth terminal 1014 can be shortened, thereby not only the length of the conductive member 23 can be shortened, but also the conductive member 23 can be prevented from being deformed due to being too long, and the temperature at both ends of the conductive member 23 can be reduced through heat dissipation of the second jumper area 18 to improve the current carrying capacity thereof.

[0160] As shown in FIGS. 6, 8 and 14, the first high-side inverter chip 11 has a control electrode flow channel 19, the second load electrode pad 1001 of the first high-side inverter chip 11 includes two sub load electrode pads 10011, the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011, and the control electrode flow channel 19 of the first high-side inverter chip 11 extends in the first direction.

[0161] Specifically, the first high-side inverter chip 11 can be a reverse-conducting insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor. The first high-side inverter chip 11 is provided with the control electrode flow channel 19 extending in the first direction, and the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19 in the reverse-conducting insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor.

[0162] In the embodiment of the present application, the second load electrode pad 1001 on the first high-side inverter chip 11 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011 to ensure the structural reliability of the first high-side inverter chip 11.

[0163] In combination with FIGS. 6 and 8, the first jumper area 17 is located in the middle of the first high-side inverter chip upper core area 5 in the first direction, so that the setting area of the first high-side inverter chip 11 and the second high-side inverter chip 12 on the first high-side inverter chip upper core area 5 is enlarged, and the setting area of the first high-side inverter chip 11 and the second high-side inverter chip 12 on the first high-side inverter chip upper core area 5 is more balanced and reasonable, which can prevent one of the first high-side inverter chip 11 and the second high-side inverter chip 12 from having a larger setting area and the other from having a smaller setting area, resulting in that one of the first high-side inverter chip 11 and the second high-side inverter chip 12 cannot be normally set on the first substrate portion 2021, so that the structural layout of the first substrate portion 2021 can be further optimized.

[0164] In combination with FIGS. 6 and 8, the first substrate portion 2021 further has a third jumper area 20 connected to one end of the first jumper area 17 adjacent to the first low-side inverter chip upper core area 6, the third jumper area 20 extends from the first jumper area 17 in the first direction away from the second substrate portion 2031, and a conductive member 23 is connected between the third jumper area 20 and the first low-side inverter chip upper core area 6.

[0165] Specifically, the third jumper area 20 is connected to the first jumper area 17, so that the third jumper area 20 is electrically connected to the first jumper area 17. The third jumper area 20 is located at one end of the first jumper area 17 adjacent to the first low-side inverter chip upper core area 6, so that the third jumper area 20 is arranged close to the first low-side inverter chip upper core area 6, so as to facilitate wire bonding of the third jumper area 20 and the structure on the first low-side inverter chip upper core area 6.

[0166] The third jumper area 20 extends in the first direction, so that the area of the third jumper area 20 is increased, and wire bonding on the third jumper area 20 is facilitated. In addition, the third jumper area 20 extends in a direction away from the second substrate portion 2031 from the first jumper area 17, so that the distance between the third jumper area 20 and the first low-side inverter chip upper core area 6 is shortened, a conductive member 23 is connected between the third jumper area 20 and the first low-side inverter chip upper core area 6, and such arrangement is conducive to shortening the length of the conductive member 23 between the first low-side inverter chip upper core area 6 and the third jumper area 20, so as to avoid deformation of the conductive member 23 due to excessive length, and to ensure the structural reliability of the conductive member 23.

[0167] In combination with FIG. 2, the first low-side inverter chip 14 is arranged more adjacent to the second substrate portion 2031 in the first direction on the first low-side inverter chip upper core area 6, and a conductive member 23 is connected between one side of the first low-side inverter chip upper core area 6 away from the second substrate portion 2031 and the third jumper area 20.

[0168] Specifically, the first low-side inverter chip 14 and the wire-bonding positions on the first low-side inverter chip upper die area 6 are arranged at intervals in the first direction of the first low-side inverter chip upper die area 6, so that the wire-bonding positions of the conductive member 23 on the first low-side inverter chip upper die area 6 do not encroach on the arrangement position of the first low-side inverter chip 14 in the second direction of the first low-side inverter chip upper die area 6, thereby facilitating an increase in the effective area of the first low-side inverter chip 14 on the first substrate portion 2021, facilitating the arrangement of a first low-side inverter chip 14 of a larger specification in the first substrate portion 2021, and thereby improving the current-carrying capacity of the semiconductor module 100 of the embodiment of the present application.

[0169] Further, this also ensures that the length of the conductive member 23 between the control electrode pad 1002 of the first low-side inverter chip 14 and the external terminal 101 is as short as possible under the premise of structural consistency of the plurality of inverter chips 10, thereby further improving the switching stability of the control electrode pad 1002 of the first low-side inverter chip 14.

[0170] In combination with FIG. 6, the first substrate portion 2021 further has a fourth jumper area 21 connected to the end of the first jumper area 17 away from the first low-side inverter chip upper die area 6, so that the fourth jumper area 21 is electrically connected to the first jumper area 17. The fourth jumper area 21 extends from the first jumper area 17 in the direction of the second substrate portion 2031 in the first direction, which not only increases the area of the fourth jumper area 21, but also facilitates wire bonding on the fourth jumper area 21, and further allows the fourth jumper area 21 to avoid the arrangement of the second jumper area 18.

[0171] In the embodiment of the present application, in combination with FIG. 5 and FIG. 6, the fifth terminal 1015 is located on the side of the fourth jumper area 21 facing the second substrate portion 2031 in the first direction, and the fifth terminal 1015 and the fourth jumper area 21 are connected by a conductive member 23. In this way, the fifth terminal 1015 can be arranged to avoid the fourth terminal 1014 while ensuring reliable connection of the conductive member 23 between the fourth jumper area 21 and the fifth terminal 1015, thereby facilitating a reduction in the length of the conductive member 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the second jumper area 18, and facilitating a reduction in the length of the conductive member 23 between the second jumper area 18 and the fourth terminal 1014.

[0172] According to the embodiment of the present application, as shown in FIG. 9, the first high-side inverter chip on-chip area 5 includes dimensions L2, L3, L4, L5 and L6, wherein L2 is 20.8 mm, L3 is 22.4 mm, L5 is 7.7 mm, and L6 is 2.1 mm. The second jumper area 18 includes dimensions L7 and L8, wherein L7 is 2.2 mm and L8 is 1.6 mm. The fourth jumper area 21 includes dimensions L9 and L12, wherein L9 is and L12 is 1.6 mm. The third jumper area 20 includes dimensions L10 and L11, wherein L10 is 6.34 mm and L11 is 2.1 mm. The first low-side inverter chip on-chip area 6 includes dimensions L13 and L14, wherein L13 is 17.4 mm and L14 is 8.4 mm.

[0173] As shown in FIGS. 5, 6 and 10, the third high-side inverter chip 13 is located in the middle of the second substrate portion 2031 in the first direction, so that the two sides of the third high-side inverter chip 13 in the first direction are located at a similar distance from the two sides of the second substrate portion 2031 in the first direction. In this way, the heat of the two sides of the third high-side inverter chip 13 in the first direction can be simultaneously transmitted to the edges of the second substrate portion 2031, so that the heat dissipation efficiency of the two sides of the third high-side inverter chip 13 in the first direction is the same, thereby ensuring the heat dissipation effect of the two sides of the third high-side inverter chip 13 in the first direction, and solving the problem of heat accumulation caused by low heat dissipation efficiency of one side of the third high-side inverter chip 13 in the first direction, thereby facilitating the improvement of the heat dissipation performance of the third high-side inverter chip 13.

[0174] As shown in FIGS. 5, 6 and 10, the control electrode pad 1002 of the third high-side inverter chip 13 is arranged more proximate to the high side 10001 of the semiconductor module 100 on the third high-side inverter chip 13 in the second direction; and the control electrode pad 1002 of the third high-side inverter chip 13 is arranged more proximate to the first substrate portion 2021 on the third high-side inverter chip 13 in the first direction.

[0175] Specifically, the third high-side inverter chip 13 is a high-side power chip in the semiconductor module 100, and the control electrode pad 1002 thereof is arranged proximate to the high side 10001 of the semiconductor module 100 in the second direction and proximate to the first substrate portion 2021 in the first direction. The eighth terminal 1018 on the shell 1 is provided with a conductive member 23 between the control electrode pad 1002 of the third high-side inverter chip 13, and the eighth terminal 1018 is located on the side of the third high-side inverter chip 13 away from the first substrate portion 2021 in the first direction. In this way, the conductive member 23 between the control electrode pad 1002 on the third high-side inverter chip 13 and the eighth terminal 1018 can be prevented from being too long and deformed, and the reliability of the conductive member 23 between the control electrode pad 1002 on the third high-side inverter chip 13 and the eighth terminal 1018 can be ensured.

[0176] As shown in FIGS. 5, 6, 10 and 14, the third high-side inversion chip 13 has a control electrode flow channel 19, the second load electrode pad 1001 of the third high-side inversion chip 13 includes two sub load electrode pads 10011, the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011, and the control electrode flow channel 19 of the third high-side inversion chip 13 extends in the first direction.

[0177] Specifically, the third high-side inversion chip 13 can be an inverse- conduction type insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor, etc. Among them, the control electrode flow channel 19 is arranged on the third high-side inversion chip 13, and the control electrode flow channel 19 extends in the first direction. In the inverse-conduction type insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0178] In the embodiment of the application, the second load electrode pad 1001 on the third high-side inversion chip 13 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011, thereby ensuring the structural reliability of the third high-side inversion chip 13.

[0179] As shown in FIGS. 5, 6 and 10, the second substrate part 2031 further has a fifth jumper area 22, and the fifth jumper area 22 is located on the side of the second high-side inversion chip upper chip area 7 away from the first substrate part 2021 in the first direction. In this way, the fifth jumper area 22 can be arranged between the third high-side inversion chip 13 and the eighth terminal 1018, and the conductive member 23 is connected between the control electrode pad 1002 of the third high-side inversion chip 13 and the fifth jumper area 22.

[0180] Specifically, when the third high-side inversion chip 13 is wire-bonded with the eighth terminal 1018, the conductive member 23 is arranged between the third high-side inversion chip 13 and the fifth jumper area 22, and the conductive member 23 is arranged between the fifth jumper area 22 and the eighth terminal 1018. In this way, on the one hand, the third high-side inversion chip 13 can be connected with the eighth terminal 1018, and on the other hand, by arranging the fifth jumper area 22, the length of the conductive member 23 arranged between the third high-side inversion chip 13 and the eighth terminal 1018 can be shortened, thereby reducing the heat generation of the conductive member 23, reducing the temperature at both ends of the conductive member 23, and thus improving the reliability of the semiconductor module 100.

[0181] As shown in FIGS. 5, 6 and 10, the third low-side inversion chip 16 is located in the middle of the second substrate portion 2031 in the first direction, so that the two sides of the third low-side inversion chip 16 in the first direction are located at a similar distance from the two sides of the second substrate portion 2031 in the first direction. In this way, heat from the two sides of the third low-side inversion chip 16 in the first direction can be simultaneously transferred to the edges of the second substrate portion 2031, so that the heat dissipation efficiency of the two sides of the third low-side inversion chip 16 in the first direction is the same, thereby ensuring the heat dissipation effect of the two sides of the third low-side inversion chip 16 in the first direction, and solving the problem of heat accumulation caused by low heat dissipation efficiency of one side of the third low-side inversion chip 16 in the first direction, thereby facilitating the improvement of the heat dissipation performance of the third low-side inversion chip 16.

[0182] In addition, the second load electrode pad 1001 on the third low-side inversion chip 16 needs to be connected to the jumper area on the first substrate portion 2021 through the conductive member 23, and the control electrode pad 1002 on the third low-side inversion chip 16 needs to be connected to the jumper area on the part of the second substrate portion 2031 away from the third low-side inversion chip 16 in the first direction through the conductive member 23. By locating the third low-side inversion chip 16 in the middle of the second substrate portion 2031 in the first direction, the conductive member 23 between the second load electrode pad 1001 on the third low-side inversion chip 16 and the jumper area on the first substrate portion 2021 will not be too long, and the conductive member 23 between the control electrode pad 1002 on the third low-side inversion chip 16 and the jumper area on the part of the second substrate portion 2031 away from the third low-side inversion chip 16 in the first direction will not be too long, thereby preventing one of the two conductive members 23 from being too long and affecting the performance of the third low-side inversion chip 16. In this way, the lengths of the two conductive members 23 are reasonably balanced, thereby improving the performance of the third low-side inversion chip 16.

[0183] As shown in FIGS. 5, 6 and 10, the control electrode pad 1002 of the third low-side inversion chip 16 is arranged more adjacent to the low side 10002 on the third low-side inversion chip 16 in the second direction; and the control electrode pad 1002 of the third low-side inversion chip 16 is arranged more adjacent to the side of the third low-side inversion chip 16 away from the first substrate portion 2021 in the first direction.

[0184] Specifically, the third low-side inverter chip 16 is a low-side power chip in the semiconductor module 100, the control electrode pad 1002 of which is arranged in the second direction close to the low side 10002 of the semiconductor module 100, and in the first direction adjacent to the side of the third low-side inverter chip 16 away from the first substrate portion 2021. The twelfth terminal 10112 on the shell 1 is provided with the conductive member 23 between the control electrode pad 1002 of the third low-side inverter chip 16, and the twelfth terminal 10112 is located in a position closer to the low side 10002 in the second direction of the semiconductor module 100, so that the control electrode pad 1002 on the third low-side inverter chip 16 is arranged close to the twelfth terminal 10112, which can avoid the deformation of the conductive member 23 between the control electrode pad 1002 on the third low-side inverter chip 16 and the twelfth terminal 10112 due to the excessive length, and can ensure the reliability of the conductive member 23 between the control electrode pad 1002 on the third low-side inverter chip 16 and the twelfth terminal 10112.

[0185] As shown in FIGS. 5, 6, 10 and 14, the third low-side inverter chip 16 has a control electrode flow channel 19, the second load electrode pad 1001 of the third low-side inverter chip 16 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011. The control electrode flow channel 19 of the third low-side inverter chip 16 extends in the first direction.

[0186] Specifically, the third low-side inverter chip 16 can be an inverse-conducting insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor, etc. The control electrode flow channel 19 is arranged on the third low-side inverter chip 16 and extends in the first direction. In the inverse-conducting insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0187] In the embodiment of the present application, the second load electrode pad 1001 on the third low-side inverter chip 16 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011 to ensure the structural reliability of the third low-side inverter chip 16.

[0188] In the embodiment of the present application, the fourteenth terminal 10114 corresponding to the first substrate portion 2021 is provided with the conductive member 23 between the second load electrode pad 1001 on the third low-side inverter chip 16.

[0189] As shown in FIGS. 2-7, the second low-side inverter chip 15 is arranged in the first direction more adjacent to the first substrate portion 2021 on the second substrate portion 2031.

[0190] Specifically, this can make the second low-side inverter chip 15 and the third low-side inverter chip 16 staggered in the first direction. In this way, on the one hand, it can prevent the second low-side inverter chip 15 and the third low-side inverter chip 16 from being too close, causing the heat of the semiconductor module 100 to concentrate and reducing the reliability of the semiconductor module 100. On the other hand, since the second load electrode pad 1001 on the second low-side inverter chip 15 is connected to the jumper area of the first substrate part 2021 by the conductive piece 23, the second low-side inverter chip 15 is arranged more adjacent to the first substrate part 2021 in the first direction on the second substrate part 2031, which can make the conductive piece between the second load electrode pad 1001 on the second low-side inverter chip 15 and the jumper area of the first substrate part 2021 shorter, thereby reducing the internal inductance to suppress the surge voltage between the first load electrode pad and the second load electrode pad 1001 on the second low-side inverter chip 15, and further improving the stability of the conductive piece between the second load electrode pad 1001 on the second low-side inverter chip 15 and the jumper area of the first substrate part 2021, thereby improving the performance of the second load electrode pad 1001 on the second low-side inverter chip 15.

[0191] It should be noted that the jumper area on the first substrate part 2021 that is electrically connected to the second load electrode pad 1001 on the second low-side inverter chip 15 needs to be electrically connected to the external terminal again.

[0192] In combination with FIGS. 5, 6 and 10, the control electrode pad 1002 of the second low-side inverter chip 15 is arranged more adjacent to the low side 10002 in the second direction on the second low-side inverter chip 15; the control electrode pad 1002 of the second low-side inverter chip 15 is arranged more adjacent to the side of the second low-side inverter chip 15 away from the first substrate part 2021 in the first direction on the second low-side inverter chip 15.

[0193] Specifically, the second low-side inverter chip 15 is a low-side power chip in the semiconductor module 100, and the control electrode pad 1002 thereof is arranged in the second direction close to the low side 10002 of the semiconductor module 100 and in the first direction adjacent to the side of the second low-side inverter chip 15 away from the first substrate portion 2021. The thirteenth terminal 10113 on the housing 1 is provided with the conductive member 23 between the control electrode pad 1002 of the second low-side inverter chip 15, and the thirteenth terminal 10113 is arranged in a position closer to the low side 10002 in the second direction of the semiconductor module 100, so that the control electrode pad 1002 on the second low-side inverter chip 15 is arranged close to the thirteenth terminal 10113, and the conductive member 23 between the control electrode pad 1002 on the second low-side inverter chip 15 and the thirteenth terminal 10113 can be prevented from being too long and deformed, and the reliability of the conductive member 23 between the control electrode pad 1002 on the second low-side inverter chip 15 and the thirteenth terminal 10113 can be ensured.

[0194] As shown in FIGS. 5, 6, 10 and 14, the second low-side inverter chip 15 has a control electrode flow channel 19, the second load electrode pad 1001 of the second low-side inverter chip 15 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011. The control electrode flow channel 19 of the second low-side inverter chip 15 extends in the first direction.

[0195] Specifically, the second low-side inverter chip 15 can be an inverse-parallel insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor, etc. The control electrode flow channel 19 is arranged on the second low-side inverter chip 15 and extends in the first direction. In the inverse-parallel insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0196] In the embodiment, the second load electrode pad 1001 on the second low-side inverter chip 15 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011 to ensure the structural reliability of the second low-side inverter chip 15.

[0197] According to an embodiment of the present application, as shown in FIG. 11, the second high-side inverter chip-on-die area 7 includes dimensions L15 and L16, where L15 is 11.9 mm and L16 is 9.44 mm. The third low-side inverter chip-on-die area 9 includes dimensions L17 and L18, where L17 is 14.4 mm and L18 is 8.66 mm. The second low-side inverter chip-on-die area 8 includes dimensions L19 and L20, where L19 is 13 mm and L20 is 8.5 mm. The fifth jumper area 22 includes dimensions L21 and L22, where L21 is 4.3 mm and L22 is 1.41 mm.

[0198] As shown in FIGS. 5, 6 and 12, the substrate 2 further has a third substrate portion 2011 disposed on a side of the first substrate portion 2021 away from the second substrate portion 2031 in the first direction, and the third substrate portion 2011 is provided with the brake chip-on-die area 3 and the rectifier chip-on-die area 4.

[0199] Specifically, the third substrate portion 2011 is provided with the brake chip-on-die area 3 and the rectifier chip-on-die area 4. The brake chip-on-die area 3 and the rectifier chip-on-die area 4 are disposed apart from each other in the second direction. The brake chip-on-die area 3 is arranged with a brake chip 301 including a brake diode 3011 and a brake transistor 3012. The rectifier chip-on-die area 4 is arranged with a rectifier chip 401 including a first rectifier diode 4011 and a second rectifier diode 4012.

[0200] According to an embodiment of the present application, as shown in FIG. 13, the rectifier chip-on-die area 4 includes dimensions L23, L24, L25, L26, L27, L28 and L46, where L23 is 6.2 mm, L24 is 6.2 mm, L25 is 6.5 mm, L26 is 12.6 mm, L27 is 10.4 mm, L28 is 11.8 mm, and L46 is 20.2 mm. The brake chip-on-die area 3 includes dimensions L29 and L30, where L29 is 22.4 mm and L30 is 6.1 mm.

[0201] In an embodiment of the present application, as shown in FIGS. 5 and 6, the shell 1 has a plurality of regularly arranged external terminals 101 around the periphery, and the brake chip 301, the rectifier chip 401 and the inverter chip 10 are respectively connected to corresponding external terminals 101, and the external terminals 101 at least partially extend outward from the shell 1.

[0202] The plurality of external terminals 101 are defined as a first terminal 1011, a second terminal 1012, a third terminal 1013, a fourth terminal 1014, a fifth terminal 1015, a sixth terminal 1016, a seventh terminal 1017, an eighth terminal 1018, a ninth terminal 1019, a tenth terminal 10110, an eleventh terminal 10111, a twelfth terminal 10112, a thirteenth terminal 10113, a fourteenth terminal 10114, a fifteenth terminal 10115, a sixteenth terminal 10116, a seventeenth terminal 10117, an eighteenth terminal 10118, a nineteenth terminal 10119, a twentieth terminal 10120, a twenty-first terminal 10121, a twenty-second terminal 10122, and a twenty-third terminal 10123.

[0203] The first terminal 1011, the second terminal 1012, the third terminal 1013, the fourth terminal 1014, the fifth terminal 1015, the sixth terminal 1016, and the seventh terminal 1017 are located on one side of the second direction of the housing 1 and are sequentially and spaced apart in the first direction, the eighth terminal 1018, the ninth terminal 1019, the tenth terminal 10110, and the eleventh terminal 10111 are located on one side of the first direction of the housing 1 and are sequentially and spaced apart in the second direction, the twelfth terminal 10112, the thirteenth terminal 10113, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, the seventeenth terminal 10117, the eighteenth terminal 10118, and the nineteenth terminal 10119 are located on the other side of the second direction of the housing 1 and are sequentially and spaced apart in the first direction, and the twentieth terminal 10120, the twenty-first terminal 10121, the twenty-second terminal 10122, and the twenty-third terminal 10123 are located on the other side of the first direction of the housing 1 and are sequentially and spaced apart in the second direction.

[0204] The first terminal 1011, the second terminal 1012, the eighteenth terminal 10118, and the nineteenth terminal 10119 correspond to the third substrate portion 2011 in the second direction, the third terminal 1013, the fourth terminal 1014, the fifth terminal 1015, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, and the seventeenth terminal 10117 correspond to the first substrate portion 2021 in the second direction, and the sixth terminal 1016, the seventh terminal 1017, the twelfth terminal 10112, and the thirteenth terminal 10113 correspond to the second substrate portion 2031 in the second direction.

[0205] In this way, the basic structure of the semiconductor module 100 can be formed, and the brake circuit, the rectifier circuit, and the inverter circuit can be integrated, thereby simplifying the layout of the circuit and the construction of the heat dissipation system.

[0206] Embodiment two of the present application provides a semiconductor module 100, and the semiconductor module 100 according to the embodiments of the present application is described below with reference to FIGS. 15-28, which includes but is not limited to a PIM (Power Integrated Module).

[0207] As shown in FIGS. 16-21, the semiconductor module 100 according to the present application has a first direction and a second direction, and a high side 10001 and a low side 10002 oppositely arranged in the second direction, which can mainly include a housing 1, a substrate 2, and a plurality of inverter chips 10.

[0208] The substrate 2 is arranged in the housing 1, and the substrate 2 has a third substrate portion 2011, a first substrate portion 2021, and a second substrate portion 2031 arranged in sequence and spaced apart in the first direction, and a plurality of elements can be arranged on the third substrate portion 2011, the first substrate portion 2021, and the second substrate portion 2031, respectively, to constitute the basic structure of the semiconductor module 100.

[0209] The third substrate portion 2011 is provided with a brake chip upper core area 3 and a rectifier chip upper core area 4, and the brake chip upper core area 3 and the rectifier chip upper core area 4 are arranged spaced apart from each other in the second direction. The brake chip upper core area 3 is arranged with a brake chip 301, and the brake chip 301 includes a brake diode 3011 and a brake transistor 3012. The rectifier chip upper core area 4 is arranged with a rectifier chip 401, and the rectifier chip 401 includes a first rectifier diode 4011 and a second rectifier diode 4012.

[0210] In the embodiments of the present application, as shown in FIGS. 19-21, the housing 1 has a plurality of regularly arranged external terminals 101 around the periphery, and the brake chip 301, the rectifier chip 401, and the inverter chip 10 are respectively connected to the corresponding external terminals 101, and the external terminals 101 at least partially extend outward from the housing 1.

[0211] The plurality of external terminals 101 are defined as a first terminal 1011, a second terminal 1012, a third terminal 1013, a fourth terminal 10104, a fifth terminal 1015, a sixth terminal 1016, a seventh terminal 1017, an eighth terminal 1018, a ninth terminal 1019, a tenth terminal 10110, an eleventh terminal 10111, a twelfth terminal 10112, a thirteenth terminal 10113, a fourteenth terminal 10114, a fifteenth terminal 10115, a sixteenth terminal 10116, a seventeenth terminal 10117, an eighteenth terminal 10118, a nineteenth terminal 10119, a twentieth terminal 10120, a twenty-first terminal 10121, a twenty-second terminal 10122, and a twenty-third terminal 10123.

[0212] The first terminal 1011, the second terminal 1012, the third terminal 1013, the fourth terminal 10104, the fifth terminal 1015, the sixth terminal 1016 and the seventh terminal 1017 are located on one side of the second direction of the housing 1 and are arranged in the first direction in sequence with intervals, the eighth terminal 1018, the ninth terminal 1019, the tenth terminal 10110, the eleventh terminal 10111 are located on the other side of the first direction of the housing 1 and are arranged in the second direction in sequence with intervals, the twelfth terminal 10112, the thirteenth terminal 10113, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, the seventeenth terminal 10117, the eighteenth terminal 10118 and the nineteenth terminal 10119 are located on the other side of the second direction of the housing 1 and are arranged in the first direction in sequence with intervals, the twentieth terminal 10120, the twenty-first terminal 10121, the twenty-second terminal 10122 and the twenty-third terminal 10123 are located on the other side of the first direction of the housing 1 and are arranged in the second direction in sequence with intervals.

[0213] Furthermore, the first terminal 1011, the second terminal 1012, the eighteenth terminal 10118 and the nineteenth terminal 10119 correspond to the second substrate part 2031 in the second direction, the third terminal 1013, the fourth terminal 10104, the fifth terminal 1015, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116 and the seventeenth terminal 10117 correspond to the third substrate part 2011 in the second direction, the sixth terminal 1016, the seventh terminal 1017, the twelfth terminal 10112 and the thirteenth terminal 10113 correspond to the first substrate part 2021 in the second direction.

[0214] In this way, the basic structure of the semiconductor module 100 can be formed, and the brake circuit, the rectifier circuit and the inverter circuit can be integrated, so that the layout of the circuit and the construction of the heat dissipation system can be simplified.

[0215] As shown in FIG. 18, the housing 1 is obtained by molding encapsulation, which can be generated by transfer molding with thermoplastic materials or with chemically cured materials, and the molding material can be epoxy resin. The second substrate part 2031, the third substrate part 2011, the first substrate part 2021, the brake chip 301, the rectifier chip 401, the inverter chip 10 and at least part of the external terminals 101 are arranged in the housing 1, and the housing 1 can also be filled with silicone gel 102, so that the housing 1 and the silicone gel 102 can provide physical and electrical protection for the second substrate part 2031, the third substrate part 2011, the first substrate part 2021, the brake chip 301, the rectifier chip 401, the inverter chip 10 and at least part of the external terminals 101, to prevent structural damage caused by external environmental impact and ensure normal operation of the semiconductor module 100.

[0216] In the embodiment of the present application, the constituent material of the silicone gel 102 includes, but is not limited to, a silicone gel and a rigid molding compound. The silicone gel 102 can be at least partially filled inside the housing 1 to cover the components and electrical connections on the substrate 2. The external terminal 101 is partially embedded in the silicone gel 102. Further, at least part of the external terminal 101 is not covered by the silicone gel 102 and protrudes through the silicone gel 102 to the outside of the housing 1. The silicone gel 102 is configured to protect the components and electrical connections inside the semiconductor module 100, in particular, to prevent the components and electrical connections inside the housing 1 from environmental influences and mechanical damage.

[0217] The first substrate portion 2021 is provided with the first high-side inverter chip-on-core region 5 and the first low-side inverter chip-on-core region 6 arranged along the second direction at intervals, and the first high-side inverter chip-on-core region 5 is more adjacent to the high side 10001 of the semiconductor module 100 than the first low-side inverter chip-on-core region 6, so that the high-voltage power chip can be arranged at the high side 10001 of the first substrate portion 2021. The second substrate portion 2031 is provided with the second high-side inverter chip-on-core region 7, the second low-side inverter chip-on-core region 8, and the third low-side inverter chip-on-core region 9 arranged along the second direction at intervals in sequence, and the second high-side inverter chip-on-core region 7 is more adjacent to the high side 10001 of the semiconductor module 100 than the second low-side inverter chip-on-core region 8, so that the high-voltage power chip can be arranged at the high side 10001 of the second substrate portion 2031.

[0218] In the embodiment of the present application, the first high-side inverter chip-on-core region 5, the second high-side inverter chip-on-core region 7, the first low-side inverter chip-on-core region 6, the second low-side inverter chip-on-core region 8, and the third low-side inverter chip-on-core region 9 can all be used to arrange the power chip in the semiconductor module 100.

[0219] The semiconductor module 100 is provided with a plurality of inverter chips 10, each of which is a single chip. Each of the plurality of inverter chips 10 is provided with a control electrode pad 1002, a first load electrode pad, and a second load electrode pad 1001, and the control between the first load electrode pad and the second load electrode pad 1001 is controlled by applying a driving voltage to the control electrode pad 1002 and the second load electrode pad 1001. For example, the inverter chip 10 is an inverse- conduction type insulated gate bipolar transistor, or a metal oxide semiconductor field effect transistor, etc.

[0220] When the inverter chip 10 is an inverse-conduction type insulated gate bipolar transistor, the first load electrode pad is a collector electrode pad, the second load electrode pad 1001 is an emitter electrode pad, and the control electrode pad 1002 is a gate electrode pad.

[0221] When the inverter chip 10 is a metal oxide semiconductor field effect transistor, the first load electrode pad is a drain pad, the second load electrode pad 1001 is a source pad, and the control electrode pad 1002 is a gate pad.

[0222] In the prior art, as shown in FIG. 15, each inverter chip 10 in the semiconductor module 100 includes an insulated gate bipolar transistor 25 and a fast recovery diode 24. For example, when the inverter chip 10 is arranged on the substrate 2, at least one insulated gate bipolar transistor 25 and one fast recovery diode 24 need to be arranged, so that the number of chips in the semiconductor module 100 of the prior art is large.

[0223] In the embodiments of the present application, the inverter chip 10 can integrate the insulated gate bipolar transistor 25 and the fast recovery diode 24 on one chip, which can reduce the number of chips in the semiconductor module 100 of the present application and integrate the functions of the chips. In this way, the number of conductive members 23 can be reduced, so that not only the manufacturing efficiency can be improved, but also the inductance can be reduced, so that the performance of the semiconductor module 100 can be improved.

[0224] It should be noted that in some embodiments of the present application, the conductive member 23 can be an electrically connected wire or an electrically connected sheet, etc.

[0225] The plurality of inverter chips 10 includes a first high-side inverter chip 11, a second high-side inverter chip 12, a third high-side inverter chip 13, a first low-side inverter chip 14, a second low-side inverter chip 15, and a third low-side inverter chip 16.

[0226] Further, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged on the first high-side inverter chip upper chip area 5 and are spaced apart in the first direction. In the embodiments of the present application, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged in the first direction of the first high-side inverter chip upper chip area 5, and mainly occupy the arrangement size of the first high-side inverter chip upper chip area 5 in the first direction. The first high-side inverter chip 11 and the second high-side inverter chip 12 are spaced apart, which not only ensures that the first high-side inverter chip 11 and the second high-side inverter chip 12 are independent of each other, but also is beneficial to heat dissipation of the first high-side inverter chip 11 and the second high-side inverter chip 12, and can prevent the first high-side inverter chip 11 and the second high-side inverter chip 12 from accumulating heat due to too close spacing, so that the first high-side inverter chip 11 and the second high-side inverter chip 12 can be prevented from being overheated and failing, and the reliability of the first high-side inverter chip 11 and the second high-side inverter chip 12 can be ensured.

[0227] In addition, the first high-side inverter chip 11 is farther away from the second substrate portion 2031 than the second high-side inverter chip 12 in the first direction, so that the arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12 on the first substrate portion 2021 can be facilitated, and the connection of the first high-side inverter chip 11 and the second high-side inverter chip 12 with other structures in the semiconductor module 100 can be facilitated.

[0228] The third high-side inverter chip 13 is arranged on the second high-side inverter chip upper die area 7, so that the third high-side inverter chip 13 is away from the first high-side inverter chip 11 and the second high-side inverter chip 12, to prevent the three inverter chips 10 from being too close to cause thermal failure of the device or the substrate 2.

[0229] The first low-side inverter chip 14 is arranged on the first low-side inverter chip upper die area 6, the second low-side inverter chip 15 is arranged on the second low-side inverter chip upper die area 8, and the third low-side inverter chip 16 is arranged on the third low-side inverter chip upper die area 9. In this way, the first high-side inverter chip 11, the second high-side inverter chip 12, the third high-side inverter chip 13, the third low-side inverter chip 16, the second low-side inverter chip 15, and the third low-side inverter chip 16 in the semiconductor module 100 can be arranged separately to form the basic structure of the semiconductor module 100, so as to ensure the normal operation of the semiconductor module 100.

[0230] The first low-side inverter chip upper die area 6 includes a wiring portion 601 and an upper die portion 602 connected to each other, the wiring portion 601 and the upper die portion 602 are arranged along the first direction, and the upper die portion 602 is located on the side of the wiring portion 601 facing the second substrate portion 2031. In the first low-side inverter chip upper die area 6, the wiring portion 601 can be used for wire bonding of the first low-side inverter chip upper die area 6, and the upper die portion 602 can be used for arranging the first low-side inverter chip 14. The upper die portion 602 is connected to the wiring portion 601, so that the upper die portion 602 is electrically connected to the wiring portion 601, the first load electrode pad of the first low-side inverter chip 14 is electrically connected to the upper die portion 602, and the wiring portion 601 is electrically connected to the first load electrode pad of the first low-side inverter chip 14, so as to ensure the normal operation of the first low-side inverter chip 14.

[0231] Further, the upper die portion 602 is close to the second substrate portion 2031 in the first direction, so that the first low-side inverter chip 14 can be arranged close to the second substrate portion 2031 in the first direction of the first low-side inverter chip upper die area 6, so as to reserve a position for the wiring portion 601 of the first low-side inverter chip upper die area 6 for wire bonding on the first low-side inverter chip upper die area 6.

[0232] The side of the upper core part 602 facing the low side 10002 is protruded toward the low side 10002 relative to the side of the wiring part 601 facing the low side 10002 to form a third avoiding gap 603, and the sixth jumper area 2201 is arranged in the third avoiding gap 603, so that the side of the first low side inverter core area 6 facing the low side 10002 is reserved for the sixth jumper area 2201.

[0233] Further, the sixth jumper area 2201 is arranged adjacent to the upper core part 602 in the first direction and adjacent to the wiring part 601 in the second direction, so that the sixth jumper area 2201 is arranged adjacent to the first low side inverter core area 6, to improve the structural compactness of the sixth jumper area 2201 and the first low side inverter core area 6 on the second substrate 2. The conductive member 23 is connected between the sixth jumper area 2201 and the control electrode pad 1002 of the brake chip 301.

[0234] In combination with FIG. 1, in the prior art, the inverter chip 10 is composed of at least two chips, including an insulated gate bipolar transistor 25 and a fast recovery diode 24, the fast recovery diode 24 and the insulated gate bipolar transistor 25 are arranged in the first direction and spaced apart on the first low side inverter core area 6, and the fast recovery diode 24 is arranged close to the third substrate part 2011. Because the fast recovery diode 24 needs to be wired, an additional pad needs to be arranged between the upper core part 602 and the sixth jumper area 2201 for wiring with the fast recovery diode 24. This additional pad occupies the arrangement space of the first low side inverter core area 6 in the first direction, limits the effective area of the first low side inverter core area 6 for arranging the inverter chip 10, and cannot arrange a larger specification inverter chip 10 on the substrate 2. Therefore, the current-carrying capacity of the semiconductor module 100 of the prior art is poor and cannot carry a larger current.

[0235] In the embodiment of the present application, as shown in FIGS. 19-21, each inverter chip 10 is a single chip, and integrates the functions of the insulated gate bipolar transistor 25 and the fast recovery diode 24, which is beneficial to reduce the number of chips in the semiconductor module 100, and further beneficial to reduce the stray inductance in the semiconductor module 100.

[0236] Further, in the first low side inverter core area 6, the first low side inverter chip 14 is a single chip, and there is no need to arrange an additional wiring area between the sixth jumper area 2201 and the upper core part 602, i.e., the upper core part 602 and the sixth jumper area 2201 are arranged adjacent to each other in the first direction on the edge of the first low side inverter core area 6 facing the low side 10002, so that the size of the upper core part 602 in the first direction can be increased.

[0237] In addition, the side of the upper core portion 602 facing the low side 10002 is convex toward the low side 10002 relative to the side of the wiring portion 601 facing the low side 10002, which can increase the size of the upper core portion 602 in the second direction.

[0238] In this way, the effective area for arranging the inverter chip 10 in the first low-side inverter chip upper core area 6 can be increased, and thus a first low-side inverter chip 14 of a larger specification and size can be arranged in the first low-side inverter chip upper core area 6, which can improve the current carrying capacity of the semiconductor module 100.

[0239] The fifteenth terminal 10115 on the housing 1 is electrically connected to the control electrode pad 1002 of the first low-side inverter chip 14, and the fifteenth terminal 10115 corresponds to the edge of the first substrate portion 2021 facing the low side 10002. By arranging the control electrode pad 1002 of the first low-side inverter chip 14 on the first low-side inverter chip 14 along the second direction to be more adjacent to the low side 10002, the distance between the control electrode pad 1002 of the first low-side inverter chip 14 and the fifteenth terminal 10115 electrically connected in the second direction can be shortened.

[0240] Further, by arranging the control electrode pad 1002 of the first low-side inverter chip 14 on the first low-side inverter chip 14 along the first direction to be more adjacent to the third substrate portion 2011, the conductive member 23 between the control electrode pad 1002 of the first low-side inverter chip 14 and the fifteenth terminal 10115 can be prevented from interfering with the arrangement of other conductive members 23 in the semiconductor module 100.

[0241] In some embodiments of the present application, as shown in FIGS. 20 and 23, the sum of the sizes of the upper core portion 602 and the wiring portion 601 in the first direction is A2, and the size of the upper core portion 602 in the first direction is B2. A2 and B2 satisfy the relationship B2≥0.5A2.

[0242] It can be understood that the size of the upper core portion 602 in the first direction cannot be too small, otherwise the arrangement of the first low-side inverter chip 14 on the upper core portion 602 along the first direction will be limited, and the inverter chip 10 of a larger specification and size cannot be arranged on the upper core portion 602. In order to arrange the first low-side inverter chip 14 of a larger specification and size in the first low-side inverter chip upper core area 6, B2 / A2 is set to be not less than 0.5. For example, B2 / A2 can be 0.5, 0.6, or 0.7. In a specific design, a suitable specific parameter is selected.

[0243] Therefore, by setting the first low-side inverter chip 14 as a single chip, and arranging the upper core area 6 of the first low-side inverter chip on the upper core portion 602 close to the second substrate portion 2031, and making the size of the upper core portion 602 in the first direction at least half of the size of the upper core area 6 of the first low-side inverter chip in the first direction, the effective area for setting the first low-side inverter chip 14 on the first substrate portion 2021 can be increased, so that a larger specification inverter chip 10 can be set in the semiconductor module 100. In this way, under the same package specification of the semiconductor module 100 in the prior art and the semiconductor module 100 in the embodiment of the present application, the current-carrying capacity of the semiconductor module 100 in the embodiment of the present application can be improved, and the performance of the semiconductor module 100 in the embodiment of the present application can be improved.

[0244] In the prior art, the size of the upper core portion 602 of the first low-side inverter chip upper core area 6 in the first direction is 8.3 mm.

[0245] In the embodiment of the present application, the upper core portion 602 and the sixth jumper area 2201 are arranged adjacent in the first direction, so that the size of the upper core portion 602 in the first direction can be increased, and a larger first low-side inverter chip 14 than in the prior art can be arranged in the first low-side inverter chip upper core area 6.

[0246] In some specific embodiments of the present application, as shown in FIGS. 20 and 23, the size of the upper core portion 602 in the first direction is B2, which satisfies the relationship: B2≥9.27 mm.

[0247] It can be understood that the size of the upper core portion 602 in the first direction in the embodiment of the present application cannot be too small, otherwise a larger specification inverter chip 10 cannot be arranged, and the current-carrying capacity of the semiconductor module 100 cannot be improved. In order to arrange a larger specification inverter chip 10 in the upper core portion 602 of the first low-side inverter chip upper core area 6, the size B2 of the upper core portion 602 in the first direction is set to be not less than 9.27 mm. For example, B2 can be 9.27 mm, 9.35 mm, or 9.43 mm. In the specific design, a suitable specific parameter is selected.

[0248] In some specific embodiments of the present application, the first low-side inverter chip 14 has a control electrode flow channel 19, the second load electrode pad 1001 of the first low-side inverter chip 14 includes two sub-load electrode pads 10011, the control electrode flow channel 19 is arranged between the two sub-load electrode pads 10011, and the control electrode flow channel 19 of the first low-side inverter chip 14 extends along the second direction.

[0249] Specifically, the first low-side inverter chip 14 can be a reverse-conducting insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor. The first low-side inverter chip 14 is provided with a control electrode flow channel 19 extending in the second direction. In the reverse-conducting insulated gate bipolar transistor or the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0250] In the embodiment of the present application, the second load electrode pad 1001 on the first low-side inverter chip 14 includes two sub-load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub-load electrode pads 10011. In this way, the two sub-load electrode pads 10011 can extend in the same direction as the control electrode flow channel 19, and the conductive member 23 on the two sub-load electrode pads 10011 can be parallel to the control electrode flow channel 19, thereby ensuring the structural reliability of the first low-side inverter chip 14.

[0251] In some specific embodiments of the present application, as shown in FIGS. 20 and 23, the sixth jumper area 2201 is also connected with the conductive member 23 between the external terminal 101. The size of the sixth jumper area 2201 in the first direction is C2, and C2 satisfies the relationship C2≥4.4 mm.

[0252] Specifically, the brake transistor 3012 includes a control electrode pad 1002, and the control electrode pad 1002 on the brake transistor 3012 is connected with the conductive member 23 between the sixth jumper area 2201 and the external terminal 101.

[0253] In the prior art, the conductive member 23 between the control electrode pad 1002 of the brake chip 301 and the sixth jumper area 2201 and the conductive member 23 between the sixth jumper area 2201 and the external terminal 101 have the same thickness, and the two are connected through a jumper point on the sixth jumper area 2201. The sixth jumper area 2201 has a small settable area.

[0254] In the embodiment of the present application, the conductive members 23 between the control electrode pad 1002 of the brake chip 301 and the sixth jumper area 2201 and the sixth jumper area 2201 and the external terminal 101 can select conductive members 23 of different thicknesses to be suitable for different sizes of current. However, conductive members 23 of different thicknesses cannot be connected through one jumper point, and the conductive members 23 between the control electrode pad 1002 of the brake chip 301 and the sixth jumper area 2201 and the conductive members 23 between the sixth jumper area 2201 and the external terminal 101 need to be provided with jumper points on the sixth jumper area 2201, and the electrical connection is realized through the sixth jumper area 2201. Therefore, the settable area of the sixth jumper area 2201 needs to be increased.

[0255] Therefore, the size of the sixth jumper area 2201 in the first direction in the embodiment of the present application cannot be too small, otherwise it cannot meet the requirement of providing at least two jumper points on the sixth jumper area 2201, and further makes the control electrode pad 1002 of the brake chip 301 and the external terminal 101 cannot be connected by conductive members 23 of different sizes.

[0256] In order to ensure that the conductive members 23 between the control electrode pad 1002 of the brake chip 301 and the sixth jumper area 2201 and the conductive members 23 between the sixth jumper area 2201 and the external terminal 101 can select different conductive members 23, the size C2 of the sixth jumper area 2201 in the first direction in the embodiment of the present application is not less than 4.4 mm. For example, C2 can be 4.4 mm, 5.0 mm, or 5.5 mm. In the specific design, a suitable specific parameter is selected.

[0257] In some specific embodiments of the present application, in combination with FIG. 22, the fourth avoiding gap 604 is provided on the first high-side inverter chip upper chip area 5, and the seventh jumper area 2202 is provided in the fourth avoiding gap 604, so that the first high-side inverter chip upper chip area 5 avoids the setting of the seventh jumper area 2202 on the first substrate part 2021.

[0258] The seventh jumper area 2202 includes a first jumper area 5021 and a second jumper area 5022, the first jumper area 5021 extends in the second direction and is located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction, and the conductive member 23 is connected between the second load electrode pad 1001 of the first high-side inverter chip 11 and the first jumper area 5021. In this way, the second load electrode pad 1001 of the first high-side inverter chip 11 can be electrically connected to the first jumper area 5021 to ensure that the first high-side inverter chip 11 can be normally driven when working.

[0259] As shown in FIGS. 20, 21 and 22, the second jumper area 5022 is connected to the first jumper area 5021 at an end of the first low side 10002 in the second direction, and the second jumper area 5022 extends towards the side of the third substrate portion 2011 in the first direction, and the conductive member 23 is connected between the second jumper area 5022 and the wiring portion 601.

[0260] Specifically, the second jumper area 5022 is connected to the first jumper area 5021, so that the second jumper area 5022 is electrically connected to the first jumper area 5021. The second jumper area 5022 is located at the end of the first low side 10002 in the second direction, so that the second jumper area 5022 is close to the first low side inverter chip upper core area 6. In this way, the length of the conductive member 23 between the wiring portion 601 and the third jumper can be shortened, and the deformation of the conductive member 23 due to the excessive length can be avoided, so as to ensure the structural reliability of the conductive member 23.

[0261] The extension direction of the second jumper area 5022 is from the first jumper area 5021 towards the side of the third substrate portion 2011 in the first direction, so that the area of the second jumper area 5022 can be increased, and the wire bonding on the second jumper area 5022 can be facilitated.

[0262] In some embodiments of the present application, as shown in FIGS. 20, 21 and 22, the eighth jumper area 2203 is further provided on the first substrate portion 2021, and the eighth jumper area 2203 includes the third jumper area 1701, the fourth jumper area 1702 and the fifth jumper area 1703.

[0263] The third jumper area 1701 is arranged at the side of the first low side inverter chip upper core area 6 adjacent to the low side 10002 in the second direction, and the third jumper area 1701 extends in the first direction. This not only increases the size of the eighth jumper area 2203 in the first direction, but also at least partially arranges the eighth jumper area 2203 between the first low side inverter chip 14 and the external terminal 101, so as to facilitate the wire bonding between the first low side inverter chip 14 and the eighth jumper area 2203, and facilitate the wire bonding between the external terminal 101 and the first low side inverter chip 14.

[0264] In this way, the length of the conductive member 23 between the first low side inverter chip 14 and the external terminal 101 can be shortened, and the stray inductance in the semiconductor module 100 can be reduced. In addition, the heat dissipation of the conductive member 23 between the first low side inverter chip 14 and the external terminal 101 can be facilitated, the heat accumulation in the semiconductor module 100 can be reduced, and the current carrying capacity of the conductive member 23 can be improved.

[0265] Specifically, the conductive piece 23 between the two sub-load electrode pads 10011 on the first low-side inverter chip 14 and the third jumper area 1701 is connected by the conductive piece 23, and the third jumper area 1701 and the fourteenth terminal 10114 are connected by the conductive piece 23.

[0266] Further, the fourth jumper area 1702 and the fifth jumper area 1703 are respectively connected at both ends of the first direction of the third jumper area 1701, and the fourth jumper area 1702 and the fifth jumper area 1703 extend towards the side more adjacent to the high side 10001 in the second direction. In this way, on the one hand, the size of the eighth jumper area 2203 in the second direction can be increased, and the jumper point of the conductive piece 23 can be provided with a setting position, on the other hand, it can be convenient to arrange the jumper point on both sides of the eighth jumper area 2203 in the first direction, so as to facilitate the wire bonding between the third substrate part 2011 and the first substrate part 2021, and can facilitate the wire bonding between the second substrate part 2031 and the first substrate part 2021.

[0267] In the embodiment of the present application, the second load electrode pad 1001 on the brake transistor 3012 is connected with the eighth jumper area 2203 by the conductive piece 23, and the second load electrode pad 1001 on the third low-side inverter chip 16 and the second low-side inverter chip 15 in the second substrate part 2031 are connected with the eighth jumper area 2203 by the conductive piece 23.

[0268] In the prior art, the first high-side inverter chip 11 is composed of a fast recovery diode 24 and an insulated gate bipolar transistor 25, and the fast recovery diode 24 is arranged on the first high-side inverter chip on the position adjacent to the first low-side inverter chip on the chip area 5. Since the fast recovery diode 24 in the first high-side inverter chip 11 needs to be wire-bonded, in the second direction, a jumper area needs to be arranged between the eighth jumper area 2203 and the first high-side inverter chip on the chip area 5, so as to facilitate the arrangement of the jumper point of the fast recovery diode 24. In this way, the eighth jumper area 2203 and the first high-side inverter chip on the chip area 5 need to avoid the jumper area, which causes the area of the eighth jumper area 2203 close to the second substrate part 2031 to be unable to continue to extend towards the high side 10001 in the second direction, and further to the eighth jumper area 2203 and the conductive piece 23 on the second substrate part 2031 is longer, and the stability and heat dissipation are poor.

[0269] In the embodiments of the present application, the first high-side inverter chip-on-chip region 5 is provided with a fifth avoiding gap 605 on the side adjacent to the second substrate portion 2031 in the first direction, the fifth avoiding gap 605 is located at the end of the first high-side inverter chip-on-chip region 5 more adjacent to the low side 10002 in the second direction, and the end of the fifth jumper area 1703 adjacent to the high side 10001 in the second direction at least partially extends into the fifth avoiding gap 605.

[0270] The first high-side inverter chip 11 is a single chip, the number of chips is reduced, and the functions of the insulated gate bipolar transistor 25 and the fast recovery diode 24 can be integrated, the second load electrode pad 1001 on the first high-side inverter chip 11 is directly wired with the second substrate portion 2031, and there is no need to arrange an additional jumper area between the first high-side inverter chip-on-chip region 5 and the eighth jumper area 2203, so that the end of the fifth jumper area 1703 in the eighth jumper area 2203 adjacent to the high side 10001 in the second direction at least partially extends into the fifth avoiding gap 605. In this way, the size of the fifth jumper area 1703 in the second direction can be extended, and the fifth jumper area 1703 can be arranged close to the high side 10001 of the second substrate portion 2031 in the second direction.

[0271] In this way, the distance between the fifth jumper area 1703 in the second direction and the high side 10001 region of the second substrate portion 2031 can be shortened, and the length of the at least partial conductive member 23 between the second substrate portion 2031 and the fifth jumper area 1703 can be shortened, so as to improve the structural reliability and heat dissipation of the partial conductive member 23. Therefore, compared with the prior art, the performance of the semiconductor module 100 in the present application is better.

[0272] In some embodiments of the present application, as shown in FIGS. 20, 21 and 22, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged more adjacent to the high side 10001 of the semiconductor module 100 in the second direction on the first high-side inverter chip-on-chip region 5, and the first high-side inverter chip 11 and the second high-side inverter chip 12 are both high-voltage power chips in the semiconductor module 100.

[0273] As shown in FIGS. 16-21, the second load electrode pad 1001 of the first high-side inverter chip 11 is connected with the seventh jumper area 2202 through the conductive member 23, the control electrode pad 1002 of the first high-side inverter chip 11 is arranged more adjacent to the high side 10001 in the second direction on the first high-side inverter chip 11, and the control electrode pad 1002 of the first high-side inverter chip 11 is electrically connected with the external terminal 101.

[0274] In the prior art, as shown in FIG. 15, the first high-side inverter chip 11 and the second high-side inverter chip 12 are composed of at least one insulated gate bipolar transistor 25 and one fast recovery diode 24. When the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged on the third substrate part 2011, the fast recovery diode 24 and the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 are arranged in the second direction, and the fast recovery diode 24 constituting the first high-side inverter chip 11 is closer to the high side 10001, and the insulated gate bipolar transistor 25 is closer to the low side 10002. The seventh jumper area 2202 connected to the second load electrode pad 1001 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is arranged between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction. In order to ensure stable connection between the second load electrode pad 1001 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 and the seventh jumper area 2202, the control electrode flow channel 19 between the two sub load electrode pads 10011 in the second load electrode pad 1001 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 needs to be arranged in the first direction. In this case, the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is on the side closer to the low side 10002 in the second direction of the insulated gate bipolar transistor 25, and the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is on the side closer to the first substrate part 2021 in the first direction of the insulated gate bipolar transistor 25. At this time, in order to avoid the excessive length of the conductive part 23 between the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 and the external terminal 101, the ninth jumper area 2204 needs to be arranged to electrically connect to the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11. Due to the limitation of the position of the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11, the ninth jumper area 2204 can only be arranged between the first high-side inverter chip 11 and the second high-side inverter chip 12, so that the conductive part 23 between the ninth jumper area 2204 and the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is stably connected, and does not intersect with other conductive parts 23.

[0275] The prior art is thus arranged, which causes the size of the fourth avoiding gap 604 in the first direction between the first high-side inverter chip 11 and the second high-side inverter chip 12 to be large enough to accommodate the seventh jumper area 2202 and the ninth jumper area 2204, that is, the size of the part of the first high-side inverter chip 11 and the second high-side inverter chip 12 arranged on the first high-side inverter chip upper area 5 in the first direction is small in the prior art. When the first high-side inverter chip 11 and the second high-side inverter chip 12 are both composed of at least one insulated gate bipolar transistor 25 and one fast recovery diode 24, and the insulated gate bipolar transistor 25 and the fast recovery diode 24 are spaced apart in the second direction, the arrangement area of the chip can meet the demand. However, when the first high-side inverter chip 11 and the second high-side inverter chip 12 are single chips and large in size, the layout of the third substrate part 2011 of the prior art cannot meet the arrangement area of the first high-side inverter chip 11 and the second high-side inverter chip 12.

[0276] In the embodiment of the present application, the control electrode pad 1002 of the first high-side inverter chip 11 can be directly electrically connected with the external terminal 101; or the control electrode pad 1002 of the first high-side inverter chip 11 can be electrically connected with the jumper pad through the conductive piece 23, and then the jumper pad can be electrically connected with the external terminal 101 through the conductive piece 23.

[0277] In an embodiment of the present application, the control electrode pad 1002 of the first high-side inverter chip 11 is directly electrically connected with the external terminal 101. Since the control electrode pad 1002 of the first high-side inverter chip 11 is arranged more adjacent to the high side 10001 on the first high-side inverter chip 11 in the second direction, the path of the electrical connection between the control electrode pad 1002 of the first high-side inverter chip 11 and the external terminal 101 is short.

[0278] In another embodiment of the present application, the ninth jumper area 2204 is further arranged on the first substrate part 2021. It should be noted that the ninth jumper area 2204 is the jumper pad described above. The ninth jumper area 2204 is arranged in the fourth avoiding gap 604. The edge of the first high-side inverter chip 11 closer to the high side 10001 in the second direction is defined as the high side edge 1104. The ninth jumper area 2204 is arranged on the side of the high side edge 1104 in the second direction facing the high side 10001, and is arranged on the side of the first jumper area 5021 away from the second substrate part 2031 in the first direction. The control electrode pad 1002 of the first high-side inverter chip 11 is arranged more adjacent to the high side 10001 on the first high-side inverter chip 11 in the second direction, and is arranged more away from the second substrate part 2031 on the first high-side inverter chip 11 in the first direction.

[0279] Specifically, the fourth terminal 10104 corresponds to the first substrate portion 2021, and is arranged on the side of the first substrate portion 2021 close to the high side 10001. The fourth terminal 10104 is arranged on the side close to the second high-side inverter chip 12 in the first direction compared with the ninth jumper area 2204, so that the ninth jumper area 2204 can be arranged between the control electrode pad 1002 of the first high-side inverter chip 11 and the fourth terminal 10104.

[0280] In this way, on the one hand, the ninth jumper area 2204 can be arranged close to the first high-side inverter chip 11, and the distance between the ninth jumper area 2204 and the control electrode pad 1002 of the first high-side inverter chip 11 can be shortened, which is conducive to shortening the length of the conductive member 23 between the control electrode pad 1002 of the first high-side inverter chip 11 and the ninth jumper area 2204, and further preventing the influence of the too long conductive member 23 on the switching speed and stability of the first high-side inverter chip 11. On the other hand, the ninth jumper area 2204 can be removed from between the first high-side inverter chip 11 and the second high-side inverter chip 12, which reduces the structure between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction, and further increases the effective area of the first high-side inverter chip 11 on the inverter chip 10 arrangement area 5, so that the effective area of the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first high-side inverter chip on the inverter chip 10 arrangement area 5 can be increased while the positions of the first high-side inverter chip 11 and the second high-side inverter chip 12 remain unchanged.

[0281] In this way, in the embodiment of the present application, by adjusting the position of the ninth jumper area 2204 on the first substrate portion 2021, the first substrate portion 2021 can be conveniently arranged with a larger specification inverter chip 10, so that the semiconductor module 100 in the embodiment of the present application can improve the current-carrying capacity of the semiconductor module 100 in the embodiment of the present application under the same package specification as the semiconductor module 100 in the prior art, and further improve the performance of the semiconductor module 100 in the embodiment of the present application.

[0282] In the embodiment of the present application, the seventh jumper area 2202 further includes a sixth jumper area 5023 connected to one end of the first jumper area 5021 adjacent to the high side 10001 in the second direction, so that the sixth jumper area 5023 can be electrically connected to the first jumper area 5021. The sixth jumper area 5023 extends towards the side adjacent to the second substrate portion 2031 in the first direction, so that the area of the sixth jumper area 5023 can be increased, the wire bonding on the sixth jumper area 5023 can be facilitated, and the sixth jumper area 5023 can also avoid the arrangement of the ninth jumper area 2204.

[0283] In the embodiments of the present application, as shown in FIGS. 19, 20, and 21, the fifth terminal 1015 is located on the side of the sixth jumper region 5023 in the first direction toward the first substrate portion 2021, and a conductive member 23 is connected between the fifth terminal 1015 and the sixth jumper region 5023. In this way, the fifth terminal 1015 can be arranged to avoid the fourth terminal 10104, thereby facilitating the shortening of the conductive member 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the ninth jumper region 2204, and the shortening of the conductive member 23 between the ninth jumper region 2204 and the fourth terminal 10104.

[0284] As shown in FIGS. 19-21, the first substrate portion 2021 has a dimension D2 in the second direction, and the distance E between the edge of the first high-side inverter chip 11 toward the high side 10001 and the edge of the first substrate portion 2021 toward the high side 10001 satisfies the relationship 0.086D2≤E2≤0.117D2.

[0285] In some embodiments of the present application, E2 / D2 is not more than 0.117. For example, E2 / D2 can be 0.117, 0.116, or 0.115. If the ratio of the distance E between the edge of the first high-side inverter chip 11 toward the high side 10001 and the edge of the first substrate portion 2021 toward the high side 10001 to the dimension D2 of the first substrate portion 2021 in the second direction is too large, the first high-side inverter chip 11 will be arranged on the first substrate portion 2021 close to the low side 10002 of the semiconductor module 100, which will make the distance between the first high-side inverter chip 11 and the first low-side inverter chip 14 too close, and not conducive to the heat dissipation of the first high-side inverter chip 11. In order to ensure the heat dissipation of the first high-side inverter chip 11 and the reliability of the semiconductor module 100, E2 / D2 needs to be set to not more than 0.117, and a suitable specific parameter can be selected in the specific design.

[0286] In some embodiments of the present application, E2 / D2 is not less than 0.086. For example, E2 / D2 can be 0.086, 0.087, or 0.088. If the ratio of the distance between the edge of the first high-side inversion chip 11 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 to the size of the first substrate portion 2021 in the second direction is too small, the first high-side inversion chip 11 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, which is not conducive to the packaging of the shell 1 and will affect the structural reliability of the semiconductor module 100. Therefore, E2 / D2 needs to be set to not more than 0.117, and a suitable specific parameter is selected in the specific design.

[0287] In combination with FIGS. 5-7, the size of the first substrate portion 2021 in the second direction is D2, the distance between the edge of the second high-side inversion chip 12 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 is F2, and D2 and F2 satisfy the relationship: 0.086D2≤F2≤0.117D2.

[0288] In some embodiments of the present application, F2 / D2 is not more than 0.117. For example, F2 / D2 can be 0.117, 0.116, or 0.115. If the ratio of the distance between the edge of the second high-side inversion chip 12 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 to the size of the first substrate portion 2021 in the second direction is too large, the second high-side inversion chip 12 will be arranged on the first substrate portion 2021 close to the low side 10002 of the semiconductor module 100, which will make the second high-side inversion chip 12 too close to the first low-side inversion chip 14, which is not conducive to the heat dissipation of the second high-side inversion chip 12. To ensure the heat dissipation of the second high-side inversion chip 12 and the reliability of the semiconductor module 100, F2 / D2 needs to be set to not more than 0.117, and a suitable specific parameter is selected in the specific design.

[0289] In some embodiments of the present application, F2 / D2 is not less than 0.086. For example, F2 / D2 can be 0.086, 0.087, or 0.088. If the ratio of the distance between the edge of the second high-side inversion chip 12 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 to the size of the first substrate portion 2021 in the second direction is too small, the second high-side inversion chip 12 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, which is not conducive to the packaging of the shell 1 and will affect the structural reliability of the semiconductor module 100. Therefore, F2 / D2 needs to be set to not less than 0.086, and a suitable specific parameter is selected in the specific design.

[0290] As shown in FIGS. 19, 20, 21 and 24, the third high-side inversion chip 13 is located in the middle of the second substrate portion 2031 in the first direction, so that the two sides of the third high-side inversion chip 13 in the first direction are located at a distance close to the two sides of the second substrate portion 2031 in the first direction. In this way, the heat of the two sides of the third high-side inversion chip 13 in the first direction can be simultaneously transmitted to the edges of the second substrate portion 2031, so that the heat dissipation efficiency of the two sides of the third high-side inversion chip 13 in the first direction is the same, thereby ensuring the heat dissipation effect of the two sides of the third high-side inversion chip 13 in the first direction, and solving the problem of heat accumulation caused by low heat dissipation efficiency of one side of the third high-side inversion chip 13 in the first direction, thereby facilitating the improvement of the heat dissipation performance of the third high-side inversion chip 13

[0291] As shown in FIGS. 19, 20, 21 and 24, the control electrode pad 1002 of the third high-side inversion chip 13 is arranged more adjacent to the high side 10001 of the third high-side inversion chip 13 in the second direction; and the control electrode pad 1002 of the third high-side inversion chip 13 is arranged more adjacent to the first substrate portion 2021 of the third high-side inversion chip 13 in the first direction.

[0292] Specifically, the third high-side inversion chip 13 is a high-side power chip in the semiconductor module 100, and the control electrode pad 1002 of the third high-side inversion chip 13 is arranged close to the high side 10001 of the semiconductor module 100 in the second direction and adjacent to the first substrate portion 2021 in the first direction. The eighth terminal 1018 on the shell 1 is arranged between the control electrode pad 1002 of the third high-side inversion chip 13 and the conductive piece 23, and the eighth terminal 1018 is located on the side of the third high-side inversion chip 13 away from the first substrate portion 2021 in the first direction. In this way, the conductive piece 23 between the control electrode pad 1002 on the third high-side inversion chip 13 and the eighth terminal 1018 can be prevented from being too long and deformed, and the reliability of the conductive piece 23 between the control electrode pad 1002 on the third high-side inversion chip 13 and the eighth terminal 1018 can be ensured.

[0293] As shown in FIGS. 20, 24 and 28, the third high-side inversion chip 13 has a control electrode flow channel 19, the second load electrode pad 1001 of the third high-side inversion chip 13 includes two sub-load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub-load electrode pads 10011. The control electrode flow channel 19 of the third high-side inversion chip 13 extends in the first direction.

[0294] Specifically, the third high-side inverter chip 13 can be a reverse conducting IGBT and MOSFET. The third high-side inverter chip 13 is provided with a control electrode flow channel 19 extending in the first direction. In the reverse conducting IGBT and MOSFET, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0295] In the embodiment, the second load electrode pad 1001 on the third high-side inverter chip 13 includes two sub-load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub-load electrode pads 10011. In this way, the two sub-load electrode pads 10011 can extend in the same direction as the control electrode flow channel 19, and the conductive member 23 on the two sub-load electrode pads 10011 can be parallel to the control electrode flow channel 19, thereby ensuring the structural reliability of the third high-side inverter chip 13.

[0296] As shown in FIGS. 19, 20, 21 and 24, the second substrate portion 2031 is further provided with a tenth jumper zone 2205 located on the side of the second high-side inverter chip upper chip zone 7 away from the first substrate portion 2021 in the first direction. In this way, the tenth jumper zone 2205 can be arranged between the third high-side inverter chip 13 and the eighth terminal 1018, and the conductive member 23 is connected between the control electrode pad 1002 of the third high-side inverter chip 13 and the tenth jumper zone 2205.

[0297] Specifically, when the third high-side inverter chip 13 is wire-bonded with the eighth terminal 1018, the conductive member 23 is arranged between the third high-side inverter chip 13 and the tenth jumper zone 2205, and the tenth jumper zone 2205 is arranged between the tenth jumper zone 2205 and the eighth terminal 1018. In this way, on the one hand, the third high-side inverter chip 13 can be connected with the eighth terminal 1018, and on the other hand, the length of the conductive member 23 arranged between the third high-side inverter chip 13 and the eighth terminal 1018 can be shortened by arranging the tenth jumper zone 2205. In this way, the heat generated by the conductive member 23 can be reduced, and the temperature at both ends of the conductive member 23 can be reduced, thereby improving the reliability of the semiconductor module 100.

[0298] As shown in FIGS. 20, 21 and 24, the third low-side inversion chip 16 is arranged in the middle of the second substrate portion 2031 in the first direction, so that the two sides of the third low-side inversion chip 16 in the first direction are arranged to be close to the two sides of the second substrate portion 2031 in the first direction. In this way, the heat of the two sides of the third low-side inversion chip 16 in the first direction can be simultaneously transmitted to the edges of the second substrate portion 2031, so that the heat dissipation efficiency of the two sides of the third low-side inversion chip 16 in the first direction is the same, thereby ensuring the heat dissipation effect of the two sides of the third low-side inversion chip 16 in the first direction, and solving the problem of heat accumulation caused by low heat dissipation efficiency of one side of the third low-side inversion chip 16 in the first direction, thereby facilitating the improvement of the heat dissipation performance of the third low-side inversion chip 16.

[0299] In addition, the second load electrode pad 1001 on the third low-side inversion chip 16 needs to be connected to the jumper area on the first substrate portion 2021 through the conductive member 23, and the control electrode pad 1002 on the third low-side inversion chip 16 needs to be connected to the jumper area on the part of the second substrate portion 2031 away from the third low-side inversion chip 16 in the first direction through the conductive member 23. By arranging the third low-side inversion chip 16 in the middle of the second substrate portion 2031 in the first direction, the conductive member 23 between the second load electrode pad 1001 on the third low-side inversion chip 16 and the jumper area on the first substrate portion 2021 can not be too long, which can reduce the internal inductance, suppress the surge voltage generated between the first load electrode pad and the second load electrode pad 1001 on the second low-side inversion chip 15, and also can prevent one of the two conductive members 23 from being too long and the other from being too short, which affects the performance of the third low-side inversion chip 16. In this way, the lengths of the two conductive members 23 are reasonably balanced, thereby improving the performance of the third low-side inversion chip 16.

[0300] As shown in FIGS. 19, 20, 21 and 24, the control electrode pad 1002 of the third low-side inversion chip 16 is arranged more adjacent to the low side 10002 on the third low-side inversion chip 16 in the second direction; and the control electrode pad 1002 of the third low-side inversion chip 16 is arranged away from one end of the first substrate portion 2021 on the third low-side inversion chip 16 in the first direction.

[0301] Specifically, the third low-side inverter chip 16 is a low-side power chip in the semiconductor module 100, and the control electrode pad 1002 thereof is arranged close to the low side 10002 of the semiconductor module 100 in the second direction and away from one end of the first substrate portion 2021 in the first direction. The conductive member 23 is arranged between the twelfth terminal 10112 on the shell 1 and the control electrode pad 1002 of the third low-side inverter chip 16, and the twelfth terminal 10112 is located at a position closer to the low side 10002 of the semiconductor module 100 in the second direction, so that the control electrode pad 1002 on the third low-side inverter chip 16 is arranged close to the twelfth terminal 10112, and the conductive member 23 between the control electrode pad 1002 on the third low-side inverter chip 16 and the twelfth terminal 10112 can be prevented from being too long and deformed, and the reliability of the conductive member 23 between the control electrode pad 1002 on the third low-side inverter chip 16 and the twelfth terminal 10112 can be ensured.

[0302] As shown in FIGS. 20, 24 and 28, the third low-side inverter chip 16 has a control electrode flow channel 19, the second load electrode pad 1001 of the third low-side inverter chip 16 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011. The control electrode flow channel 19 of the third low-side inverter chip 16 extends in the first direction.

[0303] Specifically, the third low-side inverter chip 16 includes, but is not limited to, a reverse-conducting insulated gate bipolar transistor and a metal oxide semiconductor field effect transistor. The control electrode flow channel 19 is arranged on the third low-side inverter chip 16 and extends in the first direction. In the reverse-conducting insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0304] In the embodiment of the present application, the second load electrode pad 1001 on the third low-side inverter chip 16 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011. In this way, the two sub load electrode pads 10011 can extend in the same direction as the control electrode flow channel 19, and the conductive member 23 on the two sub load electrode pads 10011 can be parallel to the control electrode flow channel 19, so as to ensure the structural reliability of the third low-side inverter chip 16.

[0305] In the embodiment of the present application, the fourteenth terminal 10114 corresponding to the first substrate portion 2021 is provided with a conductive member 23 between the third low-side inversion chip 16 and the second load electrode pad 1001. The third low-side inversion chip 16 is arranged in the middle of the first substrate portion 2021, which is conducive to preventing any of the conductive member 23 connected to the control electrode pad 1002 of the third low-side inversion chip 16 and the conductive member 23 connected to the second load electrode pad 1001 from being too long, and thus the reliability of the conductive member 23 connected to the control electrode pad 1002 of the third low-side inversion chip 16 and the conductive member 23 connected to the second load electrode pad 1001 can be improved.

[0306] As shown in FIGS. 20, 21 and 24, the second low-side inversion chip 15 is arranged more adjacent to the first substrate portion 2021 along the first direction on the second substrate portion 2031, which can stagger the arrangement of the second low-side inversion chip 15 and the third low-side inversion chip 16 along the first direction. In this way, on the one hand, it can prevent the second low-side inversion chip 15 and the third low-side inversion chip 16 from being too close to each other, which can cause excessive heat accumulation in the semiconductor module 100; on the other hand, it can reduce the stray inductance generated between the second low-side inversion chip 15 and the third low-side inversion chip 16, and prevent the two ends of the second low-side inversion chip 15 and the two ends of the third low-side inversion chip 16 from generating a sharp voltage and failing, and thus the reliability of the semiconductor module 100 can be improved.

[0307] As shown in FIGS. 19, 20, 21 and 24, the control electrode pad 1002 of the second low-side inversion chip 15 is arranged more adjacent to the low side 10002 along the second direction on the second low-side inversion chip 15; and the control electrode pad 1002 of the second low-side inversion chip 15 is arranged more adjacent to the end of the second low-side inversion chip 15 away from the first substrate portion 2021 along the first direction on the second low-side inversion chip 15.

[0308] Specifically, the second low-side inverter chip 15 is a low-side power chip in the semiconductor module 100, the control electrode pad 1002 of which is arranged in the second direction close to the low side 10002 of the semiconductor module 100, and in the first direction adjacent to one end of the second low-side inverter chip 15 away from the first substrate part 2021. The thirteenth terminal 10113 on the shell 1 is provided with a conductive part 23 between the control electrode pad 1002 of the second low-side inverter chip 15, and the thirteenth terminal 10113 is arranged in a position closer to the low side 10002 in the second direction of the semiconductor module 100, so that the control electrode pad 1002 on the second low-side inverter chip 15 is arranged close to the thirteenth terminal 10113, which can prevent the conductive part 23 between the control electrode pad 1002 on the second low-side inverter chip 15 and the thirteenth terminal 10113 from being too long and deformed, and can ensure the reliability of the conductive part 23 between the control electrode pad 1002 on the second low-side inverter chip 15 and the thirteenth terminal 10113.

[0309] As shown in FIGS. 20, 24 and 28, the second low-side inverter chip 15 has a control electrode flow channel 19, the second load electrode pad 1001 of the second low-side inverter chip 15 includes two sub-load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub-load electrode pads 10011. The control electrode flow channel 19 of the second low-side inverter chip 15 extends in the first direction.

[0310] Specifically, the second low-side inverter chip 15 can be an inverse-parallel insulated gate bipolar transistor and a metal oxide semiconductor field effect transistor. The control electrode flow channel 19 is arranged on the second low-side inverter chip 15 and extends in the first direction. In the inverse-parallel insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0311] In the embodiment of the application, the second load electrode pad 1001 on the second low-side inverter chip 15 includes two sub-load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub-load electrode pads 10011. This can ensure that the two sub-load electrode pads 10011 extend in the same direction as the control electrode flow channel 19, and further ensure that the conductive part 23 on the two sub-load electrode pads 10011 is parallel to the control electrode flow channel 19, so as to ensure the structural reliability of the second low-side inverter chip 15.

[0312] According to the embodiment of the present application, as shown in FIG. 23, the first high-side inversion chip on-die area 5 includes dimensions L2, L3, L4, L5 and L6, wherein L2 is 20.8mm, L3 is 22.4mm, L5 is 7.7mm, L6 is 2.1mm. The seventh jumper area 2202 includes dimensions L7 and L8, wherein L7 is 2.2mm, L8 is 1.6mm. The ninth jumper area 2204 includes dimensions L9 and L12, wherein L9 is, L12 is 1.6mm. The eighth jumper area 2203 includes dimensions L10 and L11, wherein L10 is 6.34mm, L11 is 2.1mm. The first low-side inversion chip on-die area 6 includes dimension L14, wherein L14 is 8.4mm.

[0313] According to the embodiment of the present application, as shown in FIG. 25, the third high-side inversion chip 13 includes dimensions L15 and L16, wherein L15 is 11.9mm, L16 is 9.44mm. The third low-side inversion chip on-die area 9 includes dimensions L17 and L18, wherein L17 is 14.4mm, L18 is 8.66mm. The second low-side inversion chip on-die area 8 includes dimensions L19 and L20, wherein L19 is 13mm, L20 is 8.5mm. The tenth jumper area 2205 includes dimensions L21 and L22, wherein L21 is 4.3mm, L22 is 1.41mm.

[0314] According to the embodiment of the present application, as shown in FIG. 27, the rectifier chip on-die area 4 includes dimensions L23, L24, L25, L26, L27, L28 and L46, wherein L23 is 6.2mm, L24 is 6.2mm, L25 is 6.5mm, L26 is 12.6mm, L27 is 10.4mm, L28 is 11.8mm, L46 is 20.2mm. The brake chip on-die area 3 includes dimensions L29 and L30, wherein L29 is 22.4mm, L30 is 6.1mm.

[0315] The embodiment three of the present application provides a semiconductor module 100, and the semiconductor module 100 according to the embodiment of the present application is described below with reference to FIG. 29-FIG. 37, and the semiconductor module 100 includes but is not limited to PIM (Power Integrated Module).

[0316] As shown in FIG. 30-FIG. 34, the semiconductor module 100 according to the present application has a first direction and a second direction, and a high side 10001 and a low side 10002 oppositely arranged in the second direction, which can mainly include: a shell 1, a substrate 2 and a plurality of inversion chips 10.

[0317] The substrate 2 is arranged in the housing 1, and the substrate 2 has a first substrate portion 2021 and a second substrate portion 2031 arranged in sequence along a first direction, and a plurality of elements can be arranged on the first substrate portion 2021 and the second substrate portion 2031 respectively to form a basic structure of the semiconductor module 100.

[0318] The first substrate portion 2021 is provided with a first high-side inverter chip-on-die area 5 and a first low-side inverter chip-on-die area 6 arranged in sequence along a second direction, and the first high-side inverter chip-on-die area 5 is closer to a high side 10001 of the semiconductor module 100 than the first low-side inverter chip-on-die area 6, so that a high-voltage drive power chip can be arranged on the high side 10001 of the first substrate portion 2021. The second substrate portion 2031 is provided with a second high-side inverter chip-on-die area 7, a third low-side inverter chip-on-die area 9 and a second low-side inverter chip-on-die area 8 arranged in sequence along the second direction, and the second high-side inverter chip-on-die area 7 is closer to the high side 10001 of the semiconductor module 100 than the second low-side inverter chip-on-die area 8, so that a high-voltage drive power chip can be arranged on the high side 10001 of the second substrate portion 2031.

[0319] In the embodiments of the present application, the first high-side inverter chip-on-die area 5, the second high-side inverter chip-on-die area 7, the first low-side inverter chip-on-die area 6, the second low-side inverter chip-on-die area 8 and the third low-side inverter chip-on-die area 9 can all be used to arrange power chips in the semiconductor module 100.

[0320] The semiconductor module 100 is provided with a plurality of inverter chips 10, each of which is a single chip. Each of the plurality of inverter chips 10 is provided with a control electrode pad 1002, a first load electrode pad and a second load electrode pad 1001, and the control electrode pad 1002 and the second load electrode pad 1001 are used to apply a drive voltage to control the on and off of the first load electrode pad and the second load electrode pad 1001. For example, the inverter chip 10 is an inverse-parallel insulated gate bipolar transistor, or a metal oxide semiconductor field effect transistor, etc.

[0321] When the inverter chip 10 is an inverse-parallel insulated gate bipolar transistor, the first load electrode pad is a collector electrode pad, the second load electrode pad 1001 is an emitter electrode pad, and the control electrode pad 1002 is a gate electrode pad.

[0322] When the inverter chip 10 is a metal oxide semiconductor field effect transistor, the first load electrode pad is a drain electrode pad, the second load electrode pad 1001 is a source electrode pad, and the control electrode pad 1002 is a gate electrode pad.

[0323] In the prior art, as shown in FIG. 29, each inverter chip 10 in the semiconductor module 100 includes an insulated gate bipolar transistor 25 and a fast recovery diode 24. For example, when the inverter chip 10 is arranged on the substrate 2, at least one insulated gate bipolar transistor 25 and one fast recovery diode 24 need to be arranged, so the number of chips in the semiconductor module 100 in the prior art is large.

[0324] In the embodiments of the present application, the inverter chip 10 can integrate the insulated gate bipolar transistor 25 and the fast recovery diode 24 on one chip, so that the number of chips in the semiconductor module 100 of the present application can be reduced, and the functions of the integrated chips can be integrated. In this way, the number of conductive members can be reduced, so that not only the manufacturing efficiency can be improved, but also the inductance can be reduced, so that the performance of the semiconductor module 100 can be improved.

[0325] It should be noted that in some embodiments of the present application, the conductive member can be an electric connection wire or an electric connection sheet, etc.

[0326] The plurality of inverter chips 10 includes a first high-side inverter chip 11, a second high-side inverter chip 12, a third high-side inverter chip 13, a first low-side inverter chip 14, a second low-side inverter chip 15, and a third low-side inverter chip 16.

[0327] Further, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged on the first high-side inverter chip upper chip area 5 and are arranged at intervals along the first direction. In this way, not only can the first high-side inverter chip 11 and the second high-side inverter chip 12 be independent of each other, but also the heat dissipation of the first high-side inverter chip 11 and the second high-side inverter chip 12 can be facilitated, and the accumulation of heat between the first high-side inverter chip 11 and the second high-side inverter chip 12 can be prevented, so that the temperature of the first high-side inverter chip 11 and the second high-side inverter chip 12 can be prevented from being too high and failing, and the reliability of the first high-side inverter chip 11 and the second high-side inverter chip 12 can be facilitated. In addition, the first load electrode pad of the first high-side inverter chip 11 and the first load electrode pad of the second high-side inverter chip 12 are electrically connected.

[0328] Further, the first high-side inverter chip 11 is farther away from the second substrate portion 2031 than the second high-side inverter chip 12 in the first direction, so that the arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12 on the first substrate portion 2021 can be facilitated, and the connection of the first high-side inverter chip 11 and the second high-side inverter chip 12 with other structures in the semiconductor module 100 can be facilitated.

[0329] The third high-side inverter chip 13 is arranged on the second high-side inverter chip upper core area 7, so that the third high-side inverter chip 13 is far away from the first high-side inverter chip 11 and the second high-side inverter chip 12, thereby preventing the three inverter chips 10 from being too close to each other and causing device thermal failure.

[0330] The first low-side inverter chip 14 is arranged on the first low-side inverter chip upper core area 6, the second low-side inverter chip 15 is arranged on the second low-side inverter chip upper core area 8, and the third low-side inverter chip 16 is arranged on the third low-side inverter chip upper core area 9. In this way, the first high-side inverter chip 11, the second high-side inverter chip 12, the third high-side inverter chip 13, the third low-side inverter chip 16, the second low-side inverter chip 15, and the third low-side inverter chip 16 in the semiconductor module 100 are arranged separately to form the basic structure of the semiconductor module 100, thereby ensuring normal operation of the semiconductor module 100.

[0331] As shown in FIGS. 36 and 39, the second low-side inverter chip upper core area 8 includes a first upper core part 801 for arranging the second low-side inverter chip 15 and a first wiring part 802 for connecting wires, and the first load electrode pad of the second low-side inverter chip 15 is electrically connected to the first wiring part 802. The third low-side inverter chip upper core area 9 includes a second upper core part 901 for arranging the third low-side inverter chip 16 and a second wiring part 902 for connecting wires, and the first load electrode pad of the third low-side inverter chip 16 is electrically connected to the second wiring part 902. The second high-side inverter chip upper core area 7 includes a third upper core part 701 for arranging the third high-side inverter chip 13 and a third wiring part 702 for connecting wires, and the first load electrode pad of the third high-side inverter chip 13 is electrically connected to the third wiring part 702.

[0332] The first upper core part 801 is arranged in the second direction adjacent to one side of the low side 10002 of the second upper core part 901, so that the third low-side inverter chip 16 and the third high-side inverter chip 13 form a pair of upper and lower bridge chips in the semiconductor module 100. In the embodiment of the present application, the first low-side inverter chip 14 and the first high-side inverter chip 11 form a pair of upper and lower bridge chips in the semiconductor module 100, and the second low-side inverter chip 15 and the second high-side inverter chip 12 form a pair of upper and lower bridge chips in the semiconductor module 100.

[0333] The first wiring part 802 is connected to the side of the first upper core part 801 adjacent to the first substrate part 2021 in the first direction, so that the first wiring part 802 is closer to the first substrate part 2021 than the first upper core part 801, facilitating wire bonding between the first wiring part 802 and the first substrate part 2021. Further, the first wiring part 802 extends in the second direction, so that the size of the first wiring part 802 in the second direction is increased, facilitating wire bonding on the first wiring part 802, so as to shorten the length of the conductive member between the first wiring part 802 and the first substrate part 2021, which is beneficial to reducing the inductance in the semiconductor module 100.

[0334] The first wiring part 802 is arranged between the third low-side inverter core part 9 and the second high-side inverter core part 7 adjacent to the side of the first substrate part 2021 in the first direction, so that the third low-side inverter core part 9 and the second high-side inverter core part 7 are connected to the first substrate part 2021 through the first wiring part 802, which is beneficial to improving the stability of the electrical connection between the third low-side inverter core part 9, the second high-side inverter core part 7 and the first substrate part 2021, and improving the current-carrying capacity of the semiconductor module 100.

[0335] The second wiring part 902 is connected to the side of the second upper core part 901 away from the first substrate part 2021 in the first direction, so that the second upper core part 901 is arranged close to the first wiring part 802, which is beneficial to shortening the distance between the second upper core part 901 and the first conductive member 2301, and reducing the length of the electrical connection between the second upper core part 901 and the first conductive member 2301, and reducing the inductance generated by the electrical connection between the second upper core part 901 and the first conductive member 2301.

[0336] Further, the second wiring part 902 extends in the second direction, so that the area of the second wiring part 902 is increased, facilitating wire bonding on the second wiring part 902. In the embodiment of the present application, the second wiring part 902 is connected to the external terminal 101 through a conductive member, and the second wiring part 902 is connected to the second load electrode pad 1001 of the third high-side inverter chip 13 through a conductive member.

[0337] The second wiring part 902 is arranged between the third upper core part 701 and the side of the first substrate part 2021 away from the first substrate part 2021 in the first direction, so that the third high-side inverter chip 13 is arranged on the side of the second substrate part 2031 away from the first substrate part 2021 in the first direction, which is beneficial to improving the heat dissipation efficiency of the side of the third high-side inverter chip 13 adjacent to the first substrate part 2021 in the first direction, and preventing the third high-side inverter chip 13 from failing due to overheating.

[0338] The third wiring part 702 is connected to the side of the third upper core part 701 which is more adjacent to the low side 10002 in the second direction, and the third wiring part 702 extends in the second direction and at least partially extends between the first wiring part 802 and the second upper core part 901. In this way, not only can the third high-side inverter chip 13 be arranged close to the high side 10001 of the semiconductor module 100, but also the distance between the second load electrode pad 1001 of the third low-side inverter chip 16 and the upper core area 7 of the third high-side inverter chip 13 can be shortened. In the case where a conductive member is arranged between the second load electrode pad 1001 of the third low-side inverter chip 16 and the first substrate part 2021, and a conductive member is arranged between the third wiring part 702 and the first substrate part 2021, the length between the two conductive members can be shortened, thereby reducing the inductance between the first substrate part 2021 and the second substrate part 2031.

[0339] As shown in FIGS. 33, 34, 35, 36 and 39, the third high-side inverter chip 13 is located in the middle of the second substrate part 2031 in the first direction, so that the distance from the two sides of the third high-side inverter chip 13 in the first direction to the two sides of the second substrate part 2031 in the first direction is similar. In this way, on the one hand, the distance between the upper core area of the third high-side inverter chip 13 and the side of the second substrate part 2031 in the first direction away from the upper core area of the third high-side inverter chip 13 can be increased, which can provide more space for the second wiring part 902 in the first direction, thereby increasing the area of the second wiring part 902.

[0340] Further, the increase in the area of the second wiring part 902 can reduce the inductance of the second wiring part 902, and further reduce the inductance between the third high-side inverter chip 13 and the external terminal 101. In this way, the occurrence of a sharp voltage across the third high-side inverter chip 13 can be inhibited, and the third high-side inverter chip 13 can be prevented from failing.

[0341] On the other hand, the heat on both sides of the third high-side inverter chip 13 in the first direction can be simultaneously transmitted to the edges of the second substrate part 2031, so that the heat dissipation efficiency of both sides of the third high-side inverter chip 13 in the first direction is the same, thereby ensuring the heat dissipation effect of both sides of the third high-side inverter chip 13 in the first direction, and solving the problem of heat accumulation due to low heat dissipation efficiency on one side of the third high-side inverter chip 13 in the first direction, thereby improving the heat dissipation performance of the third high-side inverter chip 13.

[0342] As shown in FIG. 33, FIG. 34, FIG. 35, FIG. 36 and FIG. 39, the control electrode pad 1002 of the third high-side inversion chip 13 is closer to the side of the high side 10001 of the third high-side inversion chip 13 in the second direction, and the control electrode pad 1002 of the third high-side inversion chip 13 is closer to the end of the first substrate part 2021 of the third high-side inversion chip 13 in the first direction.

[0343] Specifically, the third high-side inversion chip 13 is a high-side 10001 driving power chip in the semiconductor module 100, the control electrode pad 1002 of which is arranged close to the high side 10001 of the semiconductor module 100 in the second direction, and is arranged adjacent to the first substrate part 2021 in the first direction. The eighth terminal 1018 in the external terminals 101 on the shell 1 is provided with a conductive member between the control electrode pad 1002 of the third high-side inversion chip 13, and the eighth terminal 1018 is located on the side of the third high-side inversion chip 13 away from the first substrate part 2021 in the first direction, so that the conductive member between the control electrode pad 1002 on the third high-side inversion chip 13 and the eighth terminal 1018 can be prevented from being too long and deformed, and the reliability of the conductive member between the control electrode pad 1002 on the third high-side inversion chip 13 and the eighth terminal 1018 can be ensured.

[0344] The eleventh jumper area 2206 is also arranged on the second substrate part 2031, and is arranged on the side of the second high-side inversion chip upper chip area 7 away from the first substrate part 2021 in the first direction, so that the eleventh jumper area 2206 is arranged between the third high-side inversion chip 13 and the eighth terminal 1018. The eleventh jumper area 2206 is arranged on the side of the second wiring part 902 adjacent to the high side 10001 in the second direction, and the eleventh jumper area 2206 is connected with the conductive member between the control electrode pad 1002 of the third high-side inversion chip 13.

[0345] Specifically, when the third high-side inversion chip 13 is connected with the eighth terminal 1018 by wire, the eleventh jumper area 2206 is arranged between the third high-side inversion chip 13 and the eighth terminal 1018, and the eleventh jumper area 2206 is arranged between the eleventh jumper area 2206 and the eighth terminal 1018, so that on the one hand, the third high-side inversion chip 13 and the eighth terminal 1018 can be connected, and on the other hand, the length of the conductive member arranged between the third high-side inversion chip 13 and the eighth terminal 1018 can be shortened by arranging the eleventh jumper area 2206, so that the heat generated by the conductive member can be reduced, the temperature at both ends of the conductive member can be reduced, and the reliability of the semiconductor module 100 can be improved.

[0346] As shown in FIGS. 33, 34, 35, 36 and 39, the third low-side inversion chip 16 is located in the middle of the second substrate portion 2031 in the first direction, so that the distances from the two sides of the third low-side inversion chip 16 to the two sides of the second substrate portion 2031 in the first direction are similar. In this way, the heat of the two sides of the third low-side inversion chip 16 can be simultaneously transmitted to the edges of the second substrate portion 2031, so that the heat dissipation efficiency of the two sides of the third low-side inversion chip 16 is the same, thereby ensuring the heat dissipation effect of the two sides of the third low-side inversion chip 16, and solving the problem of heat accumulation caused by low heat dissipation efficiency of one side of the third low-side inversion chip 16, thereby facilitating the improvement of the heat dissipation performance of the third low-side inversion chip 16.

[0347] As shown in FIGS. 33, 34, 35, 36 and 39, the control electrode pad 1002 in the third low-side inversion chip 16 is closer to one side of the low side 10002 in the second direction on the third low-side inversion chip 16, and the control electrode pad 1002 in the third low-side inversion chip 16 is located at the end of the third low-side inversion chip 16 away from the first substrate portion 2021 in the first direction.

[0348] Specifically, the third low-side inversion chip 16 is a low-side 10002 driving power chip in the semiconductor module 100, the control electrode pad 1002 of which is arranged close to the low side 10002 of the semiconductor module 100 in the second direction, and is arranged adjacent to the side of the third low-side inversion chip 16 away from the first substrate portion 2021 in the first direction. The conductive member is provided between the twelfth terminal 10112 on the shell 1 and the control electrode pad 1002 of the third low-side inversion chip 16, and the twelfth terminal 10112 is located at a position closer to the low side 10002 in the second direction of the semiconductor module 100. In this way, the control electrode pad 1002 on the third low-side inversion chip 16 can be arranged close to the twelfth terminal 10112, and the conductive member between the control electrode pad 1002 on the third low-side inversion chip 16 and the twelfth terminal 10112 can be prevented from being too long and deformed, thereby ensuring the reliability of the conductive member between the control electrode pad 1002 on the third low-side inversion chip 16 and the twelfth terminal 10112.

[0349] As shown in FIGS. 33, 34, 35, 36, 39 and 43, the third low-side inversion chip 16 has a control electrode flow channel 19, the second load electrode pad 1001 of the third low-side inversion chip 16 includes two sub-load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub-load electrode pads 10011. The control electrode flow channel 19 of the third low-side inversion chip 16 extends in the first direction.

[0350] Specifically, the third low-side inverter chip 16 can be a reverse conducting IGBT or a MOSFET. The third low-side inverter chip 16 is provided with a control electrode flow channel 19 extending in the first direction. In the reverse conducting IGBT or the MOSFET, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0351] In the embodiment, the second load electrode pad 1001 on the third low-side inverter chip 16 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011. In this way, the two sub load electrode pads 10011 can extend in the same direction as the control electrode flow channel 19, and the conductive members on the two sub load electrode pads 10011 can be parallel to the control electrode flow channel 19, thereby ensuring the structural reliability of the third low-side inverter chip 16.

[0352] As shown in FIGS. 34, 35, 36 and 39, the second low-side inverter chip 15 is arranged more adjacent to the first substrate portion 2021 along the first direction on the second substrate portion 2031, so that the second low-side inverter chip 15 and the third low-side inverter chip 16 are staggered in the first direction. In this way, on the one hand, it can prevent the second low-side inverter chip 15 and the third low-side inverter chip 16 from being too close to each other, so that too much heat is accumulated in the semiconductor module 100. On the other hand, it can reduce the stray inductance generated between the second low-side inverter chip 15 and the third low-side inverter chip 16, prevent the second low-side inverter chip 15 from failing due to the sharp voltage generated between the first load electrode pad and the second load electrode pad 1001, and prevent the third low-side inverter chip 16 from failing due to the sharp voltage generated between the first load electrode pad and the second load electrode pad 1001, thereby improving the reliability of the semiconductor module 100.

[0353] In the embodiment of the present application, the fourteenth terminal 10114 corresponding to the first substrate portion 2021 is provided with a conductive member between the third low-side inverter chip 16 and the second load electrode pad 1001. The third low-side inverter chip 16 is arranged to be staggered with the second low-side inverter chip 15 in the first direction. In this way, on the one hand, it can prevent the second low-side inverter chip 15 and the third low-side inverter chip 16 from being too close to each other, causing excessive heat accumulation in the semiconductor module 100. On the other hand, it can reduce the stray inductance generated between the second low-side inverter chip 15 and the third low-side inverter chip 16, prevent the second low-side inverter chip 15 from failing due to the sharp voltage generated across its first load electrode pad and second load electrode pad 1001, and prevent the third low-side inverter chip 16 from failing due to the sharp voltage generated across its first load electrode pad and second load electrode pad 1001, thereby improving the reliability of the semiconductor module 100.

[0354] As shown in FIGS. 33, 34, 35, 36 and 39, the control electrode pad 1002 of the second low-side inverter chip 15 is arranged on the side of the second low-side inverter chip 15 further away from the first substrate portion 2021 in the first direction, and the control electrode pad 1002 of the second low-side inverter chip 15 is arranged on the end of the second low-side inverter chip 15 closer to the low side 10002 in the second direction.

[0355] Specifically, the second low-side inverter chip 15 is a low-side 10002 driving power chip in the semiconductor module 100, and its control electrode pad 1002 is arranged close to the low side 10002 of the semiconductor module 100 in the second direction, and close to the side of the second low-side inverter chip 15 away from the first substrate portion 2021 in the first direction. The thirteenth terminal 10113 on the shell 1 is provided with a conductive member between the control electrode pad 1002 of the second low-side inverter chip 15, and the thirteenth terminal 10113 is arranged at a position closer to the low side 10002 of the semiconductor module 100 in the second direction, so that the control electrode pad 1002 on the second low-side inverter chip 15 is arranged close to the thirteenth terminal 10113, the conductive member between the control electrode pad 1002 on the second low-side inverter chip 15 and the thirteenth terminal 10113 is too long to deform, and the reliability of the conductive member between the control electrode pad 1002 on the second low-side inverter chip 15 and the thirteenth terminal 10113 can be ensured.

[0356] In combination with FIGS. 33, 34, 35, 36, 39 and 43, the second low-side inversion chip 15 has a control electrode flow channel 19, the second load electrode pad 1001 of the second low-side inversion chip 15 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011. The control electrode flow channel 19 of the second low-side inversion chip 15 extends in the first direction.

[0357] Specifically, the second low-side inversion chip 15 can be a reverse-conducting insulated gate bipolar transistor and a metal oxide semiconductor field effect transistor. The control electrode flow channel 19 is arranged on the second low-side inversion chip 15 and extends in the first direction. In the reverse-conducting insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0358] In the embodiment of the present application, the second load electrode pad 1001 on the second low-side inversion chip 15 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011. In this way, the two sub load electrode pads 10011 can extend in the same direction as the control electrode flow channel 19, and the conductive members on the two sub load electrode pads 10011 can be parallel to the control electrode flow channel 19, thereby ensuring the structural reliability of the second low-side inversion chip 15.

[0359] In combination with FIGS. 36 and 39, the second substrate portion 2031 further has a twelfth jumper zone 2207, which is arranged in the first direction between the first wiring portion 802 and the second upper core portion 901. In this way, the second upper core portion 901 and the first wiring portion 802 can be wire-bonded through the twelfth jumper zone 2207. This can segment the wire bonding between the second upper core portion 901 and the first wiring portion 802, thereby not only shortening the length of the conductive member, but also avoiding deformation of the conductive member due to excessive length. In addition, the twelfth jumper zone 2207 can dissipate heat to reduce the temperature at both ends of the conductive member, thereby improving the current-carrying capacity of the conductive member.

[0360] Further, the twelfth jumper zone 2207 is arranged in the second direction between the third wiring portion 702 and the first upper core portion 801. In this way, the twelfth jumper zone 2207 can not only ensure the arrangement area on the second substrate portion 2031, but also ensure that the twelfth jumper zone 2207 is arranged close to the third wiring portion 702, thereby shortening the distance between the twelfth jumper zone 2207 and the third wiring portion 702.

[0361] Further, the twelfth jumper area 2207 is connected with the first conductive member 2301 between the second load electrode pad 1001 of the third low-side inverter chip 16 and the first substrate portion 2021, the twelfth jumper area 2207 is connected with the second conductive member 2302 between the first substrate portion 2021, and the third wiring portion 702 is connected with the third conductive member 2303 between the first substrate portion 2021. The second conductive member 2302 and the third conductive member 2303 are arranged in parallel with each other.

[0362] Specifically, the first conductive member 2301 and the second conductive member 2302 are connected with the jumper point on the twelfth jumper area 2207, so that the second load electrode pad 1001 of the third low-side inverter chip 16 is connected with the conductive member between the first substrate portion 2021. The first conductive member 2301 and the second conductive member 2302 are wires of the low side 10002 in the semiconductor module 100, the current on the first conductive member 2301 flows from the second load electrode pad 1001 of the third low-side inverter chip 16 to the twelfth jumper area 2207, and the current on the second conductive member 2302 flows from the twelfth jumper area 2207 to the first substrate portion 2021.

[0363] Further, the third conductive member 2303 is a wire of the high side 10001 in the semiconductor module 100, and the current on the third conductive member 2303 flows from the first substrate portion 2021 to the third wiring portion 702. It can be understood that the current direction on the third conductive member 2303 is opposite to the current direction on the first conductive member 2301 and the second conductive member 2302.

[0364] In the embodiments of the present application, the third conductive member 2303 and the second conductive member 2302 are arranged in parallel with each other, so that the inductance on the third conductive member 2303 and the second conductive member 2302 can be reduced, thereby effectively inhibiting the generation of peak voltage in the third high-side inverter chip 13 and the second high-side inverter chip 12 to fail. It should be noted that the peak voltage will be generated between the first load electrode pad and the second load electrode pad 1001 in the third high-side inverter chip 13, and the peak voltage will be generated between the first load electrode pad and the second load electrode pad 1001 in the second low-side inverter chip 15.

[0365] In some specific embodiments of the present application, as shown in FIGS. 34, 35, 36 and 37, the first substrate portion 2021 is provided with a thirteenth jumper area 2208, and the thirteenth jumper area 2208 includes a first jumper portion 2041, a second jumper portion 2042 and a third jumper portion 2043.

[0366] The first jumper part 2041 is arranged at one side of the first low-side inversion chip 14 in the second direction of the upper chip area 6 of the first low-side inversion chip 14, and extends in the first direction. In this way, the size of the thirteenth jumper area 2208 in the first direction is increased, and the thirteenth jumper area 2208 is arranged at least partially between the first low-side inversion chip 14 and the external terminal 101, so that the first low-side inversion chip 14 and the thirteenth jumper area 2208 are wire-bonded, and the external terminal 101 and the first low-side inversion chip 14 are wire-bonded.

[0367] In this way, the length of the conductive part between the first low-side inversion chip 14 and the external terminal 101 is shortened, so that the stray inductance in the semiconductor module 100 is reduced, and the heat dissipation of the conductive part between the first low-side inversion chip 14 and the external terminal 101 is improved, so that the heat accumulation in the semiconductor module 100 is reduced, and the current carrying capacity of the conductive part is improved.

[0368] The second jumper part 2042 and the third jumper part 2043 are connected to both ends of the first jumper part 2041 in the first direction, and extend towards the side of the first low-side inversion chip 14 in the second direction. In this way, the size of the thirteenth jumper area 2208 in the second direction is increased, and the jumper points of the conductive part are arranged on both sides of the thirteenth jumper area 2208 in the first direction, so that the first substrate part 2021 and the second substrate part 2031 are wire-bonded, and the third substrate part 2011 and the second substrate part 2031 are wire-bonded.

[0369] Further, the first high-side inversion chip 11 is provided with a clearance gap 500 on the side of the upper chip area 5 of the first high-side inversion chip 11 in the first direction, and the clearance gap 500 is located at one end of the upper chip area 5 of the first high-side inversion chip 11 in the second direction. In this way, the third jumper part 2043 can extend at least partially into the clearance gap 500 on the side of the first high-side inversion chip 11.

[0370] Compared with the first high-side inversion chip 11, the second high-side inversion chip 12 is closer to the second substrate part 2031 in the first direction, so that the length of the conductive part between the second high-side inversion chip 12 and the first wiring part 802 on the third substrate part 2011 is shortened, and the length of the conductive part between the second load electrode pad 1001 on the second high-side inversion chip 12 and the third substrate part 2011 is shortened.

[0371] The second high-side inversion chip 12 is arranged in the second direction and spaced from the avoiding gap 500, and the third conductive member 2303 is connected between the part of the first high-side inversion chip upper die area 5 corresponding to the second high-side inversion chip 12 and the avoiding gap 500 and the third wiring part 702. In this way, the second high-side inversion chip 12 can avoid wire bonding between the first high-side inversion chip upper die area 5 and the third wiring part 702.

[0372] Further, the second conductive member 2302 is connected between the twelfth jumper area 2207 and the third jumper part 2043. In this way, the jumper point of the second conductive member 2302 on the third wiring part can be arranged close to the avoiding gap 500, and the jumper point of the third conductive member 2303 on the first high-side inversion chip upper die area 5 can be arranged close to the avoiding gap 500. This not only helps to shorten the distance between the second conductive member 2302 and the third conductive member 2303, but also helps to realize parallel arrangement of the third conductive member 2303 and the second conductive member 2302, thereby reducing the inductance of the third conductive member 2303 and the second conductive member 2302, and further helping to reduce the inductance of the third high-side inversion chip 13 and the third low-side inversion chip 16.

[0373] As shown in FIGS. 34, 35, 36 and 37, the first high-side inversion chip 11 and the second high-side inversion chip 12 are arranged on the part of the first high-side inversion chip upper die area 5 more adjacent to the high side 10001 in the second direction. This can make the first high-side inversion chip 11 and the second high-side inversion chip 12 away from the low side 10002 on the first substrate part 2021, and further can ensure normal driving of the high side 10001 and the low side 10002 of the semiconductor module 100.

[0374] As shown in FIGS. 34-35, the first substrate part 2021 has a dimension A1 in the second direction, and the distance between the edge of the first high-side inversion chip 11 facing the high side 10001 and the edge of the first substrate part 2021 facing the high side 10001 is B1. A1 and B1 satisfy the relationship: 0.086A1≤B1≤0.117A1.

[0375] In some embodiments of the present application, B1 / A1 is not more than 0.117. For example, B1 / A1 can be 0.117, 0.116, or 0.115. If B1 / A1 is too large, the first high-side inverter chip 11 will be arranged further away from the high side 10001 on the first substrate portion 2021, which not only makes the distance between the control electrode pad 1002 on the first high-side inverter chip 11 and the external terminal 101 and the jumper area too large, resulting in too long conductive pieces between the control electrode pad 1002 and the external terminal 101 or between the control electrode pad 1002 and the jumper area, affecting the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, but also makes the distance between the first high-side inverter chip 11 and the first low-side inverter chip 14 too close, which is not conducive to the heat dissipation of the first high-side inverter chip 11. To ensure the heat dissipation of the first high-side inverter chip 11 and the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, and to ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0376] In some embodiments of the present application, B1 / A1 is not less than 0.086. For example, B1 / A1 can be 0.086, 0.087, or 0.088. It should be noted that if B1 / A1 is too small, the first high-side inverter chip 11 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, and there will be no space on the first substrate portion 2021 to arrange the jumper area, which will result in too long conductive pieces connecting the control electrode pad 1002 of the first high-side inverter chip 11 directly to the external terminal 101, and the switch stability of the control electrode pad 1002 of the first high-side inverter chip 11 will be poor. To ensure the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, and to ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0377] As shown in FIGS. 34-35, the first substrate portion 2021 has a dimension A1 in the second direction, and the distance between the edge of the second high-side inverter chip 12 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 is C1, and A1 and C1 satisfy the relationship: 0.086A1≤C1≤0.117A1.

[0378] In some embodiments of the present application, B1 / A1 is not more than 0.117. For example, B1 / A1 can be 0.117, 0.116, or 0.115. If B1 / A1 is too large, the first high-side inverter chip 11 will be arranged further away from the high side 10001 on the first substrate portion 2021, which not only makes the distance between the control electrode pad 1002 on the first high-side inverter chip 11 and the external terminal 101 and the jumper area too large, resulting in too long conductive pieces between the control electrode pad 1002 and the external terminal 101 or between the control electrode pad 1002 and the jumper area, affecting the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, but also makes the distance between the first high-side inverter chip 11 and the first low-side inverter chip 14 too close, which is not conducive to the heat dissipation of the first high-side inverter chip 11. To ensure the heat dissipation of the first high-side inverter chip 11 and the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, and to ensure the reliability of the semiconductor module 100, a suitable specific parameter is considered to be selected in the specific design.

[0379] In some embodiments of the present application, B1 / A1 is not less than 0.086. For example, B1 / A1 can be 0.086, 0.087, or 0.088. It should be noted that if B1 / A1 is too small, the first high-side inverter chip 11 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, and there will be no space to arrange the jumper area on the first substrate portion 2021, which will result in too long conductive pieces connecting the control electrode pad 1002 of the first high-side inverter chip 11 directly to the external terminal 101, and the switch stability of the control electrode pad 1002 of the first high-side inverter chip 11 is poor. To ensure the stability of the switch of the control electrode pad 1002 on the first high-side inverter chip 11, and to ensure the reliability of the semiconductor module 100, a suitable specific parameter is considered to be selected in the specific design.

[0380] In some embodiments of the present application, B1 / A1 is not more than 0.117. For example, B1 / A1 can be 0.117, 0.116, or 0.115. If B1 / A1 is too large, the first high-side inversion chip 11 will be arranged farther away from the high side 10001 on the first substrate portion 2021, which not only makes the distance between the control electrode pad 1002 on the first high-side inversion chip 11 and the external terminal 101 and the jumper area too large, resulting in too long conductive parts between the control electrode pad 1002 and the external terminal 101 or between the control electrode pad 1002 and the jumper area, affecting the stability of the switch of the control electrode pad 1002 on the first high-side inversion chip 11, but also makes the distance between the first high-side inversion chip 11 and the first low-side inversion chip 14 too close, which is not conducive to the heat dissipation of the first high-side inversion chip 11. In order to ensure the heat dissipation of the first high-side inversion chip 11 and the stability of the switch of the control electrode pad 1002 on the first high-side inversion chip 11, and ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0381] In some embodiments of the present application, B1 / A1 is not less than 0.086. For example, B1 / A1 can be 0.086, 0.087, or 0.088. It should be noted that if B1 / A1 is too small, the first high-side inversion chip 11 will be too close to the edge of the first substrate portion 2021 facing the high side 10001, and there will be no space to arrange the jumper area on the first substrate portion 2021, which will result in too long conductive parts between the control electrode pad 1002 of the first high-side inversion chip 11 and the external terminal 101, and poor stability of the switch of the control electrode pad 1002 of the first high-side inversion chip 11. In order to ensure the stability of the switch of the control electrode pad 1002 on the first high-side inversion chip 11, and ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0382] In combination with FIGS. 34, 35, 36, 37, and 43, the control electrode pad 1002 on the first low-side inversion chip 14 is located on the side of the first low-side inversion chip 14 farther away from the second substrate portion 2031 in the first direction, and the control electrode pad 1002 on the first low-side inversion chip 14 is located on the end of the first low-side inversion chip 14 closer to the low side 10002 in the second direction.

[0383] Specifically, the fifteenth terminal 10115 on the shell 1 is electrically connected with the control electrode pad 1002 of the first low-side inverter chip 14, the fifteenth terminal 10115 corresponds to the edge of the second substrate portion 2031 towards the low side 10002, the control electrode pad 1002 of the first low-side inverter chip 14 is arranged more adjacent to the low side 10002 in the second direction on the first low-side inverter chip 14, which can shorten the distance between the control electrode pad 1002 of the first low-side inverter chip 14 and the fifteenth terminal 10115 in the second direction. In this way, the influence of the excessively long conductive part between the control electrode pad 1002 of the first low-side inverter chip 14 and the fifteenth terminal 10115 on the switching speed and stability of the first low-side inverter chip 14 can be avoided.

[0384] Further, the control electrode pad 1002 of the first low-side inverter chip 14 is arranged more away from the side of the second substrate portion 2031 in the first direction on the first low-side inverter chip 14, which can prevent the conductive part between the control electrode pad 1002 of the first low-side inverter chip 14 and the fifteenth terminal 10115 from interfering with the arrangement of other conductive parts in the semiconductor module 100.

[0385] In some embodiments of the present application, as shown in FIG. 43, the first low-side inverter chip 14 has a control electrode flow channel 19, the second load electrode pad 1001 of the first low-side inverter chip 14 includes two sub load electrode pads 10011, the control electrode flow channel 19 is arranged between the two sub load electrode pads 10011, and the control electrode flow channel 19 of the first low-side inverter chip 14 extends in the second direction.

[0386] Specifically, the first low-side inverter chip 14 can be a reverse-conducting insulated gate bipolar transistor and a metal oxide semiconductor field effect transistor. Among them, the control electrode flow channel 19 is arranged on the first low-side inverter chip 14, and the control electrode flow channel 19 extends in the second direction. In the reverse-conducting insulated gate bipolar transistor and the metal oxide semiconductor field effect transistor, the wire bonding on the second load electrode pad 1001 needs to be parallel to the control electrode flow channel 19.

[0387] In the embodiments of the present application, the second load electrode pad 1001 on the first low-side inverter chip 14 includes two sub load electrode pads 10011, and the control electrode flow channel 19 is formed between the two sub load electrode pads 10011. In this way, it can be ensured that the two sub load electrode pads 10011 extend in the same direction as the control electrode flow channel 19, and further, the conductive part on the two sub load electrode pads 10011 can be parallel to the control electrode flow channel 19, so as to ensure the structural reliability of the first low-side inverter chip 14.

[0388] In some embodiments of the application, as shown in FIGS. 34, 35 and 37, the first high-side inverter chip upper core area 5 is provided with a second avoiding gap 502, and the fourteenth jumper area 2209 is arranged in the second avoiding gap 502, so that the first high-side inverter chip upper core area 5 avoids the arrangement of the fourteenth jumper area 2209 on the second substrate 2031.

[0389] The fourteenth jumper area 2209 includes a fourth jumper part 50211 and a fifth jumper part 50212. The fourth jumper part 50211 extends in the second direction and is located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction. The second load electrode pad 1001 of the first high-side inverter chip 11 is connected with a conductive part to the fourth jumper part 50211. In this way, the second load electrode pad 1001 of the first high-side inverter chip 11 is electrically connected to the fourth jumper part 50211, so that the first high-side inverter chip 11 can be normally driven when working.

[0390] The fifth jumper part 50212 is connected to the end of the fourth jumper part 50211 that is more adjacent to the low side 10002 in the second direction. The fifth jumper part 50212 extends away from the side of the second substrate 2031 in the first direction. The part of the first low-side inverter chip upper core area 6 that is away from the first low-side inverter chip 14 is connected with a conductive part to the fifth jumper part 50212.

[0391] Specifically, the fifth jumper part 50212 is connected to the fourth jumper part 50211, so that the fifth jumper part 50212 is electrically connected to the fourth jumper part 50211. The fifth jumper part 50212 is located at the end of the fourth jumper part 50211 that is more adjacent to the low side 10002 in the second direction, so that the fifth jumper part 50212 is arranged close to the first low-side inverter chip upper core area 6. In this way, the length of the conductive part between the part of the first low-side inverter chip upper core area 6 that is away from the first low-side inverter chip 14 and the twelfth jumper area 2207 can be shortened, so that the conductive part is not deformed due to being too long, and the structural reliability of the conductive part is ensured.

[0392] The extension direction of the fifth jumper part 50212 is away from the side of the second substrate 2031 in the first direction, so that the area of the fifth jumper part 50212 can be increased, and it is convenient to wire on the fifth jumper part 50212.

[0393] As shown in FIGS. 33, 34, 35 and 41, the substrate 2 further has a third substrate 2011. The third substrate 2011 is arranged on the side of the first substrate 2021 that is away from the second substrate 2031 in the first direction. The third substrate 2011 is provided with the brake chip upper core area 3 and the rectifier chip upper core area 4.

[0394] Specifically, the third substrate portion 2011 is provided with a brake chip-on-chip region 3 and a rectifier chip-on-chip region 4. The brake chip-on-chip region 3 and the rectifier chip-on-chip region 4 are arranged at intervals in the second direction. The brake chip-on-chip region 3 is arranged with a brake chip 301 including a brake diode 3011 and a brake transistor 3012. The rectifier chip-on-chip region 4 is arranged with a rectifier chip 401 including a first rectifier diode 4011 and a second rectifier diode 4012.

[0395] In the embodiment of the present application, as shown in FIG. 33 and FIG. 34, the shell 1 has a plurality of regularly arranged external terminals 101 around the periphery, and the brake chip 301, the rectifier chip 401 and the inverter chip 10 are respectively connected to the corresponding external terminals 101, and the external terminals 101 at least partially extend outward from the shell 1.

[0396] The plurality of external terminals 101 are defined as a first terminal 1011, a second terminal 1012, a third terminal 1013, a fourth terminal 10104, a fifth terminal 1015, a sixth terminal 1016, a seventh terminal 1017, an eighth terminal 1018, a ninth terminal 1019, a tenth terminal 10110, an eleventh terminal 10111, a twelfth terminal 10112, a thirteenth terminal 10113, a fourteenth terminal 10114, a fifteenth terminal 10115, a sixteenth terminal 10116, a seventeenth terminal 10117, an eighteenth terminal 10118, a nineteenth terminal 10119, a twentieth terminal 10120, a twenty-first terminal 10121, a twenty-second terminal 10122 and a twenty-third terminal 10123.

[0397] The first terminal 1011, the second terminal 1012, the third terminal 1013, the fourth terminal 10104, the fifth terminal 1015, the sixth terminal 1016 and the seventh terminal 1017 are located on one side of the shell 1 in the second direction and arranged at intervals in the first direction, the eighth terminal 1018, the ninth terminal 1019, the tenth terminal 10110 and the eleventh terminal 10111 are located on one side of the shell 1 in the first direction and arranged at intervals in the second direction, the twelfth terminal 10112, the thirteenth terminal 10113, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, the seventeenth terminal 10117, the eighteenth terminal 10118 and the nineteenth terminal 10119 are located on the other side of the shell 1 in the second direction and arranged at intervals in the first direction, and the twentieth terminal 10120, the twenty-first terminal 10121, the twenty-second terminal 10122 and the twenty-third terminal 10123 are located on the other side of the shell 1 in the first direction and arranged at intervals in the second direction.

[0398] Also, the first terminal 1011, the second terminal 1012, the eighteenth terminal 10118, and the nineteenth terminal 10119 correspond to the third substrate portion 2011 in the second direction, the third terminal 1013, the fourth terminal 10104, the fifth terminal 1015, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, and the seventeenth terminal 10117 correspond to the first substrate portion 2021 in the second direction, and the sixth terminal 1016, the seventh terminal 1017, the twelfth terminal 10112, and the thirteenth terminal 10113 correspond to the second substrate portion 2031 in the second direction.

[0399] In this way, the basic structure of the semiconductor module 100 can be formed, the brake circuit, the rectifier circuit, and the inverter circuit can be integrated, and the layout of the circuit and the construction of the heat dissipation system can be simplified.

[0400] According to the embodiment of the present application, as shown in FIG. 38, the first high-side inverter chip upper core area 5 includes dimensions L2, L3, L4, L5, and L6, wherein L2 is 20.8 mm, L3 is 22.4 mm, L5 is 7.7 mm, and L6 is 2.1 mm. The twelfth jumper area 2207 includes dimensions L7 and L8, wherein L7 is 2.2 mm, and L8 is 1.6 mm. The fourteenth jumper area 2209 includes dimensions L9 and L12, wherein L9 is 1.6 mm, and L12 is 1.6 mm. The thirteenth jumper area 2208 includes dimensions L10 and L11, wherein L10 is 6.34 mm, and L11 is 2.1 mm. The first low-side inverter chip upper core area 6 includes dimensions L13 and L14, wherein L13 is 17.4 mm, and L14 is 8.4 mm.

[0401] According to the embodiment of the present application, as shown in FIG. 40, the third high-side inverter chip 13 includes dimensions L15 and L16, wherein L15 is 11.9 mm, and L16 is 9.44 mm. The third low-side inverter chip upper core area 9 includes dimensions L17 and L18, wherein L17 is 14.4 mm, and L18 is 8.66 mm. The second low-side inverter chip upper core area 8 includes dimensions L19 and L20, wherein L19 is 13 mm, and L20 is 8.5 mm. The fifth jumper area includes dimensions L21 and L22, wherein L21 is 4.3 mm, and L22 is 1.41 mm.

[0402] According to the embodiment of the present application, as shown in FIG. 41 and FIG. 42, the rectifier chip on-chip area 4 includes dimensions L23, L24, L25, L26, L27, L28 and L46, wherein L23 is 6.2 mm, L24 is 6.2 mm, L25 is 6.5 mm, L26 is 12.6 mm, L27 is 10.4 mm, L28 is 11.8 mm, and L46 is 20.2 mm. The brake chip on-chip area 3 includes dimensions L29 and L30, wherein L29 is 22.4 mm, and L30 is 6.1 mm.

[0403] In the semiconductor module 100 in the embodiment one, the embodiment two and the embodiment three of the present application, as shown in FIG. 4, FIG. 16-FIG. 21 and FIG. 30-FIG. 35, the housing 1 is obtained by molding encapsulation, which can be generated by transfer molding with thermoplastic material or with chemical curing material, and the molding material can be epoxy resin. The housing 1 can be a plastic shell. The third substrate part 2011, the first substrate part 2021, the second substrate part 2031, the brake chip 301, the rectifier chip 401, the inverter chip 10 and at least part of the external terminals 101 are all arranged in the housing 1, and the housing 1 can also be filled with silicone gel 102, so that the housing 1 and the silicone gel 102 can provide physical and electrical protection for the third substrate part 2011, the first substrate part 2021, the second substrate part 2031, the brake chip 301, the rectifier chip 401, the inverter chip 10 and at least part of the external terminals 101, to prevent structural damage caused by external environmental impact, and to ensure normal operation of the semiconductor module 100.

[0404] As shown in FIG. 4, FIG. 21, FIG. 30-FIG. 35, the substrate 2 includes the third sub-substrate 203, the first sub-substrate 201 and the second sub-substrate 202 arranged in sequence and spaced apart along the first direction, the first substrate part 2021 is arranged on the first sub-substrate 201, the second substrate part 2031 is arranged on the second sub-substrate 202, and the third substrate part 2011 is arranged on the third sub-substrate 203.

[0405] Specifically, in the embodiments of the present application, the substrate 2 is composed of a first sub-substrate 201, a second sub-substrate 202 and a third sub-substrate 203, the first sub-substrate 201 can provide a stable and reliable setting position for the first substrate part 2021 to ensure the position reliability of the first high-side inverter chip 11, the second high-side inverter chip 12 and the first low-side inverter chip 14 on the first substrate part 2021, the second sub-substrate 202 can provide a stable and reliable setting position for the second substrate part 2031 to ensure the position reliability of the second low-side inverter chip 15, the third low-side inverter chip 16 and the third high-side inverter chip 13 on the second substrate part 2031, and the third sub-substrate 203 can provide a stable and reliable setting position for the third substrate part 2011 to ensure the position reliability of the brake chip 301 and the rectifier chip 401 on the third substrate part 2011.

[0406] In the embodiments of the present application, the semiconductor module 100 includes a housing 1 and a substrate 2, the substrate 2 includes a dielectric insulating layer and two metal oxide layers attached to the dielectric insulating layer, the dielectric insulating layer is located between the two metal oxide layers. The composition material of the metal oxide layer includes but is not limited to at least one of copper, copper alloy, aluminum and aluminum alloy. In addition, the composition material of the metal oxide layer can also be any other metal or alloy that remains in a solid form during the operation of the semiconductor module 100. The substrate 2 includes but is not limited to a ceramic substrate 2, the composition material of the ceramic substrate 2 includes but is not limited to at least one of aluminum oxide, aluminum nitride, zirconium oxide, silicon nitride, boron nitride and any other dielectric ceramic material. The composition material of the dielectric insulating layer includes but is not limited to at least one of Al2O3, AlN, SiC, BeO or Si3N4.

[0407] For example, the substrate 2 can be any one of, for example, a direct copper bonding substrate, a direct aluminum bonding substrate and an active metal brazing substrate. In addition, the substrate 2 can also be an insulating metal substrate 2. The insulating metal substrate 2 generally includes a dielectric insulating layer, for example, the composition material of the dielectric insulating layer includes but is not limited to at least one of epoxy resin and polyimide. For example, ceramic particles can be filled in the material of the dielectric insulating layer, the composition material of the ceramic particles includes but is not limited to at least one of Si2O, Al2O3, AlN and BN. The diameter of the ceramic particles is between 1 μm-50 μm.

[0408] In addition, the substrate 2 can also be a conventional printed circuit board with a non-ceramic dielectric insulating layer. For example, the composition material of the non-ceramic dielectric insulating layer includes but is not limited to cured resin.

[0409] According to some embodiments of the present application, the substrate 2 is a whole plate body, and three third substrate parts 2011, first substrate parts 2021 and second substrate parts 2031 are sequentially and spaced apart in a first direction on the substrate 2.

[0410] In another embodiment of the present application, the substrate 2 is formed as three separate plate bodies, namely the third sub-substrate 203, the first sub-substrate 201 and the second sub-substrate 202, which are sequentially and spaced apart in the first direction. The first substrate portion 2021 is arranged on the first sub-substrate 201, the second substrate portion 2031 is arranged on the second sub-substrate 202, and the third substrate portion 2011 is arranged on the third sub-substrate 203.

[0411] In an embodiment of the present application, the semiconductor module 100 can further include a heat sink, which is in thermal contact with the substrate 2, for example, the substrate 2 is soldered on the heat sink. The third substrate portion 2011, the first substrate portion 2021 and the second substrate portion 2031 of the substrate 2 are arranged on the side of the substrate 2 away from the heat sink.

[0412] In another embodiment of the present application, the housing 1 is open at the bottom, and the heat sink is formed on the side of the substrate 2 facing the bottom of the housing 1, and the heat sink at least partially leaks out from the open side of the bottom of the housing 1.

[0413] In an embodiment of the present application, the composition of the silicone gel 102 includes but is not limited to silicone gel and rigid molding compound. The silicone gel 102 can be at least partially filled in the interior of the housing 1 to cover the components and electrical connections on the substrate 2. The housing 1 itself includes a side wall portion and a top wall portion, and the external terminal 101 is partially embedded in the housing 1 and covered by the silicone gel 102. Further, the external terminal 101 can be arranged to at least partially extend from the side wall portion of the housing 1 and not be covered by the silicone gel 102, or extend from the top wall portion of the housing 1 and not be covered by the silicone gel 102. The silicone gel 102 is configured to protect the components and conductive parts inside the semiconductor module 100, especially to prevent the components and electrical connections inside the housing 1 from being affected by the environment and mechanically damaged.

[0414] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0415] In the description of the application, reference has been made to descriptive terms such as "one embodiment", "some embodiments", "an embodiment", "exemplary embodiment", "specific example", or "some examples" etc. It is emphasized that these terms are not intended to mean that a particular feature, structure, material or characteristic was included in at least one embodiment or example. Rather, such terms are used merely for the purpose of providing an example or examples in conjunction with which the particular feature, structure, material or characteristic is described.

[0416] While the embodiments of the application have been shown and described, it is to be understood that the embodiments can be varied, modified, substituted and changed by those skilled in the art without departing from the principles and spirit of the application. The scope of the application is to be limited only by the claims and their equivalents.

Claims

1. A semiconductor module, characterized in that, The semiconductor module (100) has a first direction and a second direction, and a high side (10001) and a low side (10002) disposed opposite to each other in the second direction. The semiconductor module (100) includes: Shell (1); A substrate (2) is disposed within the housing (1). The substrate (2) has a first substrate portion (2021) and a second substrate portion (2031) arranged sequentially at intervals along the first direction. The first substrate portion (2021) has a first high-side inverter chip upper core region (5) and a first low-side inverter chip upper core region (6) arranged at intervals along the second direction. The first high-side inverter chip upper core region (5) is closer to the high side (10001) than the first low-side inverter chip upper core region (6). The second substrate portion (2031) has a second high-side inverter chip upper core region (7), a third low-side inverter chip upper core region (9), and a second low-side inverter chip upper core region (8) arranged sequentially at intervals along the second direction. The second high-side inverter chip upper core region (7) is closer to the high side (10001) than the second low-side inverter chip upper core region (8). Multiple inverter chips (10), each inverter chip (10) is a single chip, each inverter chip (10) is provided with a control electrode pad (1002), a first load electrode pad and a second load electrode pad (1001), the multiple inverter chips (10) include a first high-side inverter chip (11), a second high-side inverter chip (12), a third high-side inverter chip (13), a first low-side inverter chip (14), a second low-side inverter chip (15) and a third low-side inverter chip (16), the first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the first high-side inverter chip (16). The first high-side inverter chip (11) is further away from the second substrate portion (2031) in the first direction than the second high-side inverter chip (12). The third high-side inverter chip (13) is disposed in the second high-side inverter chip upper core area (7). The first low-side inverter chip (14) is disposed in the first low-side inverter chip upper core area (6). The second low-side inverter chip (15) is disposed in the second low-side inverter chip upper core area (8). The third low-side inverter chip (16) is disposed in the third low-side inverter chip upper core area (9). The first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the upper core area (5) of the first high-side inverter chip, closer to the high side (10001) along the second direction. The upper core area (5) of the first high-side inverter chip is provided with a clearance notch (500), and a first jumper area (17) extending along the second direction is provided in the clearance notch (500). The first jumper area (17) is spaced apart from the upper core area (5) of the first high-side inverter chip. At least a portion of the first jumper area (17) is located between the first high-side inverter chip (11) and the second high-side inverter chip (12) in the first direction. The first high-side inverter chip (11) is positioned closer to the second high-side inverter chip (12) in the first direction. The edge of the second high-side inverter chip (12) is the first edge (1101). The edge of the second high-side inverter chip (12) adjacent to the first high-side inverter chip (11) in the first direction is the second edge (1201). The edge of the first high-side inverter chip (11) adjacent to the low side (10002) in the second direction is the third edge (1102). The edge of the first high-side inverter chip (11) adjacent to the high side (10001) in the second direction is the fourth edge (1103). The edge of the second high-side inverter chip (12) adjacent to the low side (10002) in the second direction is the fifth edge (1202). The edge of the second high-side inverter chip (12) adjacent to the high side (10001) in the second direction is the sixth edge (1203). The third edge (1102) and the fifth edge (1202) that are closer to the low side (10002) are designated as the low side edge, and the fourth edge (1103) and the sixth edge (1203) that are closer to the high side (10001) are designated as the high side edge. The area enclosed by the extension lines of the first edge (1101), the second edge (1201), the high side edge, and the low side edge is designated as the interval area (1206). The portion of the interval area (1206) corresponding to the clearance gap (500) is only provided with the first jumper area (17). A conductive element (23) is connected between the second load electrode pad (1001) of the first high-side inverter chip (11) and the first jumper area (17). The control electrode pad (1002) of the first high-side inverter chip (11) is disposed on the first high-side inverter chip (11) along the second direction, which is closer to the high side (10001). The control electrode pad (1002) of the first high-side inverter chip (11) is electrically connected to the external terminal (101).

2. The semiconductor module according to claim 1, characterized in that, The first substrate portion (2021) is further provided with a second jumper area (18), which is disposed in the clearance notch (500). The second jumper area (18) is spaced apart from the fourth edge (1103) on the side facing the high side (10001) in the second direction. The second jumper area (18) is located on the side of the first jumper area (17) away from the second substrate portion (2031) in the first direction. A conductive element (23) is connected between the control electrode pad (1002) of the first high-side inverter chip (11) and the second jumper area (18). A conductive element (23) is connected between the second jumper area (18) and the external terminal (101).

3. The semiconductor module according to claim 1, characterized in that, The first high-side inverter chip (11) and the second high-side inverter chip (12) are arranged opposite to each other in the first direction, and the projections of the first high-side inverter chip (11) and the second high-side inverter chip (12) in the first direction overlap each other.

4. The semiconductor module according to claim 1, characterized in that, The portion of the first jumper area (17) located between the first high-side inverter chip (11) and the second high-side inverter chip (12) has a dimension of L1 in the first direction, and L1 satisfies the relationship: 1.7mm≤L1≤3.2mm.

5. The semiconductor module according to claim 1, characterized in that, The first substrate portion (2021) has a dimension of A1 in the second direction; The distance between the first high-side inverter chip (11) and the edge of the first substrate portion (2021) facing the high side (10001) is B1, and A1 and B1 satisfy the relationship: 0.086A1≤B1≤0.117A1; The distance between the second high-side inverter chip (12) and the edge of the first substrate (2021) facing the high side (10001) is C1, and A1 and C1 satisfy the relationship: 0.086A1≤C1≤0.117A1.

6. The semiconductor module according to claim 1, characterized in that, The control electrode pad (1002) of the first high-side inverter chip (11) is disposed on the side of the first high-side inverter chip (11) that is further away from the second substrate portion (2031) along the first direction.

7. The semiconductor module according to claim 6, characterized in that, The first high-side inverter chip (11) has a control electrode channel (19). The second load electrode pad (1001) of the first high-side inverter chip (11) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011). The control electrode channel (19) of the first high-side inverter chip (11) extends along the first direction.

8. The semiconductor module according to claim 1, characterized in that, The first jumper area (17) is located in the middle of the upper core area (5) of the first high-side inverter chip in the first direction.

9. The semiconductor module according to claim 8, characterized in that, The first substrate portion (2021) is further provided with a third jumper area (20), the third jumper area (20) is connected to one end of the first jumper area (17) adjacent to the upper core area (6) of the first low-side inverter chip, the third jumper area (20) extends from the first jumper area (17) in a first direction toward a direction away from the second substrate portion (2031), and a conductive element (23) is connected between the third jumper area (20) and the upper core area (6) of the first low-side inverter chip.

10. The semiconductor module according to claim 9, characterized in that, The first low-side inverter chip (14) is disposed on the upper core area (6) of the first low-side inverter chip, which is closer to the second substrate portion (2031) along the first direction. A conductive element (23) is connected between the upper core area (6) of the first low-side inverter chip and the third jumper area (20) on the side away from the second substrate portion (2031) in the first direction.

11. The semiconductor module according to claim 8, characterized in that, The first substrate portion (2021) is further provided with a fourth jumper area (21), which is connected to the end of the first jumper area (17) away from the upper core area (6) of the first low-side inverter chip, and the fourth jumper area (21) extends from the first jumper area (17) in a first direction toward the second substrate portion (2031).

12. The semiconductor module according to claim 1, characterized in that, The third high-side inverter chip (13) is located in the middle of the second substrate portion (2031) in the first direction.

13. The semiconductor module according to claim 12, characterized in that, The control electrode pad (1002) of the third high-side inverter chip (13) is disposed on the third high-side inverter chip (13) more closely adjacent to the high side (10001) along the second direction; The control electrode pad (1002) of the third high-side inverter chip (13) is disposed on the third high-side inverter chip (13) closer to the first substrate portion (2021) along the first direction.

14. The semiconductor module according to claim 13, characterized in that, The third high-side inverter chip (13) has a control electrode channel (19). The second load electrode pad (1001) of the third high-side inverter chip (13) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011). The control electrode channel (19) of the third high-side inverter chip (13) extends along the first direction.

15. The semiconductor module according to claim 13, characterized in that, The second substrate (2031) is further provided with a fifth jumper area (22), which is located on the side of the second high-side inverter chip core area (7) away from the first substrate (2021) in the first direction. A conductive element (23) is connected between the control electrode pad (1002) of the third high-side inverter chip (13) and the fifth jumper area (22).

16. The semiconductor module according to claim 1, characterized in that, The substrate (2) includes a first sub-substrate (201) and a second sub-substrate (202) arranged sequentially at intervals along the first direction, with the first substrate portion (2021) disposed on the first sub-substrate (201) and the second substrate portion (2031) disposed on the second sub-substrate (202).

17. The semiconductor module according to claim 16, characterized in that, The substrate (2) also has a third substrate portion (2011), which is disposed on the side of the first substrate portion (2021) away from the second substrate portion (2031) in a first direction. The third substrate portion (2011) is provided with a brake unit upper core area and a rectifier unit upper core area.

18. The semiconductor module according to claim 17, characterized in that, The substrate (2) includes a third sub-substrate (203), which is disposed at a distance from the first sub-substrate (201) on the side away from the second sub-substrate (202) in a first direction, and the third substrate portion (2011) is disposed on the third sub-substrate (203).

19. A semiconductor module, characterized in that, The semiconductor module (100) has a first direction and a second direction, and a high side (10001) and a low side (10002) disposed opposite to each other in the second direction. The semiconductor module (100) includes: Shell (1); A substrate (2) is disposed within the housing (1). The substrate (2) has a first substrate portion (2021), a second substrate portion (2031), and a third substrate portion (2011) arranged sequentially at intervals along the first direction. The third substrate portion (2011) is provided with a brake chip upper core area (3) and a rectifier chip upper core area (4). The first substrate portion (2021) is provided with a first high-side inverter chip upper core area (5) and a first low-side inverter chip upper core area (6) arranged at intervals along the second direction. The first high-side inverter chip core area (5) is closer to the high side (10001) than the first low-side inverter chip core area (6). The second substrate portion (2031) is provided with a second high-side inverter chip core area (7), a third low-side inverter chip core area (9) and a second low-side inverter chip core area (8) arranged sequentially along the second direction. The second high-side inverter chip core area (7) is closer to the high side (10001) than the second low-side inverter chip core area (8). Multiple inverter chips (10), each inverter chip (10) is a single chip, each inverter chip (10) is provided with a control electrode pad (1002), a first load electrode pad and a second load electrode pad (1001), the multiple inverter chips (10) include a first high-side inverter chip (11), a second high-side inverter chip (12), a third high-side inverter chip (13), a first low-side inverter chip (14), a second low-side inverter chip (15) and a third low-side inverter chip (16), the first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the first high-side inverter chip (16). The first high-side inverter chip (11) is further away from the second substrate portion (2031) in the first direction than the second high-side inverter chip (12). The third high-side inverter chip (13) is disposed in the second high-side inverter chip upper core area (7). The first low-side inverter chip (14) is disposed in the first low-side inverter chip upper core area (6). The second low-side inverter chip (15) is disposed in the second low-side inverter chip upper core area (8). The third low-side inverter chip (16) is disposed in the third low-side inverter chip upper core area (9). The first low-side inverter chip upper core area (6) includes a wiring portion (601) and an upper core portion (602) connected to each other. The wiring portion (601) and the upper core portion (602) are arranged along the first direction, and the upper core portion (602) is located on the side of the wiring portion (601) facing the second substrate portion (2031). The first low-side inverter chip (14) is disposed on the upper core portion (602). The side of the upper core portion (602) facing the low side (10002) is relative to the side of the wiring portion (601) facing the second substrate portion (2031). A third clearance notch (603) is formed by protruding towards the lower side (10002) on one side. A sixth jumper area (2201) is provided in the third clearance notch (603). The sixth jumper area (2201) is adjacent to the upper core (602) in the first direction and adjacent to the wiring part (601) in the second direction. A conductive element (23) is connected between the sixth jumper area (2201) and the control electrode pad (1002) of the brake chip (301). The control electrode pad (1002) of the first low-side inverter chip (14) is disposed on the first low-side inverter chip (14) more closely adjacent to the low side (10002) along the second direction, and the control electrode pad (1002) of the first low-side inverter chip (14) is disposed on the first low-side inverter chip (14) more closely adjacent to the third substrate portion (2011) along the first direction; The sum of the dimensions of the upper core (602) and the wiring part (601) in the first direction is A2, and the dimension of the upper core (602) in the first direction is B2. A2 and B2 satisfy the relationship: B2≥0.5A2.

20. The semiconductor module according to claim 19, characterized in that, B2 satisfies the relationship: B2≥9.27mm.

21. The semiconductor module according to claim 19, characterized in that, The first low-side inverter chip (14) has a control electrode channel (19), and the second load electrode pad (1001) of the first low-side inverter chip (14) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011), and the control electrode channel (19) of the first low-side inverter chip (14) extends along the second direction.

22. The semiconductor module according to claim 19, characterized in that, A conductive element (23) is also connected between the sixth jumper area (2201) and the external terminal (101). The dimension of the sixth jumper area (2201) in the first direction is C2, and C2 satisfies the relationship: C2≥4.4mm.

23. The semiconductor module according to claim 19, characterized in that, The first high-side inverter chip upper core area (5) is provided with a fourth clearance notch (604), and a seventh jumper area (2202) is provided in the fourth clearance notch (604). The seventh jumper area (2202) includes a first jumper area (5021) and a second jumper area (5022). The first jumper area (5021) extends in a second direction and is located between the first high-side inverter chip (11) and the second high-side inverter chip (12) in a first direction. The second jumper area (5022) is connected to one end of the first jumper area (5021) that is closer to the low side (10002) along the second direction. The second jumper area (5022) extends toward the side that is closer to the third substrate portion (2011) along the first direction. A conductive element (23) is connected between the first jumper area (5021) and the first high-side inverter chip (11). A conductive element (23) is connected between the wiring part (601) and the second jumper area (5022).

24. The semiconductor module according to claim 19, characterized in that, The first substrate portion (2021) is further provided with an eighth jumper area (2203), the eighth jumper area (2203) including a third jumper area (1701), a fourth jumper area (1702) and a fifth jumper area (1703). The third jumper area (1701) is spaced apart on the side of the first low-side inverter chip upper core area (6) adjacent to the low side (10002) in the second direction. The third jumper area (1701) extends in the first direction. The fourth jumper area (1702) and the fifth jumper area (1703) are respectively connected to the two ends of the third jumper area (1701) in the first direction. The fourth jumper region (1702) and the fifth jumper region (1703) are arranged to extend toward the side that is closer to the high side (10001) along the second direction. The first high-side inverter chip upper core region (5) is provided with a fifth clearance notch (605) on the side that is closer to the second substrate portion (2031) in the first direction. The fifth clearance notch (605) is located at one end of the first high-side inverter chip upper core region (5) that is closer to the low side (10002) along the second direction. The end of the fifth jumper region (1703) that is closer to the high side (10001) in the second direction extends at least partially into the fifth clearance notch (605).

25. The semiconductor module according to claim 23, characterized in that, Both the first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the upper core area (5) of the first high-side inverter chip, closer to the high side (10001) along the second direction. A conductive element (23) is connected between the second load electrode pad (1001) of the first high-side inverter chip (11) and the seventh jumper area (2202). The control electrode pad (1002) of the first high-side inverter chip (11) is disposed on the first high-side inverter chip (11) closer to the high side (10001) along the second direction. The control electrode pad (1002) of the first high-side inverter chip (11) is electrically connected to the external terminal (101).

26. The semiconductor module according to claim 25, characterized in that, The first substrate portion (2021) is further provided with a ninth jumper area (2204), which is disposed in the fourth clearance notch (604). The edge of the first high-side inverter chip (11) that is closer to the high side (10001) in the second direction is defined as the high-side edge (1104). The ninth jumper area (2204) is disposed at intervals on the side of the high-side edge (1104) facing the high side (10001) in the second direction. The ninth jumper area (2204) is disposed at intervals on the side of the first jumper area (5021) away from the second substrate portion (2031) in the first direction. The control electrode pad (1002) of the high-side inverter chip (11) is disposed on the first high-side inverter chip (11) along the second direction, which is closer to the high side (10001). The control electrode pad (1002) of the first high-side inverter chip (11) is disposed on the first high-side inverter chip (11) along the first direction, which is further away from the second substrate portion (2031). A conductive element (23) is connected between the control electrode pad (1002) of the first high-side inverter chip (11) and the ninth jumper area (2204). A conductive element (23) is connected between the ninth jumper area (2204) and the external terminal (101).

27. The semiconductor module according to claim 23, characterized in that, The seventh jumper area (2202) further includes a sixth jumper area (5023), which is connected to one end of the first jumper area (5021) adjacent to the high side (10001) in the second direction. The sixth jumper area (5023) extends toward the side adjacent to the second substrate portion (2031) in the first direction. A conductive element (23) is connected between the sixth jumper area (5023) and the external terminal (101).

28. The semiconductor module according to claim 19, characterized in that, The first substrate portion (2021) has a dimension D2 in the second direction; The distance between the first high-side inverter chip (11) and the edge of the first substrate portion (2021) facing the high side (10001) is E2, and D2 and E2 satisfy the relationship: 0.086D2≤E2≤0.117D2; The distance between the second high-side inverter chip (12) and the edge of the first substrate portion (2021) facing the high side (10001) is F2, and D2 and F2 satisfy the relationship: 0.086D2≤F2≤0.117D2.

29. The semiconductor module according to claim 1 or 25, characterized in that, The third high-side inverter chip (13) is located in the middle of the second substrate portion (2031) in the first direction.

30. The semiconductor module according to claim 29, characterized in that, The control electrode pad (1002) in the third high-side inverter chip (13) is disposed on the third high-side inverter chip (13) more closely adjacent to the high side (10001) along the second direction, and the control electrode pad (1002) in the third high-side inverter chip (13) is disposed on the third high-side inverter chip (13) more closely adjacent to the first substrate portion (2021) along the first direction.

31. The semiconductor module according to claim 30, characterized in that, The third high-side inverter chip (13) has a control electrode channel (19). The second load electrode pad (1001) of the third high-side inverter chip (13) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011). The control electrode channel (19) of the third high-side inverter chip (13) extends along the first direction.

32. The semiconductor module according to claim 29, characterized in that, The second substrate (2031) is further provided with a tenth jumper area (2205). The tenth jumper area (2205) is disposed at intervals on the side of the upper core area (7) of the second high-side inverter chip that is further away from the first substrate (2021) in the first direction. A conductive element (23) is connected between the control electrode pad (1002) of the third high-side inverter chip (13) and the tenth jumper area (2205). A conductive element (23) is connected between the tenth jumper area (2205) and the external terminal (101).

33. The semiconductor module according to claim 19, characterized in that, The substrate (2) includes a first sub-substrate (201), a second sub-substrate (202) and a third sub-substrate (203) arranged sequentially at intervals along the first direction. The third substrate portion (2011) is disposed on the first sub-substrate (201), the first substrate portion (2021) is disposed on the second sub-substrate (202), and the second substrate portion (2031) is disposed on the third sub-substrate (203).

34. A semiconductor module, characterized in that, The semiconductor module (100) has a first direction and a second direction, and a high side (10001) and a low side (10002) disposed opposite to each other in the second direction. The semiconductor module (100) includes: Shell (1); A substrate (2) is disposed within the housing (1). The substrate (2) has a first substrate portion (2021) and a second substrate portion (2031) arranged sequentially at intervals along the first direction. The first substrate portion (2021) has a first high-side inverter chip upper core region (5) and a first low-side inverter chip upper core region (6) arranged at intervals along the second direction. The first high-side inverter chip upper core region (5) is closer to the high side (10001) than the first low-side inverter chip upper core region (6). The second substrate portion (2031) has a second high-side inverter chip upper core region (7), a third low-side inverter chip upper core region (9), and a second low-side inverter chip upper core region (8) arranged sequentially at intervals along the second direction. The second high-side inverter chip upper core region (7) is closer to the high side (10001) than the second low-side inverter chip upper core region (8). Multiple inverter chips (10), each inverter chip (10) is a single chip, each inverter chip (10) is provided with a control electrode pad (1002), a first load electrode pad and a second load electrode pad (1001), the multiple inverter chips (10) include a first high-side inverter chip (11), a second high-side inverter chip (12), a third high-side inverter chip (13), a first low-side inverter chip (14), a second low-side inverter chip (15) and a third low-side inverter chip (16), the first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the first high-side inverter chip (1002), the second high-side inverter chip (12) and the third low-side inverter chip (16). The high-side inverter chip upper core area (5) is arranged at intervals along the first direction. The first high-side inverter chip (11) is further away from the second substrate portion (2031) in the first direction than the second high-side inverter chip (12). The third high-side inverter chip (13) is disposed in the second high-side inverter chip upper core area (7). The first low-side inverter chip (14) is disposed in the first low-side inverter chip (14). The second low-side inverter chip (15) is disposed in the second low-side inverter chip upper core area (8). The third low-side inverter chip (16) is disposed in the third low-side inverter chip upper core area (9). The second low-side inverter chip upper core area (8) includes a first upper core portion (801) and a first wiring portion (802), and the second low-side inverter chip (15) is disposed on the first upper core portion (801). The third low-side inverter chip upper core area (9) includes a second upper core portion (901) and a second wiring portion (902), and the third low-side inverter chip (16) is disposed on the second upper core portion (901). The second high-side inverter chip upper core area (7) includes a third upper core portion (701) and a third wiring portion (702), and the third high-side inverter chip (13) is disposed on the second low-side inverter chip upper core area (801). The three upper core portions (701) are arranged in a second direction adjacent to the low side (10002) of the second upper core portion (901), and the first wiring portion (802) is connected to the first substrate portion (2021) of the first upper core portion (801) in a first direction. The first wiring portion (802) extends in a second direction and is arranged in a second direction adjacent to the first substrate portion (2021) of the third low-side inverter chip upper core area (9) and the second high-side inverter chip upper core area (7). The second wiring portion (902) is connected to the side of the second upper core portion (901) away from the first substrate portion (2021) in a first direction and extends in a second direction. The second wiring portion (902) is spaced apart from the side of the third upper core portion (701) away from the first substrate portion (2021) in a first direction. The third wiring portion (702) is connected to the side of the third upper core portion (701) that is closer to the lower side (10002) in a second direction. The third wiring portion (702) extends in a second direction and at least partially extends between the first wiring portion (802) and the second upper core portion (901). The third high-side inverter chip (13) is located in the middle of the second substrate portion (2031) in the first direction. The control electrode pad (1002) in the third high-side inverter chip (13) is located on the side of the third high-side inverter chip (13) that is closer to the high side (10001) along the second direction. The control electrode pad (1002) in the third high-side inverter chip (13) is located on the end of the third high-side inverter chip (13) that is closer to the first substrate portion (2021) along the first direction. The second substrate (2031) is also provided with an eleventh jumper area (2206). The eleventh jumper area (2206) is spaced apart from the first substrate (2021) on the first direction of the upper core area (7) of the second high-side inverter chip. The eleventh jumper area (2206) is spaced apart from the side of the second wiring portion (902) that is closer to the high side (10001) along the second direction. The eleventh jumper area (2206) is connected to the control electrode pad (1002) of the third high-side inverter chip (13) by a conductive element.

35. The semiconductor module according to claim 1, 19, or 34, characterized in that, The third low-side inverter chip (16) is located in the middle of the second substrate portion (2031) in the first direction.

36. The semiconductor module according to claim 35, characterized in that, The control electrode pad (1002) in the third low-side inverter chip (16) is located on the side of the third low-side inverter chip (16) that is closer to the low side (10002) along the second direction; The control electrode pad (1002) in the third low-side inverter chip (16) is located at one end of the third low-side inverter chip (16) that is further away from the first substrate portion (2021) along the first direction.

37. The semiconductor module according to claim 36, characterized in that, The third low-side inverter chip (16) has a control electrode channel (19). The second load electrode pad (1001) of the third low-side inverter chip (16) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011). The control electrode channel (19) of the third low-side inverter chip (16) extends along the first direction.

38. The semiconductor module according to claim 1, 19, or 34, characterized in that, The second low-side inverter chip (15) is disposed on the second substrate portion (2031) more closely to the first substrate portion (2021) along the first direction.

39. The semiconductor module according to claim 38, characterized in that, The control electrode pad (1002) of the second low-side inverter chip (15) is provided on the side of the second low-side inverter chip (15) away from the first substrate portion (2021) in the first direction; The control electrode pad (1002) of the second low-side inverter chip (15) is disposed at one end of the second low-side inverter chip (15) in a second direction adjacent to the low side (10002).

40. The semiconductor module according to claim 39, characterized in that, The second low-side inverter chip (15) has a control electrode channel (19), and the second load electrode pad (1001) of the second low-side inverter chip (15) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011), and the control electrode channel (19) of the second low-side inverter chip (15) extends along the first direction.

41. The semiconductor module according to claim 34, characterized in that, The second substrate portion (2031) is further provided with a twelfth jumper area (2207). The twelfth jumper area (2207) is disposed at a distance between the first wiring portion (802) and the second upper core portion (901) in a first direction. The twelfth jumper area (2207) is disposed at a distance between the third wiring portion (702) and the first upper core portion (801) in a second direction. A first conductive element (2301) is connected between the twelfth jumper area (2207) and the second load electrode pad (1001) of the third low-side inverter chip (16). A second conductive element (2302) is connected between the twelfth jumper area (2207) and the first substrate portion (2021). A third conductive element (2303) is connected between the third wiring portion (702) and the first substrate portion (2021). The second conductive element (2302) and the third conductive element (2303) are arranged parallel to each other.

42. The semiconductor module according to claim 41, characterized in that, The first substrate portion (2021) is provided with a thirteenth jumper area (2208), the thirteenth jumper area (2208) includes a first jumper portion (2041), a second jumper portion (2042) and a third jumper portion (2043). The first jumper portion (2041) is spaced apart on the side of the first low-side inverter chip upper core area (6) that is closer to the low side (10002) in the second direction. The first jumper portion (2041) extends in the first direction. The second jumper portion (2042) and the third jumper portion (2043) are both connected to the two ends of the first jumper portion (2041) in the first direction. The second jumper portion (2042) and the third jumper portion (2043) both extend toward the side of the high side (10001) in the second direction. A first clearance notch (501) is provided on the side of the upper core area (5) of the first high-side inverter chip that is closer to the second substrate portion (2031) in the first direction. The first clearance notch (501) is located at one end of the upper core area (5) of the first high-side inverter chip that is closer to the low side (10002) in the second direction. The third jumper portion (2043) extends at least partially into the first clearance notch (501) at one end adjacent to the first high-side inverter chip (11). Compared with the first high-side inverter chip (11), the second high-side inverter chip (1 2) The second high-side inverter chip (12) is located closer to the second substrate portion (2031) in the first direction. The second high-side inverter chip (12) is spaced apart from the first clearance notch (501) in the second direction. The portion of the upper core area (5) of the first high-side inverter chip corresponding to the space between the second high-side inverter chip (12) and the first clearance notch (501) is connected to the third wiring portion (702) by the third conductive element (2303). The twelfth jumper area (2207) is connected to the third jumper portion (2043) by the second conductive element (2302).

43. The semiconductor module according to claim 34, characterized in that, Both the first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the upper core area (5) of the first high-side inverter chip, in a portion closer to the high side (10001) along the second direction.

44. The semiconductor module according to claim 43, characterized in that, The first substrate portion (2021) has a dimension of A1 in the second direction; The distance between the first high-side inverter chip (11) and the edge of the first substrate portion (2021) facing the high side (10001) is B1, and A1 and B1 satisfy the relationship: 0.086A1≤B1≤0.117A1; The distance between the second high-side inverter chip (12) and the edge of the first substrate (2021) facing the high side (10001) is C1, and A1 and C1 satisfy the relationship: 0.086A1≤C1≤0.117A1.

45. The semiconductor module according to claim 34, characterized in that, The first low-side inverter chip (14) is disposed on the portion of the upper core area (6) of the first low-side inverter chip that is closer to the second substrate portion (2031) along the first direction.

46. ​​The semiconductor module according to claim 45, characterized in that, The control electrode pad (1002) on the first low-side inverter chip (14) is located on the side of the first low-side inverter chip (14) further away from the second substrate portion (2031) along the first direction, and the control electrode pad (1002) on the first low-side inverter chip (14) is located on the end of the first low-side inverter chip (14) further adjacent to the low side (10002) along the second direction.

47. The semiconductor module according to claim 46, characterized in that, The first low-side inverter chip (14) has a control electrode channel (19), and the second load electrode pad (1001) of the first low-side inverter chip (14) includes two sub-load electrode pads (10011). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011), and the control electrode channel (19) of the first low-side inverter chip (14) extends along the second direction.

48. The semiconductor module according to claim 45, characterized in that, A second clearance notch (502) is provided in the upper core area (5) of the first high-side inverter chip, and a fourteenth jumper area (2209) is provided in the second clearance notch (502). The fourteenth jumper area (2209) includes a fourth jumper part (50211) and a fifth jumper part (50212). The fourth jumper part (50211) extends in a second direction and is located in a first direction between the first high-side inverter chip (11) and the second high-side inverter chip (12). Between them, the fifth jumper section (50212) is connected to the end of the fourth jumper section (50211) in the second direction that is closer to the low side (10002). The fifth jumper section (50212) extends in the first direction that is further away from the second substrate section (2031). A conductive element is connected between the portion of the upper core area (6) of the first low side inverter chip that is away from the first low side inverter chip (14) and the fifth jumper section (50212).

49. The semiconductor module according to claim 34, characterized in that, The substrate (2) includes a first sub-substrate (201) and a second sub-substrate (202) arranged sequentially along the first direction, with the first substrate portion (2021) disposed on the first sub-substrate (201) and the second substrate portion (2031) disposed on the second sub-substrate (202).

50. The semiconductor module according to claim 49, characterized in that, The substrate (2) also has a third substrate portion (2011), which is disposed on the side of the first substrate portion (2021) away from the second substrate portion (2031) in a first direction. The third substrate portion (2011) is provided with a brake unit upper core area and a rectifier unit upper core area.

51. The semiconductor module according to claim 50, characterized in that, The substrate (2) is further provided with a third sub-substrate (203), which is disposed at a distance from the first sub-substrate (201) on the side away from the second sub-substrate (202) in a first direction, and the third substrate portion (2011) is disposed on the third sub-substrate (203).

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