Computer motherboard and central processing unit configuration method

Abstract

Embodiments of the present application provide a computer motherboard and a central processing unit configuration method. The computer motherboard comprises a programmable logic device and N central processing units. The programmable logic device is connected to the N central processing units, and is configured to send configuration information to the central processing units, so as to set the computer motherboard to be in a multi-socket motherboard mode or a redundant single-socket motherboard mode; in the multi-socket motherboard mode, the N central processing units comprise one master central processing unit and N-1 slave central processing units; and in the redundant single-socket motherboard mode, the N central processing units are configured to be N master central processing units. The present application can solve the problem in the related art of being unable to achieve automatic switching between a multi-socket motherboard and a redundant single-socket motherboard, and improve the flexibility of service switching of computer motherboards, thereby achieving the effect of reducing the maintenance costs of the computer motherboards.

Description

Computer mainboard and method for setting central processing unit

[0001] Cross-reference to Related Applications

[0002] This application claims priority from the Chinese patent application No. 202410858381.0 filed on June 28, 2024, and entitled "Computer mainboard and method for setting central processing unit", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of computers, and in particular, to a computer mainboard and a method for setting a central processing unit. BACKGROUND

[0004] With the development of cloud computing, in order to guarantee the high reliability of business operation, redundancy design becomes more and more important in the field of servers. The core of redundancy design is to configure two sets of the same modules in the server, such as PSU (Power Supply Unit), fan, data disk, etc., to ensure that when a module fails, another module can seamlessly take over, thereby guaranteeing the stable operation of the system. However, the redundancy of the computing unit is the most difficult part to implement in the server and is the most critical redundancy link.

[0005] In the related art, the PCH (Platform Controller Hub) is integrated into the CPU (Central Processing Unit), which makes it possible to design multiple single-channel systems on a double-channel or multi-channel mainboard, but this is only to design multiple single-channel mainboards on the same mainboard. However, for the switching of multi-channel mainboards and redundant single-channel mainboards, it is still necessary to design on two different mainboards, which requires manual replacement of the two mainboards to meet the business architecture replacement requirements, resulting in increased development costs, single business type, and increased maintenance costs of the mainboard.

[0006] In view of the problem that the multi-channel mainboard and the redundant single-channel mainboard cannot be automatically switched in the related art, no effective solution has been proposed. SUMMARY

[0007] Embodiments of the present application provide a computer mainboard and a method for setting a central processing unit, to at least solve the problem that the multi-channel mainboard and the redundant single-channel mainboard cannot be automatically switched in the related art.

[0008] According to one embodiment of the present application, a computer mainboard is provided, comprising: a programmable logic device, N central processing units, N being an integer greater than or equal to 2, the programmable logic device being connected to the N central processing units and being configured to send configuration information to each of the central processing units to set the computer mainboard to a multi-path mainboard mode or a redundant single-path mainboard mode; in the multi-path mainboard mode, the N central processing units comprise one master central processing unit and N-1 slave central processing units, the master central processing unit loading boot software from a boot code storage area, and the N-1 slave central processing units sharing the boot software loaded by the master central processing unit; in the redundant single-path mainboard mode, the N central processing units are configured as N master central processing units, each of which loads boot software from a respective boot code storage area.

[0009] In one exemplary embodiment, the N central processing units are connected through high-speed channels; in the multi-path mainboard mode, the high-speed channels between the master central processing unit and the slave central processing units are in an enabled state, the high-speed channels between the slave central processing units are in an enabled state, or the high-speed channels between the slave central processing units are configured to be in an enabled state or a disabled state based on the configuration information; in the redundant single-path mainboard mode, the high-speed channels between the master central processing units are in a disabled state.

[0010] In one exemplary embodiment, a basic management control unit is connected to the programmable logic device and a network port and is configured to obtain the configuration information through the network port when the computer mainboard is in a power-on or power-off state and send the configuration information to the programmable logic device.

[0011] In one exemplary embodiment, each of the N central processing units is connected to a boot code storage area for storing boot software, wherein, when the computer mainboard is powered on, the programmable logic device controls the N central processing units to be powered on; in a case where a first central processing unit of the N central processing units is a master central processing unit, the first central processing unit reads first boot software from a first boot code storage area connected to the first central processing unit to start the first central processing unit through the first boot software, wherein the first central processing unit is any one of the N central processing units.

[0012] In one example embodiment, in the multi-path motherboard mode, the N central processors include one master central processor and N-1 slave central processors, the master central processor loads the boot software from the boot code storage area, and the N-1 slave central processors share the boot software loaded by the master central processor, further comprising: a slave central processor in the N central processors loads first boot software through a high-speed channel between the central processors connected thereto to start the slave central processor through the first boot software; wherein a second central processor connected adjacent to the first central processor is a slave central processor, the second central processor loads the first boot software through the high-speed channel to start the second central processor through the first boot software; a third central processor connected adjacent to the second central processor is a slave central processor, and in the case that the high-speed channel between the second central processor and the third central processor is in an enabled state, the third central processor loads the first boot software through the high-speed channel between the second central processor and the third central processor to start the third central processor through the first boot software.

[0013] In one example embodiment, in the redundant single-path motherboard mode, the N central processors are configured as N master central processors, and each of the N master central processors loads boot software from a respective boot code storage area, further comprising: a fourth central processor connected to the first central processor is a master central processor, and the fourth central processor reads fourth boot software from a fourth boot code storage area connected to the fourth central processor to start the fourth central processor through the fourth boot software.

[0014] In one example embodiment, each of the N central processors is connected to an add-on card device, and in the case that the computer motherboard is set in the multi-path motherboard mode, the master central processor sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the add-on card device connected to the master central processor and the add-on card device connected to the slave central processor according to the reset signal.

[0015] In one example embodiment, each of the N central processors is connected to an add-on card device, and in the case that the computer motherboard is set in the redundant single-path motherboard mode, each of the N master central processors sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the add-on card device connected to the corresponding master central processor according to the reset signal.

[0016] In one example embodiment, each of the N central processors is also connected to a system disk, wherein, in the case that the computer mainboard is set to the multi-path mainboard mode, the main central processor loads an operating system from the system disk connected thereto when the computer mainboard is powered on; the slave central processors of the N central processors load the operating system through the high-speed channel between the central processors connected thereto; wherein, in the case that the first central processor of the N central processors is the main central processor, the first central processor loads a first operating system from the first system disk connected to the first central processor, the first central processor being any one of the N central processors; the second central processor connected to the first central processor being the slave central processor, the second central processor loading the first operating system through the high-speed channel between the first central processor; the third central processor connected adjacently to the second central processor being the slave central processor, the third central processor loading the first operating system through the high-speed channel between the second central processor.

[0017] In one example embodiment, in the case that the computer mainboard is set to the redundant single-path mainboard mode, further comprising: the fourth central processor connected to the first central processor being the main central processor, the fourth central processor loading a fourth operating system from the fourth system disk connected to the fourth central processor.

[0018] In one example embodiment, each of the N central processors is connected to a memory, wherein, in the case that the computer mainboard is set to the multi-path mainboard mode, the main central processor reads data from the memory connected thereto; the slave central processors of the N central processors read data through the high-speed channel between the central processors connected thereto; wherein, in the case that the first central processor of the N central processors is the main central processor, the first central processor reads first data from the first memory connected to the first central processor, the first central processor being any one of the N central processors; the second central processor connected to the first central processor being the slave central processor, the second central processor reading the first data through the high-speed channel between the first central processor; the third central processor connected adjacently to the second central processor being the slave central processor, the third central processor reading the first data through the high-speed channel between the second central processor.

[0019] In one example embodiment, in the case that the computer mainboard is set to the redundant single-path mainboard mode, further comprising: the fourth central processor connected to the first central processor being the main central processor, the fourth central processor reading fourth data from the fourth memory connected to the fourth central processor.

[0020] In one example embodiment, the programmable logic device is connected to N central processors, and the programmable logic device is configured to: set the level state of a first master-slave pin of a first central processor to high level if the configuration information indicates that the first central processor is a master central processor; and set the level state of a second master-slave pin of a second central processor to low level if the configuration information indicates that the second central processor is a slave central processor.

[0021] In one example embodiment, the programmable logic device is connected to N central processors, and the programmable logic device is further configured to: connect to a reset pin on each central processor to receive a reset signal sent by each central processor through the reset pin.

[0022] In one example embodiment, the N central processors are connected in series, or the N central processors are connected in a ring.

[0023] According to yet another embodiment of the present application, a method for setting a central processor is provided, which is applied to a programmable logic device in a computer motherboard as described above, and the method comprises: obtaining configuration information from a basic management control unit when the computer motherboard is in a power-on or power-off state; and setting the computer motherboard to a multi-path motherboard mode or a redundant single-path motherboard mode according to the configuration information, wherein in the multi-path motherboard mode, N central processors include one master central processor and N-1 slave central processors, the master central processor loads start-up software from a start-up code storage area, and the N-1 slave central processors share the start-up software loaded by the master central processor; and in the redundant single-path motherboard mode, the N central processors are configured as N master central processors, and each of the N master central processors loads start-up software from a respective start-up code storage area, wherein N is an integer greater than or equal to 2.

[0024] In one example embodiment, setting the computer motherboard to the multi-path motherboard mode or the redundant single-path motherboard mode according to the configuration information comprises: setting the level state of a master-slave pin of a master central processor indicated in the configuration information to high level when the computer motherboard is set to the multi-path motherboard mode; setting the level state of a master-slave pin of a slave central processor indicated in the configuration information to low level; and setting the level state of a master-slave pin of each of the N central processors to high level when the computer motherboard is set to the redundant single-path motherboard mode.

[0025] In one example embodiment, after the computer motherboard is set to the multi-path motherboard mode or the redundant single-path motherboard mode according to the configuration information, the method further comprises: receiving a reset signal from a reset pin of the master central processing unit in the case that the computer motherboard is set to the multi-path motherboard mode; performing a reset operation on the expansion card device connected to the master central processing unit and the slave central processing unit respectively according to the reset signal; and receiving a reset signal from the N master central processing units respectively in the case that the computer motherboard is set to the redundant single-path motherboard mode, and performing a reset on the expansion card device connected to the corresponding master central processing unit according to the reset signal.

[0026] According to another embodiment of the present application, a method for starting a central processing unit is provided, which is applied to the master central processing unit in the computer motherboard, and comprises: when the computer motherboard is powered on, the master central processing unit reads the starting software from the starting code storage area connected thereto to start the master central processing unit through the starting software, wherein the working mode of the computer motherboard comprises: a multi-path motherboard mode and a redundant single-path motherboard mode, in the multi-path motherboard mode, the N central processing units comprise one master central processing unit and N-1 slave central processing units, and in the redundant single-path motherboard mode, the N central processing units are configured as N master central processing units; in the case that the computer motherboard is set to the multi-path motherboard mode, the master central processing unit loads the starting software from the starting code storage area and sends the starting software to the N-1 slave central processing units, so that the N-1 slave central processing units share the starting software loaded by the master central processing unit; and in the case that the computer motherboard is set to the redundant single-path motherboard mode, the N master central processing units load the starting software from the respective starting code storage areas.

[0027] In one example embodiment, after the master central processing unit is started through the starting software, the method further comprises: in the case that the computer motherboard is set to the multi-path motherboard mode, the master central processing unit sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the master central processing unit and the expansion card device connected to the slave central processing unit; and in the case that the computer motherboard is set to the redundant single-path motherboard mode, the N central processing units respectively send a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the corresponding master central processing unit.

[0028] According to another embodiment of the present application, a method for starting a central processing unit is provided, which is applied to a slave central processing unit in the computer mainboard, and comprises the following steps: in the case that the computer mainboard is set to a multi-path mainboard mode, the slave central processing unit acquires starting software from a central processing unit connected thereto through a high-speed channel, and the slave central processing unit performs a starting operation through the starting software, wherein in the multi-path mainboard mode, N central processing units in the computer mainboard comprise one master central processing unit and N-1 slave central processing units, the master central processing unit loads starting software from a starting code storage area, and the N-1 slave central processing units share the starting software loaded by the master central processing unit, and N is an integer greater than or equal to 2.

[0029] According to another embodiment of the present application, a programmable logic device is provided, which comprises: a first acquisition module configured to acquire configuration information from a basic management control unit in the case that a computer mainboard is in a power-on and power-off state; and a setting module configured to set the computer mainboard to a multi-path mainboard mode or a redundant single-path mainboard mode according to the configuration information, wherein in the multi-path mainboard mode, N central processing units comprise one master central processing unit and N-1 slave central processing units, the master central processing unit loads starting software from a starting code storage area, and the N-1 slave central processing units share the starting software loaded by the master central processing unit; and in the redundant single-path mainboard mode, the N central processing units are configured as N master central processing units, and each of the N master central processing units loads starting software from a respective starting code storage area, wherein N is an integer greater than or equal to 2.

[0030] According to another embodiment of the present application, a master central processing unit is provided, which comprises: a first reading module configured to read starting software from a starting code storage area connected thereto to start the master central processing unit through the starting software when a computer mainboard is powered on, wherein the working mode of the computer mainboard comprises a multi-path mainboard mode and a redundant single-path mainboard mode, in the multi-path mainboard mode, N central processing units comprise one master central processing unit and N-1 slave central processing units, and in the redundant single-path mainboard mode, the N central processing units are configured as N master central processing units; a first loading module configured to load the starting software from the starting code storage area and send the starting software to the N-1 slave central processing units to make the N-1 slave central processing units share the starting software loaded by the master central processing unit in the case that the computer mainboard is set to the multi-path mainboard mode; and a second loading module configured to load the starting software from a respective starting code storage area in the case that the computer mainboard is set to the redundant single-path mainboard mode.

[0031] According to another embodiment of the present application, a slave central processing unit is provided, comprising: a second obtaining module configured to, when a computer mainboard is set to a multi-mainboard mode, obtain, from a master central processing unit connected thereto, through a high-speed channel, boot software from the master central processing unit, and perform, by the slave central processing unit, a boot operation through the boot software, wherein in the multi-mainboard mode, N central processing units in the computer mainboard include one master central processing unit and N-1 slave central processing units, the master central processing unit loads the boot software from a boot code storage area, and the N-1 slave central processing units share the boot software loaded by the master central processing unit, and N is an integer greater than or equal to 2.

[0032] According to still another embodiment of the present application, a computer nonvolatile readable storage medium is further provided, and the computer nonvolatile readable storage medium stores a computer program, wherein the computer program is configured to perform the steps in any of the method embodiments above when executed.

[0033] According to still another embodiment of the present application, an electronic device is further provided, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the method embodiments above.

[0034] According to still another embodiment of the present application, a computer program product is further provided, comprising a computer program, and the computer program is executed by a processor to implement the steps in any of the method embodiments above.

[0035] According to the present application, the programmable logic device is connected to N central processing units and is configured to send configuration information to each of the central processing units to set the computer mainboard to a multi-mainboard mode or a redundant single-mainboard mode; in the multi-mainboard mode, the N central processing units include one master central processing unit and N-1 slave central processing units, the master central processing unit loads boot software from a boot code storage area, and the N-1 slave central processing units share the boot software loaded by the master central processing unit; and in the redundant single-mainboard mode, the N central processing units are configured as N master central processing units, and each of the N master central processing units loads boot software from a respective boot code storage area.

[0036] Since the programmable logic device can master-slave configure each of the central processing units according to the configuration information, the central processing units can be flexibly configured as master central processing units or slave central processing units according to requirements, and automatic switching of the multi-mainboard or the redundant single-mainboard of the mainboard is achieved. Therefore, the problem that the multi-mainboard and the redundant single-mainboard cannot be automatically switched in the related art is solved, the flexibility of the computer mainboard service switching is improved, and the effect of reducing the maintenance cost of the computer mainboard is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a structural schematic diagram of a computer motherboard according to an embodiment of the present application;

[0038] Figure 2 is a structural schematic diagram of a computer motherboard according to an embodiment of the present application;

[0039] Figure 3 is a CPU configuration signal connection diagram according to an embodiment of the present application;

[0040] Figure 4 is a motherboard topology diagram of a dual CPU according to an embodiment of the present application;

[0041] Figure 5 is a dual-path motherboard reset signal topology diagram according to an embodiment of the present application;

[0042] Figure 6 is a redundant single-path motherboard reset signal topology diagram according to an embodiment of the present application;

[0043] Figure 7 is a flowchart of a method of setting a central processing unit according to an embodiment of the present application;

[0044] Figure 8 is a flowchart of a method of starting a central processing unit according to an embodiment of the present application;

[0045] Figure 9 is a flowchart of a method of starting a central processing unit according to an embodiment of the present application;

[0046] Figure 10 is a structural block diagram of a programmable logic device according to an embodiment of the present application;

[0047] Figure 11 is a structural block diagram of a master central processing unit according to an embodiment of the present application;

[0048] Figure 12 is a structural block diagram of a slave central processing unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to better understand the embodiments of the present application, some words in the present application are explained as follows:

[0050] CPLD: Complex Programmable Logic Device, programmable logic device, which can control the pin signal through the internally embedded software written.

[0051] BMC: Basic Management Control Unit, basic management control unit, the main function of which is to manage the entire server.

[0052] CPU: Central Processing Unit, central processing unit, the main computing and processing unit of a computer and a server.

[0053] Redundancy: two identical modules are designed in a set of servers, such as PSU, fan, data disk, etc. For example, two PSUs are often designed in a set of servers, when one of the PSUs fails, the other PSU can continue to power the server to ensure the normal operation of the server; or multiple fans, when one fan fails, the other fans can continue to work to ensure the normal heat dissipation of the server; or the data hard disk needs to be designed redundantly, the data disk contains a large amount of key data required by the business, when one disk fails, if there is no redundant design, it will inevitably lead to data loss and cause serious failure.

[0054] Multi-path motherboard: multiple CPUs are designed on a PCB (Printed Circuit Board) motherboard, one main CPU and the others are slave CPUs. Each CPU is interconnected through a high-speed bus, and the main CPU is interconnected with the PCH. These main chips form a whole and run one operating system. The computing and processing tasks performed by multiple CPUs are all for this one operating system.

[0055] Redundant single-path motherboard: two CPUs are designed on a motherboard, and the two CPUs are not connected to each other. Each CPU connects an operating system, which is equivalent to running two independent operating systems on the motherboard. When one CPU and the operating system disk fail, the other one continues to run to realize the redundant motherboard design.

[0056] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.

[0057] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0058] In the present embodiment, a computer motherboard is provided, and Fig. 1 is a structural schematic diagram of a computer motherboard according to an embodiment of the present application. As shown in Fig. 1, the computer motherboard comprises N central processing units, N is an integer greater than or equal to 2, and comprises a programmable logic device connected to the N central processing units, which is configured to send configuration information to each central processing unit to set the computer motherboard to a multi-path motherboard mode or a redundant single-path motherboard mode. In the multi-path motherboard mode, the N central processing units comprise one main central processing unit and N-1 slave central processing units. The main central processing unit loads startup software from a startup code storage area, and the N-1 slave central processing units share the startup software loaded by the main central processing unit. In the redundant single-path motherboard mode, the N central processing units are configured as N main central processing units, and each of the N main central processing units loads startup software from a respective startup code storage area.

[0059] The computer mainboard can be a mainboard in a server case, and mainly comprises a programmable logic device (CPLD) and a central processing unit (CPU), wherein the CPLD is configured to implement logic control and data processing of various functional modules, and the CPU is configured to execute various algorithms and logic operations, and multiple CPUs can work cooperatively on the computer mainboard.

[0060] Specifically, the N central processing units are connected through high-speed channels; in the multi-path mainboard mode, the high-speed channels between the master central processing units and the slave central processing units are in an enabled state, the high-speed channels between the slave central processing units are in an enabled state, or the high-speed channels between the slave central processing units are configured to be in an enabled state or a closed state based on configuration information; in the redundant single-path mainboard mode, the high-speed channels between the master central processing units are in a closed state.

[0061] In the embodiment, the multiple CPUs are sequentially interconnected through the high-speed channels, and the configuration pins of each CPU are connected with the CPLD, so that the enable signals of the CPUs for controlling the power-on of the peripheral devices can be uniformly allocated by the CPLD; in the case that the working mode of the computer mainboard is the multi-path mainboard mode, one of the multiple CPUs is configured as a master CPU, and the rest of the CPUs are configured as slave CPUs, wherein the master CPU can be any specified one of the multiple CPUs, or a CPU that is pre-set in the multiple CPUs by default, and the high-speed channels between the multiple CPUs are in an enabled state; in the case that the working mode of the computer mainboard is the redundant single-path mainboard mode, all the multiple CPUs are configured as master CPUs, and the high-speed channels between the multiple CPUs are in a closed state.

[0062] In some embodiments, the computer mainboard further comprises a basic management control unit connected to the programmable logic device and the network port, and configured to acquire the configuration information through the network port when the computer mainboard is in a power-on and shutdown state, and send the configuration information to the programmable logic device.

[0063] The computer mainboard can be a mainboard in a server case, and the mainboard further comprises a basic management control unit (BMC) configured to monitor and manage the running state and communication function of the whole system, wherein one end of the BMC is connected with the CPLD, and the other end is interconnected with an external switch through a network port. When the computer mainboard is in a power-on and shutdown state, the CPLD and the BMC are in a power-on working state, and each CPU is in a non-power-on and non-working state. At this time, a technician can access the BMC through a network to issue a control instruction, so that the BMC obtains the control instruction through the network port and sends the control instruction to the CPLD. The control instruction is used to indicate whether the working mode of the computer mainboard is a multi-path mainboard mode or a redundant single-path mainboard mode, and the control instruction comprises configuration information of each CPU, which is used to indicate whether each CPU is a master CPU or a slave CPU. After receiving the control instruction, the CPLD analyzes the control instruction to obtain the configuration information of each CPU, and sets configuration pins of each connected CPU according to the configuration information, and performs corresponding operations on the high-speed channel between the CPUs according to the configuration of each CPU.

[0064] In some embodiments, setting the configuration pins of each CPU further comprises: determining the CPUs that need to be configured from the plurality of CPUs according to the control instruction, and the CPUs that need to be configured can be all or part of the CPUs on the computer mainboard. Each CPU that needs to be configured is configured as a master central processing unit or a slave central processing unit according to the configuration information of each CPU that needs to be configured.

[0065] In some embodiments, when the two adjacent CPUs are both the CPUs that need to be configured, corresponding operations are performed on the high-speed channel between the two adjacent CPUs according to the configuration information of the two adjacent CPUs, and when the two adjacent CPUs are neither the CPUs that need to be configured, or one of the two adjacent CPUs is the CPU that needs to be configured and the other is not, the high-speed channel between the two adjacent CPUs is in a closed state.

[0066] In some embodiments, when the two adjacent CPUs are a master CPU and a slave CPU respectively, the high-speed channel between the two adjacent CPUs is in an enabled state, when the two adjacent CPUs are both master CPUs, the high-speed channel between the two adjacent CPUs is in a closed state, and when the two adjacent CPUs are both slave CPUs, the high-speed channel between the two adjacent CPUs is in an enabled state.

[0067] In some embodiments, as shown in FIG. 1, a technician sends a control instruction to the BMC through the network, the control instruction being to configure the CPUs 1-3 into a multi-path motherboard mode, the BMC receives the control instruction through the network and sends the control instruction to the CPLD, the CPLD receives the control instruction and parses the control instruction to obtain configuration information of the CPUs 1-3, wherein the CPU 1 is configured as a master CPU and the CPUs 2 and 3 are configured as slave CPUs, the CPLD sets configuration pins of the CPUs 1-3 according to the configuration information of the CPUs 1-3, and simultaneously, according to the configuration information of the CPUs 1-3, the CPLD opens high-speed channels between the CPU 1 and 2 and between the CPU 2 and 3, and closes high-speed channels between other CPUs.

[0068] In some embodiments, as shown in FIG. 1, a technician sends a control instruction to the BMC through the network, the control instruction being to configure the CPUs 1-3 into a single-path redundant motherboard mode, the BMC receives the control instruction through the network and sends the control instruction to the CPLD, the CPLD receives the control instruction and parses the control instruction to obtain configuration information of the CPUs 1-3, wherein the CPUs 1, 2 and 3 are all configured as master CPUs, the CPLD sets configuration pins of the CPUs 1-3 according to the configuration information of the CPUs 1-3, and simultaneously, according to the configuration information of the CPUs 1-3, the CPLD closes high-speed channels between the CPU 1 and 2 and between the CPU 2 and 3, and closes high-speed channels between other CPUs.

[0069] Through the above computer motherboard, multiple CPUs are designed on one motherboard, wherein the master-slave configuration pins of the CPUs are controlled by the CPLD, the CPLD can switch the CPUs to be master or slave by changing the master-slave configuration pins of the CPUs, thereby realizing automatic switching of the multi-path or single-path redundancy of the motherboard, improving the performance and efficiency of the system, and ensuring that the system can quickly switch to a standby path when facing a sudden situation, thereby ensuring the normal operation of the system. In addition, the automatic switching of the multi-path or single-path redundancy can also simplify the maintenance and management of the system, reduce the need for manual intervention, reduce maintenance costs, and improve the operability and maintainability of the system.

[0070] In some embodiments, each of the N central processing units is connected to a startup code storage area for storing startup software, wherein, when the computer motherboard is powered on, the programmable logic device controls the N central processing units to be powered on; in the case that a first central processing unit of the N central processing units is a master central processing unit, the first central processing unit reads a first startup software from a first startup code storage area connected to the first central processing unit to start the first central processing unit through the first startup software, wherein the first central processing unit is any central processing unit of the N central processing units.

[0071] The startup code storage area can be a startup software storage area, and the startup software can be a Basic Input / Output System (BIOS). The first central processing unit can be a main central processing unit (main CPU). When the computer mainboard is powered on, the main CPU loads the startup code BIOS from the startup code storage area. Before startup, the BIOS needs to access the BMC or access the special registers in the CPLD. When the multi-mainboard mode is read, the BIOS enables the high-speed channel between the CPUs to the enabled state, and performs the startup process. After the startup is completed, the main CPU sends a reset signal to the CPLD, and the CPLD performs a global reset of the server, thereby realizing normal startup of the multi-mainboard.

[0072] In some embodiments, in the multi-mainboard mode, the N central processing units include one main central processing unit and N-1 slave central processing units. The main central processing unit loads the startup software from the startup code storage area. The N-1 slave central processing units share the startup software loaded by the main central processing unit, and further include: a slave central processing unit in the N central processing units loads the first startup software through the high-speed channel connected with the slave central processing unit, to start the slave central processing unit through the first startup software. The second central processing unit connected with the first central processing unit is a slave central processing unit. The second central processing unit loads the first startup software through the high-speed channel, to start the second central processing unit through the first startup software. The third central processing unit connected with the second central processing unit is a slave central processing unit. When the high-speed channel between the second central processing unit and the third central processing unit is in the enabled state, the third central processing unit loads the first startup software through the high-speed channel between the second central processing unit and the third central processing unit, to start the third central processing unit through the first startup software.

[0073] In the case where the working mode is the multi-mainboard mode, the first central processing unit can be a main central processing unit (main CPU), and the second central processing unit and the third central processing unit can be slave central processing units (slave CPUs). In the case where the main CPU and the slave CPUs are directly connected, the main CPU enables the high-speed channel between the main CPU and the slave CPUs through the startup code BIOS, so that the slave CPUs can obtain the startup software of the main CPU through the high-speed channel. In the case where the main CPU and the slave CPUs are indirectly connected through other slave CPUs, the main CPU enables the high-speed channels between the main CPU and the slave CPUs and between the slave CPUs through the startup code BIOS, so that the third central processing unit can obtain the startup software of the first central processing unit through the second central processing unit and the high-speed channel.

[0074] For example, as shown in FIG. 1, in the case that the connection mode of the plurality of CPUs is serial connection, the slave CPU obtains the startup software of the master CPU through the CPU adjacent to the master CPU, for example, in FIG. 1, if CPU1 is the master CPU and the other CPUs are slave CPUs, CPU2 obtains the startup software in the startup code storage area of CPU1 through the high-speed channel between CPU1 and CPU2, CPU3 obtains the startup software in the startup code storage area of CPU1 through the high-speed channel between CPU2 and CPU3, and so on. CPU N-1 can only obtain the startup software of CPU1 by sequentially passing through CPU N-2, CPU N-1, and the like.

[0075] In some embodiments, the N central processors are sequentially connected or the N central processors are connected in a ring.

[0076] In some embodiments, as shown in FIG. 2, in the case that the connection mode of the plurality of CPUs is ring connection, the slave CPU obtains the startup software of the master CPU through any one of the CPUs adjacent to the master CPU, for example, in FIG. 2, if CPU1 is the master CPU, CPU N-1 can obtain the startup software of CPU1 by sequentially passing through CPU N-2, CPU N-1, and the like, or can obtain the startup software of CPU1 through CPU N, thereby greatly reducing the channel path for the slave CPU to obtain the startup software of the master CPU and enabling the slave CPU to obtain the startup software of the master CPU more quickly.

[0077] In some embodiments, the slave CPU can obtain the startup software in the startup code storage area of the master CPU according to the shortest path of the ring connection formed by the plurality of CPUs, in the case that the i-th CPU is the master CPU and the other CPUs are slave CPUs among the plurality of CPUs connected in a ring, since the plurality of CPUs are connected in a ring, there are two paths (assuming a first path and a second path) for the j-th CPU to reach the i-th CPU. The j-th CPU can calculate the number of nodes on the first path and the second path, and the j-th CPU selects the path with the least number of nodes to obtain the startup software from the i-th CPU. i and j are integers greater than or equal to 1, and i is not equal to j. In this embodiment, the slave CPU obtains the startup software from the master CPU based on the shortest path, which can accelerate the startup speed of the slave CPU and also achieve the technical effect of saving resources.

[0078] In some embodiments, in the redundant single-path motherboard mode, the N central processors are configured as N master central processors, and the N master central processors load startup software from respective startup code storage areas, including: the fourth central processor connected with the first central processor is a master central processor, and the fourth central processor reads fourth startup software from the fourth startup code storage area connected with the fourth central processor to start the fourth central processor through the fourth startup software.

[0079] The startup code storage area can be a startup software storage area, and the startup software can be a startup code BIOS. The first central processor and the fourth central processor can be master central processors (master CPUs). Each master CPU has a separate boot system. When the computer mainboard is powered on, each master CPU loads the startup code BIOS from its own startup code storage area. Before startup, the BIOS needs to access the BMC or access a special register in the CPLD. When the redundant single-path mainboard mode is read, each master CPU respectively closes the high-speed channel between the CPUs through the respective BIOS, and performs the boot startup process. After the boot startup is completed, each master CPU sends a reset signal to the CPLD, and the CPLD controls the devices connected to each master CPU to reset, thereby realizing the normal boot of the redundant single-path CPU.

[0080] In some embodiments, each of the N central processors is connected to an add-on card device. In the case where the computer mainboard is set to the multi-path mainboard mode, the master central processor sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the add-on card device connected to the master central processor and the add-on card device connected to the slave central processor according to the reset signal.

[0081] In some embodiments, each of the N central processors is connected to an add-on card device. In the case where the computer mainboard is set to the redundant single-path mainboard mode, the N master central processors respectively send a reset signal to the programmable logic device to instruct the programmable logic device to reset the add-on card device connected to the corresponding master central processor according to the reset signal.

[0082] In some embodiments, each of the N central processors is also connected to a system disk. In the case where the computer mainboard is set to the multi-path mainboard mode, when the computer mainboard is powered on, the master central processor loads an operating system from the system disk connected thereto. The slave central processor in the N central processors loads the operating system through the high-speed channel between the central processors connected thereto. In the case where the first central processor in the N central processors is the master central processor, the first central processor loads a first operating system from the first system disk connected to the first central processor, and the first central processor is any central processor in the N central processors. The second central processor connected to the first central processor is the slave central processor, and the second central processor loads the first operating system through the high-speed channel with the first central processor. The third central processor connected adjacent to the second central processor is the slave central processor, and the third central processor loads the first operating system through the high-speed channel with the second central processor.

[0083] In some embodiments, in the case that the computer mainboard is set to the redundant single-path mainboard mode, further comprising: the fourth central processing unit connected with the first central processing unit is the main central processing unit, and the fourth central processing unit loads a fourth operating system from a fourth system disk connected with the fourth central processing unit.

[0084] In some embodiments, in the case that the computer mainboard is set to the redundant single-path mainboard mode, further comprising: the fourth central processing unit connected with the first central processing unit is the main central processing unit, and the fourth central processing unit loads a fourth operating system from a fourth system disk connected with the fourth central processing unit.

[0085] In some embodiments, each of the N central processing units is connected with a memory, wherein, in the case that the computer mainboard is set to the multi-path mainboard mode, the main central processing unit reads data from the memory connected with the main central processing unit; the slave central processing units read data through the high-speed channel between the central processing units connected with the slave central processing units; wherein, in the case that the first central processing unit of the N central processing units is the main central processing unit, the first central processing unit reads first data from the first memory connected with the first central processing unit, and the first central processing unit is any one of the N central processing units; the second central processing unit connected with the first central processing unit is the slave central processing unit, and the second central processing unit loads the first data through the high-speed channel between the first central processing unit and the second central processing unit; the third central processing unit connected with the second central processing unit is the slave central processing unit, and the third central processing unit loads the first data through the high-speed channel between the second central processing unit and the third central processing unit.

[0086] In some embodiments, in the case that the computer mainboard is set to the redundant single-path mainboard mode, further comprising: the fourth central processing unit connected with the first central processing unit is the main central processing unit, and the fourth central processing unit reads fourth data from the fourth memory connected with the fourth central processing unit.

[0087] In some embodiments, the programmable logic device is connected with the N central processing units, comprising: in the case that the configuration information indicates that the first central processing unit is the main central processing unit, the programmable logic device is set to control the level state of the first master-slave pin of the first central processing unit to be high; in the case that the configuration information indicates that the second central processing unit is the slave central processing unit, the programmable logic device is set to control the level state of the second master-slave pin of the second central processing unit to be low.

[0088] The above master-slave pin can be a legacy_SKT pin on an Intel platform, as shown in FIG. 3, in the case that the CPU is the master CPU, the CPLD will pull the master-slave pin of the CPU to high level, and in the case that the CPU is the slave CPU, the CPLD will pull the master-slave pin of the CPU to low level.

[0089] In some embodiments, the programmable logic device is connected to the N central processing units, and further comprises: a reset pin of the programmable logic device is connected to each central processing unit to receive a reset signal sent by each central processing unit through the reset pin.

[0090] As shown in FIG. 3, the reset signal reset can be sent from the CPU to the CPLD through the reset pin, and the CPLD controls the external plug-in card and other peripheral devices after receiving the reset signal.

[0091] In some embodiments, FIG. 4 is a schematic diagram of a motherboard topology of a dual-CPU according to an embodiment of the present application. As shown in FIG. 4, two CPUs are designed on a motherboard, and a high-speed interconnection channel is designed between the two CPUs to interconnect the two CPUs; each CPU is connected to independent memory, a system disk, a boot code (BIOS) storage area, an external plug-in card, etc.; at the same time, the pins of the CPLD are connected to the configuration pins of the CPU; the BMC module has a network port to the outside and is connected to the CPLD internally. When a user needs to configure the entire machine, the entire machine is powered on first, and before a key is pressed, the entire machine is in a shutdown state, and only the BMC and the CPLD and other management modules are in a working state, and other modules are in a power-off non-working state.

[0092] The user accesses the BMC through the network port and selects a mode to be configured for the entire machine under the BMC management interface. When the mode is configured as a dual-board (dual-CPU), the BMC sends an instruction to the CPLD, and the instruction contains configuration information. The CPLD controls the level state of the configuration pins connected to each CPU, configures CPU1 as a master CPU and configures CPU2 as a slave CPU. At this time, the power-on key is pressed, and the power-on key signal is transmitted to the CPLD, and the CPLD controls all devices to be powered on. After CPU1 is powered on, the boot software is loaded from the boot code storage area, and the configuration information read by the BIOS is configured as a master CPU, and the high-speed channel between CPU1 and CPU2 is enabled. After CPU2 is powered on, the configuration information read is a slave CPU, and the boot software loaded by CPU1 is not loaded from the boot code storage area. When CPU1 and CPU2 are started, as shown in FIG. 5, the master CPU (CPU1) sends a reset signal to the CPLD, and the CPLD receives the reset signal. Because the CPLD also knows that the configuration is a dual-configuration at this time, the CPLD sends a reset signal to all external plug-in card devices connected to the CPU, realizes successful connection of the high-speed link, all devices can work with the CPU, and all external plug-in card devices can be seen under the same operating system.

[0093] When configured as a redundant single-path mainboard (redundant single-path CPU), the BMC sends a command to the CPLD, and the command contains configuration information. The CPLD controls the level state of the configuration pins connected to the CPUs, and configures CPU1 and CPU2 as master CPUs. At this time, press the power-on button, and the power-on button signal is transmitted to the CPLD, and the CPLD controls the power-on of all devices. After CPU1 is powered on, it is configured as a master CPU according to the read configuration information, loads the startup software from the startup code storage area, and closes the high-speed channel between CPU1 and CPU2. After CPU2 is powered on, it is configured as a master CPU according to the read configuration information, loads the startup software from the startup code storage area, and closes the high-speed channel between CPU1 and CPU2. At this time, CPU1 and CPU2 each load their own software programs and do not affect each other. When CPU1 and CPU2 are started, as shown in FIG. 6, CPU1 and CPU2 respectively send a reset signal to the CPLD. After the CPLD receives the reset signal, because the CPLD also knows that this configuration is a redundant single-path configuration, the CPLD sends a respective reset signal to the external plug-in card device connected to each CPU, realizes successful connection of the high-speed link, and all devices work with their respective CPUs. Under this configuration, each CPU has its own independent operating system disk, and the operating system running on each CPU is also independent and does not affect each other. When the CPLD receives the reset signal from each different CPU, if some CPU does not send a reset signal, the CPLD will reset the external plug-in card device connected to the CPU that has sent a reset signal, but will not reset the external plug-in card device connected to the CPU that has not sent a reset signal. Until the CPLD receives the reset signal of the corresponding CPU, the CPLD will reset the corresponding connected external plug-in card, thereby completing the connection and use of the late-starting CPU and its external plug-in card device.

[0094] A method for setting a central processing unit is provided in the embodiment, and FIG. 7 is a flowchart of the method for setting a central processing unit according to the embodiment of the application. As shown in FIG. 7, the method is applied to the programmable logic device in the computer mainboard, and the specific flow includes the following steps:

[0095] In step S702, configuration information is obtained from the basic management control unit when the computer mainboard is in a power-on and shutdown state.

[0096] The configuration information can be configuration information of a central processing unit (CPU) configuration pin, which is used to configure multiple CPUs as master CPUs or slave CPUs. The programmable logic device (CPLD) obtains a control instruction from the basic management control unit (BMC), and the control instruction is used to indicate that the working mode of the computer mainboard is a multi-path mainboard mode or a redundant single-path mainboard mode. The configuration information is included in the control instruction, and the configuration information is obtained by the CPLD after the control instruction is parsed.

[0097] In step S704, the computer mainboard is set to a multi-path mainboard mode or a redundant single-path mainboard mode according to the configuration information. In the multi-path mainboard mode, the N central processing units include one master central processing unit and N-1 slave central processing units, the master central processing unit loads the startup software from the startup code storage area, and the N-1 slave central processing units share the startup software loaded by the master central processing unit. In the redundant single-path mainboard mode, the N central processing units are configured as N master central processing units, and each of the N master central processing units loads the startup software from the respective startup code storage area, where N is an integer greater than or equal to 2.

[0098] In some embodiments, in the case where the computer mainboard is set to the multi-path mainboard mode, the level state of the master-slave pin of the master central processing unit indicated in the configuration information is set to a high level, and the level state of the master-slave pin of the slave central processing unit indicated in the configuration information is set to a low level. In the case where the computer mainboard is set to the redundant single-path mainboard mode, the level state of the master-slave pin of each of the N central processing units is set to a high level.

[0099] The master-slave pin of the CPU is connected to the pin of the CPLD, and the master-slave pin can be a legacy_SKT pin. The CPLD sets the master-slave pin of the CPU according to the configuration information, so as to configure each CPU as a master CPU or a slave CPU. In some embodiments, in the case where the CPU is configured as a master CPU, the level state of the master-slave pin is set to a high level, and in the case where the CPU is configured as a slave CPU, the level state of the master-slave pin is set to a low level.

[0100] Through the above steps, in the case where the computer mainboard is in a power-on and power-off state, the configuration information is obtained from the basic management control unit, which indicates that each of the N central processing units connected to the programmable logic device is a master central processing unit or a slave central processing unit, and N is an integer greater than or equal to 2. Each central processing unit is set to a master central processing unit or a slave central processing unit according to the configuration information, which solves the problem that the multi-path mainboard and the redundant single-path mainboard cannot be automatically switched in the related art, and improves the reliability of the server and the flexibility of the business.

[0101] The execution subject of the above steps can be a server, a terminal, and the like, but is not limited thereto.

[0102] In some embodiments, after the computer mainboard is set to the multi-mainboard mode or the redundant single-mainboard mode according to the configuration information, the method further comprises: receiving a reset signal from a reset pin of the master central processor in the case that the computer mainboard is set to the multi-mainboard mode; performing a reset operation on the expansion card device connected to the master central processor and the slave central processor respectively according to the reset signal; and receiving a reset signal from the N master central processors respectively in the case that the computer mainboard is set to the redundant single-mainboard mode, and performing a reset on the expansion card device connected to the corresponding master central processor according to the reset signal.

[0103] After the computer mainboard is configured to the multi-mainboard mode, the computer mainboard is started, and the CPU on the mainboard is in the power-on working state. At this time, each CPU on the mainboard knows its own configuration as the master CPU or the slave CPU. At this time, the master CPU sends a reset signal to the CPLD, so that the CPLD performs a global reset of the server according to the reset signal, and performs a reset operation on the first expansion card device connected to the master CPU and the slave CPU.

[0104] In the embodiment, a method for starting a central processor is provided. FIG. 8 is a flowchart of a method for starting a central processor according to an embodiment of the present application. As shown in FIG. 8, the method is applied to the master central processor in the computer mainboard, and the optional flowchart comprises the following steps:

[0105] In step S802, when the computer mainboard is started, the master central processor reads the starting software from the starting code storage area connected thereto, so as to start the master central processor through the starting software. The working mode of the computer mainboard comprises a multi-mainboard mode and a redundant single-mainboard mode. In the multi-mainboard mode, the N central processors comprise one master central processor and N-1 slave central processors. In the redundant single-mainboard mode, the N central processors are configured as N master central processors.

[0106] In step S804, in the case that the computer mainboard is set to the multi-mainboard mode, the master central processor loads the starting software from the starting code storage area and sends the starting software to the N-1 slave central processors, so that the N-1 slave central processors share the starting software loaded by the master central processor.

[0107] In step S806, in the case that the computer mainboard is set to the redundant single-mainboard mode, the N master central processors load the starting software from the respective starting code storage areas.

[0108] The startup code storage area can be a startup software storage area, and the startup software can be a startup code BIOS. Before startup, the startup code BIOS can access the BMC or access a special register in the CPLD. When a multi-way motherboard mode is read, the master-slave state of each CPU is configured, and the high-speed channel between the CPUs is enabled to an enabled state by the master CPU to perform a startup process. When the computer motherboard is started, the master CPU loads the startup code BIOS from the startup code storage area and sends it to each slave CPU to complete the startup process.

[0109] The execution subject of the steps can be a server, a terminal, and the like, but is not limited thereto.

[0110] In some embodiments, after the master central processing unit is started by the startup software, the method further includes: in the case where the computer motherboard is set to a multi-way motherboard mode, the master central processing unit sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the master central processing unit and the expansion card device connected to the slave central processing unit; and in the case where the computer motherboard is set to a redundant single-way motherboard mode, the N central processing units respectively send reset signals to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the corresponding master central processing unit.

[0111] In the embodiment, a method for starting a central processing unit is provided, and Fig. 9 is a flowchart II of the method for starting a central processing unit according to the embodiment of the application. As shown in Fig. 9, the method is applied to a slave central processing unit in the computer motherboard, and the optional flowchart includes the following steps:

[0112] In the case where the computer motherboard is set to a multi-way motherboard mode, the slave central processing unit acquires startup software from the central processing unit connected thereto through the high-speed channel, and the slave central processing unit performs a startup operation through the startup software. In the multi-way motherboard mode, the N central processing units in the computer motherboard include one master central processing unit and N-1 slave central processing units. The master central processing unit loads startup software from the startup code storage area, and the N-1 slave central processing units share the startup software loaded by the master central processing unit. N is an integer greater than or equal to 2.

[0113] The execution subject of the steps can be a server, a terminal, and the like, but is not limited thereto.

[0114] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software necessary general hardware platform, of course, can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application or the part that contributes to the related art can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM (Read-Only Memory), a RAM (Random Access Memory), a magnetic disk, or an optical disc) and includes a plurality of instructions for causing an end device (which can be a mobile phone, a computer, a server, or a network device) to execute the method of each embodiment of the present application.

[0115] In the embodiments, an apparatus is also provided, which is configured to implement the above embodiments and optional implementation manners, and will not be described herein. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware or a combination of software and hardware is also possible and contemplated.

[0116] FIG. 10 is a structural block diagram of a programmable logic device according to an embodiment of the present application. As shown in FIG. 10, the apparatus includes a first obtaining module 1002 configured to obtain configuration information from a basic management control unit when a computer mainboard is in a power-on and power-off state; and a setting module 1004 configured to set the computer mainboard to a multi-mainboard mode or a redundant single-mainboard mode according to the configuration information, wherein in the multi-mainboard mode, N central processing units include one master central processing unit and N-1 slave central processing units, the master central processing unit loads startup software from a startup code storage area, and the N-1 slave central processing units share the startup software loaded by the master central processing unit; and in the redundant single-mainboard mode, the N central processing units are configured as N master central processing units, and each of the N master central processing units loads startup software from a respective startup code storage area, wherein N is an integer greater than or equal to 2.

[0117] In one example embodiment, the apparatus is further configured to, when the computer mainboard is set to the multi-mainboard mode, set a level state of a master-slave pin of the master central processing unit indicated in the configuration information to a high level; set a level state of a master-slave pin of the slave central processing unit indicated in the configuration information to a low level; and when the computer mainboard is set to the redundant single-mainboard mode, set a level state of a master-slave pin of each of the N central processing units to a high level.

[0118] In one example embodiment, the apparatus is further configured to receive a reset signal from a reset pin of the master central processor in the case that the computer motherboard is set to the multi-path motherboard mode; perform a reset operation on the expansion card device connected to the master central processor and the slave central processor according to the reset signal; and receive a reset signal from each of the N master central processors in the case that the computer motherboard is set to the redundant single-path motherboard mode, and perform a reset operation on the expansion card device connected to the corresponding master central processor according to the reset signal.

[0119] Fig. 11 is a structural block diagram of a master central processor according to an embodiment of the present application. As shown in Fig. 11, the apparatus comprises: a first reading module 1102 configured to read boot software from a boot code storage area connected to the master central processor to start the master central processor by the boot software when the computer motherboard is powered on, wherein the working mode of the computer motherboard comprises a multi-path motherboard mode and a redundant single-path motherboard mode, in the multi-path motherboard mode, the N central processors comprise one master central processor and N-1 slave central processors, and in the redundant single-path motherboard mode, the N central processors are configured as N master central processors; a first loading module 1104 configured to load the boot software from the boot code storage area and send the boot software to the N-1 slave central processors to make the N-1 slave central processors share the boot software loaded by the master central processor in the case that the computer motherboard is set to the multi-path motherboard mode; and a second loading module 1106 configured to load the boot software from the respective boot code storage area in the case that the computer motherboard is set to the redundant single-path motherboard mode.

[0120] In one example embodiment, the apparatus is further configured to send a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the master central processor and the expansion card device connected to the slave central processor in the case that the computer motherboard is set to the multi-path motherboard mode; and send a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the corresponding master central processor in the case that the computer motherboard is set to the redundant single-path motherboard mode.

[0121] Fig. 12 is a structural block diagram of a slave central processor according to an embodiment of the present application. As shown in Fig. 12, the device comprises a second obtaining module 1202 configured to, in a case where a computer mainboard is set to a multi-path mainboard mode, obtain, from a central processor connected thereto, start software through a high-speed channel, and perform a start operation through the start software, wherein in the multi-path mainboard mode, N central processors in the computer mainboard comprise one master central processor and N-1 slave central processors, the master central processor loads start software from a start code storage area, and the N-1 slave central processors share the start software loaded by the master central processor, and N is an integer greater than or equal to 2.

[0122] It should be noted that each of the above modules can be implemented by software or hardware, and for the latter, the following implementation manners can be used, but are not limited thereto: all of the above modules are located in the same processor; or the above modules are located in different processors in any combination.

[0123] Embodiments of the present application further provide a computer readable storage medium, which can be a non-volatile readable storage medium, and the computer readable storage medium stores a computer program. The computer program is configured to execute the steps in any of the above method embodiments when running.

[0124] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic or optical disk, and various media that can store computer programs.

[0125] Embodiments of the present application further provide an electronic device comprising a memory and a processor. The memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the above method embodiments.

[0126] In an example embodiment, the above electronic device can further comprise a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0127] Embodiments of the present application further provide a computer program product comprising a computer program. The computer program is executed by a processor to implement the steps in any of the above method embodiments.

[0128] The optional examples in the present embodiment can refer to the examples described in the above embodiments and exemplary embodiments, which will not be repeated here.

[0129] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be centralized on a single computing device or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be respectively manufactured into individual integrated circuit modules, or multiple modules or steps among them can be manufactured into a single integrated circuit module to realize. Thus, the present application is not limited to any specific combination of hardware and software.

[0130] The above is only optional embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A computer motherboard, characterized by, A programmable logic device, N central processing units, the N being an integer greater than or equal to 2, comprising: The programmable logic device is connected to the N central processing units and is configured to send configuration information to each of the central processing units to set the computer mainboard to a multi-mainboard mode or a redundant single-mainboard mode; in the multi-mainboard mode, the N central processing units include one master central processing unit and N-1 slave central processing units, the master central processing unit loads boot software from a boot code storage area, and the N-1 slave central processing units share the boot software loaded by the master central processing unit; in the redundant single-mainboard mode, the N central processing units are configured as N master central processing units, and each of the N master central processing units loads boot software from a respective boot code storage area.

2. The computer motherboard of claim 1, wherein, Comprising: The N central processing units are connected through high-speed channels; In the multi-mainboard mode, the high-speed channels between the master central processing unit and the slave central processing units are in an enabled state, the high-speed channels between the slave central processing units are in the enabled state, or the high-speed channels between the slave central processing units are configured to be in the enabled state or a closed state based on the configuration information; in the redundant single-mainboard mode, the high-speed channels between the master central processing units are in a closed state.

3. The computer motherboard of claim 1, wherein, The computer mainboard further comprises: A basic management control unit connected to the programmable logic device and a network port and configured to obtain configuration information through the network port when the computer mainboard is in a power-on and power-off state, and send the configuration information to the programmable logic device.

4. The computer motherboard of any of claims 1 to 3, wherein, Each of the N central processing units is connected to a boot code storage area for storing boot software, wherein, When the computer mainboard is powered on, the programmable logic device controls the N central processing units to be powered on; In the case that a first central processing unit of the N central processing units is the master central processing unit, the first central processing unit reads first boot software from a first boot code storage area connected to the first central processing unit to start the first central processing unit through the first boot software, wherein the first central processing unit is any one of the N central processing units.

5. The computer motherboard of claim 4, wherein, In the multi-mainboard mode, the N central processing units include one master central processing unit and N-1 slave central processing units, the master central processing unit loads boot software from a boot code storage area, and the N-1 slave central processing units share the boot software loaded by the master central processing unit further comprising: The slave central processing units of the N central processing units load the first boot software through the high-speed channels between the central processing units connected thereto to start the slave central processing units through the first boot software; Wherein, a second central processing unit adjacent to the first central processing unit is the slave central processing unit, and the second central processing unit loads the first boot software through the high-speed channel to start the second central processing unit through the first boot software; In the case that a third central processor connected adjacent to the second central processor is the slave central processor, and a high-speed channel between the second central processor and the third central processor is the enable state, the third central processor loads the first start software through the high-speed channel between the second central processor to start the third central processor through the first start software.

6. The computer motherboard of claim 4, wherein, In the redundant single-mainboard mode, the N central processors are configured as N main central processors, and the N main central processors load start software from respective start code storage areas, comprising: A fourth central processor connected to the first central processor is the main central processor, and the fourth central processor reads fourth start software from a fourth start code storage area connected to the fourth central processor to start the fourth central processor through the fourth start software.

7. The computer motherboard of claim 1, wherein, Each of the N central processors is connected to an expansion card device, wherein, In the case that the computer mainboard is set to the multi-mainboard mode, the main central processor sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the main central processor and the expansion card device connected to the slave central processor according to the reset signal.

8. The computer motherboard of claim 1, wherein, Each of the N central processors is connected to an expansion card device, wherein, In the case that the computer mainboard is set to the redundant single-mainboard mode, the N main central processors respectively send a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the corresponding main central processor according to the reset signal.

9. The computer motherboard of claim 1, wherein, Each of the N central processors is also connected to a system disk, wherein, In the case that the computer mainboard is set to the multi-mainboard mode, when the computer mainboard is powered on, the main central processor loads an operating system from the system disk connected thereto; and the slave central processors of the N central processors load the operating system through the high-speed channel between the central processors connected thereto; In the case that a first central processor of the N central processors is the main central processor, the first central processor loads a first operating system from a first system disk connected to the first central processor, and the first central processor is any central processor of the N central processors; A second central processor connected to the first central processor is the slave central processor, and the second central processor loads the first operating system through the high-speed channel between the first central processor; A third central processor connected adjacent to the second central processor is the slave central processor, and the third central processor loads the first operating system through the high-speed channel between the second central processor.

10. The computer motherboard of claim 9, wherein, In the case that the computer mainboard is set to the redundant single-mainboard mode, further comprising: A fourth central processing unit connected with the first central processing unit is the master central processing unit, and the fourth central processing unit loads a fourth operating system from a fourth system disk connected with the fourth central processing unit.

11. The computer motherboard of claim 1, wherein, Each of the N central processing units is connected with a memory, wherein, In a case where the computer mainboard is set as the multi-path mainboard mode, the master central processing unit reads data from a memory connected with the master central processing unit, and the slave central processing units read the data through high-speed channels between the central processing units connected with the slave central processing units. In a case where a first central processing unit of the N central processing units is the master central processing unit, the first central processing unit reads first data from a first memory connected with the first central processing unit, and the first central processing unit is any one of the N central processing units. A second central processing unit connected with the first central processing unit is the slave central processing unit, and the second central processing unit loads the first data through a high-speed channel between the first central processing unit and the second central processing unit. A third central processing unit connected with the second central processing unit is the slave central processing unit, and the third central processing unit loads the first data through a high-speed channel between the second central processing unit and the third central processing unit.

12. The computer motherboard of claim 11, wherein, In a case where the computer mainboard is set as the redundant single-path mainboard mode, the computer mainboard further comprises: A fourth central processing unit connected with the first central processing unit is the master central processing unit, and the fourth central processing unit reads fourth data from a fourth memory connected with the fourth central processing unit.

13. The computer motherboard of claim 1, wherein, The programmable logic device is connected with the N central processing units, and comprises: In a case where the configuration information indicates that a first central processing unit is the master central processing unit, the programmable logic device is set to control a level state of a first master-slave pin of the first central processing unit as a high level; In a case where the configuration information indicates that a second central processing unit is the slave central processing unit, the programmable logic device is set to control a level state of a second master-slave pin of the second central processing unit as a low level.

14. The computer motherboard of claim 1, wherein, The programmable logic device is connected with the N central processing units, and further comprises: The programmable logic device is connected with a reset pin on each of the central processing units to receive a reset signal sent by each of the central processing units through the reset pin.

15. The computer motherboard of claim 1, wherein, Further comprising: The N central processing units are sequentially connected, or the N central processing units are connected in a ring shape.

16. A method of setting up a central processing unit, characterized by The programmable logic device applied to the computer mainboard in any one of the above 1 to 15, comprises: In a case where the computer mainboard is in a power-on and power-off state, configuration information is acquired from a basic management control unit; In a case where the computer mainboard is in a power-on and power-off state, configuration information is acquired from a basic management control unit; setting the computer mainboard to a multi-mainboard mode or a redundant single-mainboard mode according to the configuration information, wherein in the multi-mainboard mode, N central processing units include one master central processing unit and N-1 slave central processing units, the master central processing unit loads start software from a start code storage area, and the N-1 slave central processing units share the start software loaded by the master central processing unit; in the redundant single-mainboard mode, the N central processing units are configured as N master central processing units, and each of the N master central processing units loads start software from a respective start code storage area, wherein the N is an integer greater than or equal to 2.

17. The method of claim 16, wherein, setting the computer mainboard to a multi-mainboard mode or a redundant single-mainboard mode according to the configuration information, comprising: in a case where the computer mainboard is set to the multi-mainboard mode, setting a level state of a master-slave pin of a master central processing unit indicated in the configuration information to a high level, and setting a level state of a master-slave pin of a slave central processing unit indicated in the configuration information to a low level; in a case where the computer mainboard is set to the redundant single-mainboard mode, setting a level state of a master-slave pin of each of the N central processing units to a high level.

18. The method of claim 16, wherein, after setting the computer mainboard to the multi-mainboard mode or the redundant single-mainboard mode according to the configuration information, the method further comprises: in a case where the computer mainboard is set to the multi-mainboard mode, receiving a reset signal from a reset pin of the master central processing unit, and performing a reset operation on an expansion card device connected to the master central processing unit and the slave central processing unit according to the reset signal; in a case where the computer mainboard is set to the redundant single-mainboard mode, receiving a reset signal from each of the N master central processing units, and performing a reset operation on an expansion card device connected to the corresponding master central processing unit according to the reset signal.

19. A method of starting a central processing unit, characterized by, a master central processing unit applied to the computer mainboard in any one of the preceding 1 to 15, comprising: when the computer mainboard is started, the master central processing unit reads start software from a start code storage area connected thereto to start the master central processing unit through the start software, wherein a working mode of the computer mainboard includes a multi-mainboard mode and a redundant single-mainboard mode, in the multi-mainboard mode, N central processing units include one master central processing unit and N-1 slave central processing units, in the redundant single-mainboard mode, the N central processing units are configured as N master central processing units; in a case where the computer mainboard is set to the multi-mainboard mode, the master central processing unit loads start software from a start code storage area and sends the start software to N-1 slave central processing units, so that the N-1 slave central processing units share the start software loaded by the master central processing unit; in a case where the computer mainboard is set to the redundant single-mainboard mode, each of the N master central processing units loads start software from a respective start code storage area.

20. The method of claim 19, wherein, after starting the master central processing unit through the start software, the method further comprises: In the case that the computer mainboard is set to the multi-mainboard mode, the main central processor sends a reset signal to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the main central processor and the expansion card device connected to the slave central processor. In the case that the computer mainboard is set to the redundant single-mainboard mode, the N central processors respectively send reset signals to the programmable logic device to instruct the programmable logic device to reset the expansion card device connected to the corresponding central processor.

21. A method of starting a central processing unit, characterized by, The slave central processor applied to the computer mainboard in any one of the preceding claims 1 to 15, comprising: In the case that the computer mainboard is set to the multi-mainboard mode, the slave central processor acquires the starting software from the central processor connected thereto through the high-speed channel, and the slave central processor performs starting operation through the starting software, wherein in the multi-mainboard mode, the N central processors in the computer mainboard include one central processor and N-1 slave central processors, the main central processor loads the starting software from the starting code storage area, and the N-1 slave central processors share the starting software loaded by the main central processor, and the N is an integer greater than or equal to 2.

22. A programmable logic device, comprising: The method applied to any one of the preceding claims 16 to 18, comprising: The first acquisition module is configured to acquire the configuration information from the basic management control unit in the case that the computer mainboard is in the power-on and shutdown state; The setting module is configured to set the computer mainboard to the multi-mainboard mode or the redundant single-mainboard mode according to the configuration information, wherein in the multi-mainboard mode, the N central processors include one main central processor and N-1 slave central processors, the main central processor loads the starting software from the starting code storage area, and the N-1 slave central processors share the starting software loaded by the main central processor; in the redundant single-mainboard mode, the N central processors are configured as N main central processors, and the N main central processors load the starting software from the respective starting code storage areas, wherein the N is an integer greater than or equal to 2.

23. A host central processor, comprising: The method applied to any one of the preceding claims 19 to 20, comprising: The first reading module is configured to read the starting software from the starting code storage area connected to the main central processor to start the main central processor through the starting software when the computer mainboard is powered on, wherein the working mode of the computer mainboard includes the multi-mainboard mode and the redundant single-mainboard mode, in the multi-mainboard mode, the N central processors include one main central processor and N-1 slave central processors, and in the redundant single-mainboard mode, the N central processors are configured as N main central processors. The first loading module is configured to load the starting software from the starting code storage area and send the starting software to N-1 slave central processing units to make the N-1 slave central processing units share the starting software loaded by the master central processing unit when the computer mainboard is set to the multi-mainboard mode. The second loading module is configured to load the starting software from the respective starting code storage area when the computer mainboard is set to the redundant single-mainboard mode.

24. A central processing unit from which, The method of claim 21, comprising: The second obtaining module is configured to obtain the starting software from the central processing unit connected thereto through the high-speed channel when the computer mainboard is set to the multi-mainboard mode, and the slave central processing unit performs the starting operation through the starting software, wherein, in the multi-mainboard mode, N central processing units in the computer mainboard include one master central processing unit and N-1 slave central processing units, the master central processing unit loads the starting software from the starting code storage area, and the N-1 slave central processing units share the starting software loaded by the master central processing unit, and N is an integer greater than or equal to 2.

25. A computer non-volatile readable storage medium, comprising: The computer non-volatile readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of the method of any one of claims 16-18 or 19-20 or 21.

26. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor executes the computer program to implement the steps of the method of any one of claims 16-18 or 19-20 or 21.

27. A computer program product, comprising a computer program, wherein: The computer program is executed by a processor to implement the steps of the method of any one of claims 16-18 or 19-20 or 21.

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