Signal processing device and communication system

Abstract

The present application relates to a signal processing device, comprising: a first switch, which receives a first analog signal; a first analog-to-digital converter, which is coupled to the first switch, and converts the first analog signal into a first digital signal; a core processor, which is coupled to the first analog-to-digital converter, processes the first digital signal and outputs a second digital signal comprising at least digital pre-distortion information; a digital-to-analog converter, which is coupled to the core processor, and converts the second digital signal into a second analog signal; a second switch, which is coupled to a first digital-to-analog converter, and outputs the second analog signal; and a second analog-to-digital converter, which receives an output signal from a power amplifier external to the signal processing device, converts the output signal into a third digital signal, and provides the third digital signal to the core processor, wherein the core processor obtains, on the basis of the first digital signal and the third digital signal, the second digital signal carrying digital pre-distortion information, and the second switch is further coupled to the first switch to jointly form an uplink channel. The signal processing device further comprises a downlink channel.

Description

A signal processing apparatus and a communication system TECHNICAL FIELD

[0001] The present application relates to the field of communications, and in particular to a signal processing apparatus and a communication system. BACKGROUND

[0002] The development of communication systems has been limited by the materials and process level of components, especially radio frequency components, and faces the contradiction between the transmission bandwidth, transmission power, signal linearity and system efficiency. Increasing the transmission power may cause signal distortion or poor linearity, and pursuing signal linearity without distortion may reduce system efficiency and increase heat dissipation burden.

[0003] Fig. 1 and Fig. 2 are schematic diagrams of the transmission part of the existing communication system. A general communication system includes both transmission and reception parts, and each part may have multiple paths working simultaneously or non-simultaneously.

[0004] A radio frequency power amplifier (RF power amplifier or PA) is used to amplify a small radio frequency signal to increase the transmission distance. Limited by the material, the design of the RF power amplifier needs to make a trade-off among important indicators such as output power, linearity, efficiency and output bandwidth.

[0005] In order to reduce or eliminate the non-linear problems caused by the power amplifier, the current RF enhancement technology is mainly concentrated in the digital intermediate frequency position or the baseband chip. However, this scheme has a high threshold and a fixed system structure, which limits the application of RF enhancement function in the terminal field and is only used in a small range of high-power equipment.

[0006] The system in Fig. 1 needs an FPGA in the baseband to support the implementation of digital signal processing function to achieve the purpose of optimizing the RF performance, such as reducing or eliminating the non-linear effects caused by the power amplifier. The digital signal processing module in the two schemes is located in the baseband chip and is usually implemented by FPGA, and the area of FPGA is large and the production cost is high, so the system performance and cost will be affected by the performance of FPGA and RF chip. The system shown in Fig. 2 needs the cooperation of the FPGA in the baseband chip and the digital signal processing module 210 in the high-integration RF chip 200 to achieve the purpose of optimizing the RF performance. The performance of the digital signal processing module 210 in the high-integration RF chip 200 is limited and the adaptability is not strong, and it can only be used in limited application scenarios. The RF chip 200 needs to cooperate with the FPGA and needs to be connected by using a high-speed digital interface, and the high cost of this interface will increase the overall product cost. SUMMARY

[0007] Aiming at the technical problems in the prior art, the application provides a signal processing device, which comprises a first switch configured to receive a first analog signal; a first analog-digital converter coupled to the first switch and configured to convert the first analog signal into a first digital signal; a core processor coupled to the first analog-digital converter and configured to process the first digital signal and output a second digital signal comprising at least digital pre-distortion information; a digital-analog converter coupled to the core processor and configured to convert the second digital signal into a second analog signal; a second switch coupled to the first digital-analog converter and configured to output the second analog signal; the signal processing device further comprises a second analog-digital converter configured to receive an output signal of a power amplifier outside the signal processing device, convert the output signal of the power amplifier into a third digital signal and provide the third digital signal to the core processor; wherein the core processor is configured to obtain the second digital signal with the digital pre-distortion information based on the first digital signal and the third digital signal; wherein the second switch is further coupled to the first switch to form an uplink channel; and the signal processing device further comprises a downlink channel configured to send the first analog signal received by the first switch to the second switch and output the first analog signal after the first analog signal sequentially passes through the first analog-digital converter, the core processor and the digital-analog converter and is processed correspondingly.

[0008] In particular, the device is a chip manufactured by using integrated circuit technology.

[0009] The scheme provided by the application can compensate or calibrate the non-linear distortion generated by the power amplifier without changing the existing baseband chip or radio frequency chip, thereby reducing the cost of the device and making the device compatible with various communication devices or systems.

[0010] The application also relates to a communication system, comprising: a baseband module, a radio frequency module, and a radio frequency front-end module; and an analog interface signal processing module coupled between the baseband module and the radio frequency module; the analog interface signal processing module is configured to receive at least a first analog signal from the baseband module; wherein the analog interface signal processing module comprises a signal processing device configured to perform a digital pre-distortion operation based on at least the first analog signal, so as to obtain a second analog signal with digital pre-distortion information; wherein the signal processing device comprises: a first switch configured to receive the first analog signal; a first analog-to-digital converter coupled to the first switch and configured to convert the first analog signal into a first digital signal; a core processor coupled to the first analog-to-digital converter and configured to process the first digital signal and output a second digital signal with at least digital pre-distortion information; a digital-to-analog converter coupled to the core processor and configured to convert the second digital signal into a second analog signal; and a second switch coupled to the digital-to-analog converter and configured to output the second analog signal; wherein the second switch is also coupled to the first switch to form an uplink channel.

[0011] In particular, the system, wherein the analog interface signal processing module further comprises a feedback channel configured to receive radio frequency feedback signals from the radio frequency front-end module, convert the radio frequency feedback signals into third analog signals and provide the third analog signals to the signal processing device; wherein the feedback channel comprises: a feedback selection switch coupled to the radio frequency front-end module and configured to select and output multiple radio frequency feedback signals; a down-conversion subunit coupled between the feedback selection switch and the signal processing device and configured to perform a down-conversion operation on the radio frequency feedback signals and provide third analog signals generated after the down-conversion operation to the signal processing device; and a high-frequency clock subunit coupled to the down-conversion subunit and configured to generate a local oscillator signal required by the down-conversion subunit.

[0012] In particular, the system, wherein the signal processing device further comprises a second analog-to-digital converter coupled to the core processor and configured to receive the third analog signals and provide the third analog signals to the core processor.

[0013] In particular, the system, wherein the signal processing device obtains the second digital signal with digital pre-distortion information based on the first analog signal and the third analog signal.

[0014] In particular, the system, wherein the analog interface signal processing module is further configured to receive multiple baseband analog signals and radio frequency feedback signals.

[0015] In particular, the system, wherein the system is a WiFi router, and wherein the analog interface signal processing module further comprises a plurality of transmit-receive switch, configured to select whether to pass the signal processing device in the analog interface signal processing device in the transmit or receive mode.

[0016] The communication system provided in the application can weaken or eliminate the non-linear problem of the signal generated by the power amplifier, and can further improve the power, efficiency and bandwidth of the power amplifier under the premise of the same signal quality, and reduce the cost of the device.

[0017] The application also relates to a communication system, comprising: a baseband module, a radio frequency module, and a radio frequency front-end module; and a radio frequency interface signal processing module coupled between the radio frequency module and the radio frequency front-end module; the radio frequency interface signal processing module is configured to receive at least a first radio frequency signal from the radio frequency module; wherein the radio frequency interface signal processing module comprises a signal processing device configured to perform a digital pre-distortion operation based on at least the first radio frequency signal, thereby obtaining a second radio frequency signal with digital pre-distortion information; wherein the signal processing device comprises: a first switch configured to receive a first analog signal; a first analog-to-digital converter configured to convert the first analog signal into a first digital signal; a core processor coupled to the first analog-to-digital converter and configured to process the first digital signal and output a second digital signal with at least digital pre-distortion information; a digital-to-analog converter coupled to the core processor and configured to convert the second digital signal into a second analog signal; and a second switch coupled to the digital-to-analog converter and configured to output the second analog signal; wherein the second switch is also coupled to the first switch to form an uplink channel.

[0018] In particular, the system, wherein the radio frequency interface signal processing module comprises: a down-conversion unit configured to receive the first radio frequency signal and perform a down-conversion operation to obtain the first analog signal; and an up-conversion unit configured to perform an up-conversion operation on the second analog signal generated by the signal processing device to obtain a second radio frequency signal; the signal processing device is coupled between the up-conversion unit and the down-conversion unit, and is configured to receive the first analog signal and convert it into a first digital signal, and perform a digital pre-distortion operation on the first digital signal to obtain a second digital signal and convert it into the second analog signal.

[0019] In particular, the system, the radio frequency interface signal processing module further comprises a feedback channel configured to receive a radio frequency feedback signal from the radio frequency front end module, convert the radio frequency feedback signal into a third analog signal and provide the third analog signal to the signal processing device; the feedback channel comprises: a feedback selection switch coupled to the radio frequency front end module and configured to select and output multiple radio frequency feedback signals; a frequency down-conversion subunit configured to perform frequency down-conversion operation on the radio frequency feedback signal and provide a third analog signal generated after frequency conversion to the signal processing device; and a high-frequency clock subunit configured to generate a local oscillator signal required by the frequency down-conversion subunit.

[0020] In particular, the system, wherein the radio frequency interface signal processing module is further configured to receive multiple radio frequency analog signals and a radio frequency feedback signal.

[0021] In particular, the system, wherein the signal processing device further comprises a second analog-to-digital converter coupled to the core processor and configured to receive the third analog signal, convert the third analog signal into a third digital signal and provide the third digital signal to the core processor.

[0022] In particular, the system, wherein the signal processing device obtains a second radio frequency signal with pre-distortion information based on the first radio frequency signal and the radio frequency feedback signal.

[0023] In particular, the system, wherein the system is a WiFi router, and the radio frequency interface signal processing module further comprises a clock selection switch configured to select local oscillator signals generated by multiple high-frequency clock subunits.

[0024] The communication system provided in the present application reduces the design threshold of using the pre-distortion method by the system, increases the universality of the pre-distortion method, can weaken or eliminate the non-linear problem of the signal generated by the power amplifier, and further improves the power, efficiency and bandwidth that can be realized by the power amplifier under the same signal quality. BRIEF DESCRIPTION OF DRAWINGS

[0025] In the following, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, in which:

[0026] FIGS. 1-2 are schematic diagrams of a transmitting part of an existing communication system;

[0027] FIG. 3 shows a module schematic diagram of a signal processing device according to an embodiment of the present application;

[0028] FIG. 4 shows a module schematic diagram of an analog interface signal processing module according to an embodiment of the present application;

[0029] FIG. 5 shows a partial module schematic diagram of a communication system according to an embodiment of the present application;

[0030] Figure 6 shows a schematic diagram of a radio frequency interface signal processing module according to an embodiment of the application;

[0031] Figure 7 shows a schematic diagram of part of a communication system according to another embodiment of the application

[0032] Figure 8 shows a schematic diagram of part of a prior art base station;

[0033] Figure 9 shows a schematic diagram of part of another prior art base station;

[0034] Figure 10 shows a schematic diagram of part of a base station according to an embodiment of the application;

[0035] Figure 11 shows a schematic diagram of part of a prior art WiFi router;

[0036] Figure 12 shows a schematic diagram of part of a WiFi router according to an embodiment of the application;

[0037] Figure 13 shows a schematic diagram of part of a WiFi router according to another embodiment of the application;

[0038] Figure 14 shows a schematic diagram of part of a WiFi router according to an embodiment of the application. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0040] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this description. In the drawings, similar symbols

[0041] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art(s) can not be discussed in any detail in order to avoid obscuring the present application. For the avoidance of doubt, the number of lines of communication between elements in the accompanying drawings is indicative only and not comprehensive of all possibilities as to communication between those elements. Further, the number of lines of communication between two elements is indicative of at least the number of signals involved in the communication or at least the number of outputs involved in the communication between those two elements, and is not limiting as to the signals that can be communicated between those two elements as depicted in the drawings.

[0042] In the prior art, compensation for digital signals is performed by the digital signal processing module 120 in FIG. 1 or the digital signal processing module 210 in FIG. 2, in an attempt to solve the problem of signal linearity. In addition, peripheral devices such as ADCs and DACs and corresponding clock circuits are required, making the system design face challenges in terms of interface, electrical characteristic matching, etc., and further increasing the cost, area, and power consumption of the system. In addition, the signal processing algorithm is not strongly targeted, and cannot process signals according to the use scenario and signal quality, etc. At present, there are some applications or devices that do not have such a digital signal processing module. Or, based on cost considerations, for some device manufacturers, the current expectation or trend is to provide devices that do not include a digital processing module or only include a digital processing module with basic functions. Such a status quo leads to a communication system that either reduces power amplifier efficiency or uses high cost to achieve signal linearity performance. But more expectations are to be able to achieve the improvement of linearity with lower cost and better design scheme while achieving optimal efficiency.

[0043] The present application provides a signal processing device to overcome the performance and linearity problems caused by power amplifiers in the form of independent functional modules, with higher processing performance and adaptability, thereby reducing the application threshold of radio frequency enhancement technology and reducing the cost of the system. In addition, the signal processing algorithm carried in the signal processing device includes customized pre-distortion processing, which can more effectively improve the linearity of radio frequency signals. Under the same signal quality, the power, efficiency, and bandwidth that the power amplifier can achieve are further improved.

[0044] FIG. 3 shows a module schematic diagram of a signal processing device according to an embodiment of the present application. In the present application, “analog” refers to a relatively low-frequency analog signal with a center frequency near zero frequency; “radio frequency” refers to a relatively high-frequency analog signal with a center frequency outside zero frequency, such as 900 MHz.

[0045] As shown in the figure, the signal processing device 300 can include a switch 30, an analog-to-digital converter 40 coupled to the switch 30, an output of the analog-to-digital converter 40 coupled to an input of a core processor 50, an output of the core processor 50 coupled to an input of a digital-to-analog converter 40', an output of the digital-to-analog converter 40' coupled to a switch 30', and a master control 60 coupled or electrically connected to all other units. The switches 30 and 30' can include analog switches with high bandwidth and high linearity characteristics, capable of processing high-frequency signals and maintaining the integrity of the signals. In some embodiments, the analog switches include cascaded transistors, and the linearity of the analog switches can be adjusted by adjusting the size of the cascaded transistors.

[0046] According to an embodiment, the signal processing device proposed in the present solution can be implemented in a general-purpose device or can be a chip manufactured using integrated circuit technology. In order to improve linearity, each component in the chip can provide more specialized characteristics, and has advantages in signal processing speed and efficiency, reduces power consumption and area of the signal processing module, and is more cost-effective.

[0047] Compared with a digital signal processing module implemented by a traditional FPGA, when the signal processing device is implemented in a chip, the signal transmission path is shorter, and needs to be optimized to match the performance of the internal circuit in terms of transmission and signal processing capability, so that it can quickly respond to changes in the input signal, and overcome the mutual interference between the internal elements of the signal processing device to reduce noise.

[0048] According to an embodiment, the switch 30 is configured to receive a baseband analog signal from a baseband.

[0049] According to an embodiment, one output of the switch 30' is configured to provide a processed high-speed analog signal to the outside of the signal processing device 300.

[0050] According to an embodiment, the switch 30' can be coupled to the switch 30 to form a transceiver mode shared by the analog interface.

[0051] According to other embodiments, in some application scenarios, the signal processing device 300 can also not include the switches 30 and 30'.

[0052] According to an embodiment, the master control 60 can be electrically connected to all other units and configure initialization parameters and startup procedures of other units, communicate with external control units such as MCUs, exchange commands and data, and also monitor the working state of the signal processing device 300 system, implement abnormal recovery processing and maintainable monitoring functions.

[0053] According to one embodiment, the switch 30 and the switch 30' can be used as a signal exchange intermediary inside and outside the signal processing device 300, which can support two working modes, mode A: switching channels according to the instruction of the master 60; mode B: switching channels according to the indication of the external pin. By controlling the signal to adapt the switching uplink and downlink circuit, the uplink and downlink signal selection of the time division duplex (TDD) scene can be supported, or it can be commonly used as the TX or RX interval, and used as a dedicated processing channel of the corresponding channel.

[0054] According to one embodiment, the signal processing device 300 can include uplink and downlink circuits / channels. When the signal processing device 300 is in a receiving mode (RX), the switch 30 and the switch 30' in the signal processing device are switched to an uplink mode, the switch 30 and the switch 30' are directly electrically connected, and are configured to receive and directly pass an analog signal, for example, from a radio frequency chip, without the need for processing by the core processor. In this case, the uplink circuit / channel can only include the switch 30 and the switch 30'. When the signal processing device 300 is in a transmitting mode (TX), the switch 30 and the switch 30' in the signal processing device are switched to a downlink mode, and the downlink circuit / channel includes the switch 30, the analog-to-digital converter 40, the core processor 50, the digital-to-analog converter 40', and the switch 30'.

[0055] In one embodiment of the present application, the signal processing device 300 can include N downlink channels, and the N channels share, for example, one core processor, where N is greater than or equal to 1.

[0056] According to one embodiment, the analog-to-digital converter 40 or the digital-to-analog converter 40' can respectively use a high-precision high-sampling-rate ADC or DAC module, which can support I_P / I_N / Q_P / Q_N; or I / Q single-ended; or a single-channel standard analog signal format. The analog-to-digital converter 40 is configured to convert the corresponding analog signal into a digital signal. The digital-to-analog converter 40' is configured to convert the digital signal processed by the core processor 50 into an analog signal. The addition of the analog-to-digital converter 40 or the digital-to-analog converter 40' increases the compatibility of the signal processing device 300.

[0057] According to one embodiment, in the analog-to-digital converter 40, the analog bandwidth of the ADC needs to be greater than the bandwidth of the baseband analog signal received by the switch 30, and the sampling rate is greater than twice the bandwidth of the baseband analog signal. For a high-rate communication system, the sampling rate of the ADC generally needs to be above 160 MHz. The accuracy of the ADC determines the upper limit of the signal-to-noise ratio SNR, which can vary depending on the system requirement. In addition, the sampling rate and resolution indicators need to be balanced with the system requirements.

[0058] According to one embodiment, the resolution requirement of the DAC in the digital-to-analog converter 40' is similar to the resolution requirement of the ADC in the analog-to-digital converter 40.

[0059] According to an embodiment, the analog-to-digital converter 40 is configured to convert the analog signal received by the switch 30 into a digital signal. The digital-to-analog converter 40' is configured to convert the digital signal processed by the core processor 50 into an analog signal.

[0060] According to an embodiment, the digital-to-analog converter 40' includes an out-of-band pre-distortion signal for canceling the out-of-band distortion of the radio frequency signal, and the actual bandwidth of the output signal of the signal processing device is greater than the bandwidth of the baseband analog signal. In the conventional technology, the actual bandwidth of the output signal of the data processing module is three times or more than the bandwidth of the baseband analog signal. The core processor 50 of the present application has the function of reducing the bandwidth of the conventional pre-distortion, so the output bandwidth of the DAC needs to be at least 1.2 times the bandwidth of the baseband analog signal. The sampling rate of the DAC needs to be at least two times or more than the output bandwidth of the DAC, i.e. 2.4 times the bandwidth of the baseband analog signal. The requirement of the resolution of the DAC in the digital-to-analog converter 40' is similar to the requirement of the resolution of the ADC in the analog-to-digital converter 40, and a balance needs to be made on the system. Too large resolution will increase the power consumption and area of the system, and too small resolution will affect the signal-to-noise ratio of the system.

[0061] Pure analog signal processing has the disadvantages of difficult to realize complex functions, not easy to program and adjust, low integration, difficult to high integration and miniaturization, etc. This is also the reason why there are few high-performance analog processing chips on the market. Through the digital conversion of the baseband analog signal, complex operations and other functions can be completed by the core processor 50, achieving the purpose of high-performance analog chips.

[0062] According to an embodiment, the signal processing device 300 can further include an analog-to-digital converter 40", which can also include a high-precision high-sampling-rate ADC, the input end of which is configured to receive the output signal of the power amplifier, and the output end of which is coupled with the input end of the core processor 50, thereby forming a feedback observation channel, which can collect observation point data of the target and observe external data in real time, so that the signal processing device 300 calculates the corresponding parameters. The feedback observation channel can greatly improve the tracking performance of the system, so that the signal processing device 300 can process external scenes such as rapid cooling, heating, impedance change, etc. According to an embodiment, the core processor 50 compares the output of the analog-to-digital converter 40" with the output of the analog-to-digital converter 40, and adjusts the signal with nonlinear information in real time according to the difference obtained after the comparison, so as to minimize the difference.

[0063] According to an embodiment, the requirements for the analog-to-digital converter 40" are similar to the requirements for the analog-to-digital converter 40.

[0064] According to an embodiment, the core processor 50 can have functions of quantization error correction (QEC), digital pre-distortion (PD), clipping processing (CFR), digital filtering (FIR), signal rate conversion (Resample), and DC offset correction, etc.

[0065] According to an embodiment, the core processor 50 can include a crest factor reduction function module, a DC compensation function module, an equalization function module, a frequency conversion quadrature compensation function module, and a digital pre-distortion function module.

[0066] According to an embodiment, the crest factor reduction function module is configured to perform clipping and peak suppression on an input signal. The input signal can be a digital signal from the analog-to-digital converter 40.

[0067] The clipping and peak suppression (CFR) technology is a method for reducing signal peaks to improve the efficiency of power amplifiers (PAs) and reduce signal distortion. By monitoring the amplitude of the input signal, the peak part exceeding the set threshold is detected; the peak part exceeding the threshold is clipped to limit its amplitude to the set maximum value; filtering or other techniques are used to restore the quality of the signal and reduce the negative effects of clipping.

[0068] According to an embodiment, the CFR function structure in the core processor 50 can perform the following operations:

[0069] According to an embodiment, the clipped signal y(t) can be represented as

[0070]

[0071] where x(t) is the input signal, |x(t)| is the amplitude of the input signal, A clip ​ is the clipping threshold. When the amplitude of the input signal is less than or equal to the clipping threshold, the output signal is . When the amplitude of the input signal is greater than the clipping threshold, the output signal is .

[0072] According to an embodiment, the DC compensation function module includes a receive DC compensation subunit, a transmit DC compensation subunit, and a feedback DC compensation subunit, which are respectively configured to compensate for the DC component in the input signal, the digital pre-distortion processing, and the feedback observation channel. The existence of DC signal affects the system EVM and the calibration stability of the digital pre-processing PD, increases power consumption, and even causes the RF power amplifier to burn out.

[0073] According to an embodiment, the equalization function module includes an equalization filter configured to perform a spectral equalization correction (EQ) function for compensating for frequency response related distortion and interference introduced in the channel, so as to recover the original signal. The equalization function module can include an input equalization subunit, a transmit equalization subunit, and a feedback equalization subunit, which are respectively configured to perform spectral flatness correction operations on the input signal, the distortion and interference introduced in the digital pre-distortion processing, and the feedback observation channel. The purpose of the equalization filter is to reverse the effects of the channel on the signal.

[0074] According to an embodiment, the frequency conversion quadrature compensation function module is configured to implement a mirror correction (QEC) function to compensate for IQ mirror problems caused by IQ signal link inconsistency. The frequency conversion quadrature compensation function module includes an input down-conversion quadrature compensation subunit, a transmit up-conversion quadrature compensation, and a feedback down-conversion quadrature compensation. The IQ mirror existing within the zero intermediate frequency signal bandwidth can greatly affect the EVM performance of the entire system. The mirror correction reduces the IQ mirror to below the system EVM index.

[0075] According to an embodiment, the mirror correction QEC function structure in the core processor 50 can be configured to perform the following operations:

[0076] Let the input signal be an intermediate frequency signal :

[0077] After passing through a non-ideal frequency converter, the component

[0078]

[0079] Such mirror components can be hidden in the main signal or symmetrical with the LO frequency point, affecting the spectrum or in-band signal quality of the air interface.

[0080] According to an embodiment, the frequency conversion quadrature compensation function module can collect the signal after frequency conversion through the feedback observation channel, so as to compensate for the component, and improve performance.

[0081] According to an embodiment, the digital pre-distortion function module in the core processor 50 is configured to implement a digital pre-distortion PD function.

[0082] According to an embodiment, the PD function structure in the core processor 50 can perform the following operations:

[0083] The nonlinearity of the power amplifier (PA) in the radio frequency signal processing system outside the signal processing device can cause distortion of the input signal after amplification, which is usually manifested as gain compression and phase distortion. Nonlinear distortion can be described by a nonlinear model, such as a polynomial model or a Volterra series.

[0084]

[0085] wherein represents an enhanced signal, is an input signal, k and l are memory depths, and LUT is a lookup table.

[0086] Digital predistortion (PD) is a function implemented in the digital domain, which functions to introduce distortion opposite to the nonlinear characteristics of a power amplifier. The output signal of a signal processing device processed by PD is just able to balance the distortion generated by the power amplifier after passing through the power amplifier, so as to enable the signal output by the radio frequency signal processing system to be restored to linearity.

[0087] According to one embodiment of the present application, by comparing the input signal with the output signal of the power amplifier, the signal processing device adjusts the received input signal in reverse until the output signal of the power amplifier is consistent with the input signal received by the signal processing device, thereby realizing digital predistortion.

[0088] According to one embodiment, the design method of digital predistortion is as follows:

[0089] Let be an input signal, be an output signal of a power amplifier, and n be a digital domain signal sample bit, then the difference signal is:

[0090]

[0091] The coefficient for generating a predistortion signal is calculated as , wherein is a multi-dimensional coefficient, and the specific dimension depends on the complexity of modeling. Assuming that the predistortion weighting coefficient vector of digital predistortion PD is Through feedback observation of a channel, the weighting coefficient can be given by data modeling and applied to the input signal to achieve a predistortion effect

[0092] wherein, is a predistortion coefficient, n = 0, 1, 2,..., N is an index of a time domain signal, N is the total length of an array, M is the order of the predistortion coefficient, is a Hilbert transform of is a transpose matrix of is a conjugate of , and y(n) is an output. ​​

[0093] For example, for one-dimensional coefficients , is the coefficient series group at sample n, with the size of 1 x M, where sample time , N is the total number of samples. At this time, the coefficient is:

[0094]

[0095] where is the cross-correlation of and is the autocorrelation of , is the iteration step size.

[0096] The output signal with pre-distortion information is:

[0097]

[0098] where is the matrix model of pre-distortion calculation.

[0099] After adopting the scheme of the present application, the key linearity indicators, the leakage suppression ratio (ACLR) can be reduced by 40 dB at most, and the vector amplitude error (EVM) can be reduced by more than 10 dB.

[0100] According to an embodiment, the FIR function structure in the core processor 50 can provide LPF filtering with a transition band <10 Mhz suppression degree> 40 dbc, which is more than 10 times better than the performance of a traditional analog LPF.

[0101] In some embodiments, the output of the analog-to-digital conversion module 40 sequentially flows through the peak clipping subunit, the receive DC compensation subunit, the input equalization subunit, and the input down-conversion orthogonal compensation subunit in the form of a data stream, and the output signal of the power amplifier after the digital pre-distortion subunit and the analog-to-digital converter 40", the feedback DC compensation subunit, the feedback equalization subunit, and the feedback down-conversion orthogonal compensation subunit are compared and calculated, and a signal with digital pre-distortion information is generated. The signal with digital pre-distortion information obtained is output to the digital-to-analog converter 40' through the transmit DC compensation subunit, the transmit up-conversion orthogonal compensation subunit, and the transmit equalization subunit.

[0102] The present application also includes an electronic device comprising the signal processing apparatus as claimed in any one of the preceding claims.

[0103] ​The signal processing device provided in the application is helpful to improve the performance and linearity of the power amplifier, uses the analog-to-digital converter and digital-to-analog converter before and after the core processor and the feedback analog-to-digital converter to improve the adaptability of the signal processing device, expands the application scenarios of the signal processing device through the high-speed and high-linearity analog switch, has stronger practicability and compatibility, reduces the application threshold of the radio frequency enhancement technology, and also reduces the cost of the system.

[0104] Fig. 4 shows a module schematic diagram of an analog interface signal processing module according to an embodiment of the application. The analog interface signal processing module provided in the application can be used as an independent module between the baseband module and the radio frequency module which communicate by using analog signals and are separate from each other. The signal-to-noise ratio of the module is high, the cost is low, and the module is suitable for application scenarios with high requirements for bottom noise and phase noise.

[0105] According to an embodiment, as shown in the figure, the analog interface signal processing module 400 can include a signal processing device 410.

[0106] According to an embodiment, the analog interface signal processing module 400 is configured to receive a plurality of baseband analog signals and a radio frequency feedback signal, process the baseband analog signals and the radio frequency feedback signal by using the signal processing device 410, and generate and output a baseband analog transmission signal with digital pre-distortion information.

[0107] According to an embodiment, the digital pre-distortion function in the signal processing device 410 needs to use the feedback signal to monitor and correct the state in real time, which requires obtaining the radio frequency feedback signal carrying nonlinear information.

[0108] According to an embodiment, the analog interface signal processing module 400 can further include a feedback channel, which can include a feedback selection switch 420, which can be coupled to a coupler in a radio frequency front-end module, and the state of the feedback selection switch 420 can be in a state of obtaining the feedback radio frequency signal. A down-conversion subunit 430 is coupled to the feedback selection switch 420 and a high-frequency clock subunit 440, and can be configured to receive the radio frequency feedback signal from the feedback selection switch 420; the high-frequency clock subunit 440 can be configured to generate a local oscillator signal and provide the local oscillator signal to the down-conversion subunit 430. The frequency of the local oscillator signal provided by the high-frequency clock subunit 440 is greater than or equal to the frequency of the radio frequency signal. The down-conversion subunit 730 can also be coupled to the signal processing device 410. The down-converted radio frequency feedback signal can be provided to the signal processing device 410 for iterative optimization.

[0109] According to an embodiment, the analog interface signal processing module 400 can further include a control unit (not shown) configured to control the feedback module switching and control each part in the analog interface signal processing module.

[0110] According to one embodiment, the analog interface signal processing module 400 supports multipath radio frequency feedback signals multiplexing one feedback channel. The feedback selection switch 420 selects the multipath radio frequency feedback signals.

[0111] According to one embodiment, the analog-to-digital conversion input and the digital-to-analog conversion output in the signal processing device 410 can be single-ended, differential, quadrature IQ or non-quadrature. The input of the down-conversion subunit 430 can be differential or single-ended input, and the input frequency can be any frequency, as long as the high frequency modulation signal of the input is reduced to the sampling range of the signal processing device 410.

[0112] The analog interface signal processing module proposed in the present application is independent of the baseband module and the radio frequency module, eliminates the constraints and limitations brought by the FPGA, has higher processing performance and higher adaptability, and users can obtain better linearity without changing the original architecture.

[0113] Figure 5 shows a schematic diagram of part of the modules of a communication system according to one embodiment of the present application. The system can include a baseband module 501, a radio frequency module 503 supporting multiple frequency bands, and a radio frequency front end 504 supporting multiple frequency bands. The radio frequency module 503 and the radio frequency front end module 504 can be integrated or separate.

[0114] According to one embodiment, the radio frequency front end module 504 can include a power amplifier unit 541 coupled to the radio frequency module 503 and configured to send radio frequency signals outward. The radio frequency front end module 504 can also include a coupler 542 coupled to the power amplifier 541. The coupler is configured to receive the radio frequency signals output by the power amplifier and feed back to the analog interface signal processing module 502.

[0115] According to one embodiment, an analog interface signal processing module 502 can be coupled between the baseband module 501 and the radio frequency module 503 and configured to receive baseband analog signals from the baseband module 501 and perform digital mirror correction, digital pre-distortion processing, peak clipping processing, etc. on the baseband analog signals, and output baseband analog transmission signals with pre-distortion information.

[0116] According to one embodiment, the analog interface signal processing module 502 can also track the output signals of the power amplifier unit in real time, so as to adjust the baseband analog transmission signals with digital pre-distortion information. The radio frequency feedback signal can be the radio frequency signal output by the power amplifier unit with nonlinear information.

[0117] The communication system provided in the present application uses an analog interface signal processing module with pre-distortion processing capability to pre-compensate the radio frequency signal, so that the radio frequency signal has good linearity, improves the performance of the communication system, and greatly increases the adaptability of the high-performance pre-distortion method in the radio frequency system, reduces the development complexity and application cost of the high-performance pre-distortion method.

[0118] Figure 6 shows a schematic diagram of a radio frequency interface signal processing module according to an embodiment of the present application. The radio frequency interface signal processing module provided in the present application can be located between the radio frequency module and the radio frequency front-end module which communicate using radio frequency signals and are separate from each other.

[0119] According to an embodiment, as shown in the figure, the radio frequency interface signal processing module 600 can include a down-conversion unit 610 configured to down-convert the output of the radio frequency module to obtain an analog signal; a signal processing device 620 coupled to the output end of the down-conversion unit 610, configured to convert the analog signal to a digital signal and process it, for example, pre-distortion processing, etc., and convert the processed digital signal to an analog signal output; an up-conversion unit 630 coupled to the signal processing device 620, configured to up-convert the analog signal output by the signal processing device 620 to obtain a radio frequency transmission signal; a feedback channel configured to feed back a radio frequency feedback signal with nonlinear information received from the outside to the signal processing device 620. The radio frequency feedback signal can include the radio frequency signal with nonlinear information output by the power amplifier. In an embodiment, the feedback channel can be coupled to the output end of the coupler in the radio frequency front-end module.

[0120] According to an embodiment, the signal processing device 620 can integrate multiple signal processing functions, including image correction (QEC), pre-distortion (PD), clipping processing (CFR), power detection (PD), digital filtering (FIR), and direct current offset correction (DC-Offset EQ). These functions can greatly improve the quality of the radio frequency signal output by the power amplifier, so that the power amplifier can work with higher efficiency and power, while reducing the performance requirements of the radio frequency and analog devices.

[0121] According to an embodiment, the feedback channel can monitor the output of the external radio frequency front-end module in real time, which can help the signal processing device 620 to calibrate and adjust in real time, thereby improving the performance and reliability of the entire communication system. This closed-loop calibration function not only improves the nonlinearity and anti-aging performance of the devices (such as power amplifier, up-conversion unit, digital-to-analog converter), but also improves the yield and consistency. According to an embodiment, the feedback channel can support multiple channels, such as 2 / 4 / 6 / 8… channel input time division switching.

[0122] According to one embodiment, the feedback channel comprises a feedback selection switch 650, which can be coupled to a coupler of the radio frequency front end module, configured to select and output the multiple radio frequency feedback signals; a high frequency clock subunit 660, configured to provide a local oscillator signal, the frequency of the local oscillator signal provided by the high frequency clock subunit 660 being greater than or equal to the frequency of the radio frequency signal; and a down-conversion subunit 670, coupled to the feedback selection switch 650 and the high frequency clock subunit 660, configured to apply the local oscillator signal from the high frequency clock subunit 660 to the output of the feedback selection switch 650, down-convert the signal output by the feedback selection switch 650, and output an analog signal to the signal processing device 620.

[0123] According to another embodiment of the present application, for application scenarios that do not require real-time tracking of the signal output by the power amplifier, the output of the power amplifier is used to calibrate the coefficients at the time of factory shipment, and the coefficients are recorded in a non-volatile memory, which are called by the signal processing device each time the power is turned on.

[0124] According to one embodiment, the radio frequency interface signal processing module 600 can further comprise a control unit (not shown), configured to control each part in the radio frequency interface signal processing module. The control unit can comprise a processor with control processing capability, such as an MCU.

[0125] The radio frequency interface signal processing module proposed in the present application can contain an enhanced algorithm for improving signal linearity and is independent of the baseband and radio frequency modules, and can be applied in different architectures, having higher processing performance, adaptability, and economy. Moreover, the pre-distortion related parameters can be adjusted in real time, and the baseband module or the high-integration radio frequency module is no longer needed for digital signal processing and debugging.

[0126] FIG. 7 shows a schematic diagram of part of the modules of a communication system according to another embodiment of the present application. It comprises a baseband module 701, a radio frequency module 702 and a radio frequency front end module 704 coupled to the baseband module 701, and a radio frequency interface signal processing module 703 coupled between the radio frequency module 702 and the radio frequency front end module 704. The radio frequency front end module 704 can comprise a power amplifier unit 7041, configured to receive the radio frequency transmission signal output by the radio frequency interface signal processing module 703, and a coupler coupled to the output of the power amplifier unit 7041, the output of the coupler being coupled to the radio frequency interface signal processing module 703, configured to feed back the signal output by the power amplifier with nonlinear information to the radio frequency interface signal processing module 703.

[0127] In some embodiments of the present application, the baseband module 701 and the radio frequency module 702 can be located together in a baseband package. In other embodiments, the radio frequency module 702 can be a high-integration radio frequency module.

[0128] But no matter what the structure of the baseband module and the radio frequency module is, the radio frequency interface signal processing module can be used to improve the linearity of the signal.

[0129] According to an embodiment, the radio frequency interface signal processing module 703 is configured to receive the radio frequency signal output by the radio frequency module 702, change the radio frequency signal to a low frequency, and then perform operations such as digital mirror correction, digital pre-distortion processing, peak clipping processing, and the like, to obtain a radio frequency transmission signal with digital pre-distortion information.

[0130] According to an embodiment, the radio frequency interface signal processing module 703 is configured to raise the signal processed by the pre-distortion operation to the frequency point of the received radio frequency signal and output it.

[0131] According to an embodiment, the radio frequency interface signal processing module 703 can also be configured to obtain a radio frequency transmission signal with digital pre-distortion information based on at least the radio frequency signal and the radio frequency feedback signal.

[0132] The communication system proposed in the present application includes a radio frequency interface signal processing module with pre-distortion processing capability and independent of the baseband and radio frequency modules, which performs pre-compensation on the radio frequency signal output by the power amplifier, so that the radio frequency signal of the system has good linearity, improves the performance of the communication system, reduces the requirements for the physical characteristics of the power amplifier and other devices, greatly increases the adaptability of high-performance pre-distortion methods in radio frequency systems, and reduces the development complexity and application cost of high-performance pre-distortion methods.

[0133] FIG. 8 shows a schematic diagram of part of a conventional base station. As shown in the figure, the FPGA processing unit 822 is responsible for processing the digital signal generated by the base station. The base station shown in the figure includes a baseband module 801, an intermediate frequency processing module 802, a radio frequency module 803, and a radio frequency front-end module 804. The intermediate frequency processing module 802 includes an FPGA processing unit 822 with signal processing capability. The present scheme has high requirements for the resources and performance of the FPGA processing unit 822, thus greatly increasing the system cost, system power consumption, and design cost.

[0134] In some embodiments, the radio frequency interface signal processing module proposed in the present application can be located between the radio frequency module 803 and the radio frequency front-end module 804 in FIG. 8, for example, to perform pre-distortion operations. The radio frequency interface signal processing module is configured to receive signals from the radio frequency module and the radio frequency front-end module. The input and output signals of the radio frequency interface signal processing module are radio frequency signals.

[0135] Figure 9 shows another schematic diagram of a part of a base station. As shown in the figure, the base station includes a baseband module 901, an intermediate frequency processing module 902, a high-integration radio frequency module 903, and a radio frequency front-end module 904. The high-integration radio frequency module 903 includes a digital signal processing unit 931 and an up-conversion unit 932, a down-conversion unit 933. As shown in the figure, the FPGA processing unit 922 and the digital signal processing unit 931 in the high-integration radio frequency module 903 are jointly responsible for processing the digital signals generated by the base station. However, a high-speed digital interface must be used between the intermediate frequency processing module 902 and the high-integration radio frequency module 903, which is costly. Moreover, the signal processing capability of the high-integration radio frequency module cannot be guaranteed.

[0136] In some embodiments, the radio frequency interface signal processing module proposed in the present application can be located between the high-integration radio frequency module 903 and the radio frequency front-end module 904 in Figure 9, for example, and configured to receive signals from the high-integration radio frequency module and the radio frequency front-end module, to implement, for example, pre-distortion operations.

[0137] In some other applications, the radio frequency interface signal processing module proposed in the present application can also be applied to the repeater scenario of the base station, to observe the signals output by the power amplifier unit in the radio frequency front-end module in real time, and to calculate and adjust the output signals of the radio frequency interface signal processing module in real time.

[0138] Figure 10 shows a schematic diagram of a part of a base station according to an embodiment of the present application. The present embodiment solves the performance of the base station without changing the architecture of the existing base station. As shown in the figure, the base station includes a baseband module 1001, an intermediate frequency processing module 1002 coupled to the baseband module 1001, a radio frequency module 1004, and a radio frequency front-end module 1005 coupled to the radio frequency module 1004. Among them, the analog interface signal processing module 1003 is coupled between the intermediate frequency processing module 1002 and the radio frequency module 1004, and is configured to receive the baseband analog signals output by the intermediate frequency processing module 1002. The signal processing device in the analog interface signal processing module 1003 is configured to process the signals output by the intermediate frequency processing module 1002, such as pre-distortion processing, etc. The radio frequency module includes up-conversion and down-conversion sub-units.

[0139] According to an embodiment, the intermediate frequency processing module 1002 is configured to convert the baseband digital signals from the baseband module 1001 into baseband analog signals.

[0140] According to an embodiment, the power amplifier units 10510 to 1051n in the radio frequency front-end module 1005 are configured to receive radio frequency transmission signals. The radio frequency front-end module 1005 further includes couplers 10520 to 1052n coupled to the output ends of the power amplifier units 10510 to 1051n, and configured to receive the output signals of the power amplifier units 10510 to 1051n.

[0141] According to an embodiment, the analog interface signal processing module 1003 is configured to receive the baseband analog signal from the intermediate frequency processing module 1002 and the radio frequency feedback signal with nonlinear information from the coupler 10520 to 1052n in the radio frequency front end module 1005, and output the radio frequency transmission signal with pre-distortion information after pre-distortion processing. The analog interface signal processing module 1003 in the embodiment can also be the signal processing device 300 described in the foregoing of the present application, cooperating with the feedback selection switch and multiplexing the down-conversion structure of the radio frequency module 803 in FIG. 8 to realize the analog interface signal processing module. The input and output interfaces of the analog interface signal processing module can be differential or single-ended interfaces of quadrature (IQ).

[0142] According to an embodiment, the radio frequency front end module 1005 can also feed back the radio frequency signal output by the radio frequency front end module 1005 to the down-conversion structure in the radio frequency module, and then to the analog interface signal processing module, for iteration and optimization.

[0143] FIG. 11 shows a schematic diagram of part of the modules of a conventional WiFi router. As shown in the figure, the WiFi router includes a baseband module 1101, a radio frequency module 1102 and a radio frequency front end module 1103. The signals in each channel are at the same frequency. In some embodiments, the baseband module 1101 and the radio frequency module 1102 are located in a WiFi chip and can be integrated together or separated.

[0144] The power amplifier used in the current WiFi router focuses on linearity and output bandwidth, and gives up efficiency and output power. In this way, in the high modulation scenario (1024QAM and 4096QAM), the output power cannot meet the requirements, causing problems such as insufficient coverage area at high throughput and excessive heat generation. The current WiFi chip solution providers provide some signal processing and power amplifier linearization functions. However, these functions are currently integrated in the baseband module and have limited performance, and cannot meet the purpose of improving output power to greatly improve the coverage area at high throughput.

[0145] FIG. 12 shows a schematic diagram of part of the modules of a WiFi router according to an embodiment of the present application. As shown in the figure, the analog interface signal processing module 1202 is coupled between the baseband module 1201 and the radio frequency module 1203. The radio frequency front end module 1204 is coupled to the radio frequency module 1203.

[0146] According to an embodiment, the input end of the analog interface signal processing module 1202 inputs and the output end outputs analog signals (i.e. low frequency signals), which can be differential or single-ended interfaces of quadrature (IQ).

[0147] According to an embodiment, the transmit-receive switch 12210 to 1221n and the transmit-receive switch 12250 to 1225n in the analog interface signal processing module 1202 can be used to select whether to pass through other modules in the analog interface signal processing module 1202 in the transmit or receive mode. For example, in the receive scenario (uplink mode), the transmit-receive switch 12250 directly outputs the output of the radio frequency module to the transmit-receive switch 12210; in the transmit scenario (downlink mode), the transmit-receive switch 12210 provides the output signal of the baseband module to the signal processing device 1222 for processing, and then outputs by the transmit-receive switch 12250. In an embodiment of the present application, the signal processing device can not include the switches 30 and 30', and the transmit-receive switch 12210 and the transmit-receive switch 12250 are used to realize the similar functions of the switches 30 and 30' in the signal processing device.

[0148] According to an embodiment, in the receive scenario (uplink mode), the switch state of the transmit-receive switch 12210 to 1221n can be determined by the radio frequency module 1203. When there is a signal inside the signal processing device that needs to be output, the switch state of the transmit-receive switch 12250 to 1225n is controlled by the signal processing device 1222.

[0149] According to an embodiment, the signal processing device 1222 (which can have the functions and structures introduced in the foregoing embodiments) in the analog interface signal processing module 1202 can provide the functions of digital pre-distortion (DPD) processing of the power amplifier, frequency response equalizer (EQ), crest factor reduction (CFR), quadrature imbalance calibration (QE), local oscillator leakage calibration (LOL), filter, power statistics, etc.

[0150] According to an embodiment, the signal processing device 1222 can support single channel or multiple channels. According to an embodiment, the system supports N channels, where N is an integer greater than or equal to 1. The frequencies of the signals in different channels can be different.

[0151] According to an embodiment, if it is necessary to track the radio frequency performance in real time, a coupler 12430 to 1243n or a power divider needs to be added at the output end of the power amplifier unit 12410 to 1241n in the radio frequency front-end module 1204, and the output port of the coupler 12430 to 1243n is coupled to the feedback selection switch 1223 in the analog interface signal processing module 1202 for selecting the feedback channel that needs to be observed by the analog interface signal processing module currently.

[0152] According to one embodiment, the output of the feedback selection switch 1223 is coupled to a down-conversion subunit 1227, which converts the radio frequency feedback signal to baseband and provides it to the signal processing device 1222 for real-time observation of the radio frequency transmit signal, calculation and real-time adjustment of the baseband analog transmit signal of the analog interface signal processing module.

[0153] According to one embodiment, the down-conversion subunit 1227 requires a high frequency clock subunit 1226 to provide a local oscillator signal for down-conversion. The high frequency clock subunit 1226 needs to be synchronized with the reference clock of the radio frequency module 1203. The low noise amplifiers 12420 to 1242n of the radio frequency front end module 1204 are electrically connected to the receive ports of the radio frequency module 1203.

[0154] Figure 13 shows a schematic diagram of part of a WiFi router according to another embodiment of the application. As can be seen, an analog interface signal processing module 1302 is coupled between a baseband module 1301 and a radio frequency module 1303. The radio frequency module 1303 is coupled to a radio frequency front end module 1304. The radio frequency front end module 1304 comprises power amplifier units 13410 to 1341n and couplers 13420 to 1342n coupled to the power amplifier units 13410 to 1341n, the outputs of which are used for calibration.

[0155] According to one embodiment, the signal processing device 1322 in the analog interface signal processing module 1302 (which can have the functions and structures described in the foregoing embodiments) can provide functions such as digital pre-distortion (DPD) processing. According to one embodiment, the signal processing device 1322 can support single channel or multi-channel.

[0156] According to one embodiment, the transmit-receive switching switches 13210 to 1321n and the transmit-receive switching switches 13250 to 1325n in the analog interface signal processing module 1302 can be used to select whether to pass through other modules in the analog interface signal processing module 1322 in the transmit or receive mode.

[0157] If real-time tracking of the quality of the radio frequency signal output by the power amplifier is not required, the architecture shown in Figure 13 can be used. In this case, the output of the power amplifier is used for factory calibration of the coefficients and the coefficients are recorded in the non-volatile memory. Each time the device is powered on, the relevant links and modules including the couplers, the power adjustment, the feedback selection switch, the down-conversion of the feedback channel, the high frequency clock subunit, etc. are fed back. However, training needs to be performed in advance and the coefficients are recorded in the non-volatile memory for the signal processing device 1322 to call each time it is powered on.

[0158] Figure 14 shows a partial block diagram of a WiFi router according to an embodiment of the present application. As shown, the RF interface signal processing module 1402 can be coupled between the WiFi die 1401 and the RF front end module 1403, where the RF module is located in the WiFi die 1401 and the power amplifier units 14310 to 1431n are located in the RF front end module 1403. This embodiment solves the RF performance of the WiFi router without separating the baseband module from the RF module.

[0159] According to an embodiment, the system supports N channels, where N is an integer greater than or equal to 1. The frequencies of the signals in different channels can be different. The RF transmit interfaces 14110 to 1411n in the WiFi die 1401 are coupled to the down-conversion units 14210 to 1421n in the RF interface signal processing module 1402. The signals output by the down-conversion units are provided to the signal processing device 1426 and converted to digital signals by the analog-to-digital converters in the signal processing device 1426 for, e.g., pre-distortion processing.

[0160] According to an embodiment, the signal processing device 1426 (as in the previous embodiment) can provide pre-distortion processing functions, as well as frequency response equalization (EQ), clipping and folding reduction (CFR), quadrature imbalance calibration (QE), local oscillator leakage calibration (LOL), filters, power statistics, etc.

[0161] According to an embodiment, because the WiFi signal has a high requirement for EVM, in order to reduce the impact of the additional down-conversion and up-conversion units on the EVM based on the WiFi die 1401, the down-conversion and up-conversion units in the same channel need to use the same high-frequency clock sub-unit to provide the local oscillator signal, e.g., the same high-frequency clock is used by the down-conversion and up-conversion units. In addition, when the high-frequency clock is 1 MHz or above, the point frequency phase noise needs to be as small as possible. When the frequency of the high-frequency clock is below 1 MHz, the phase noise requirement is relatively low. The high-frequency clock sub-units 14230 to 1423n used by different channels can be the same or different clock sources, depending on the application requirements.

[0162] In an embodiment of the present application, the down-conversion unit 14210 and the up-conversion unit 14220 are in the same channel and can jointly receive the local oscillator signal from the high-frequency clock sub-unit 14230. The down-conversion unit 1421n and the up-conversion unit 1422n are in the same channel and can jointly receive the local oscillator signal from the high-frequency clock sub-unit 1423n.

[0163] According to one embodiment, if real-time tracking of the radio frequency performance is needed, a coupler 14320 to 1432n or a power divider needs to be set at the output of the power amplifier unit 14310 to 1431n in the radio frequency front end module 1403. The output of the coupler 14320 to 1432n can be electrically connected to the input of the feedback selection switch 14250 for selecting the feedback channel that the radio frequency interface signal processing module 1402 currently needs to observe. According to other embodiments, the signals fed back to the feedback selection switch 14250 by the couplers 14320 and 1432n can have different frequencies.

[0164] According to one embodiment, the output of the feedback selection switch 14250 is electrically connected to a down-conversion subunit 14270 for converting the radio frequency feedback signal to the baseband and providing the radio frequency feedback signal to the signal processing device 1426 for real-time observation of the radio frequency feedback signal, calculation, and real-time adjustment of the output signal of the radio frequency interface signal processing module.

[0165] According to one embodiment, the down-conversion subunit 14270 needs a high-frequency clock source to provide the local oscillator. If there are multiple high-frequency clock subunits, such as high-frequency clock subunits 14230 to 1423n, in the system, the multiple clocks need to be selected by a clock switching switch 14240 before being input to the down-conversion subunit 14270 as the local oscillator. The selection of the clock switching switch is related to the radio frequency feedback signal that needs to be monitored.

[0166] According to one embodiment, in the feedback channel, the clock switching switch 14240 is configured to select the local oscillator signal generated by the high-frequency clock subunit 14230 or 1423n based on the radio frequency feedback signal to be observed, and select the same high-frequency clock source as the transmission link that currently needs to be monitored, for example, to monitor the radio frequency signal in the channel of the coupler 14320, the same high-frequency clock source as the up-conversion unit 14220 and the down-conversion unit 14210 needs to be selected, that is, the high-frequency clock subunit 14230. The high-frequency clock subunits 14230 to 1423n do not need to share the reference signal with the WiFi die 1401.

[0167] According to one embodiment, the down-conversion subunit 14270 is configured to apply the local oscillator signal provided by the clock switching switch 14240 to the signal output by the feedback selection switch 14250, so as to down-convert the radio frequency feedback signal to the baseband.

[0168] According to one embodiment, the low-noise amplifiers 14340 to 1434n of the radio frequency front end module 1403 are electrically connected to the radio frequency receiving interfaces 14120 to 1412n of the WiFi die 1401. The radio frequency receiving interfaces 14120 to 1412n of the WiFi die 1401 are configured to receive radio frequency receiving signals from the low-noise amplifiers 14340 to 1434n.

[0169] According to different embodiments of the present application, the above signal processing device or the radio frequency interface signal processing module can be used in different communication devices, such as base stations, unmanned aerial vehicles, mobile phones, walkie-talkies, cars, satellites, or wireless cameras, etc., which can reduce the product cost while realizing the digital enhancement processing function.

[0170] The radio frequency feedback signal output by the radio frequency front-end module and the radio frequency signal output by the radio frequency module are converted to baseband by the radio frequency interface signal processing module and provided to the signal processing device in the radio frequency interface signal processing module for pre-distortion operation, and the processed signal is up-converted to the frequency point of the radio frequency transmission signal.

[0171] The radio frequency interface signal processing module proposed in the present application can be directly applied between the radio frequency module and the radio frequency front-end module without changing the original Wifi router or base station framework, without changing the radio frequency module, and can realize the improvement of the linearity of the radio frequency signal output by the power amplifier, thereby reducing the application threshold of the radio frequency enhancement technology and the cost of the baseband chip or the radio frequency chip.

[0172] The analog interface signal processing module proposed in the present application can be directly applied between the baseband and the radio frequency module without changing the original Wifi router or base station framework, and can compensate the radio frequency signal, so that the radio frequency signal output by the power amplifier has good linearity, improves the performance of the communication system, and reduces the requirements for the physical characteristics of the power amplifier and other devices.

[0173] The above embodiments are only for illustrating the present application and are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application, therefore, all equivalent technical solutions shall belong to the scope of the present application.

Claims

1. A signal processing apparatus, comprising: The first switch is configured to receive a first analog signal; A first analog-to-digital converter, coupled to the first switch, is configured to convert the first analog signal into a first digital signal; A core processor, coupled to the first analog-to-digital converter, is configured to process the first digital signal and output a second digital signal that includes at least digital predistortion information; A digital-to-analog converter, coupled to the core processor, is configured to convert the second digital signal into a second analog signal; A second switch is coupled to the first digital-to-analog converter and configured to output the second analog signal; The signal processing device further includes a second analog-to-digital converter, configured to receive the output signal of a power amplifier outside the signal processing device, convert the output signal of the power amplifier into a third digital signal and provide it to the core processor; wherein, the core processor is configured to obtain a second digital signal with digital predistortion information based on the first digital signal and the third digital signal. The second switch is also coupled to the first switch to form an uplink channel; and the signal processing device further includes a downlink channel, which sequentially processes the first analog signal received by the first switch through a first analog-to-digital converter, a core processor, and a digital-to-analog converter, and then sends it to the second switch for output.

2. The apparatus according to claim 1, wherein the apparatus is a chip manufactured using integrated circuit technology.

3. A communication system, comprising: Baseband module, RF module, and RF front-end module; And an analog interface signal processing module coupled between the baseband module and the radio frequency module; the analog interface signal processing module is configured to receive at least a first analog signal from the baseband module; in, The analog interface signal processing module includes a signal processing device, which is configured to perform a digital predistortion operation based at least on the first analog signal to obtain a second analog signal with digital predistortion information. The signal processing device includes: a first switch configured to receive the first analog signal; a first analog-to-digital converter coupled to the first switch configured to convert the first analog signal into a first digital signal; a core processor coupled to the first analog-to-digital converter configured to process the first digital signal and output a second digital signal with at least digital predistortion information; a digital-to-analog converter coupled to the core processor configured to convert the second digital signal into a second analog signal; and a second switch coupled to the digital-to-analog converter configured to output the second analog signal; wherein the second switch is also coupled to the first switch to jointly form an uplink channel.

4. The system according to claim 3, wherein, The analog interface signal processing module further includes a feedback channel, which is configured to receive an RF feedback signal from the RF front-end module, convert the RF feedback signal into a third analog signal, and provide it to the signal processing device. These include, A feedback selection switch, coupled to the RF front-end module, is configured to select and output multiple RF feedback signals; a down-conversion subunit, coupled between the feedback selection switch and the signal processing device, is configured to perform down-conversion on the RF feedback signals and provide the third analog signal generated after frequency conversion to the signal processing device; a high-frequency clock subunit, coupled to the down-conversion subunit, is configured to generate the local oscillator signal required by the down-conversion subunit.

5. The system according to claim 4, wherein, The signal processing device further includes a second analog-to-digital converter coupled to the core processor and configured to receive the third analog signal and provide it to the core processor.

6. The system according to claim 5, wherein, The signal processing device obtains a second digital signal with digital predistortion information based on the first analog signal and the third analog signal.

7. The system according to claim 6, wherein, The analog interface signal processing module is also configured to receive multiple baseband analog signals and radio frequency feedback signals.

8. The system according to claim 7, wherein, The system is a WiFi router, wherein the analog interface signal processing module further includes multiple transmit / receive switching switches, configured to select whether to use the signal processing device in the analog interface signal processing device in transmit or receive mode.

9. A communication system, comprising: Baseband module, RF module, and RF front-end module; And, a radio frequency interface signal processing module coupled between the radio frequency module and the radio frequency front-end module; The radio frequency interface processing module is configured to receive at least a first radio frequency signal from the radio frequency module; The radio frequency interface signal processing module includes a signal processing device configured to perform digital predistortion operation based at least on the first radio frequency signal to obtain a second radio frequency signal with digital predistortion information. The signal processing device includes: a first switch configured to receive a first analog signal; a first analog-to-digital converter configured to convert the first analog signal into a first digital signal; a core processor coupled to the first analog-to-digital converter configured to process the first digital signal and output a second digital signal with at least digital predistortion information; a digital-to-analog converter coupled to the core processor configured to convert the second digital signal into a second analog signal; and a second switch coupled to the digital-to-analog converter configured to output the second analog signal. The second switch is also coupled to the first switch to jointly form an uplink channel.

10. The system according to claim 9, wherein, The radio frequency interface signal processing module includes: The downconversion unit is configured to receive the first radio frequency signal and perform a downconversion operation to obtain the first analog signal; The upconversion unit is configured to perform an upconversion operation on the second analog signal generated by the signal processing device to obtain a second radio frequency signal; The signal processing device is coupled between the upconversion unit and the downconversion unit and is configured to receive the first analog signal and convert it into a first digital signal, and to perform digital predistortion processing on the first digital signal to obtain a second digital signal and convert it into the second analog signal.

11. The system according to claim 10, wherein the radio frequency interface signal processing module further includes a feedback channel configured to receive a radio frequency feedback signal from the radio frequency front-end module and convert the radio frequency feedback signal into a third analog signal to provide to the signal processing device; The feedback channel includes: A feedback selection switch, coupled to the RF front-end module, is configured to select and output multiple RF feedback signals; a down-conversion subunit is configured to perform down-conversion on the RF feedback signals and provide the third analog signal generated after frequency conversion to the signal processing device; a high-frequency clock subunit is configured to generate the local oscillator signal required by the down-conversion subunit.

12. The system according to claim 11, wherein, The radio frequency interface signal processing module is also configured to receive multiple radio frequency analog signals and radio frequency feedback signals.

13. The system according to claim 12, wherein, The signal processing device further includes a second analog-to-digital converter coupled to the core processor, configured to receive the third analog signal, convert the third analog signal into a third digital signal, and provide it to the core processor.

14. The system according to claim 13, wherein, The signal processing device obtains a second radio frequency signal with pre-distortion information based on the first radio frequency signal and the radio frequency feedback signal.

15. The system according to claim 14, wherein, The system is a WiFi router, and the radio frequency interface signal processing module further includes a clock selection switch configured to select the local oscillator signal generated by multiple high-frequency clock subunits.

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