Host backplane and valve control apparatus

Abstract

The present application belongs to the technical field of power distribution control. Provided are a host backplane (10) and a valve control apparatus. The host backplane (10) comprises a circuit substrate (100), the circuit substrate (100) being provided with at least two CPU board connectors (111, 112) and a plurality of interface board connectors (121-124), wherein different CPU board connectors (111 / 112) and the same interface board connector (121 / 122 / 123 / 124) are connected by means of signal transceiving lines of the same length (130). The signal transceiving lines (130) between different CPU board connectors (111, 112) and the same interface board connector (121 / 122 / 123 / 124) are set to have the same length, and thus synchronous reception / transmission of the communication between different CPU boards and the same interface board is achieved, timing consistency is maintained, and the requirement of realizing synchronous communication as much as possible is met. In addition, since there are signal transceiving lines (130) between different CPU board connectors (111 / 112) and the same interface board connector (121 / 122 / 123 / 124), effective communication can still be maintained in the case of a failure of a single signal transceiving line (130), thereby improving the reliability of the system.

Description

Host backplane and valve control device

[0001] This application claims priority to the Chinese patent application No. 202421525216.5, filed on June 28, 2024, and entitled "Host backplane and valve control device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application belongs to the technical field of power distribution control, and in particular relates to a host backplane and a valve control device. BACKGROUND

[0003] The high-voltage direct-hanging energy storage valve control device is an important hub between the direct-current control protection and the energy storage valve sub-module. The controller of the valve control device communicates with the interface (i.e., I / O port) board through a low-voltage differential signaling (LVDS) bus. However, the communication between the controller and the interface board cannot meet the requirement of as much as possible synchronous communication.

[0004] SUMMARY

[0005] In view of the above problems, the present application provides a host backplane and a valve control device valve control system, which aims to solve the problem that the communication between the controller and the interface board of the valve control device cannot meet the requirement of as much as possible synchronous communication.

[0006] In a first aspect, the embodiments of the present application provide a host backplane, comprising a circuit backboard, wherein the circuit backboard is provided with at least two CPU board connectors and a plurality of interface board connectors.

[0007] In the technical scheme of the embodiments of the present application, the signal transceiving lines of different CPU board connectors and the same interface board connector are set to be equal in length, so that the communication between different CPU boards and the same interface board can be as much as possible synchronous receiving / delivery, keeping the timing consistent, meeting the requirement of as much as possible synchronous communication, and thus meeting the higher speed communication. In some embodiments, the different CPU board connectors and the same interface board connector both have signal transceiving lines, which can still maintain effective communication when a single signal transceiving line fails, improving the reliability of the system.

[0008] In the technical scheme of the embodiments of the present application, the signal transceiving lines of different CPU board connectors and the same interface board connector are set to be equal in length, so that the communication between different CPU boards and the same interface board can be as much as possible synchronous receiving / delivery, keeping the timing consistent, meeting the requirement of as much as possible synchronous communication, and thus meeting the higher speed communication. In some embodiments, the different CPU board connectors and the same interface board connector both have signal transceiving lines, which can still maintain effective communication when a single signal transceiving line fails, improving the reliability of the system.

[0009] In some embodiments, the equal-length signal transceiving lines include equal-length signal transmitting lines and equal-length signal receiving lines.

[0010] In the technical solution of the embodiment of the application, the equal-length signal transmitting and receiving lines between different CPU board connectors and the same interface board connector are composed of independent signal transmitting lines and signal receiving lines, so that low-power and low-error-rate serial communication can be realized.

[0011] In some embodiments, the signal transmitting and receiving lines include copper cladding arranged on the circuit board. In the technical solution of the embodiment of the application, an implementation of the signal transmitting and receiving lines is provided.

[0012] In some embodiments, the copper cladding includes a bent trace.

[0013] In the technical solution of the embodiment of the application, the equal-length signal transmitting and receiving lines are arranged on the circuit board by using the bent copper cladding, so that the space of the circuit board is saved.

[0014] In some embodiments, the bent trace has a gap between the CPU board connector and the interface board connector. During communication, the interference between the bent trace and the CPU board connector and the interface board connector is improved, and the reliability of communication is improved.

[0015] In some embodiments, the signal transmitting and receiving lines include a connection cable connected to the circuit board.

[0016] In the technical solution of the embodiment of the application, another implementation of the signal transmitting and receiving lines is provided.

[0017] In some embodiments, the signal transmitting lines include a pair of differential signal transmitting lines, and the signal receiving lines include a pair of differential signal receiving lines.

[0018] In the technical solution of the embodiment of the application, a signal transmitting line communication mode of low-voltage differential signal is provided.

[0019] In some embodiments, two CPU board connectors are included.

[0020] In the technical solution of the embodiment of the application, a double-CPU board host backboard is provided, which provides sufficient computing power and reliability.

[0021] In some embodiments, the two CPU board connectors are arranged in the middle region of the circuit board.

[0022] In the technical solution of the embodiment of the application, the signal transmitting and receiving lines of the CPU board connector to the interface board connectors on the opposite sides or around are arranged to be equal in length.

[0023] In some embodiments, a plurality of interface board connectors are distributed on the opposite sides or around the two CPU board connectors.

[0024] The technical scheme of the embodiment of the present application can meet the requirement of the symmetrical structure layout of the CPU board or the interface board which can interchange positions at any time, improve the redundancy of the system, and facilitate the arrangement of the signal receiving / transmitting lines of the CPU board connector to the interface board connectors on the opposite sides or around.

[0025] In some embodiments, the distance between the edges of the two CPU board connectors is greater than the distance between the edges of the two adjacent interface board connectors.

[0026] The technical scheme of the embodiment of the present application is beneficial to the heat dissipation of the CPU board connected by the CPU board connector.

[0027] In some embodiments, two groups of redundant signal lines are connected between the CPU board connectors.

[0028] The technical scheme of the embodiment of the present application improves the communication reliability of the CPU board connected by the CPU board connector.

[0029] In the second aspect, the embodiment of the present application provides a valve control device, which comprises the host backboard, two CPU boards and at least one interface board, the two CPU boards are connected to the two CPU board connectors of the host backboard, and the interface board is connected to the interface board connector of the host backboard.

[0030] The technical scheme of the embodiment of the present application can make the communication between the different CPU boards and the same interface board as synchronized as possible, keep the time sequence consistent, meet the requirement of as synchronized communication as possible, and improve the reliability of the valve control device.

[0031] The above description is only a summary of the technical scheme of the present application, in order to make the technical means of the present application more clearly understood and implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0032] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments, and are not to be considered as limiting of the present application. Moreover, in the drawings, like reference numerals denote similar parts throughout the several views. In the drawings:

[0033] FIG. 1 shows a structural schematic diagram of a host backboard according to an embodiment of the present application;

[0034] FIG. 2 shows a circuit board structural schematic diagram of a host backboard according to an embodiment of the present application;

[0035] FIG. 3 shows a schematic diagram of a circuit board structure of a host backplane according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The embodiments of the present application will be described in detail with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical scheme of the present application, and therefore only serve as examples, and cannot be used to limit the protection scope of the present application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the specification herein is for describing particular embodiments only and is not intended to be limiting of the application; the use herein of terms such as "comprise" and "have" and any variations thereof are intended to cover the inclusion of the stated features but not the exclusion of other features.

[0038] In the description of the embodiments of the present application, the technical terms "first", "second", and the like are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0039] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents a "or" relationship between the front and rear associated objects.

[0041] In the description of the embodiments of the present application, the term "a plurality of" refers to two or more (including two), and similarly, "a plurality of groups" refers to two or more groups (including two groups), and "a plurality of pieces" refers to two or more pieces (including two pieces).

[0042] In the description of the embodiments of the present application, unless explicitly defined and limited otherwise, the technical terms "mounting", "connection", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be direct connection, can also be indirect connection through an intermediate medium, can be internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0043] According to some embodiments of the present application, referring to FIG. 1, FIG. 1 shows a structural schematic diagram of a host backboard provided by an embodiment of the present application, only parts related to the present embodiment are shown for the convenience of description, which are described in detail as follows:

[0044] The host backboard 10 can be applied to a high-voltage direct-hanging energy storage valve control device (hereinafter referred to as a valve control device), which is an important hub between DC control protection and energy storage valve submodules. The host backboard 10 includes a circuit bottom plate 100, and the circuit bottom plate 100 is provided with at least two central processing unit (CPU) board connectors 111 and 112 and a plurality of interface board connectors 121-124; wherein different CPU board connectors 111 and 112 are respectively connected with a signal transceiving line 130 of the same interface board connector 121 / 122 / 123 / 124, and the lengths of the signal transceiving lines are equal.

[0045] The circuit bottom plate 100 is generally a conventional printed circuit board (PCB). The CPU board is a control board or a communication board for mounting a CPU, and the CPU board connector 111 is used for plugging the CPU board. In FIG. 1, the interface board connectors are four, which are interface board connector 121, interface board connector 122, interface board connector 123 and interface board connector 124; the interface board connectors 121-124 complete the start-stop operation and control protection function of the energy storage valve of the energy storage submodule through optical fiber communication, and provide reliable communication control for the energy storage submodule.

[0046] In the technical scheme of the embodiments of the present application, by setting the signal transceiving lines 130 of different CPU board connectors 111 and 112 and the same interface board connector 121 / 122 / 123 / 124 to be equal in length, the communication between different CPU boards and the same interface board can be received / sent as synchronously as possible, the timing is kept consistent, the requirement of synchronous communication is met as much as possible, and higher speed communication is met. The signal transceiving line 130 can be a line in serial communication or parallel communication mode.

[0047] In some embodiments, the signal transmission and reception lines 130 of different CPU board connectors 111, 112 and the same interface board connector 121 / 122 / 123 / 124 can keep effective communication when a single signal transmission and reception line 130 fails, thereby improving the reliability of the system.

[0048] The signal transmission and reception lines 130 include signal transmission lines and signal reception lines.

[0049] In some embodiments, the signal transmission line and the signal reception line of one CPU board connector connected with one interface board connector are the same wire. At this time, the signal transmission line and the signal reception line of different CPU board connectors 111, 112 connected with the same interface board connector 121 / 122 / 123 / 124 are equal in length.

[0050] According to some embodiments of the present application, referring to FIG. 2 and FIG. 3, FIG. 2 shows a structural schematic diagram of a host backplane provided by an embodiment of the present application, and FIG. 3 shows a structural schematic diagram of a host backplane provided by an embodiment of the present application. For the convenience of description, only parts related to the present embodiments are shown, and the details are as follows:

[0051] In some embodiments, the signal transmission line and the signal reception line of one CPU board connector connected with one interface board connector are different wires. For example, the equal-length signal transmission and reception lines 130 include equal-length signal transmission lines TX1-TX4 and equal-length signal reception lines RX1-RX4. This makes the communication between the CPU boards inserted by different CPU board connectors 111, 112 and the interface boards inserted by the same interface board connector 121 / 122 / 123 / 124 as synchronized as possible, thereby keeping the timing consistent. In some embodiments, the equal-length signal transmission and reception lines 130 are composed of independent signal transmission lines TX1-TX4 and signal reception lines RX1-RX4, and can realize low-power, low-error-rate serial communication.

[0052] According to some embodiments of the present application, please continue to refer to FIG. 2 and FIG. 3, the signal transmission and reception lines 130 include copper cladding arranged on the circuit board 100. The copper cladding is the copper cladding of the PCB, which can be composed of straight copper cladding and / or curved copper cladding. According to some embodiments of the present application, the copper cladding includes a bent trace.

[0053] As shown in FIG. 2, the signal transmission line TX1 connects the CPU board connector 111 and the interface board connector 121, the signal transmission line TX2 connects the CPU board connector 112 and the interface board connector 121, and the signal transmission line TX1 is equal in length to the signal transmission line TX2; the signal reception line RX1 connects the CPU board connector 111 and the interface board connector 121, the signal reception line RX2 connects the CPU board connector 112 and the interface board connector 121, and the signal transmission line RX1 is equal in length to the signal transmission line RX2.

[0054] In this embodiment, the distance between the CPU board connector 111 and the interface board connector 121 is less than the distance between the CPU board connector 112 and the interface board connector 121. Therefore, in order to make the signal transmission line TX1 equal in length to the signal transmission line TX2, a bending trace 131 is arranged on the signal transmission line TX1; similarly, a bending trace 132 is arranged on the signal reception line RX1, thereby saving the space of the circuit board 100.

[0055] As shown in FIG. 3, the signal transmission line TX3 connects the CPU board connector 111 and the interface board connector 122, the signal transmission line TX4 connects the CPU board connector 112 and the interface board connector 122, and the signal transmission line TX3 is equal in length to the signal transmission line TX4; the signal reception line RX3 connects the CPU board connector 111 and the interface board connector 122, the signal reception line RX4 connects the CPU board connector 112 and the interface board connector 122, and the signal transmission line RX3 is equal in length to the signal transmission line RX4.

[0056] In this embodiment, the distance between the CPU board connector 111 and the interface board connector 122 is less than the distance between the CPU board connector 112 and the interface board connector 122. Therefore, in order to make the signal transmission line TX3 equal in length to the signal transmission line TX4, a bending trace 133 is arranged on the signal transmission line TX3; similarly, a bending trace 134 is arranged on the signal reception line RX3, thereby saving the space of the circuit board 100.

[0057] According to some embodiments of the present application, the bending traces have gaps between the CPU board connectors 111, 112 and the interface board connectors 121 / 122 / 123 / 124. During communication, the interference isolation degree between the bending traces and the CPU board connectors 111, 112 and the interface board connectors 121 / 122 / 123 / 124 is improved, mutual interference is reduced, and the reliability of communication is improved.

[0058] According to some embodiments of the present application, the signal transmission / reception line 130 includes a connection cable connected to the circuit board 100. The connection cable is made based on a flexible printed circuit (FPC) or other balanced cable, for example.

[0059] According to some embodiments of the present application, please continue to refer to FIG. 2 and FIG. 3, the equal-length signal transmission lines TX1-TX4 include a pair of differential signal transmission lines, and the signal receiving lines RX1-RX4 include a pair of differential signal receiving lines. In the technical solution of the embodiments of the present application, the host backplane 10 provides a signal transmission line communication mode of LVDS, which has low power consumption and low bit error rate.

[0060] According to some embodiments of the present application, please continue to refer to FIG. 1 to FIG. 3, the host backplane 10 includes two CPU board connectors 111, 112. In the technical solution of the embodiments of the present application, a host backplane 10 with dual CPU boards is provided, which provides sufficient computing power and reliability.

[0061] According to some embodiments of the present application, please continue to refer to FIG. 1 to FIG. 3, the two CPU board connectors 111, 112 are arranged in the middle region of the circuit board 100; and the plurality of interface board connectors 121-124 are distributed on the opposite sides or around the two CPU board connectors 111, 112.

[0062] In the technical solution of the embodiments of the present application, the signal transmission and reception lines 130 of the CPU board connectors 111, 112 to the interface board connectors 121-124 on the opposite sides or around are arranged to be equal in length, and the symmetrical structure layout can meet the requirement of interchanging the positions of the CPU board or the interface board at any time, thereby improving the redundancy of the system.

[0063] According to some embodiments of the present application, please continue to refer to FIG. 2 and FIG. 3, the distance between the edges of the two CPU board connectors 111, 112 is greater than the distance between the edges of two adjacent interface board connectors. This is conducive to heat dissipation of the CPU board plugged into the CPU board connectors 111, 112.

[0064] According to some embodiments of the present application, please continue to refer to FIG. 1, two groups of redundant signal lines are connected between each of the CPU board connectors 111, 112.

[0065] In the technical solution of the embodiments of the present application, two groups of redundant signal lines are arranged between each of the CPU board connectors 111, 112, thereby improving the communication reliability of the CPU board plugged into each of the CPU board connectors 111, 112.

[0066] It can be understood that the above-mentioned equal length should be relative equal length. Through some tests, it is known that the line length error is related to the signal transmission rate, for example:

[0067] When the signal transmission rate is less than 1 gigabit per second (Gbps), the line length error between the two lines is allowed to be ±0.5 millimeters (mm).

[0068] When the signal transmission rate is 1Gbps-10Gbps, the line length error between the two lines is allowed to be ±0.25mm.

[0069] When the signal transmission rate is greater than 10Gbps, the line length error between the two lines is allowed to be ±0.125mm.

[0070] In the second aspect, the embodiments of the present application provide a valve control device, which comprises the host backplane 10 as above, and two CPU boards and at least one interface board, the two CPU boards are respectively plugged with the two CPU board connectors 111 and 112 of the host backplane 10, and the interface board is plugged with the interface board connectors 121-124 of the host backplane 10.

[0071] According to some embodiments of the present application, each interface board needs to communicate with each energy storage sub-module in double ways, and the effective control of the energy storage sub-module can be maintained when the single-way control system fails.

[0072] In the technical scheme of the embodiments of the present application, the host backplane 10 and the valve control device have at least the following functions or effects:

[0073] The same CPU board can be interchanged in the two CPU board connectors 111, and the data of the two CPU boards can keep normal communication.

[0074] Each CPU board and each interface board can realize high-speed differential signal communication, and each interface board and the two CPU boards realize double-way communication redundant control.

[0075] The same interface board can be inserted into all the interface board connectors 121-124, and the double-way communication redundant control between the interface board and the two CPU boards can be realized.

[0076] The signal transmission time delay of the same interface board to the two CPU boards is the same, and the timing consistency is ensured.

[0077] A set of valve control devices only needs one type of CPU board and one type of interface board to meet the device installation requirements, and effectively reduces the types of board cards.

[0078] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some or all of the technical features can be replaced equivalently. Such modifications or replacements do not change the essence of the corresponding technical solutions, which should be covered in the scope of the claims and the specification of the present application. In particular, the technical features mentioned in each embodiment can be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A host backplane, wherein, Includes a circuit board base, on which at least two CPU board connectors and multiple interface board connectors are provided; The different CPU board connectors and the same interface board connector are respectively connected to signal transceiver lines of equal length.

2. The host backplane as described in claim 1, wherein, The equal-length signal transceiver lines include equal-length signal transmitting lines and equal-length signal receiving lines.

3. The host backplane as described in claim 1 or 2, wherein, The signal transceiver lines include copper plating arranged on the circuit board.

4. The host backplane as described in claim 3, wherein, The copper cladding includes bent traces.

5. The host backplane as described in claim 4, wherein, There is a gap between the bent trace and the CPU board connector and the interface board connector.

6. The host backplane as described in claim 1 or 2, wherein, The signal transceiver line includes a connecting cable that is connected to the circuit base plate.

7. The host backplane as described in any one of claims 2 to 6, wherein, The signal transmission line includes a pair of differential signal transmission lines, and the signal reception line includes a pair of differential signal reception lines.

8. The host backplane as described in any one of claims 1 to 6, wherein, Includes two of the aforementioned CPU board connectors.

9. The host backplane as described in claim 8, wherein, The two CPU board connectors are located in the middle area of ​​the circuit board.

10. The host backplane as described in claim 8 or 9, wherein, Multiple interface board connectors are distributed on opposite sides or around the two CPU board connectors.

11. The host backplane as claimed in any one of claims 8 to 10, wherein, The distance between the edges of the two CPU board connectors is greater than the distance between the edges of the two adjacent interface board connectors.

12. The host backplane as claimed in any one of claims 1 to 11, wherein, Two sets of redundant signal lines are connected between each of the CPU board connectors.

13. A valve control device, wherein, It includes a host backplane as described in any one of claims 1 to 12, two CPU boards and at least one interface board, wherein the two CPU boards are respectively plugged into two CPU board connectors of the host backplane, and the interface board is plugged into an interface board connector of the host backplane.

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