Clock domain conversion circuit and method, and related apparatus

Abstract

The present application belongs to the technical field of data transmission. Disclosed are a clock domain conversion circuit and method, and a related apparatus. The clock domain conversion circuit comprises: a first control unit, wherein an input end of the first control unit is connected to a receiving end of the clock domain conversion circuit; a processing unit, wherein an input end of the processing unit is connected to an output end of the first control unit; and a second control unit, wherein an input end of the second control unit is connected to an output end of the processing unit, and an output end of the second control unit is connected to a sending end of the clock domain conversion circuit. The first control unit is used for sending data to the processing unit when data belonging to a first clock domain is acquired from the receiving end; the processing unit is used for storing the data and converting the clock domain of the data from the first clock domain to a second clock domain when the data is received from the first control unit; and the second control unit is used for acquiring converted data from the processing unit and outputting the converted data by means of the sending end.

Description

Clock domain conversion circuit, method and related apparatus

[0001] The present application claims priority to the Chinese patent application No. 202410829895.3, filed on June 25, 2024, and entitled "Clock domain conversion circuit, method and related apparatus", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the technical field of data transmission, and specifically relates to a clock domain conversion circuit, method and related apparatus. BACKGROUND

[0003] Generally, when two functional modules belonging to different clock domains in an electronic device perform data transmission, one of the functional modules can first send data to an asynchronous first input first output (FIFO) so that the asynchronous FIFO can convert the clock domain of the data from the clock domain of the one functional module to the clock domain of the other functional module, and send the converted data to the other functional module, so that the other functional module can accurately identify and process the converted data to use the processed data.

[0004] However, since the above-mentioned other functional module may not be able to identify and process the converted data in time, the above-mentioned one functional module may still send subsequent data to the asynchronous FIFO so that the asynchronous FIFO sends the converted subsequent data to the other functional module, which may result in the other functional module discarding the converted subsequent data due to the inability to identify and process the converted subsequent data, thus, the converted data received by the other functional module may be incomplete, which leads to poor quality of data transmission of the functional modules belonging to different clock domains in the electronic device. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a clock domain conversion circuit, method and related apparatus, which can avoid the situation that the data received by one of the functional modules belonging to different clock domains is incomplete, thereby improving the quality of data transmission of the functional modules belonging to different clock domains.

[0006] In a first aspect, an embodiment of the present application provides a clock domain conversion circuit, comprising: a first control unit, an input end of the first control unit being connected with a receiving end of the clock domain conversion circuit; a processing unit, an input end of the processing unit being connected with an output end of the first control unit; a second control unit, an input end of the second control unit being connected with an output end of the processing unit, and an output end of the second control unit being connected with a sending end of the clock domain conversion circuit; wherein the first control unit is configured to send data to the processing unit in a case that the data belonging to a first clock domain is obtained from the receiving end; the processing unit is configured to store the data and convert a clock domain of the data from the first clock domain to a second clock domain in a case that the data is received from the first control unit; and the second control unit is configured to obtain the converted data from the processing unit and output the converted data through the sending end.

[0007] In a second aspect, an embodiment of the present application provides a clock domain conversion method, applied to the clock domain conversion circuit of the first aspect, comprising: sending data to a processing unit of the clock domain conversion circuit through a first control unit of the clock domain conversion circuit in a case that the data belonging to a first clock domain is received at a receiving end of the clock domain conversion circuit; storing the data and converting a clock domain of the data from the first clock domain to a second clock domain through the processing unit; and obtaining the converted data from the processing unit through a second control unit of the processing unit, and outputting the converted data through a sending end of the clock domain conversion circuit.

[0008] In a third aspect, an embodiment of the present application provides a clock domain conversion device, comprising: a sending module, configured to send data to a processing unit of the clock domain conversion circuit through a first control unit of the clock domain conversion circuit in a case that the data belonging to a first clock domain is received at a receiving end of the clock domain conversion circuit; a processing module, configured to store the data sent by the sending module and convert a clock domain of the data from the first clock domain to a second clock domain through the processing unit; an obtaining module, configured to obtain the converted data from the processing unit through a second control unit of the processing unit; and an output module, configured to output the converted data obtained by the obtaining module through a sending end of the clock domain conversion circuit.

[0009] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, the memory storing programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the method of the second aspect.

[0010] In a fifth aspect, an embodiment of the present application provides a readable storage medium, the readable storage medium storing programs or instructions, and the programs or instructions are executed by the processor to implement the steps of the method of the second aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a chip, which comprises a processor and a communication interface, the communication interface is coupled with the processor, and the processor is configured to run programs or instructions to implement the method in the second aspect.

[0012] In a seventh aspect, an embodiment of the present application provides a computer program product stored in a storage medium, which is executed by at least one processor to implement the method in the second aspect.

[0013] In the embodiment of the present application, the clock domain conversion circuit comprises a first control unit, a processing unit, and a second control unit; the input end of the first control unit is connected with the receiving end of the clock domain conversion circuit; the input end of the processing unit is connected with the output end of the first control unit; the input end of the second control unit is connected with the output end of the processing unit, and the output end of the second control unit is connected with the sending end of the clock domain conversion circuit; the first control unit is configured to send the data to the processing unit when the data belonging to the first clock domain is obtained from the receiving end; the processing unit is configured to store the data and convert the clock domain of the data from the first clock domain to the second clock domain when the data is received from the first control unit; and the second control unit is configured to obtain the converted data from the processing unit and output the converted data through the sending end. Since the processing unit can not only convert the clock domain of the data from the first clock domain to the second clock domain, but also store the data (i.e., complete data), the second control unit can obtain the converted complete data from the processing unit at an appropriate time (for example, when the functional module connected with the sending end can identify and process the converted data in time) and output the converted complete data to the functional module, so that the functional module can accurately identify and process the converted complete data, and the converted complete data is received, thus, the situation that the functional module discards the converted data due to the inability to identify and process the converted data can be avoided, the situation that the converted data received by the functional module is incomplete can be avoided, and thus, the quality of data transmission between the functional modules belonging to different clock domains in the electronic device can be improved.

[0014] In the embodiment of the present application, in the case that the electronic device receives data belonging to the first clock domain at the receiving end of the clock domain conversion circuit, the electronic device can send the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit, and store the data and convert the clock domain of the data from the first clock domain to the second clock domain through the processing unit. Thus, the electronic device can obtain the converted data from the processing unit through the second control unit of the processing unit, and output the converted data through the sending end of the clock domain conversion circuit. After the data belonging to the first clock source is sent to the processing unit through the first control unit of the clock domain conversion circuit, the processing unit can not only convert the clock domain of the data from the first clock domain to the second clock domain, but also store the data (i.e. complete data). In this way, the electronic device can obtain the converted complete data from the processing unit through the second control unit at an appropriate time (for example, when the functional module connected to the sending end can identify and process the converted data in time), and output the converted complete data to the functional module through the output end, so that the functional module can accurately identify and process the converted complete data. Therefore, the functional module can avoid discarding the converted data due to the inability to identify and process the converted data, thereby avoiding the case that the converted data received by the functional module is incomplete. In this way, the quality of data transmission between functional modules belonging to different clock domains in the electronic device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is one of the data flow diagrams of the data sent from the functional module 1 to the functional module 2 in the related art;

[0016] FIG. 2 is another of the data flow diagrams of the data sent from the functional module 1 to the functional module 2 in the related art;

[0017] FIG. 3 is one of the data flow diagrams of the data sent from the functional module 1 to the functional module 2 and forwarded by the processing unit of the clock domain conversion circuit according to the embodiment of the present application;

[0018] FIG. 4 is another of the data flow diagrams of the data sent from the functional module 1 to the functional module 2 and forwarded by the processing unit of the clock domain conversion circuit according to the embodiment of the present application;

[0019] FIG. 5 is one of the circuit structure diagrams of the clock domain conversion circuit according to the embodiment of the present application;

[0020] FIG. 6 is another of the circuit structure diagrams of the clock domain conversion circuit according to the embodiment of the present application;

[0021] FIG. 7 is a third of the circuit structure diagrams of the clock domain conversion circuit according to the embodiment of the present application;

[0022] FIG. 8 is a circuit structure diagram of a first processing channel of a processing unit of the clock domain conversion circuit according to an embodiment of the present application;

[0023] FIG. 9 is a data processing timing diagram of the first processing channel of the processing unit of the clock domain conversion circuit according to an embodiment of the present application;

[0024] FIG. 10 is a fourth circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0025] FIG. 11 is a circuit structure diagram of a second processing channel of a processing unit of the clock domain conversion circuit according to an embodiment of the present application;

[0026] FIG. 12 is a data processing timing diagram of the second processing channel of the processing unit of the clock domain conversion circuit according to an embodiment of the present application;

[0027] FIG. 13A is a fifth circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0028] FIG. 13B is a sixth circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0029] FIG. 13C is a seventh circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0030] FIG. 14 is an eighth circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0031] FIG. 15 is a timing diagram of operation of data when the check unit of the clock domain conversion circuit is enabled according to an embodiment of the present application;

[0032] FIG. 16 is a timing diagram of operation of data when the check unit of the clock domain conversion circuit is disabled according to an embodiment of the present application;

[0033] FIG. 17 is a ninth circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0034] FIG. 18 is a tenth circuit structure diagram of the clock domain conversion circuit according to an embodiment of the present application;

[0035] FIG. 19 is a flow diagram of a clock domain conversion method according to an embodiment of the present application;

[0036] FIG. 20 is a structure diagram of a clock domain conversion apparatus according to an embodiment of the present application;

[0037] FIG. 21 is a hardware structure diagram of an electronic device according to an embodiment of the present application;

[0038] FIG. 22 is a second hardware structure diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0040] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", and the like are generally of a kind and are not limited in number, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0041] The clock domain conversion circuit, method and related device provided by the embodiments of the present application will be described in detail below with reference to the drawings, through specific embodiments and their application scenarios.

[0042] The clock domain conversion circuit provided by the embodiments of the present application can be applied to the scene of data transmission between two functional modules belonging to different clock domains in an electronic device.

[0043] At present, a system on chip (SOC) in an electronic device includes a plurality of functional modules, such as a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), etc. Part of the plurality of functional modules can belong to different clock domains, and the interfaces of the plurality of functional modules can be connected through a bus and an asynchronous FIFO, so that the plurality of functional modules can perform cross-clock domain data interaction through the bus and the asynchronous FIFO.

[0044] In the related art, assuming that the plurality of functional modules include two functional modules, for example, functional module 1 and functional module 2, the functional module 1 belongs to clock domain 1, and the functional module 2 belongs to clock domain 2, when the functional module 1 wants to send data (for example, data d0-d3) to the functional module 2, the functional module 1 can first send the data d0-d3 to the asynchronous FIFO through the bus, so that the asynchronous FIFO can convert the clock domain of the data d0-d3 from the clock domain 1 to the clock domain 2, and send the converted data d0-d3 to the functional module 2, so that the functional module 2 can accurately identify and process the converted data d0-d3 to use the processed data d0-d3. However, due to the limited data processing capability of the functional module 2, it may occur that the functional module 2 processes too much data and cannot timely identify and process the converted data, for example, as shown in FIG. 1, the interface of the functional module 1 and the functional module 2 does not support back pressure function (that is, when the functional module 2 processes too much data, the functional module 1 will not stop sending data), when the functional module 2 identifies and processes the converted data d0, the functional module 2 processes too much data and cannot timely identify and process the converted data, that is, the output end back pressure occurs, at this time the functional module 1 may still send subsequent data (that is, data d1-d3) to the asynchronous FIFO, so that the asynchronous FIFO sends the converted subsequent data d1-d3 to the functional module 2, in this way, the functional module 2 may discard the converted subsequent data (for example, discarding data d1 and data d2) due to the inability to identify and process the converted subsequent data d1-d3, therefore, it may cause the data received by the functional module 2 to be incomplete, that is, only data d1 and data d3 in data d0-d3 are received. Moreover, since it may occur that the functional module 1 sends the data d0-d3 to the asynchronous FIFO through the bus, and then waits for data to be sent, for example, as shown in FIG. 2, after the functional module 1 sends the data d0 and the data d1 to the asynchronous FIFO through the bus, it waits for data to be sent, that is, the functional module 1 sends the data d2 to the asynchronous FIFO through the bus again after waiting for a certain time, and after sending the data d2 to the asynchronous FIFO through the bus, it waits for data to be sent, that is, the functional module 1 sends the data d3 to the asynchronous FIFO through the bus again after waiting for a certain time, in this way, it may cause the converted data d0-d3 output by the asynchronous FIFO to be discontinuous, therefore, it may cause the data received by the functional module 2 to be discontinuous, in this way, the quality of data transmission between the functional modules belonging to different clock domains is affected.

[0045] However, in the embodiment of the present application, the clock domain conversion circuit can be arranged in the electronic device, and the interfaces of the plurality of functional modules can be connected through the bus and the clock domain conversion circuit. In this way, when the functional module 1 wants to send data (for example, data d0-d3) to the functional module 2, the functional module 1 can first send the data d0-d3 to the clock domain conversion circuit through the bus, so that the first control unit of the clock domain conversion circuit can receive the data d0-d3 through the receiving end and send the data d0-d3 to the processing unit of the clock domain conversion circuit. In this way, the clock domain conversion circuit can store the data d0-d3 and convert the clock domain of the data d0-d3 from the clock domain 1 to the clock domain 2. Next, the second control unit can obtain the converted data d0 from the processing unit and output the converted data d0 through the output end of the clock domain conversion circuit, so that the functional module 2 can receive the data d0. For example, as shown in FIG. 3, the interfaces of the functional module 1 and the functional module 2 do not support the back pressure function, and when the functional module 2 identifies and processes the converted data d0, the functional module 2 processes too much data and cannot identify and process the converted data in time. At this time, the second control unit can pause obtaining the converted data d1-d3 from the processing unit and continue obtaining the converted data d1-d3 from the processing unit at an appropriate time (for example, when the functional module 2 can identify and process the converted data in time) and outputting the converted data d1-d3 through the output end, so that the functional module 2 can accurately identify and process the converted data d1-d3, so that the functional module 2 can receive the converted data d0-d3 (that is, the complete converted data). Therefore, it can be avoided that the data received by the functional module 2 is incomplete. Moreover, when the functional module 1 sends the data d0-d3 to the clock domain conversion circuit through the bus and waits to send data, for example, as shown in FIG. 4, after the functional module 1 sends the data d0 and the data d1 to the clock domain conversion circuit through the bus, the functional module 1 waits to send data, that is, the functional module 1 sends the data d2 to the clock domain conversion circuit through the bus again after waiting for a certain time, and after the functional module 1 sends the data d2 to the clock domain conversion circuit through the bus, the functional module 1 waits to send data, that is, the functional module 1 sends the data d3 to the clock domain conversion circuit through the bus again after waiting for a certain time. At this time, the processing unit in the clock domain conversion circuit can store the data d0-d3. In this way, the second control module can obtain the converted data d0-d3 from the processing unit at an appropriate time (for example, when the processing unit converts a certain amount of data) and continuously output the converted data d0-d3 through the output end, so that the converted data d0-d3 can be continuously outputted, and thus it can be avoided that the converted data received by the functional module 2 is discontinuous. In this way, the quality of data transmission between functional modules belonging to different clock domains is improved.

[0046] FIG. 5 shows a circuit structure diagram of the clock domain conversion circuit provided in the embodiments of the present application. As shown in FIG. 5, the clock domain conversion circuit provided in the embodiments of the present application can include: a first control unit 10, an input end 101 of the first control unit 10 being connected with a receiving end 11 of the clock domain conversion circuit; a processing unit 12, an input end 121 of the processing unit 12 being connected with an output end 102 of the first control unit 10; a second control unit 13, an input end 131 of the second control unit 13 being connected with an output end 122 of the processing unit 12, and an output end 132 of the second control unit 13 being connected with a sending end 14 of the clock domain conversion circuit.

[0047] In some embodiments of the present application, the receiving end 11 can be connected with at least one functional module in the electronic device, so that the receiving end 11 can receive data belonging to the first clock domain from an interface of the at least one functional module.

[0048] In some embodiments of the present application, the first control unit 10 can be any one of the following: a CPU, a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, and a microprocessor. Of course, the first control unit 10 can also be other control units, which are not limited in the embodiments of the present application.

[0049] In some embodiments of the present application, the first control unit 10 can be referred to as a write control unit. Of course, the first control unit 10 can also be referred to as other units, which are not limited in the embodiments of the present application.

[0050] In the embodiments of the present application, the first control unit 10 is configured to send data to the processing unit 12 in the case of obtaining data belonging to the first clock domain from the receiving end 11.

[0051] In some embodiments of the present application, the first control unit 10 belongs to the first clock domain. It can be understood that in the case of rising or falling edge of the clock signal of the first clock domain, the first control unit 10 can receive data from the receiving end 11 and send data to the processing unit 12.

[0052] In some examples, the first control unit 10 can send a write data request signal to the processing unit 12 in a case where data is received from the receiving end 11, so that the processing unit 12 can determine whether the amount of data received by the processing unit 12 reaches the upper limit, and send a full signal to the first control unit 10 in a case where it is determined that the amount of received data reaches the upper limit, the full signal being used to indicate that the amount of data received by the processing unit 12 reaches the upper limit, or not send the full signal to the first control unit 10 in a case where it is determined that the amount of received data does not reach the upper limit. Thus, the first control unit 10 can determine whether the full signal is received within a first preset time period from the time when the write data request signal is sent, and send the write data request signal to the processing unit 12 again after a second preset time period in a case where the full signal is received, or can send data to the processing unit 12 in a case where the full signal is not received.

[0053] It can be understood that, since the first control unit 10 can first send the write data request signal to the processing unit 12, so that the processing unit 12 can determine whether the amount of data received by the processing unit 12 reaches the upper limit, and indicate to the first control unit 10 whether the amount of data received by the processing unit 12 reaches the upper limit, the first control unit 10 can send data to the processing unit 12 only in a case where the amount of data received by the processing unit 12 does not reach the upper limit, so that the situation that the processing unit 12 cannot receive data due to the amount of data received by the processing unit 12 reaching the upper limit, and thus the data to be transmitted is lost, can be avoided.

[0054] In the embodiment of the present application, the processing unit 12 is configured to store data and convert the clock domain of the data from the first clock domain to the second clock domain in a case where data is received from the first control unit 10.

[0055] In the embodiment of the present application, the second clock domain is different from the first clock domain.

[0056] It should be noted that, the order of storing data and converting the clock domain of the data from the first clock domain to the second clock domain by the processing unit 12 is not limited in the embodiment of the present application. In one example, the processing unit 12 can first store data, and then convert the clock domain of the data from the first clock domain to the second clock domain; in another example, the processing unit 12 can first convert the clock domain of the data from the first clock domain to the second clock domain, and then store the data.

[0057] In some embodiments of the present application, the input end 121 of the processing unit 12 described above can belong to a first clock domain, and the output end 122 of the processing unit 12 can belong to a second clock domain. It can be understood that, in the case that the processing unit 12 stores data first and then converts the clock domain of the data from the first clock domain to the second clock domain, the processing unit 12 can store the data when the clock signal of the first clock domain appears in the rising or falling edge, and the processing unit 12 can convert the clock domain of the data from the first clock domain to the second clock domain when the clock signal of the second clock domain appears in the rising or falling edge. In the case that the processing unit 12 converts the clock domain of the data from the first clock domain to the second clock domain first and then stores the data, the processing unit 12 can convert the clock domain of the data from the first clock domain to the second clock domain when the clock signal of the first clock domain appears in the rising or falling edge, and the processing unit 12 can store the data when the clock signal of the second clock domain appears in the rising or falling edge.

[0058] In some embodiments of the present application, the processing unit 12 described above can include at least one processing channel, and the processing channel can include at least one memory and at least one asynchronous FIFO. It can be understood that the processing unit 12 can store data through the memory and convert the clock domain of the data from the first clock domain to the second clock domain through the asynchronous FIFO.

[0059] In some examples, the memory described above can include at least one of the following: a static random access memory (SRAM), a random access memory (RAM). Of course, the memory can also be other storage devices, and the embodiments of the present application are not limited here.

[0060] It should be noted that the description of converting the clock domain of the data from the first clock domain to the second clock domain by the asynchronous FIFO can refer to the specific description in the related art, and the embodiments of the present application will not be repeated here.

[0061] In some examples, each of the at least one processing channel can first store the data and then convert the clock domain of the data from the first clock domain to the second clock domain. Wherein the input end of the at least one memory and the at least one asynchronous FIFO of each processing channel belongs to the first clock domain, and the output end of the at least one asynchronous FIFO belongs to the second clock domain, so that the at least one memory can obtain the data from the first control unit 10 and send the data to the at least one asynchronous FIFO when the clock signal of the first clock domain appears rising or falling edge, and the at least one asynchronous FIFO can convert the clock domain of the data from the first clock domain to the second clock domain when the clock signal of the second clock domain appears rising or falling edge.

[0062] In other examples, each of the at least one processing channel can first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data. Wherein the input end of the at least one asynchronous FIFO belongs to the first clock domain, and the output end of the at least one asynchronous FIFO and the at least one memory belong to the second clock domain, so that the at least one asynchronous FIFO can obtain the data from the first control unit 10 when the clock signal of the first clock domain appears rising or falling edge, and the at least one asynchronous FIFO can convert the clock domain of the data from the first clock domain to the second clock domain and send the converted data to the at least one memory when the clock signal of the second clock domain appears rising or falling edge, so that the at least one memory can store the converted data.

[0063] In yet other examples, a part of the at least one processing channel can first store the data and then convert the clock domain of the data from the first clock domain to the second clock domain, and another part of the at least one processing channel can first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data. Wherein the input end of the at least one memory and the at least one asynchronous FIFO of the part of the processing channel belongs to the first clock domain, and the output end of the at least one asynchronous FIFO belongs to the second clock domain; the input end of the at least one asynchronous FIFO of the other part of the processing channel belongs to the first clock domain, and the output end of the at least one asynchronous FIFO and the at least one memory belong to the second clock domain.

[0064] The following will be illustrated by taking at least one processing channel including two processing channels as an example.

[0065] In some embodiments of the present application, as shown in Figure 6, the processing unit 12 comprises a first processing channel 123, an input end 1231 of the first processing channel 123 being connected with the output end 102 of the first control unit 10, and an output end 1232 of the first processing channel 123 being connected with the input end 131 of the second control unit 13; and a second processing channel 124, an input end 1241 of the second processing channel 124 being connected with the output end 102 of the first control unit 10, and an output end 1242 of the second processing channel 124 being connected with the input end 131 of the second control unit 13.

[0066] In the embodiments of the present application, the first processing channel 123 is configured to store the data received from the first control unit 10 and convert the clock domain of the data from the first clock domain to the second clock domain.

[0067] In some embodiments of the present application, the input end 1231 of the first processing channel 123 belongs to the first clock domain, and the output end 1232 of the first processing channel 123 belongs to the second clock domain.

[0068] In some embodiments of the present application, the first processing channel 123 can comprise at least one memory and at least one asynchronous FIFO, an input end of the at least one memory being connected with the output end 102 of the first control unit 10, and an output end of the at least one asynchronous FIFO being connected with the input end 131 of the second control unit 13, the at least one memory and the at least one asynchronous FIFO being connected in series and / or in parallel. Thus, the first processing channel 123 can store the data received from the first control unit 10 and convert the clock domain of the data from the first clock domain to the second clock domain. In this case, the input end of the at least one memory and the at least one asynchronous FIFO of the first processing channel 123 belongs to the first clock domain, and the output end of the at least one asynchronous FIFO belongs to the second clock domain.

[0069] In the embodiments of the present application, since the first clock domain and the second clock domain are different, the frequency of the clock signal of the first clock domain and the frequency of the clock signal of the second clock domain are also different, and thus the frequency of the clock signal of the first clock domain can be greater than the frequency of the clock signal of the second clock domain. In this case, if the first processing channel 123 first converts the clock domain of the data from the first clock domain to the second clock domain and then stores the data, that is, the rate of the asynchronous FIFO input data is greater than the rate of the asynchronous FIFO output data (and the rate of the storage of the memory for storing the converted data), the asynchronous FIFO can not be able to receive data due to the small storage space of the asynchronous FIFO, and thus data loss can occur, and the utilization rate of the memory can be low due to the slow rate of the asynchronous FIFO output of the converted data and the small amount of data that can be stored in the memory.

[0070] The following will be described by taking an example in which the first processing channel 123 includes one memory and one asynchronous FIFO.

[0071] In some embodiments of the present application, in combination with FIG. 5 and FIG. 6, as shown in FIG. 7, the first processing channel 123 includes: a first memory 1233, an input end 12331 of the first memory 1233 being connected with an output end 102 of the first control unit 10; and a first asynchronous FIFO 1234, an input end 12341 of the first asynchronous FIFO 1234 being connected with an output end 12332 of the first memory 1233, and an output end 12342 of the first asynchronous FIFO 1234 being connected with an input end 131 of the second control unit 13.

[0072] In some embodiments of the present application, the first memory 1233 can include at least one of a static random access memory (SRAM) and a random access memory (RAM). Of course, the first memory 1233 can also be other memory devices, which are not limited in the embodiments of the present application.

[0073] In the embodiments of the present application, the first memory 1233 is used to store data.

[0074] In some embodiments of the present application, the first control unit 10 can send a write data request signal to the first memory 1233 when a rising or falling edge of the clock signal in the first clock domain occurs in the case of receiving data from the receiving end 11, so that the first memory 1233 can determine whether the amount of data received by the first memory 1233 reaches an upper limit when a rising or falling edge of the clock signal in the first clock domain occurs, in combination with FIG. 7, as shown in FIG. 8, and send a full signal buf_full to the first control unit 10 when a rising or falling edge of the clock signal in the first clock domain occurs in the case of determining that the amount of received data reaches the upper limit, the full signal buf_full being used to indicate that the amount of data received by the first memory 1233 reaches the upper limit, or not send the full signal buf_full to the first control unit 10 in the case of determining that the amount of received data does not reach the upper limit. Thus, the first control unit 10 can determine whether the full signal buf_full is received within a first preset time length from the time when the write data request signal is sent when a rising or falling edge of the clock signal in the first clock domain occurs, and wait for a second preset time length after receiving the full signal buf_full, and then send the write data request signal to the first memory 1233 again when a rising or falling edge of the clock signal in the first clock domain occurs, or can send a buf_wr signal to the first memory 1233 when a rising or falling edge of the clock signal in the first clock domain occurs in the case of not receiving the full signal buf_full, the buf_wr signal being used to carry the above-mentioned data. Then, the first memory 1233 can send an afifo_wr signal to the first asynchronous FIFO 1234 when a rising or falling edge of the clock signal in the first clock domain occurs, the afifo_wr signal being used to carry the above-mentioned data, so that the first asynchronous FIFO 1234 can receive the data.

[0075] In the embodiments of the present application, the first asynchronous FIFO 1234 is used to convert the clock domain of data from the first clock domain to the second clock domain.

[0076] It should be noted that the description of converting the clock domain of data from the first clock domain to the second clock domain by the first asynchronous FIFO 1234 can refer to the specific description in the related art, which will not be repeated here.

[0077] In some embodiments of the present application, in combination with FIG. 8, when the first asynchronous FIFO 1234 does not receive data, the first asynchronous FIFO 1234 can send an empty signal afifo_empty to the second control unit 13 at the rising or falling edge of the clock signal of the second clock domain, the empty signal afifo_empty being used to indicate that no data is stored in the first asynchronous FIFO 1234, so as to avoid the second control unit 13 obtaining data from the first asynchronous FIFO 1234 at the rising or falling edge of the clock signal of the second clock domain. Moreover, the first asynchronous FIFO 1234 can obtain the data from the first memory 1233 at the rising or falling edge of the clock signal of the first clock domain, and convert the clock domain of the data from the first clock domain to the second clock domain at the rising or falling edge of the clock signal of the second clock domain, and then stop sending the empty signal afifo_empty to the second control unit 13, so that the second control unit 13 can obtain the converted data from the first asynchronous FIFO 1234 at the rising or falling edge of the clock signal of the second clock domain, for example, at an appropriate time (for example, the functional module connected to the sending end 14 can recognize and process the converted data in time).

[0078] In the embodiments of the present application, the first processing channel 123 can first store data in the first memory 1233, and then convert the clock domain of the data from the first clock domain to the second clock domain through the first asynchronous FIFO 1234, so as to avoid the case that the utilization rate of the first memory 1233 is low and data is lost when the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain.

[0079] Exemplarily, FIG. 9 shows a data processing timing diagram of the first processing channel 123. It is assumed that the input end 12341 of the first asynchronous FIFO 1234 of the first processing channel 123 is connected with the output end 102 of the first control unit 10, the output end 12342 of the first asynchronous FIFO 1234 is connected with the input end 12331 of the first memory 1233, and the output end 12332 of the first memory 1233 is connected with the input end 131 of the second control unit 13, i.e. it is assumed that the first processing channel 123 firstly converts the clock domain of data from the first clock domain to the second clock domain, and then stores the data, the frequency of the clock signal rx_clk of the first clock domain is twice the frequency of the clock signal co_clk of the second clock domain, the depth of the first asynchronous FIFO 1234 is 4, and the storage space of the first memory 1233 is greater than the storage space of the first asynchronous FIFO 1234. As shown in FIG. 9, when the clock signal rx_clk has a rising edge at T0, the first asynchronous FIFO 1234 can receive data (for example, data d0-d5) from the first control unit 10, at this time, the first control unit 10 sends an afifo_wr signal to the first asynchronous FIFO 1234, and the afifo_wr signal is used to carry the data d0-d5, i.e. the afifo_wr signal becomes high at T0, so that the first asynchronous FIFO 1234 can convert the clock domain of the received data from the first clock domain to the second clock domain when the clock signal co_clk has a rising edge after the time of receiving the data and after one clock cycle of the clock signal co_clk, however, since the depth of the first asynchronous FIFO 1234 is 4, when the first asynchronous FIFO 1234 receives four data (i.e. data d0-d3), the storage space of the first asynchronous FIFO 1234 is full, at this time, the first asynchronous FIFO 1234 can send a full signal afifo_full to the first control unit 10 when the clock signal co_clk has a falling edge (i.e. at T1), i.e. the afifo_wr signal becomes high at T1, and stop sending an empty signal afifo_empty to the first memory 1233 when the clock signal co_clk has a falling edge after the first asynchronous FIFO 1234 receives the data d1.In this way, the first control unit 10 can stop sending the afifo_wr signal to the first asynchronous FIFO 1234 at the rising edge of the clock signal rx_clk after the time when the full signal afifo_full is received and after one clock cycle of the clock signal rx_clk, but the first control unit 10 can have already sent the data D4 and the data D5, and thus the data D4 and the data D5 can be lost due to the fact that the first asynchronous FIFO 1234 cannot receive the data D4 and the data D5; and the first memory 1233 can send the afifo_rd signal to the first memory 1233 at the rising edge of the clock signal co_clk after the time when the empty signal afifo_empty is not received and after one clock cycle of the clock signal co_clk, and the afifo_rd signal can only carry the data d0 at this time because the first asynchronous FIFO 1234 can only convert the clock domain of the data d0 from the first clock domain to the second clock domain, that is, the first memory 1233 can only store one data (i.e., the data d0) at this time, and thus the utilization rate of the first memory 1233 is low. It can be known from the above that, in the case where the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, if the data is to be stored and the clock domain of the data is to be converted from the first clock domain to the second clock domain through the first processing channel 123, the data should be stored first and then the clock domain of the data is converted from the first clock domain to the second clock domain.

[0080] It can be known in this way that, since the output end of the first control unit is connected to the first memory and the first asynchronous FIFO in sequence, the data can be stored first and then the clock domain of the data is converted from the first clock domain to the second clock domain when the data is stored and the clock domain of the data is converted from the first clock domain to the second clock domain through the first processing channel, and thus the utilization rate of the first memory is low and the data is lost due to the fact that the storage space of the first asynchronous FIFO is full in the case where the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain.

[0081] In the embodiments of the present application, the second processing channel 124 is used to convert the clock domain of the data from the first clock domain to the second clock domain first and then store the data in the case where the data is received from the first control unit 10.

[0082] In some embodiments of the present application, the input end 1241 of the second processing channel 124 belongs to the first clock domain, and the output end of the second processing channel 124 belongs to the second clock domain.

[0083] In some embodiments of the present application, the second processing channel 124 can include at least one memory and at least one asynchronous FIFO, an input end of the at least one asynchronous FIFO can be connected with the output end 102 of the first control unit 10, an output end of the at least one memory can be connected with the input end 131 of the second control unit 13, and the at least one memory and the at least one asynchronous FIFO can be connected in series and / or in parallel. Thus, the second processing channel 124 can first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data in the case of receiving the data from the first control unit 10. Wherein, the input end of the at least one asynchronous FIFO of the second processing channel 124 belongs to the first clock domain, and the output end of the at least one memory and the at least one asynchronous FIFO belongs to the second clock domain.

[0084] In the embodiments of the present application, since the first clock domain and the second clock domain are different, the frequency of the clock signal of the first clock domain and the frequency of the clock signal of the second clock domain are also different, so that the frequency of the clock signal of the first clock domain can be less than the frequency of the clock signal of the second clock domain. The output rate of the asynchronous FIFO (and the storage rate of the converted data in the memory) is greater than the input rate of the asynchronous FIFO, therefore, the second processing channel 124 can first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data, so as to reduce the time of storing the converted data into the memory.

[0085] In the following, an example of the second processing channel 124 including one memory and one asynchronous FIFO will be described.

[0086] In some embodiments of the present application, as shown in FIG. 10, in combination with FIG. 5 and FIG. 6, the second processing channel 124 includes: a second asynchronous FIFO 1243, an input end 12431 of the second asynchronous FIFO 1243 is connected with the output end 102 of the first control unit 10; and a second memory 1244, an input end 12441 of the second memory 1244 is connected with an output end 12432 of the second asynchronous FIFO 1243, and an output end 12442 of the second memory 1244 is connected with the input end 131 of the second control unit 13.

[0087] In the embodiments of the present application, the second asynchronous FIFO 1243 is used to convert the clock domain of the data from the first clock domain to the second clock domain.

[0088] It should be noted that the description of converting the clock domain of the data from the first clock domain to the second clock domain by the second asynchronous FIFO 1243 can refer to the specific description in the related art, and the embodiments of the present application will not be described here.

[0089] In some embodiments of the present application, the first control unit 10 can send a write data request signal to the second asynchronous FIFO 1243 when a rising or falling edge of the clock signal in the first clock domain occurs in the case of receiving data from the receiving end 11, so that the second asynchronous FIFO 1243 can determine whether the amount of data received by the second asynchronous FIFO 1243 reaches an upper limit when a rising or falling edge of the clock signal in the first clock domain occurs, in combination with FIG. 11, and send a full signal afifo_full to the first control unit 10 when a rising or falling edge of the clock signal in the first clock domain occurs in the case of determining that the amount of received data reaches the upper limit, the full signal afifo_full being used to indicate that the amount of data received by the second asynchronous FIFO 1243 reaches the upper limit, or not sending the full signal afifo_full to the first control unit 10 in the case of determining that the amount of received data does not reach the upper limit. Thus, the first control unit 10 can determine whether the full signal afifo_full is received within a first preset time length from the time when the write data request signal is sent when a rising or falling edge of the clock signal in the first clock domain occurs, and wait for a second preset time length after the full signal afifo_full is received, and then send the write data request signal to the second asynchronous FIFO 1243 again when a rising or falling edge of the clock signal in the first clock domain occurs, or can send the afifo_wr signal to the second asynchronous FIFO 1243 when a rising or falling edge of the clock signal in the first clock domain occurs in the case of not receiving the full signal afifo_full, the afifo_wr signal being used to carry the data. Next, the second asynchronous FIFO 1243 can convert the clock domain of the data from the first clock domain to the second clock domain when a rising or falling edge of the clock signal in the second clock domain occurs, and send the buf_wr signal to the second memory 1244, the buf_wr signal being used to carry the converted data.

[0090] In some embodiments of the present application, the second memory 1244 described above can include at least one of a static random access memory (SRAM) and a random access memory (RAM). Of course, the second memory 1244 can also be other storage devices, which are not limited herein.

[0091] In the embodiments of the present application, the second memory 1244 described above is used to store data.

[0092] In some embodiments of the present application, in combination with FIG. 11, when the second memory 1244 does not receive data, the second memory 1244 can send an empty signal buf_empty to the second control unit 13 when the clock signal of the second clock domain appears a rising edge or a falling edge, the empty signal buf_empty being used to indicate that no data is stored in the second memory 1244, so as to avoid the second control unit 13 obtaining data from the second memory 1244 when the clock signal of the second clock domain appears a rising edge or a falling edge. Moreover, the second memory 1244 can obtain the converted data from the second asynchronous FIFO 1243 when the clock signal of the second clock domain appears a rising edge or a falling edge, and stop sending the empty signal buf_empty to the second control unit 13, so that the second control unit 13 can obtain a buf_rd signal from the second memory 1244 when the clock signal of the second clock domain appears a rising edge or a falling edge, the buf_rd signal being used to carry the converted data, for example, at an adaptive timing (for example, the functional module connected with the sending end 14 can identify and process the converted data in time).

[0093] In the embodiments of the present application, the second processing channel 124 can first convert the clock domain of data from the first clock domain to the second clock domain through the second asynchronous FIFO 1243, and then store the converted data in the second memory 1244, so as to reduce the time of storing the converted data in the second memory 1244.

[0094] Exemplarily, FIG. 12 shows a data processing timing diagram of the second processing channel 124. It is assumed that the frequency of the clock signal co_clk of the second clock domain is twice the frequency of the clock signal rx_clk of the first clock domain, the depth of the second asynchronous FIFO 1243 is 4, and the storage space of the second memory 1244 is larger than that of the second asynchronous FIFO 1243. As shown in FIG. 12, when the clock signal rx_clk has a rising edge at T0, the second asynchronous FIFO 1243 can receive data (for example, data d0-d4) from the first control unit 10. At this time, the first control unit 10 sends the afifo_wr signal to the second asynchronous FIFO 1243, and the afifo_wr signal carries the data d0-d4, that is, the afifo_wr signal becomes high at T0, so that the second asynchronous FIFO 1243 can convert the clock domain of the received data d0 from the first clock domain to the second clock domain when the clock signal co_clk has a rising edge after the time of receiving the data (that is, data d0) and one clock period of the clock signal co_clk, and sends the afifo_rd signal to the second memory 1244 when the clock signal co_clk has a rising edge after one clock period of the clock signal co_clk (that is, at T1), that is, the afifo_rd signal carries the converted data, and the afifo_rd signal becomes high at T1, so that the second memory 1244 can store the converted data d0, and the second asynchronous FIFO 1243 can send the afifo_empty signal to the second memory 1244, and the afifo_empty signal indicates that the second asynchronous FIFO 1243 does not store any data, that is, the afifo_rd signal becomes low at T1, so as to avoid the second memory 1244 reading data from the second asynchronous FIFO 1243 when the clock signal co_clk has a rising edge. In this way, the converted data d1-d4 are sent to the second memory 1244. Furthermore, after the second memory 1244 stores the converted data d0, one clock period of the clock signal co_clk (for example, at T2), the second memory 1244 can stop sending the buf_empty signal to the second control unit 13, and the buf_empty signal indicates that the second memory 1244 does not store any data, that is, the buf_empty signal becomes low at T2.Thus, the second control unit 13 can read the converted data from the second memory 1244 at an appropriate time (for example, when the converted data d0-d4 is stored in the second memory 1244), for example, at time T3. That is, the second memory 1244 sends a buf_rd signal to the second control unit 13, where the buf_rd signal carries the converted data. At time T3, the buf_rd signal becomes high, and thus the second control unit 13 can receive the converted data d0-d4. It can be understood that, since the second control unit 13 reads the converted data from the second memory 1244 at an appropriate time, the second control unit 13 can continuously obtain the converted data d0-d4. It can be understood that, since the second asynchronous FIFO 1243 can store the converted data in the second memory 1244 in time, the storage space of the second asynchronous FIFO 1243 will not be full of data during the transmission of the data d0-d4, that is, the afifo_full signal is always low.

[0095] Thus, it can be known that, since the output end of the first control unit can be connected to the second asynchronous FIFO and the second memory in sequence, when storing data through the second processing channel and converting the clock domain of the data from the first clock domain to the second clock domain, the clock domain of the data is first converted from the first clock domain to the second clock domain, and then the data is stored. Thus, the time for storing the converted data in the second memory is reduced, and thus the time for processing the data through the second processing channel can be reduced.

[0096] In the embodiment of the present application, the first control unit 10 is specifically configured to send data to the first processing channel 123 when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain, or send data to the second processing channel 124 when the frequency of the clock signal in the first clock domain is less than the frequency of the clock signal in the second clock domain.

[0097] It can be understood that, when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain, the first control unit 10 can send data to the first processing channel 123 to process the data through the first processing channel 123; or when the frequency of the clock signal in the first clock domain is less than the frequency of the clock signal in the second clock domain, the first control unit 10 can send data to the second processing channel 124 to process the data through the second processing channel 124.

[0098] In summary, since the first control unit can select the first processing channel or the second processing channel to process data according to the size relationship between the frequency of the clock signal of the first clock domain and the frequency of the clock signal of the second clock domain, in the case that the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, the situation that the utilization of the first memory is low and data is lost due to the full storage space of the first asynchronous FIFO can be avoided; or in the case that the frequency of the clock signal of the first clock domain is less than the frequency of the clock signal of the second clock domain, the time-consuming of processing data by the second processing channel can be reduced.

[0099] In some embodiments of the present application, the second control unit 13 can be any one of the following: a CPU, a PLD, an FPGA, a controller, a microcontroller, and a microprocessor. Of course, the second control unit 13 can also be other control units, which are not limited in the embodiments of the present application.

[0100] In some embodiments of the present application, the second control unit 13 can be referred to as a reading control unit. Of course, the second control unit 13 can also be referred to as other units, which are not limited in the embodiments of the present application.

[0101] In the embodiments of the present application, the second control unit 13 is configured to obtain the converted data from the processing unit 12 and output the converted data through the sending end 14.

[0102] In some embodiments of the present application, the second control unit 13 can obtain the converted data from the processing unit 12 at an appropriate time and output the converted data through the sending end 14.

[0103] The appropriate time can include that the functional module connected to the sending end 14 can timely identify and process the converted data. The appropriate time can also include that the processing unit 12 converts a certain amount of data, and the amount can be pre-set. Of course, the appropriate time can also include other times, which can be set according to the needs of those skilled in the art, and are not limited in the embodiments of the present application.

[0104] The embodiment of the present application provides a clock domain conversion circuit, which comprises a first control unit connected with a receiving end of the clock domain conversion circuit, a processing unit connected with an output end of the first control unit, and a second control unit connected with an input end of the processing unit and an output end of the clock domain conversion circuit; wherein the first control unit is used for sending data to the processing unit in the case that the data belonging to a first clock domain is obtained from the receiving end; the processing unit is used for storing the data and converting the clock domain of the data from the first clock domain to a second clock domain in the case that the data is received from the first control unit; and the second control unit is used for obtaining the converted data from the processing unit and outputting the converted data through the output end. Since the processing unit can not only convert the clock domain of the data from the first clock domain to the second clock domain, but also store the data (i.e. complete data), the second control unit can obtain the converted complete data from the processing unit at an appropriate time (for example, when the functional module connected with the output end can identify and process the converted data in time) and output the converted complete data to the functional module, so that the functional module can accurately identify and process the converted complete data, and the converted complete data is received, thus the situation that the functional module discards the converted data due to the inability to identify and process the converted data can be avoided, the situation that the converted data received by the functional module is incomplete can be avoided, and thus the quality of data transmission of the functional module belonging to different clock domains in the electronic equipment can be improved.

[0105] Moreover, since the processing unit can not only convert the clock domain of the data from the first clock domain to the second clock domain, but also store the data (i.e. complete data), the second control unit can obtain the converted data from the processing unit at an appropriate time (for example, when the processing unit converts a certain amount of data) and continuously output the converted data through the output end, so that the situation that the converted data is not continuous can be avoided, the situation that the data received by the functional module connected with the output end is not continuous can be avoided, and thus the quality of data transmission of the functional module belonging to different clock domains in the electronic equipment can be improved.

[0106] Of course, in order to ensure the accuracy of the data transmitted by the functional module belonging to different clock domains in the electronic equipment, a verification unit can also be arranged in the clock domain conversion circuit to determine whether the data is incorrect through the verification unit, which will be illustrated below.

[0107] In some embodiments of the present application, the clock domain conversion circuit further comprises a verification unit connected with at least one of the first control unit 10 and the second control unit 13.

[0108] It should be noted that the structure of the verification unit can be described in the related art, and the embodiments of the present application will not be described here.

[0109] In some embodiments of the present application, the number of the above-mentioned verification units can be at least one.

[0110] In some examples, when the number of the verification units is one, the verification unit can be connected with the first control unit 10, and / or the verification unit can be connected with the second control unit 13.

[0111] For example, assuming that the number of the above-mentioned verification units is one, in combination with FIG. 5, as shown in FIG. 13A, the verification unit 15 can be connected with the first control unit 10. Alternatively, in combination with FIG. 5, as shown in FIG. 13B, the verification unit 15 can be connected with the second control unit 13. Alternatively, in combination with FIG. 5, as shown in FIG. 13C, the verification unit 15 can be connected with the first control unit 10 and the second control unit 13.

[0112] In other examples, when the number of the verification units is at least two, at least one of the verification units can be connected with the first control unit 10, and at least one of the other verification units can be connected with the second control unit 13. It can be understood that a larger number of verification units can be set to check the above-mentioned data a larger number of times, so as to accurately determine the data with packet loss and the data without packet loss, discard the data with packet loss and send the data without packet loss, thereby ensuring the accuracy of the data sent.

[0113] For example, assuming that the number of the above-mentioned verification units is at least two, in combination with FIG. 5, as shown in FIG. 14, the verification units can include a verification unit 16 and a verification unit 17, the verification unit 16 can be connected with the first control unit 10, and the verification unit 17 can be connected with the second control unit 13.

[0114] In the embodiments of the present application, the above-mentioned verification unit is used to control the connected control unit to send the data acquired by the connected control unit when it is determined that the data acquired by the connected control unit does not have packet loss, or control the connected control unit to discard the data acquired by the connected control unit when it is determined that the data acquired by the connected control unit has packet loss.

[0115] It should be noted that the process of determining whether the data acquired by the connected control unit has packet loss by the verification unit can be described in the related art, and the embodiments of the present application will not be described here.

[0116] It can be understood that, in the case that the checking unit is connected with the first control unit 10, the checking unit is configured to control the first control unit 10 to send the acquired data to the processing unit 12 in the case that there is no packet loss in the data acquired by the first control unit 10, or control the first control unit 10 to discard the acquired data in the case that it is determined that there is packet loss in the data acquired by the first control unit 10. And / or, in the case that the checking unit is connected with the second control unit 13, the checking unit is configured to control the second control unit 13 to send the acquired data to the processing unit 12 in the case that there is no packet loss in the data acquired by the second control unit 13, or control the second control unit 13 to discard the acquired data in the case that it is determined that there is packet loss in the data acquired by the second control unit 13.

[0117] In some embodiments of the present application, in the case that the checking function of the checking unit is enabled, the checking unit is configured to control the connected control unit to send the acquired data in the case that it is determined that there is no packet loss in the data acquired by the connected control unit, or control the connected control unit to discard the acquired data in the case that it is determined that there is packet loss in the data acquired by the connected control unit.

[0118] For example, FIG. 15 shows a timing diagram of the operation of the checking unit on data when the checking function of the checking unit is enabled. It is assumed that the checking unit is connected with the first control unit 10, as shown in FIG. 15, the first control unit 10 can receive data (for example, data d0-d5) from the sending end 14 of the clock domain conversion circuit when the rising or falling edge of the clock signal in the first clock domain occurs, at this time, the checking unit can check the data d0-d5. If the checking unit determines that there is packet loss in the data d0-d5, the checking unit can send a check_error signal to the first control unit 10, the check_error signal is used to indicate that there is packet loss in the data d0-d5, that is, the check_error signal can change to high level, so that the first control unit 10 will not send an afifo_wr signal to the processing unit 12, the afifo_wr signal is used to carry the data d0-d5, that is, the afifo_wr signal maintains at low level, that is, the processing unit 12 will not store the data d0-d5 and convert the clock domain of the data d0-d5 from the first clock domain to the second clock domain.

[0119] For example, FIG. 16 shows a timing diagram of the operation of the data when the check unit is closed. As shown in FIG. 16, the first control unit 10 can receive the data (for example, data d0-d5) from the sending end 14 of the clock domain conversion circuit when the rising or falling edge of the clock signal of the first clock domain occurs, and the check unit does not check the data d0-d5 because the check unit is closed, that is, the check_error signal is maintained at a low level, so that the first control unit 10 can send the afifo_wr signal to the processing unit 12, and the afifo_wr signal carries the data d0-d5, that is, the afifo_wr signal can change to a high level, and the processing unit 12 can store the data d0-d5 and convert the clock domain of the data d0-d5 from the first clock domain to the second clock domain regardless of whether the data d0-d5 has a packet loss.

[0120] Therefore, the check unit can control the connected control unit to discard the data with packet loss or control the connected control unit to send the data without packet loss, that is, the check unit can control the connected control unit to discard the error data or control the connected control unit to send the accurate data, so that the accuracy of the sent data can be ensured.

[0121] Of course, in order to ensure that the converted data output by the sending end of the clock domain conversion circuit is continuous data, a counting unit can also be arranged in the clock domain conversion circuit to determine whether the converted data stored in the processing unit 12 is sufficient, which will be illustrated below.

[0122] In some embodiments of the present application, as shown in FIG. 17, the clock domain conversion circuit further comprises a counting unit 18 connected to the processing unit 12 and the second control unit 13.

[0123] In the embodiments of the present application, the counting unit 18 is used to record the number of the converted data stored in the processing unit 12. The second control unit 13 is specifically configured to acquire the converted data from the processing unit 12 when the number of the converted data recorded by the counting unit 18 is greater than or equal to a predetermined number.

[0124] In some embodiments of the present application, the counting unit 18 can first acquire the data output position required by each output data, and then determine the predetermined number according to the data related information and the data output position, and determine whether the number of the data stored in the processing unit 12 is greater than or equal to the predetermined number.

[0125] In some examples, assuming that the above data is data of an image, and the above data output position is the end of each row of pixels of the image, the counting unit 18 can first obtain the data output position required for each output data (for example, the end of each row of pixels), and determine the above predetermined number value according to the number of each row of pixels of the data of the image and the end of each row of pixels, the predetermined number value is equal to the number of each row of pixels of the image, so that in the case that the number value of the data of the image input in the processing unit 12 is greater than or equal to the above predetermined number value, the counting unit 18 can increase the counting value by 1, the counting value is used to indicate the number of a row of pixels stored in the processing unit 12, so that the second control unit 13 can obtain the converted data from the processing unit 12 in the case that the counting value of the counting unit 18 is greater than 0, that is, in the case that the number value of the data of the image stored in the processing unit 12 is greater than or equal to the above predetermined number value.

[0126] It should be noted that in the above examples, the data output position is the end of each row of pixels of the image, and in actual application, a person skilled in the art can set the data output position according to the needs, and the embodiments of the present application do not limit this.

[0127] As can be seen, since the counting unit can be set in the clock domain conversion circuit, the electronic device can determine whether the number value of the converted data stored in the processing unit is greater than or equal to the predetermined number value through the counting unit, and control the second control unit to obtain the converted data from the processing unit in the case that the number value of the converted data stored in the processing unit is greater than or equal to the predetermined number value, that is, in the case that a sufficient number of converted data is stored in the processing unit, so that it can be ensured that the second control unit outputs continuous converted data through the sending end, so that the functional module connected with the sending end can receive continuous converted data.

[0128] Of course, due to the diversity of application scenarios, even for the same interface type, the allocated clock resources may not be consistent, so the asynchronous bridge unit 19 can be set in the clock domain conversion circuit to synchronize the timing relationship between the sending end and the connected functional module through the asynchronous bridge unit 19, which will be illustrated below.

[0129] In some embodiments of the present application, as shown in FIG. 18, the clock domain conversion circuit further comprises: an asynchronous bridge unit 19, the input end 191 of the asynchronous bridge unit 19 is connected with the output end of the sending end 14.

[0130] It should be noted that the structure of the asynchronous bridge unit 19 can be referred to the specific description in the related art, and the embodiments of the present application will not be repeated here.

[0131] In some embodiments of the present application, the asynchronous bridge unit 19 described above can be connected with a functional module. Wherein, the functional module is the functional module connected with the sending end 14 in the above-described embodiments.

[0132] In the embodiments of the present application, the asynchronous bridge unit 19 described above is used to convert the clock domain of the converted data from the second clock domain to the third clock domain in the case of obtaining the converted data from the sending end 14.

[0133] In some embodiments of the present application, the electronic device can first obtain the third clock domain from the functional module connected with the sending end 14, and then convert the clock domain of the converted data from the second clock domain to the third clock domain through the asynchronous bridge unit 19.

[0134] It should be noted that the description of the asynchronous bridge unit 19 converting the clock domain of the converted data from the second clock domain to the third clock domain can refer to the specific description in the related art, and the embodiments of the present application will not be described here.

[0135] As can be seen, since the asynchronous bridge unit is also provided in the clock domain conversion circuit, the clock domain of the converted data can be converted from the second clock domain to the required clock domain through the asynchronous bridge unit, so that the functional module connected with the sending end can accurately identify and use the data converted again, and therefore, it can be ensured that the functional module can receive the data.

[0136] FIG. 19 shows a flowchart of a clock domain conversion method provided by the embodiments of the present application, applied to an electronic device, which includes the clock domain conversion circuit as shown in FIGS. 5 to 18. As shown in FIG. 19, the clock domain conversion method provided by the embodiments of the present application can include the following steps 101 to 103.

[0137] Step 101, in the case of receiving data belonging to the first clock domain at the receiving end of the clock domain conversion circuit, the electronic device sends the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit.

[0138] In some embodiments of the present application, in the case that the functional module connected with the receiving end of the electronic device wants to send data to the functional module connected with the sending end, in the case that the clock signal of the first clock domain appears a rising edge or a falling edge, the functional module connected with the receiving end can send data belonging to the first clock domain to the receiving end, so that the receiving end can receive the data.

[0139] It should be noted that the description of the electronic device sending the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit can refer to the specific description in the above-described embodiments, and the embodiments of the present application will not be described here.

[0140] In step 102, the electronic device stores the data by the processing unit and converts the clock domain of the data from the first clock domain to the second clock domain.

[0141] It should be noted that the description of the electronic device storing the data by the processing unit and converting the clock domain of the data from the first clock domain to the second clock domain can refer to the specific description in the above embodiments, and the embodiments of the present application will not be described here.

[0142] In some embodiments of the present application, before the above step 102, the clock domain conversion method provided by the embodiments of the present application can further include the following step 201, and the above step 102 can be implemented by the following step 102a or step 102b.

[0143] In step 201, the electronic device determines the size relationship between the frequency of the clock signal of the first clock domain and the frequency of the clock signal of the second clock domain by the first control unit.

[0144] In step 102a, in the case that the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, the electronic device controls the first control unit to send the data to the first processing channel of the processing unit, so as to store the data by the first processing channel first, and then convert the clock domain of the data from the first clock domain to the second clock domain.

[0145] In step 102b, in the case that the frequency of the clock signal of the first clock domain is less than the frequency of the clock signal of the second clock domain, the electronic device controls the first control unit to send the data to the second processing channel of the processing unit, so as to convert the clock domain of the data from the first clock domain to the second clock domain by the second processing channel first, and then store the data.

[0146] Therefore, since the electronic device can select the first processing channel or the second processing channel to process the data according to the size relationship between the frequency of the clock signal of the first clock domain and the frequency of the clock signal of the second clock domain by the first control unit, in the case that the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, the situation that the utilization rate of the first memory is low and the data is lost due to the full storage space of the first asynchronous FIFO can be avoided, or in the case that the frequency of the clock signal of the first clock domain is less than the frequency of the clock signal of the second clock domain, the time-consuming of processing the data by the second processing channel can be reduced.

[0147] In step 103, the electronic device acquires the converted data from the processing unit by the second control unit of the processing unit, and outputs the converted data by the sending end of the clock domain conversion circuit.

[0148] In some embodiments of the present application, before step 103, the clock domain conversion method provided by the embodiments of the present application can further include step 202, and step 103 can be implemented by step 103a.

[0149] In step 202, the electronic device obtains the quantity value of the data stored in the processing unit through the counting unit of the clock domain conversion circuit.

[0150] It should be noted that the embodiments of the present application do not limit the execution order of steps 201 and 202. In some examples, the electronic device can first execute step 201 and then execute step 202. In other examples, the electronic device can first execute step 202 and then execute step 201. In yet other examples, the electronic device can execute step 201 and step 202 at the same time.

[0151] In step 103a, when the quantity value is greater than or equal to the predetermined quantity value, the electronic device obtains the converted data from the processing unit through the second control unit.

[0152] As can be seen, since the electronic device can determine whether the quantity value of the converted data stored in the processing unit is greater than or equal to the predetermined quantity value through the counting unit, and when the quantity value of the converted data stored in the processing unit is greater than or equal to the predetermined quantity value, i.e., when there is a sufficient quantity of converted data stored in the processing unit, the converted data is obtained from the processing unit through the second control unit, it can be ensured that the second control unit outputs continuous converted data through the sending end, so that the functional module connected to the sending end can receive continuous converted data.

[0153] The embodiment of the present application provides a clock domain conversion method, in the case that the electronic device receives data belonging to a first clock domain at the receiving end of a clock domain conversion circuit, the electronic device can send the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit, and store the data and convert the clock domain of the data from the first clock domain to a second clock domain through the processing unit, so that the electronic device can obtain the converted data from the processing unit through the second control unit of the processing unit, and output the converted data through the sending end of the clock domain conversion circuit. After the first control unit of the clock domain conversion circuit sends the data belonging to the first clock source to the processing unit, the processing unit can not only convert the clock domain of the data from the first clock domain to the second clock domain, but also store the data (i.e. complete data), so that the electronic device can obtain the converted complete data from the processing unit through the second control unit at an appropriate time (for example, when the functional module connected to the sending end can identify and process the converted data in time), and output the converted complete data to the functional module through the output end, so that the functional module can accurately identify and process the converted complete data, and receive the converted complete data, so that the situation that the functional module discards the converted data due to the inability to identify and process the converted data can be avoided, and the situation that the converted data received by the functional module is incomplete can be avoided, so that the quality of data transmission of the functional modules belonging to different clock domains in the electronic device can be improved.

[0154] In some embodiments of the present application, before the step 101, the clock domain conversion method provided by the embodiment of the present application can further include the following step 203, and the step 101 can be implemented through the following step 101a.

[0155] The step 203, in the case that the data belonging to the first clock domain is received at the receiving end of the clock domain conversion circuit, the electronic device determines whether the data obtained by the first control unit has packet loss through the checking unit of the clock domain conversion circuit.

[0156] The step 101a, in the case that it is determined that the data obtained by the first control unit has no packet loss, the electronic device controls the first control unit to send the data to the processing unit through the checking unit.

[0157] In some embodiments of the present application, the step 101a can be replaced by the following step 101b.

[0158] The step 101b, in the case that it is determined that the data obtained by the first control unit has packet loss, the electronic device controls the first control unit to discard the obtained data through the checking unit.

[0159] Thus, the electronic device can determine, by the checking unit, whether the data acquired by the first control unit has packet loss, so that the electronic device can control, by the checking unit, the first control unit to discard the data with packet loss or send the data without packet loss, that is, the electronic device can control, by the checking unit, the first control unit to discard the incorrect data or the first control unit to send the correct data, thereby ensuring the accuracy of the data sent by the first control unit.

[0160] In some embodiments of the present application, before the step 103 of "outputting the converted data by the sending end of the clock domain conversion circuit", the clock domain conversion method provided by the embodiments of the present application can further include the following step 204, and the step 103 can be implemented by the following step 103b.

[0161] The step 204 includes: acquiring, by the electronic device through the second control unit of the processing unit, the converted data from the processing unit, and determining, by the checking unit of the clock domain conversion circuit, whether the data acquired by the second control unit has packet loss.

[0162] The step 103b includes: in the case that it is determined that the data acquired by the second control unit has no packet loss, controlling, by the checking unit, the second control unit to output the converted data by the sending end.

[0163] In some embodiments of the present application, the step 103b can be replaced by the following step 103c.

[0164] The step 103c includes: in the case that it is determined that the data acquired by the second control unit has packet loss, controlling, by the checking unit, the second control unit to discard the acquired data.

[0165] Thus, the electronic device can determine, by the checking unit, whether the data acquired by the second control unit has packet loss, so that the electronic device can control, by the checking unit, the second control unit to discard the data with packet loss or send the data without packet loss, that is, the electronic device can control, by the checking unit, the second control unit to discard the incorrect data or the second control unit to send the correct data, thereby ensuring the accuracy of the data sent by the second control unit.

[0166] In some embodiments of the present application, after the step 103, the clock domain conversion method provided by the embodiments of the present application can further include the following steps 301 and 302.

[0167] The step 301 includes: acquiring, by the electronic device through the asynchronous bridge unit of the clock domain conversion circuit, a third clock domain to which a receiving interface corresponding to the data belongs.

[0168] In the embodiments of the present application, the receiving interface corresponding to the data can be understood as an interface of a functional module connected with the sending end.

[0169] In step 302, the electronic device converts the clock domain of the converted data from the second clock domain to a third clock domain through the asynchronous bridge unit.

[0170] Therefore, the functional module connected with the sending end can accurately identify and use the data converted again, and thus the functional module can receive the data.

[0171] The clock domain conversion method provided in the embodiments of the present application can be executed by a clock domain conversion device. The clock domain conversion device provided in the embodiments of the present application is described by taking the clock domain conversion device as an example.

[0172] FIG. 20 shows a structural schematic diagram of the clock domain conversion device provided in the embodiments of the present application. As shown in FIG. 20, the clock domain conversion device 40 provided in the embodiments of the present application can include a sending module 41, a processing module 42, an obtaining module 43, and an output module 44. The sending module 41 is configured to send data to a processing unit of a clock domain conversion circuit through a first control unit of the clock domain conversion circuit when the clock domain conversion circuit receives data belonging to a first clock domain at a receiving end of the clock domain conversion circuit. The processing module 42 is configured to store the data sent by the sending module 41 and convert the clock domain of the data from the first clock domain to a second clock domain through the processing unit. The obtaining module 43 is configured to obtain the data converted by the processing module 42 from the processing unit through a second control unit of the processing unit. The output module 44 is configured to output the converted data obtained by the obtaining module 43 through a sending end of the clock domain conversion circuit.

[0173] The embodiment of the present application provides a clock domain conversion device, after the first control unit of the clock domain conversion circuit sends data belonging to a first clock source to a processing unit, the processing unit can not only convert the clock domain of the data from the first clock domain to a second clock domain, but also can store the data (i.e. complete data), so that the clock domain conversion device can obtain the converted complete data from the processing unit at a proper time (for example, when the function module connected with the sending end can identify and process the converted data in time) through the second control unit, and outputs the converted complete data to the function module through the output end, so that the function module can accurately identify and process the converted complete data, and receives the converted complete data, so that the situation that the function module discards the converted data due to the inability to identify and process the converted data can be avoided, the situation that the converted data received by the function module is incomplete can be avoided, and therefore, the quality of data transmission of the function module belonging to different clock domains in the clock domain conversion device can be improved.

[0174] In a possible implementation, the processing module 42 is further configured to: before the data is stored by the processing unit and the clock domain of the data is converted from the first clock domain to the second clock domain, determine, by the first control unit, a size relationship between a frequency of the clock signal of the first clock domain and a frequency of the clock signal of the second clock domain; and in the case that the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, control the first control unit to send the data to the first processing channel of the processing unit, so that the data is first stored by the first processing channel, and then the clock domain of the data is converted from the first clock domain to the second clock domain; or in the case that the frequency of the clock signal of the first clock domain is less than the frequency of the clock signal of the second clock domain, control the first control unit to send the data to the second processing channel of the processing unit, so that the clock domain of the data is first converted from the first clock domain to the second clock domain by the second processing channel, and then the data is stored.

[0175] In a possible implementation, the processing module 42 is further configured to: before the sending module 41 sends the data to the processing unit by the first control unit, determine, by a checking unit of the clock domain conversion circuit, whether the data obtained by the first control unit has packet loss. The sending module 41 is specifically configured to: in the case that the processing module 42 determines that the data obtained by the first control unit has no packet loss, control the first control unit to send the data to the processing unit by the checking unit. The sending module 41 is further configured to: in the case that the processing module 42 determines that the data obtained by the first control unit has packet loss, control the first control unit to discard the obtained data by the checking unit.

[0176] In a possible implementation, the processing module 42 is further configured to determine, by the checking unit of the clock domain conversion circuit, whether the data obtained by the second control unit has packet loss before the output module 44 outputs the converted data through the sending end. The output module 44 is specifically configured to control the second control unit to output the converted data through the sending end, by the checking unit, in a case where the processing module 42 determines that the data obtained by the second control unit has no packet loss. The output module 44 is further configured to control the second control unit to discard the obtained data, by the checking unit, in a case where the processing module 42 determines that the data obtained by the second control unit has packet loss.

[0177] In a possible implementation, the obtaining module 43 is further configured to obtain, by the counting unit of the clock domain conversion circuit, a quantity value of the data stored in the processing unit before the second control unit obtains the converted data from the processing unit. The obtaining module 43 is specifically configured to obtain the converted data from the processing unit by the second control unit in a case where the quantity value is greater than or equal to a predetermined quantity value.

[0178] In a possible implementation, the obtaining module 43 is further configured to obtain, by the asynchronous bridge unit of the clock domain conversion circuit, a third clock domain to which a receiving interface corresponding to the data belongs after the output module 44 outputs the converted data through the sending end. The processing module 42 is further configured to convert, by the asynchronous bridge unit, the clock domain of the converted data from the second clock domain to the third clock domain obtained by the obtaining module 43.

[0179] The clock domain conversion apparatus in the embodiments of the present application can be an electronic device or a component in an electronic device, for example, an integrated circuit or a chip. The electronic device can be a terminal or other devices other than the terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a mobile internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and the like, and can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, and the like, and the embodiments of the present application are not limited in this regard.

[0180] The clock domain conversion apparatus in the embodiments of the present application can be an apparatus with an operating system. The operating system can be an Android operating system, an iOS operating system, or other possible operating systems, which are not limited in the embodiments of the present application.

[0181] The clock domain conversion apparatus provided in the embodiments of the present application can realize each process of the method embodiment of FIG. 19, and thus details are not repeated here.

[0182] Optionally, as shown in FIG. 21, the embodiments of the present application further provide an electronic device 50, which includes a processor 51 and a memory 52, and the memory 52 stores programs or instructions executable on the processor 51. The programs or instructions are executed by the processor 51 to realize each process step of the above clock domain conversion method embodiments and achieve the same technical effects. Details are not repeated here.

[0183] It should be noted that the electronic device in the embodiments of the present application includes the above mobile electronic device and non-mobile electronic device.

[0184] FIG. 22 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.

[0185] The electronic device 100 includes, but is not limited to, a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, and a processor 110, etc.

[0186] Those skilled in the art can understand that the electronic device 100 can further include a power supply (such as a battery) for supplying power to each component, and the power supply can be logically connected to the processor 110 through a power management system, so as to realize functions such as management of charging, discharging, and power consumption management through the power management system. The electronic device structure shown in FIG. 22 does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than shown, or combine certain components, or different component arrangements, which are not repeated here.

[0187] The processor 110 is configured to, in a case that the clock domain conversion circuit receives data belonging to a first clock domain at a receiving end of the clock domain conversion circuit, send the data to a processing unit of the clock domain conversion circuit through a first control unit of the clock domain conversion circuit, store the data by the processing unit, and convert a clock domain of the data from the first clock domain to a second clock domain by the processing unit; and acquire the converted data from the processing unit by a second control unit of the processing unit, and output the converted data by a sending end of the clock domain conversion circuit.

[0188] The embodiment of the present application provides an electronic device, after the first control unit of the clock domain conversion circuit sends data belonging to the first clock source to the processing unit, the processing unit can not only convert the clock domain of the data from the first clock domain to the second clock domain, but also can store the data (i.e. complete data), so that the electronic device can obtain the converted complete data from the processing unit at a proper time (for example, the function module connected to the sending end can identify and process the converted data in time) through the second control unit, and outputs the converted complete data to the function module through the output end, so that the function module can accurately identify and process the converted complete data, and receives the converted complete data, so that the situation that the function module discards the converted data due to the inability to identify and process the converted data can be avoided, the situation that the converted data received by the function module is incomplete can be avoided, and therefore, the quality of data transmission of the function module belonging to different clock domains in the electronic device can be improved.

[0189] In a possible implementation, the processor 110 is further configured to determine, by the first control unit, a size relationship between a frequency of a clock signal of the first clock domain and a frequency of a clock signal of the second clock domain, before the data is stored by the processing unit and the clock domain of the data is converted from the first clock domain to the second clock domain.

[0190] The processor 110 is specifically configured to perform any one of the following: in a case where the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, control the first control unit to send the data to the first processing channel of the processing unit, so as to store the data by the first processing channel first, and then convert the clock domain of the data from the first clock domain to the second clock domain; in a case where the frequency of the clock signal of the first clock domain is less than the frequency of the clock signal of the second clock domain, control the first control unit to send the data to the second processing channel of the processing unit, so as to convert the clock domain of the data from the first clock domain to the second clock domain by the second processing channel first, and then store the data.

[0191] In a possible implementation, the processor 110 is further configured to determine, by the checking unit of the clock domain conversion circuit, whether the data acquired by the first control unit has packet loss, before the first control unit of the clock domain conversion circuit sends the data to the processing unit of the clock domain conversion circuit.

[0192] The processor 110 is specifically configured to control the first control unit to send the data to the processing unit by the checking unit, in a case where it is determined that the data acquired by the first control unit has no packet loss.

[0193] The processor 110 is further configured to discard the acquired data by the first control unit through the checking unit in a case where it is determined that the acquired data by the first control unit has packet loss.

[0194] In a possible implementation, the processor 110 is further configured to determine, by the checking unit of the clock domain conversion circuit, whether the acquired data by the second control unit has packet loss before the converted data is output by the sending end of the clock domain conversion circuit.

[0195] The processor 110 is specifically configured to control the second control unit to output the converted data by the sending end in a case where it is determined that the acquired data by the second control unit has no packet loss.

[0196] The processor 110 is further configured to discard the acquired data by the second control unit through the checking unit in a case where it is determined that the acquired data by the second control unit has packet loss.

[0197] In a possible implementation, the processor 110 is further configured to acquire, by the counting unit of the clock domain conversion circuit, a quantity value of the data stored in the processing unit before the converted data is acquired by the second control unit of the processing unit from the processing unit.

[0198] The processor 110 is specifically configured to acquire the converted data by the second control unit from the processing unit in a case where the quantity value is greater than or equal to a predetermined quantity value.

[0199] In a possible implementation, the processor 110 is further configured to acquire, by the asynchronous bridge unit of the clock domain conversion circuit, a third clock domain to which a receiving interface corresponding to the data belongs after the converted data is output by the sending end of the clock domain conversion circuit; and convert, by the asynchronous bridge unit, the clock domain of the converted data from the second clock domain to the third clock domain.

[0200] It should be understood that in the embodiments of the present application, the input unit 104 can include a graphics processing unit (GPU) 1041 and a microphone 1042. The graphics processing unit 1041 processes image data of a still picture or a video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 can include a display panel 1061, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 can include two parts of a touch detection device and a touch controller. The other input devices 1072 can include, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, etc.), a trackball, a mouse, a joystick, and the like, which will not be described here.

[0201] The memory 109 can be used to store software programs and various data. The memory 109 can mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, etc.), and the like. In addition, the memory 109 can include a volatile memory or a non-volatile memory, or the memory 109 can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synch link DRAM (SLDRAM), and a direct rambus RAM (DRRAM). The memory 109 in the embodiments of the present application includes but is not limited to these and any other suitable types of memory.

[0202] The processor 110 can include one or more processing units; optionally, the processor 110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and an application program, and the modem processor mainly processes a wireless communication signal, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 110.

[0203] The embodiment of the present application further provides a readable storage medium, and the readable storage medium stores a program or instructions, which are executed by a processor to realize the processes of the above-mentioned clock domain conversion method embodiments and achieve the same technical effects. To avoid repetition, details are not described herein.

[0204] The processor is the processor in the electronic device in the above-mentioned embodiments. The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0205] The embodiment of the present application further provides a chip, and the chip includes a processor and a communication interface. The communication interface is coupled with the processor. The processor is configured to run a program or instructions to realize the processes of the above-mentioned clock domain conversion method embodiments and achieve the same technical effects. To avoid repetition, details are not described herein.

[0206] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system level chip, a system chip, a chip system, or a system on chip, etc.

[0207] The embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to realize the processes of the above-mentioned clock domain conversion method embodiments and achieve the same technical effects. To avoid repetition, details are not described herein.

[0208] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Furthermore, it is to be understood that the method and apparatus of the present application can be carried out by more than one process, method, article, or apparatus either simultaneously, concurrently, or with intervening action that are carried out at the same time, either in a simultaneous fashion or in a fashion that is interleaved in time. For example, the described methods can be performed in a different order from that described, and / or various steps can be combined or omitted, and / or additional steps can be added, without departing from the scope of the present application. Also, features described with respect to certain examples can be combined in other examples.

[0209] From the above description of the embodiments, it is apparent that the above-mentioned method can be realized by means of software and necessary universal hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solution of the present application can be embodied in the form of computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) execute the method described in various embodiments of the present application.

[0210] The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, rather than limiting, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

A clock domain conversion circuit, comprising: A first control unit, the input terminal of which is connected to the receiving terminal of the clock domain conversion circuit; A processing unit, wherein the input terminal of the processing unit is connected to the output terminal of the first control unit; The second control unit has its input terminal connected to the output terminal of the processing unit, and its output terminal connected to the transmitting terminal of the clock domain conversion circuit. The first control unit is used to send the data to the processing unit when it receives data belonging to the first clock domain from the receiving end; The processing unit is configured to store the data and convert the clock domain of the data from the first clock domain to the second clock domain when receiving the data from the first control unit. The second control unit is used to obtain the converted data from the processing unit and output the converted data through the sending end. According to claim 1, the clock domain conversion circuit, wherein, The processing unit includes: A first processing channel, the input end of which is connected to the output end of the first control unit, and the output end of which is connected to the input end of the second control unit; The second processing channel has its input terminal connected to the output terminal of the first control unit, and its output terminal connected to the input terminal of the second control unit. The first processing channel is used to, upon receiving the data from the first control unit, first store the data and then convert the clock domain of the data from the first clock domain to the second clock domain. The second processing channel is used to, when receiving the data from the first control unit, first convert the clock domain of the data from the first clock domain to the second clock domain, and then store the data; The first control unit is specifically configured to send the data to the first processing channel when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain; or, to send the data to the second processing channel when the frequency of the clock signal in the first clock domain is less than the frequency of the clock signal in the second clock domain. According to claim 2, the clock domain conversion circuit, wherein, The first processing channel includes: A first memory, the input terminal of which is connected to the output terminal of the first control unit; The first asynchronous first-in-first-out FIFO has its input terminal connected to the output terminal of the first memory, and its output terminal connected to the input terminal of the second control unit. The first memory is used to store the data, and the first asynchronous FIFO is used to convert the clock domain of the data from the first clock domain to the second clock domain. The clock domain conversion circuit according to claim 2 or 3, wherein, The second processing channel includes: A second asynchronous FIFO, the input of which is connected to the output of the first control unit; The second memory has its input terminal connected to the output terminal of the second asynchronous FIFO, and its output terminal connected to the input terminal of the second control unit. The second asynchronous FIFO is used to convert the clock domain of the data from the first clock domain to the second clock domain, and the second memory is used to store the data. According to claim 1, the clock domain conversion circuit, wherein, The clock domain conversion circuit also includes: A verification unit, wherein the verification unit is connected to at least one of the first control unit and the second control unit; The verification unit is configured to control the connected control unit to send the acquired data if it determines that the data acquired by the connected control unit does not have packet loss; or, if it determines that the data acquired by the connected control unit has packet loss, control the connected control unit to discard the acquired data. According to claim 1, the clock domain conversion circuit, wherein, The clock domain conversion circuit also includes: A counting unit, which is connected to the processing unit and the second control unit; The counting unit is used to record the quantity of the converted data stored in the processing unit; The second control unit is specifically used to obtain the converted data from the processing unit when the number of converted data recorded by the counting unit is greater than or equal to a predetermined number. According to claim 1, the clock domain conversion circuit, wherein, The clock domain conversion circuit also includes: An asynchronous bridge unit, wherein the input of the asynchronous bridge unit is connected to the output of the transmitting end; The asynchronous bridge unit is used to convert the clock domain of the converted data from the second clock domain to the third clock domain when the converted data is obtained from the transmitting end. A clock domain conversion method is applied to an electronic device, the electronic device including a clock domain conversion circuit as described in any one of claims 1 to 7, the method comprising: When the receiving end of the clock domain conversion circuit receives data belonging to the first clock domain, the data is sent to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit. The processing unit stores the data and converts the clock domain of the data from the first clock domain to the second clock domain. The second control unit of the processing unit obtains the converted data from the processing unit and outputs the converted data through the transmitting end of the clock domain conversion circuit. According to the clock domain conversion method of claim 8, wherein, Before storing the data through the processing unit and converting the clock domain of the data from the first clock domain to the second clock domain, the method further includes: The first control unit determines the magnitude relationship between the frequency of the clock signal in the first clock domain and the frequency of the clock signal in the second clock domain. The step of storing the data through the processing unit and converting the clock domain of the data from the first clock domain to the second clock domain includes any one of the following: When the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain, the first control unit is controlled to send the data to the first processing channel of the processing unit, so that the data is first stored through the first processing channel and then the clock domain of the data is converted from the first clock domain to the second clock domain. When the frequency of the clock signal in the first clock domain is less than the frequency of the clock signal in the second clock domain, the first control unit is controlled to send the data to the second processing channel of the processing unit, so that the clock domain of the data is first converted from the first clock domain to the second clock domain through the second processing channel, and then the data is stored. According to the clock domain conversion method of claim 8, wherein, Before the first control unit of the clock domain conversion circuit sends the data to the processing unit of the clock domain conversion circuit, the method further includes: The verification unit of the clock domain conversion circuit determines whether there is packet loss in the data acquired by the first control unit; The process of sending the data from the first control unit of the clock domain conversion circuit to the processing unit of the clock domain conversion circuit includes: If it is determined that there is no packet loss in the data acquired by the first control unit, the verification unit controls the first control unit to send the data to the processing unit; The method further includes: If it is determined that there is packet loss in the data acquired by the first control unit, the verification unit controls the first control unit to discard the acquired data. According to the clock domain conversion method of claim 8, wherein, Before outputting the converted data through the transmitting end of the clock domain conversion circuit, the method further includes: The verification unit of the clock domain conversion circuit determines whether there is packet loss in the data acquired by the second control unit; The step of outputting the converted data through the transmitting end of the clock domain conversion circuit includes: If it is determined that there is no packet loss in the data acquired by the second control unit, the verification unit controls the second control unit to output the converted data through the sending end; The method further includes: If it is determined that there is packet loss in the data acquired by the second control unit, the verification unit controls the second control unit to discard the acquired data. According to the clock domain conversion method of claim 8, wherein, Before the second control unit of the processing unit obtains the converted data from the processing unit, the method further includes: The counting unit of the clock domain conversion circuit obtains the quantity value of the data stored in the processing unit; The second control unit of the processing unit obtains the converted data from the processing unit, including: If the quantity value is greater than or equal to a predetermined quantity value, the converted data is obtained from the processing unit by the second control unit. According to the clock domain conversion method of claim 8, wherein, After the converted data is output through the transmitting end of the clock domain conversion circuit, the method further includes: The third clock domain to which the receiving interface corresponding to the data belongs is obtained through the asynchronous bridge unit of the clock domain conversion circuit. The asynchronous bridge unit converts the clock domain of the transformed data from the second clock domain to the third clock domain. A clock domain conversion device, comprising: The transmitting module is used to transmit data belonging to the first clock domain to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit when the receiving end of the clock domain conversion circuit receives data belonging to the first clock domain. A processing module is used to store the data sent by the sending module and convert the clock domain of the data from the first clock domain to the second clock domain through the processing unit; An acquisition module is used to acquire the data converted by the processing module from the processing unit through the second control unit of the processing unit; The output module is used to output the converted data acquired by the acquisition module through the transmitting end of the clock domain conversion circuit. An electronic device includes a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the clock domain conversion method as described in any one of claims 8 to 13. A readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the clock domain conversion method as described in any one of claims 8 to 13. A chip includes a processor and a communication interface coupled to the processor, the processor being configured to run a program or instructions to implement the steps of the clock domain conversion method as described in any one of claims 8 to 13. A computer program product, the program product being stored in a storage medium, the program product being executed by at least one processor to implement the steps of the clock domain conversion method as described in any one of claims 8 to 13.

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