Reconfigurable electronic device using ambipolar two-dimensional semiconductor, method for manufacturing same, and logic device using same

Abstract

Provided are a reconfigurable electronic device capable of performing various operations by controlling the type and concentration of charges stored in a floating gate, a method for manufacturing same, and a logic device using same. The reconfigurable electronic device comprises: a control gate; a floating gate formed on the control gate and electrically insulated from the surroundings; a tunneling layer formed on the floating gate; a channel layer formed on the tunneling layer and made of an ambipolar two-dimensional semiconductor; and first and second electrodes formed spaced apart from each other on the channel layer. Here, the channel layer has the characteristics of any one of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor depending on the polarity and magnitude of a program voltage applied to the control gate.

Description

Reconfigurable electronic devices using bipolar two-dimensional semiconductors, methods for manufacturing the same, and logic devices using the same

[0001] The present invention relates to a reconfigurable electronic device, a method for manufacturing the same, and a logic device using the same, and more particularly, to a reconfigurable electronic device having transistor and memory functions using an ambipolar two-dimensional semiconductor, a method for manufacturing the same, and a logic device using the same.

[0002] Current commercial silicon semiconductor transistors are primarily being developed to reduce device size to increase device integration. However, due to limitations in miniaturization process technology and the single-channel effect, there are physical limitations to further reducing device size.

[0003] To address these issues, two-dimensional materials with high charge mobility and suppression of single-channel effects are being developed as semiconductor materials to replace silicon. Research is also actively underway on three-dimensional integrated circuits, which vertically stack electronic components to achieve high integration and performance. However, unlike memory, transistor-based three-dimensional integration technology generates high heat during computation, limiting the number of vertical layers that can be stacked.

[0004] Accordingly, new methods for improving device integration are needed. Reconfigurable transistors, which can perform various operations by reconfiguring the electrical characteristics of a single device, have recently attracted attention. Reconfigurable transistors enable a variety of operations in a single circuit, thereby improving area efficiency, and thus, extensive research is being conducted on this topic. However, conventional reconfigurable transistor devices consist of two or more gate terminals, which complicates the circuit configuration and reduces practical integration efficiency.

[0005] The problem to be solved by the present invention is to provide a reconfigurable electronic device capable of performing various operations in a single device by controlling the type and concentration of charge stored in a floating gate.

[0006] Another problem that the present invention seeks to solve is to provide a method for manufacturing such a reconfigurable electronic device.

[0007] Another problem that the present invention seeks to solve is to provide a logic element using such reconfigurable electronic elements.

[0008] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0009] According to one embodiment of the present invention for achieving the above object, a reconfigurable electronic device having transistor and memory functions using an ambipolar two-dimensional semiconductor comprises: a control gate; a floating gate formed on the control gate and electrically insulated from the surroundings; a tunneling layer formed on the floating gate; a channel layer formed on the tunneling layer and made of an ambipolar two-dimensional semiconductor; and a first electrode and a second electrode formed spaced apart from each other on the channel layer. Here, depending on the polarity and magnitude of a program voltage applied to the control gate, the channel layer has any one of the characteristics of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor.

[0010] The above channel layer may be formed of at least one bipolar two-dimensional semiconductor selected from the group consisting of WSe2, MoTe2, and BP.

[0011] The floating gate may be formed of at least one two-dimensional conductor selected from the group consisting of graphene and PtTe2.

[0012] The above tunneling layer may be formed of at least one two-dimensional insulator selected from the group consisting of hBN and Sb2O3.

[0013] The floating gate, the tunneling layer, and the channel layer are all made of two-dimensional materials and can be sequentially laminated on the control gate using a dry transfer method using a PDMS stamp.

[0014] As the absolute value of the above program voltage increases bipolarly, the channel layer can sequentially have the properties of an insulator, a p-type semiconductor, and a conductor.

[0015] As the absolute value of the above program voltage increases toward negative polarity, the channel layer can sequentially have the properties of an insulator, an n-type semiconductor, and a conductor.

[0016] In the first paragraph, when the first voltage < second voltage < third voltage < 0 < fourth voltage < fifth voltage < sixth voltage, when the program voltage is lower than or equal to the first voltage or higher than or equal to the sixth voltage, the channel layer may have conductor characteristics, when the program voltage is the first voltage to the second voltage, the channel layer may have n-type semiconductor characteristics, when the program voltage is the second voltage to the third voltage or the fourth voltage to the fifth voltage, the channel layer may have insulator characteristics, and when the program voltage is the fifth voltage to the sixth voltage, the channel layer may have p-type semiconductor characteristics.

[0017] When the program voltage is -60 V or less or 60 V or more, the channel layer may have conductor characteristics, when the program voltage is -60 V to -45 V, the channel layer may have n-type semiconductor characteristics, when the program voltage is -45 V to -30 V or 30 V to 45 V, the channel layer may have insulator characteristics, and when the program voltage is 45 V to 60 V, the channel layer may have p-type semiconductor characteristics.

[0018]

[0019] According to one embodiment of the present invention for achieving the above-described other object, a method for manufacturing a reconfigurable electronic device having transistor and memory functions using an ambipolar two-dimensional semiconductor comprises the steps of: preparing a control gate; sequentially stacking a floating gate, a tunneling layer, and a channel layer on the control gate using a dry transfer method using a PDMS stamp, wherein the channel layer is made of an ambipolar two-dimensional semiconductor; forming a resist pattern on the channel layer; and forming a first electrode and a second electrode spaced apart from each other on the channel layer exposed by the resist pattern. Here, the channel layer has the characteristics of any one of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor depending on the polarity and magnitude of a program voltage applied to the control gate.

[0020]

[0021] According to one embodiment of the present invention for achieving the above-described further object, a logic element comprises first and second electronic elements having the same structure as the aforementioned electronic elements, a first power source, and a second power source, wherein the first electronic element and the second electronic element are connected in series between the first power source and the second power source, a first electrode of the first electronic element is connected to the first power source, a second electrode of the first electronic element is connected to the first electrode of the second electronic element, and an output signal is output from a connection point thereof, a second electrode of the second electronic element is connected to the second power source, and an identical input signal (A) is input to a control gate of the first electronic element and a control gate of the second electronic element.

[0022] Depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element, the logic element can perform four logical operations.

[0023] The above four logical operations can be A, NOT A, TRUE, and FALSE for the input signal (A).

[0024]

[0025] According to another embodiment of the present invention for achieving the above-mentioned further task, a logic element comprises first to fifth electronic elements having the same structure as the aforementioned electronic elements, a first power source, and a second power source, wherein a first electrode of the fifth electronic element is connected to the first power source, a control gate of the fifth electronic element is connected to a second electrode of the fifth electronic element, the first electronic element and the second electronic element are connected in series between the second electrode of the fifth electronic element and the second power source, the third electronic element and the fourth electronic element are connected in series between the second electrode of the fifth electronic element and the second power source, the first electrode of the first electronic element and the first electrode of the third electronic element are connected to the second electrode of the fifth electronic element, and an output signal is output from a connection point thereof, and the second electrode of the first electronic element, the first electrode of the second electronic element, the second electrode of the third electronic element, and the first electrode of the fourth electronic element are connected to each other, and the second electrode of the second electronic element and the The second electrode of the fourth electronic element is connected to the second power source, the same first input signal (A) is input to the control gate of the first electronic element and the control gate of the second electronic element, and the same second input signal (B) is input to the control gate of the third electronic element and the control gate of the fourth electronic element.

[0026] Depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element, the logic element can perform 16 logical operations.

[0027] The above 16 logical operations may be A, NOT A, B, NOT B, TRUE, FALSE, AND, OR, NOR, NAND, XOR, XNOR, IMP, NIMP, RIMP, and RNIMP for the first input signal (A) and the second input signal (B).

[0028] The channel layer of the fifth electronic element can have n-type semiconductor characteristics due to a program voltage.

[0029] Specific details of other embodiments are included in the specific contents and drawings.

[0030] As described above, the reconfigurable electronic device according to the present invention can perform memory and transistor functions through a single control gate by adding a tunneling layer and a floating gate to the existing transistor structure. For example, when a high program voltage is applied to the control gate, charges can be stored or removed in the floating gate, so that the reconfigurable electronic device can perform a memory function. In addition, when a low gate voltage is applied to the control gate, charges stored in the floating gate can be fixed without fluctuation, so that switching operations like those of a transistor device can be performed. Therefore, the reconfigurable electronic device of the present invention is a device that can be used as both a processor that performs operations and a memory chip.

[0031] Since the reconfigurable electronic device of the present invention is a three-terminal device composed of a control gate, a first electrode, and a second electrode, the electrode is not connected to the floating gate, and thus the circuit configuration is simple and the integration efficiency can be increased.

[0032] Since the channel layer of the reconfigurable electronic device of the present invention is made of an ambipolar two-dimensional semiconductor material, the type and concentration of charge stored in the floating gate can be controlled depending on the polarity and magnitude of the program voltage applied to the control gate, and accordingly, the reconfigurable electronic device can operate as any one of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor. In this way, by performing four operations using a single electronic device, integration efficiency can be increased.

[0033] The floating gate, tunneling layer, and channel layer constituting the reconfigurable electronic device of the present invention are all made of two-dimensional materials, so that charge mobility is high and single-channel effects can be suppressed.

[0034] The logic element of the present invention, which is composed of two reconfigurable electronic elements, can perform four logical operations depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element. For example, the logic element can perform the logical operations of A, NOT A, TRUE, and FALSE for an input signal (A).

[0035] The logic element composed of five reconfigurable electronic elements of the present invention can perform 16 logical operations depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element. For example, the logic element can perform the logical operations of A, NOT A, B, NOT B, TRUE, FALSE, AND, OR, NOR, NAND, XOR, XNOR, IMP, NIMP, RIMP, and RNIMP for a first input signal (A) and a second input signal (B).

[0036] FIG. 1 is a schematic diagram illustrating a reconfigurable electronic device according to one embodiment of the present invention.

[0037] Figure 2 is a cross-sectional view of the reconfigurable electronic component of Figure 1.

[0038] FIG. 3 is a diagram showing the bipolar memory characteristics of the reconfigurable electronic device of FIG. 1.

[0039] FIG. 4 is a diagram showing the electrical characteristics of the reconfigurable electronic device of FIG. 1 according to the program voltage.

[0040] Figure 5 is a circuit diagram of a logic element according to one embodiment of the present invention.

[0041] Figure 6 is a drawing explaining the operation of the logic element of Figure 5.

[0042] Figure 7 is a circuit diagram of a logic element according to another embodiment of the present invention.

[0043] Figure 8 is a diagram showing a logical operation performed by the logic element of Figure 7.

[0044] Figure 9 is a diagram showing input signals and output signals according to the logical operation of Figure 8.

[0045] FIG. 10 is a circuit diagram and a drawing showing a logic operation of a logic element block according to one embodiment of the present invention.

[0046] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals designate like elements throughout the specification.

[0047] Throughout this specification, whenever a part is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0048] Throughout this specification, when it is said that an element is "on" another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements.

[0049]

[0050] Hereinafter, the structure of a reconfigurable electronic device according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG. 1 is a schematic diagram illustrating a reconfigurable electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the reconfigurable electronic device of FIG. 1.

[0051] A reconfigurable electronic device has transistor and memory functions using an ambipolar two-dimensional semiconductor. Specifically, the reconfigurable electronic device includes a control gate (10), a blocking layer (20), a floating gate (30), a tunneling layer (40), a channel layer (50), a first electrode (60), and a second electrode (70).

[0052] The control gate (10) may be formed of a semiconductor, a two-dimensional conductor, a bulk metal, or a combination thereof. For example, the control gate (10) may be formed of at least one semiconductor selected from the group consisting of Si, GaAs, SiC, GaN, and InP. Alternatively, the control gate (10) may be formed of at least one two-dimensional conductor selected from the group consisting of graphene and PtTe2. Alternatively, the control gate (10) may be formed of at least one bulk metal selected from the group consisting of Pt and Au.

[0053] The blocking layer (20) is formed on the control gate (10) and may be formed of a two-dimensional insulator, a bulk insulator, or a combination thereof. For example, the blocking layer (20) may be formed of at least one two-dimensional insulator selected from the group consisting of hBN (hexagonal boron nitride) and Sb2O3. Alternatively, the blocking layer (20) may be formed of at least one bulk insulator selected from the group consisting of HfO2, Al2O3, ZrO2, and SiO2.

[0054] The floating gate (30) is formed on the control gate (10), preferably on the blocking layer (20). The floating gate (30) is electrically insulated from the surroundings and is not connected to a separate electrode. The floating gate (30) may be formed of a two-dimensional conductor, a bulk metal, or a combination thereof. For example, the floating gate (30) may be formed of at least one two-dimensional conductor or two-dimensional material selected from the group consisting of graphene and PtTe2. Alternatively, the floating gate (30) may be formed of at least one bulk metal selected from the group consisting of Pt and Au. Depending on the amount and type of charge stored in the floating gate (30), the reconfigurable electronic element can perform four roles: a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor.

[0055] The tunneling layer (40) is formed on the floating gate (30) and may be formed of a two-dimensional insulator, a bulk insulator, or a combination thereof. For example, the tunneling layer (40) may be formed of at least one two-dimensional insulator or two-dimensional material selected from the group consisting of hBN (hexagonal boron nitride) and Sb2O3. Alternatively, the tunneling layer (40) may be formed of at least one bulk insulator selected from the group consisting of HfO2, Al2O3, ZrO2, and SiO2.

[0056] The channel layer (50) is formed on the tunneling layer (40) and may be made of a two-dimensional semiconductor material or a two-dimensional material having high charge mobility and a single-channel suppression effect. For example, the channel layer (50) may be made of graphene, a transition metal chalcogenide, black phosphorous (BP), or a combination thereof. Here, the transition metal chalcogenide may be a transition metal dichalcogenide (TMD) represented by the chemical formula MX2 (M: transition metal, X: chalcogen element). The transition metal dichalcogenide (TMD) includes a transition metal disulfide (MS2), a transition metal diselenide (MSe2), or a transition metal ditelluride (MTe2). For example, the transition metal dichalcogenide (TMD) may be MoS2, WS2, TiS2, MoSe2, WSe2, MoTe2, or WTe2. Preferably, the channel layer (50) may be formed of an ambipolar two-dimensional semiconductor, for example, at least one ambipolar two-dimensional semiconductor selected from the group consisting of WSe2, MoTe2, and BP.

[0057] A first electrode (60) and a second electrode (70) are formed spaced apart from each other on a channel layer (50). The first electrode (60) is one of a source electrode and a drain electrode, and the second electrode (70) is the other of the source electrode and the drain electrode. In this embodiment, the case where the first electrode (60) is a source electrode and the second electrode (70) is a drain electrode is described as an example, but the present invention is not limited thereto, and the first electrode (60) may be a drain electrode and the second electrode (70) may be a source electrode. The first electrode (60) and the second electrode (70) may be formed of a semiconductor, a two-dimensional conductor, a bulk metal, or a combination thereof. For example, the first electrode (60) and the second electrode (70) may be formed of at least one semiconductor selected from the group consisting of Si, GaAs, SiC, GaN, and InP. Alternatively, the first electrode (60) and the second electrode (70) may be formed of at least one two-dimensional conductor selected from the group consisting of graphene and PtTe2. Alternatively, the first electrode (60) and the second electrode (70) may be formed of at least one bulk metal selected from the group consisting of Pt and Au.

[0058]

[0059] Hereinafter, a method for manufacturing a reconfigurable electronic device according to one embodiment of the present invention will be described in detail with reference to FIG. 2.

[0060] A control gate (10) or a control gate (10) having a blocking layer (20) formed on the upper side is prepared.

[0061] A floating gate (30), a tunneling layer (40), and a channel layer (50) are sequentially laminated on a control gate (10), preferably on a blocking layer (20), using a dry transfer method using a PDMS stamp. The dry transfer method uses a hemispherical PDMS stamp and a PC (polycarbonate) thin film on a slide glass.

[0062] Next, a resist pattern is formed on the channel layer (50). Specifically, a resist is laminated on the channel layer (50) using spin coating, and a resist pattern is formed using lithography so that a portion of the channel layer (50) is exposed. Here, the resist may be formed of a photoresist (PR), an electron beam resist (e-beam resist), etc. The lithography may be formed of photolithography, electron beam lithography, etc.

[0063] A first electrode (60) and a second electrode (70) spaced apart from each other are formed on the channel layer (50) exposed by the resist pattern. The first electrode (60) and the second electrode (70) can be formed using a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method. As a physical vapor deposition (PVD) method, electron beam evaporation (E-beam evaporation), atomic layer deposition (ALD), thermal evaporation, sputtering, etc. can be used.

[0064] After the first electrode (60) and the second electrode (70) are formed, the resist pattern is lifted off and removed.

[0065]

[0066] <Manufacturing Example 1>

[0067] To dry-transfer a two-dimensional material, a hemispherical PDMS stamp was formed on a slide glass, a polycarbonate (PC) film was attached onto the PDMS stamp, and then heated on a hot plate at atmospheric pressure of 150-200°C to ensure that the PC film was evenly attached to the PDMS stamp. The slide glass on which the PDMS stamp was formed was coupled to the positioner of a probe station, and the movement of the PDMS stamp was controlled using the positioner.

[0068] The SiO2 substrate on which the WSe2 channel layer was formed was heated to 100-150°C at atmospheric pressure, a PDMS stamp was placed on top of the SiO2 substrate, and the PDMS stamp was lowered to pick up the WSe2 channel layer.

[0069] Next, the SiO2 substrate on which the hBN tunneling layer was formed was heated to 100-150°C at atmospheric pressure, and the hBN tunneling layer was aligned on the WSe2 channel layer attached to the lower part of the PDMS stamp. Then, the PDMS stamp was lowered so that the hBN tunneling layer was attached to the WSe2 channel layer, thereby picking up the hBN tunneling layer.

[0070] Next, a SiO2 blocking layer was formed on the Si substrate used as a control gate, and a graphene floating gate was formed on the SiO2 blocking layer. The SiO2 / Si substrate on which the graphene floating gate was formed was heated to atmospheric pressure of 100-150°C, and the graphene floating gate was aligned to the WSe2 / hBN attached to the bottom of the PDMS stamp, and then the PDMS stamp was lowered so that the graphene floating gate was attached to the WSe2 / hBN.

[0071] With WSe2 / hBN attached to the graphene floating gate, the SiO2 / Si substrate was heated at 170-200℃ under atmospheric pressure to attach the PC film and WSe2 / hBN / graphene to the SiO2 / Si substrate, and the PC film was removed using an organic solvent. Through this process, a structure was formed in which a SiO2 blocking layer, a graphene floating gate, an hBN tunneling layer, and a WSe2 channel layer were sequentially stacked on the Si control gate.

[0072] An electron beam resist was applied onto the above-described stacked structure, particularly onto the WSe2 channel layer, using spin coating. The resulting material was heated at atmospheric pressure for several minutes at 120-180°C, and then an electron beam resist pattern was formed using electron beam lithography equipment.

[0073] Ti and Au were sequentially deposited using electron beam deposition on the channel layer exposed by the electron beam resist pattern to form first and second electrodes spaced apart from each other. The electron beam resist pattern was then removed, completing the reconfigurable electronic device illustrated in Fig. 2.

[0074]

[0075] Hereinafter, the performance and operation of a reconfigurable electronic device according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing the bipolar memory characteristics of the reconfigurable electronic device of FIG. 1. FIG. 4 is a diagram showing the electrical characteristics of the reconfigurable electronic device of FIG. 1 according to a program voltage.

[0076] As shown in Fig. 3, the transfer curve (V) of the reconfigurable electronic device BG -I DS ) was confirmed to have a large bipolar hysteresis in both n-type and p-type, which indicates a bipolar memory characteristic due to the charge stored in the floating gate. In addition, it was confirmed that the n-memory window and the p-memory window enlarge as the range of the gate voltage increases when the gate voltage is swept, which indicates that the concentration and type of charge stored in the floating gate change depending on the gate voltage. In addition, according to retention measurements and endurance measurements, the reconfigurable electronic device of the present invention was confirmed to have a high retention of 10,000 seconds or more and maintain a constant conductivity for 10,000 cycles, thereby confirming excellent memory characteristics.

[0077] As illustrated in Fig. 4, the type and concentration (or density) of charge trapped (or stored) in the floating gate can be controlled depending on the polarity and magnitude of the program voltage applied to the control gate, thereby controlling the doping concentration of the channel layer.

[0078] Therefore, depending on the polarity and magnitude of the program voltage applied to the control gate, the channel layer has the characteristics of one of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor. As the absolute value of the program voltage increases toward positive polarity, the channel layer sequentially has the characteristics of an insulator, a p-type semiconductor, and a conductor. As the absolute value of the program voltage increases toward negative polarity, the channel layer sequentially has the characteristics of an insulator, an n-type semiconductor, and a conductor.

[0079] If the first voltage < second voltage < third voltage < 0 < fourth voltage < fifth voltage < sixth voltage, and the program voltage is lower than or equal to the first voltage or higher than or equal to the sixth voltage, the channel layer has conductor characteristics. If the program voltage is the first voltage or the second voltage, the channel layer has n-type semiconductor characteristics. If the program voltage is the second voltage or the third voltage or the fourth voltage or the fifth voltage, the channel layer has insulator characteristics. If the program voltage is the fifth voltage or the sixth voltage, the channel layer has p-type semiconductor characteristics.

[0080] For example, when the program voltage is -60 V or less or 60 V or more, the channel layer may have conductor characteristics, when the program voltage is -60 V to -45 V, the channel layer may have n-type semiconductor characteristics, when the program voltage is -45 V to -30 V or 30 V to 45 V, the channel layer may have insulator characteristics, and when the program voltage is 45 V to 60 V, the channel layer may have p-type semiconductor characteristics. In the case of such program voltage, it may vary depending on the type and thickness of the blocking layer (or gate oxide) stacked under the control gate. In the example described above, the case where a SiO2 dielectric with a thickness of 270 to 300 nm was used as the blocking layer was shown, but if the blocking layer is formed to have a thickness of about 30 nm, the program voltage can be lowered to a level of about 1 / 6 overall.

[0081] In this embodiment, the program voltage can be applied to the control gate in the form of a pulse (e.g., 100 ms). By applying a high program voltage of 30 V or more to the control gate, the type and concentration (or density) of charge stored in the floating gate can be controlled. Depending on the type and concentration of charge stored in the floating gate, the doping type and doping concentration of the channel layer can be changed, and when a relatively small gate voltage (e.g., -5 to 5 V) is applied to the control gate, it was confirmed that the channel layer has any one of the characteristics of a conductor, an insulator, an n-type semiconductor, and a p-type semiconductor.

[0082] For example, the transfer curve (V) of Fig. 4 BG -I DS ) Referring to the green part, when the program voltage is applied to the control gate in the form of a pulse (100 ms) below -60 V, a relatively large number of electrons in the floating gate pass through the tunneling layer and move to the channel layer, doping the channel layer with electrons. The transfer curve (V) for the gate voltage of -5 V to 5 V BG -I DS ) was measured, it was confirmed that the reconfigurable electronic element or channel layer has conductive properties. In this way, the type and concentration of charge stored in the floating gate can be controlled by the program voltage, and the stored charge can be maintained for a long time, so the reconfigurable electronic element also has memory characteristics. In addition, the output curve (V DS -I DS ) has a linear relationship and exhibits ohmic contact characteristics.

[0083] For example, the transfer curve (V) of Fig. 4 BG -I DS) Referring to the red part, when the program voltage of -60 V to -45 V is applied to the control gate in a pulse form (100 ms), relatively few electrons in the floating gate pass through the tunneling layer and move to the channel layer, doping the channel layer with electrons. The transfer curve (V) for the gate voltage of -5 V to 5 V BG -I DS ) was measured, it was confirmed that the reconfigurable electronic element or channel layer has n-type semiconductor characteristics. In this way, the type and concentration of charge stored in the floating gate can be controlled by the program voltage, and the stored charge can be maintained for a long time, so the reconfigurable electronic element also has memory characteristics. In addition, the output curve (V DS -I DS ) has a linear relationship and exhibits ohmic contact characteristics.

[0084] For example, the transfer curve (V) of Fig. 4 BG -I DS ) Referring to the yellow part, when the program voltage is applied to the control gate in a pulse form (100 ms) of -45 to -30 V or 30 to 45 V, no tunneling of charges or doping of the channel layer occurs. The transfer curve (V) for the gate voltage of -5 V to 5 V BG -I DS ) was measured, it was confirmed that the reconfigurable electronic element or channel layer has insulating properties. In this way, the type and concentration of charge stored in the floating gate can be controlled by the program voltage, and the stored charge can be maintained for a long time, so the reconfigurable electronic element also has memory properties.

[0085] For example, the transfer curve (V) of Fig. 4 BG -I DS) Referring to the blue part, when a program voltage of 45 V to 60 V is applied to the control gate in a pulse form (100 ms), relatively few electrons in the channel layer pass through the tunneling layer and move to the floating gate, doping the channel layer with holes. The transfer curve (V) for the gate voltage of -5 V to 5 V BG -I DS ) was measured, it was confirmed that the reconfigurable electronic element or channel layer has p-type semiconductor characteristics. In this way, the type and concentration of charge stored in the floating gate can be controlled by the program voltage, and the stored charge can be maintained for a long time, so the reconfigurable electronic element also has memory characteristics. In addition, the output curve (V DS -I DS ) has a linear relationship and exhibits ohmic contact characteristics.

[0086] For example, when a program voltage of 60 V or more is applied to the control gate in a pulse form (100 ms), a relatively large number of electrons in the channel layer move through the tunneling layer to the floating gate, doping the channel layer with holes. The transfer curve for the gate voltage of -5 V to 5 V (V BG -I DS ) was measured, it was confirmed that the reconfigurable electronic element or channel layer has conductive properties. In this way, the type and concentration of charge stored in the floating gate can be controlled by the program voltage, and the stored charge can be maintained for a long time, so the reconfigurable electronic element also has memory characteristics. In addition, the output curve (V DS -I DS ) has a linear relationship and exhibits ohmic contact characteristics.

[0087] In this way, it was confirmed that the reconfigurable electronic device of the present invention has four distinct device characteristics (i.e., conductor, n-type semiconductor, insulator, and p-type semiconductor) depending on the program voltage.

[0088]

[0089] Hereinafter, a logic element according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 and 6. FIG. 5 is a circuit diagram of a logic element according to an embodiment of the present invention. FIG. 6 is a diagram explaining the operation of the logic element of FIG. 5.

[0090] The logic element illustrated in Fig. 5 comprises two reconfigurable electronic elements (T1, T2), a first power supply (V DD ) and the second power supply (V SS ) are included. Here, two reconfigurable electronic elements are referred to as a first electronic element (T1) and a second electronic element (T2), and each electronic element has the same structure as illustrated in FIGS. 1 and 2.

[0091] The first electronic element (T1) and the second electronic element (T2) are connected to a first power source (V DD ) and the second power supply (V SS ) are connected in series between the first power supply (V DD ) can be the power supply voltage, and the second power supply (V SS ) may be a power ground voltage. The first electrode (1) of the first electronic element (T1) may be connected to the first power source (V DD ) is connected. The second electrode (2) of the first electronic element (T1) is connected to the first electrode (1) of the second electronic element (T2), and an output signal (V) is output from the connection point thereof. OUT ) is output. The second electrode (2) of the second electronic element (T2) is connected to the second power source (V SS ) is connected. The same input signal (A) is input to the control gate (g) of the first electronic element (T1) and the control gate (g) of the second electronic element (T2).

[0092] The program voltage (V) applied to the control gate (g) of the first electronic element (T1) IN1 ) depending on the polarity and size of the second electronic element (T2), and the program voltage (V) applied to the control gate (g) of the second electronic element (T2). IN2 ) depending on the polarity and size of the logic element of the present embodiment, the logic element of the present embodiment can perform four logic operations. Here, the four logic operations are A, NOT A, TRUE, and FALSE for the input signal (A). While a conventional CMOS inverter always operates only as a NOT A logic gate when it has a structure in which an n-type transistor and a p-type transistor are connected in series, the logic element according to the present embodiment can perform four logic operations by using two reconfigurable electronic elements having the same structure.

[0093] In the case of the first logic element in Fig. 6, a program voltage of the second to third voltages or the fourth to fifth voltages is applied to the first electronic element (insulating) so that the first electronic element (insulating) has insulating characteristics, and a program voltage of the first voltage or lower or the sixth voltage or higher is applied to the second electronic element (metallic) so that the second electronic element (metallic) has conducting characteristics. This logic element performs a FALSE logical operation on the human signal (A).

[0094] In the case of the second logic element in Fig. 6, a program voltage of the first voltage to the second voltage is applied to the first electronic element (n-type) so that the first electronic element (n-type) has n-type semiconductor characteristics, and a program voltage of the fifth voltage to the sixth voltage is applied to the second electronic element (p-type) so that the second electronic element (p-type) has p-type semiconductor characteristics. This logic element performs an A logic operation on a human signal (A).

[0095] In the case of the third logic element in Fig. 6, the first electronic element (p-type) is set to have p-type semiconductor characteristics by applying a program voltage of the fifth to sixth voltages to the first electronic element (p-type), and the second electronic element (n-type) is set to have n-type semiconductor characteristics by applying a program voltage of the first to second voltages to the second electronic element (n-type). This logic element performs a NOT A logical operation on the human signal (A).

[0096] In the case of the fourth logic element in Fig. 6, a program voltage lower than or equal to the first voltage or higher than or equal to the sixth voltage is applied to the first electronic element (metallic) to set the first electronic element (metallic) to have conductor characteristics, and a program voltage of the second to third voltages or the fourth to fifth voltages is applied to the second electronic element (insulating) to set the second electronic element (insulating) to have insulator characteristics. This logic element performs a TRUE logic operation on the human signal (A).

[0097]

[0098] Hereinafter, a logic element according to another embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9. FIG. 7 is a circuit diagram of a logic element according to another embodiment of the present invention. FIG. 8 is a diagram showing a logic operation performed by the logic element of FIG. 7. FIG. 9 is a diagram showing input signals and output signals according to the logic operation of FIG. 8.

[0099] The logic element illustrated in Fig. 7 comprises five reconfigurable electronic elements (T1 to T5), a first power supply (V DD ) and the second power supply (V SS) are included. Here, the five reconfigurable electronic elements are referred to as a first electronic element (T1), a second electronic element (T2), a third electronic element (T3), a fourth electronic element (T4), and a fifth electronic element (T5), and each electronic element has the same structure as illustrated in FIGS. 1 and 2.

[0100] The first electrode (1) of the fifth electronic element (T5) is connected to the first power source (V DD ) is connected to the second electrode of the fifth electronic element (T5), and the control gate (g) of the fifth electronic element (T5) is connected to the second electrode of the fifth electronic element (T5). The first electronic element (T1) and the second electronic element (T2) are connected to the second electrode (2) of the fifth electronic element (T5) and the second power source (V SS ) are connected in series between the first power supply (V DD ) can be the power supply voltage, and the second power supply (V SS ) may be a power ground voltage. The third electronic element (T3) and the fourth electronic element (T4) may be connected to the second electrode (2) of the fifth electronic element (T5) and the second power source (V SS ) are connected in series between them. The first electrode (1) of the first electronic element (T1) and the first electrode (1) of the third electronic element (T3) are connected to the second electrode (2) of the fifth electronic element (T5), and an output signal (V) is output from the connection point thereof. OUT ) is output. The second electrode (2) of the first electronic element (T1), the first electrode (1) of the second electronic element (T2), the second electrode (2) of the third electronic element (T3) and the first electrode (1) of the fourth electronic element (T4) are connected to each other. The second electrode (2) of the second electronic element (T2) and the second electrode (2) of the fourth electronic element (T4) are connected to a second power source (V SS ) are connected. The same first input signal (A) is input to the control gate (g) of the first electronic element (T1) and the control gate (g) of the second electronic element (T2). The same second input signal (B) is input to the control gate (g) of the third electronic element (T3) and the control gate (g) of the fourth electronic element (T4).

[0101] The channel layer of the fifth electronic element (T5) is preset by a predetermined program voltage to have n-type semiconductor characteristics for all logical operations of the logic element. For example, the fifth electronic element (T5) can be preset to have n-type semiconductor characteristics by applying a program voltage of the first voltage or the second voltage to the fifth electronic element (T5).

[0102] The program voltage (V) applied to the control gate (g) of the first electronic element (T1) IN1 ) depending on the polarity and size of the second electronic element (T2), the program voltage (V) applied to the control gate (g) of the second electronic element (T2) IN2 ) depending on the polarity and size of the third electronic element (T3), the program voltage (V) applied to the control gate (g) of the third electronic element (T3) IN3 ) depending on the polarity and size of the program voltage (V) applied to the control gate (g) of the fourth electronic element (T4). IN4 ) depending on the polarity and size of the logic element of the present embodiment, the logic element of the present embodiment can perform 16 logic operations. Here, the 16 logic operations are A, NOT A, B, NOT B, TRUE, FALSE, AND, OR, NOR, NAND, XOR, XNOR, IMP, NIMP, RIMP, and RNIMP for the first input signal (A) and the second input signal (B). The logic element according to the present embodiment can perform 16 logic operations using five reconfigurable electronic elements having the same structure.

[0103] Referring to FIGS. 8 and 9, for example, a program voltage of a first voltage or lower or a sixth voltage or higher may be applied to any one of the first to fourth electronic elements to set the corresponding electronic element to have conductor characteristics. Alternatively, a program voltage of a first voltage or a second voltage may be applied to any one of the first to fourth electronic elements to set the corresponding electronic element to have n-type semiconductor characteristics. Alternatively, a program voltage of a second voltage or a third voltage or a fourth voltage or a fifth voltage may be applied to any one of the first to fourth electronic elements to set the corresponding electronic element to have insulator characteristics. Alternatively, a program voltage of a fifth voltage or a sixth voltage may be applied to any one of the first to fourth electronic elements to set the corresponding electronic element to have p-type semiconductor characteristics. Accordingly, depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element, the logic element can perform 16 logical operations.

[0104]

[0105] Hereinafter, a logic element block according to an embodiment of the present invention will be described in detail with reference to FIG. 10. FIG. 10 is a circuit diagram and a diagram showing logic operations of a logic element block according to an embodiment of the present invention.

[0106] The logic element block illustrated in Fig. 10 is configured by connecting three logic elements of Fig. 7, and can perform arithmetic operations such as addition (1-bit FA), subtraction (1-bit FS), and comparator (1-bit comparator), respectively.

[0107]

[0108] Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical concept or essential features thereof. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A reconfigurable electronic device having transistor and memory functions using an ambipolar two-dimensional semiconductor. control gate; A floating gate formed on the control gate and electrically insulated from the surroundings; A tunneling layer formed on the floating gate; A channel layer formed on the above tunneling layer and made of an ambipolar two-dimensional semiconductor; and Including a first electrode and a second electrode formed spaced apart from each other on the channel layer, A reconfigurable electronic device, characterized in that the channel layer has any one of the characteristics of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor depending on the polarity and magnitude of the program voltage applied to the control gate.

2. In paragraph 1, A reconfigurable electronic device, characterized in that the channel layer is made of at least one bipolar two-dimensional semiconductor selected from the group consisting of WSe2, MoTe2, and BP.

3. In paragraph 1, A reconfigurable electronic device, characterized in that the floating gate is made of at least one two-dimensional conductor selected from the group consisting of graphene and PtTe2.

4. In paragraph 1, A reconfigurable electronic device, characterized in that the tunneling layer is made of at least one two-dimensional insulator selected from the group consisting of hBN and Sb2O3.

5. In paragraph 1, A reconfigurable electronic device characterized in that the floating gate, the tunneling layer, and the channel layer are all made of a two-dimensional material and are sequentially laminated on the control gate using a dry transfer method using a PDMS stamp.

6. In paragraph 1, A reconfigurable electronic device characterized in that, as the absolute value of the above program voltage increases bipolarly, the channel layer sequentially has the properties of an insulator, a p-type semiconductor, and a conductor.

7. In paragraph 1, A reconfigurable electronic device characterized in that, as the absolute value of the above program voltage increases toward negative polarity, the channel layer sequentially has the properties of an insulator, an n-type semiconductor, and a conductor.

8. In the first paragraph, when the first voltage < the second voltage < the third voltage < 0 < the fourth voltage < the fifth voltage < the sixth voltage, When the program voltage is lower than or equal to the first voltage or higher than or equal to the sixth voltage, the channel layer has a conductive characteristic. When the program voltage is the first voltage or the second voltage, the channel layer has an n-type semiconductor characteristic, When the program voltage is the second voltage to the third voltage or the fourth voltage to the fifth voltage, the channel layer has an insulating characteristic, A reconfigurable electronic device, characterized in that the channel layer has p-type semiconductor characteristics when the program voltage is the fifth voltage or the sixth voltage.

9. A method for manufacturing a reconfigurable electronic device having transistor and memory functions using an ambipolar two-dimensional semiconductor, Steps to prepare the control gate; A step of sequentially stacking a floating gate, a tunneling layer, and a channel layer on the control gate using a dry transfer method using a PDMS stamp, wherein the channel layer is made of an ambipolar two-dimensional semiconductor; A step of forming a resist pattern on the channel layer; and A step of forming a first electrode and a second electrode spaced apart from each other on the channel layer exposed by the register pattern, A method for manufacturing a reconfigurable electronic device, characterized in that the channel layer has any one of the characteristics of a conductor, an n-type semiconductor, an insulator, and a p-type semiconductor depending on the polarity and magnitude of the program voltage applied to the control gate.

10. A logic element comprising a first electronic element according to paragraph 1, a second electronic element according to paragraph 1, a first power source, and a second power source, The first electronic element and the second electronic element are connected in series between the first power source and the second power source, The first electrode of the first electronic element is connected to the first power source, The second electrode of the first electronic element is connected to the first electrode of the second electronic element, and an output signal is output from the connection point thereof. The second electrode of the second electronic element is connected to the second power source, A logic element characterized in that the same input signal (A) is input to the control gate of the first electronic element and the control gate of the second electronic element.

11. In paragraph 10, A logic element characterized in that the logic element performs four logical operations depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element.

12. In paragraph 11, A logic element characterized in that the above four logical operations are A, NOT A, TRUE, and FALSE for the input signal (A).

13. A logic element comprising a first electronic element according to paragraph 1, a second electronic element according to paragraph 1, a third electronic element according to paragraph 1, a fourth electronic element according to paragraph 1, a fifth electronic element according to paragraph 1, a first power source, and a second power source, The first electrode of the fifth electronic element is connected to the first power source, and the control gate of the fifth electronic element is connected to the second electrode of the fifth electronic element. The first electronic element and the second electronic element are connected in series between the second electrode of the fifth electronic element and the second power source, The third electronic element and the fourth electronic element are connected in series between the second electrode of the fifth electronic element and the second power source, The first electrode of the first electronic element and the first electrode of the third electronic element are connected to the second electrode of the fifth electronic element, and an output signal is output from the connection point thereof. The second electrode of the first electronic element, the first electrode of the second electronic element, the second electrode of the third electronic element and the first electrode of the fourth electronic element are connected to each other, The second electrode of the second electronic element and the second electrode of the fourth electronic element are connected to the second power source, The same first input signal (A) is input to the control gate of the first electronic element and the control gate of the second electronic element, A logic element characterized in that the same second input signal (B) is input to the control gate of the third electronic element and the control gate of the fourth electronic element.

14. In paragraph 13, A logic element characterized in that the logic element performs 16 logical operations depending on the polarity and magnitude of the program voltage applied to the control gate of each electronic element.

15. In paragraph 14, A logic element characterized in that the above 16 logical operations are A, NOT A, B, NOT B, TRUE, FALSE, AND, OR, NOR, NAND, XOR, XNOR, IMP, NIMP, RIMP, and RNIMP for the first input signal (A) and the second input signal (B).

16. In paragraph 13, A logic element characterized in that the channel layer of the fifth electronic element is set to have n-type semiconductor characteristics by a program voltage.

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