Method for matching structures of a layout of a microelectronic component layer

Abstract

The invention relates to the field of lithographic processes. A method for matching structures of the layout of a layer of a microelectronic component with structures of the layout of a desired layer includes the steps of: obtaining a structure of a desired layout of a layer of a silicon wafer of a microelectronic component; obtaining at least one image of the surface of a manufactured silicon wafer of the microelectronic component; processing said at least one image using a neural-network based machine learning model trained to mark structures of the layout of a layer of a microelectronic component; generating at least one marked image of at least one structure of the layout of the layer of the microelectronic component; matching the at least one marked image of the structure of the layout of the layer of the manufactured silicon wafer of the microelectronic component with a structure of the desired layout of said layer of the silicon wafer of the microelectronic component; generating a set of images which contains at least one pair of images that corresponds to an image of the structure of the desired layout of the layer of the silicon wafer of the microelectronic component and an image of the same structure on the image of the manufactured layer. The result is an increase in the accuracy with which structures of the layout of a layer of a microelectronic component are matched with structures of the layout of a desired layer.

Description

METHOD FOR COMPARING STRUCTURES OF THE LAYER TOPOLOGY OF A MICROELECTRONIC COMPONENT AREA OF TECHNOLOGY

[0001] The claimed technical solution generally relates to the field of lithographic processes, and in particular to a method for matching the topology structures of a microelectronic component layer with the topology structures of a designed layer. LEVEL OF TECHNOLOGY

[0002] In lithography, to achieve the best possible approximation of the geometric shape and dimensions of the resulting layer topology structures of a microelectronic component to the design rules, attempts to correct optical proximity effects (abbreviated OPC) began with a simple displacement of the elements of the structure drawing or the addition of artificial elements to the original structure. These methods belonged to the first generation of OPC and were called rule-based (the first seminal works were published in the 1980s ([Saleh and Sayegh, 1981], [Nashold and Saleh, 1985]). Then, as chip sizes continued to decrease and available computing resources increased, OPC became more sophisticated and evolved into the SRAF-based approach.Around the same time, the concept of inverse lithography technology (ILT) emerged - a technology (inverse approach), which determines the shape of the mask that allows the desired result to be obtained on the wafer, is considered worldwide as a promising solution to many problems of lithography with improved nodes, whether optical or EUV.

[0003] Due to the specifics of the lithographic process, when creating a chip based on OPC-ILT technology, it is necessary to obtain a reliable set of data, including: knowledge of the geometry of isolated structures; knowledge of the data and parameters of the survey; information on the position and angle of the field of view of the SEM (scanning electron microscope) relative to the original topology of the drawing of the layer of the microelectronic component; information on the calibration of the lithograph exposure mode; information that allows for reliable identification structures placed on the drawing and determine its exact position on a series of SEM images.

[0004] The lithographic process involves many production stages that have a strong impact on the final result: from the photomask illumination stage, exposure processes, development chemistry, curing and cleaning, each of which is often itself an iterative process, which can lead to cumulative error in the final result.

[0005] To minimize errors due to resolution limitations in the lithography process, integrated circuit (IC) manufacturing processes inspect unfinished or finished components to ensure they are manufactured according to the design and free of defects. This includes, for example, verifying that the geometry of structures produced on the silicon wafer matches the design intent, as well as verifying compliance with Mask Rule Check (MRC) conditions on the manufacturer's actual equipment.

[0006] The result of such checks, both of the intermediate and final OPC-ILT result, is an accurate correlation of the obtained ILT structure with the designed drawing.

[0007] During the initial stages of preparing a microelectronic component layer, such as a photomask (PM), the structures proposed for placement may be unevenly distributed across the drawing surface. During the imaging and calibration process, the structures, which have been processed through the OPC-ILT optimizer model and the equipment simulator using the developed technology, undergo changes. Their shape, center coordinates, and contour boundaries may shift relative to the overall coordinate system of the drawing. The dimensions of these structures can vary widely, which can lead to significant accumulated errors. The manufacturer physically fabricates the PM mask in several stages, including intermediate tests of the target topology in accordance with its technological process and the production of test PMs. The quality of the resulting PMs is monitored by scanning the entire photoresist surface or a portion of it using SEM technology.

[0008] Photographing the manufactured FS using SEM, followed by searching and matching the frame with the corresponding group in vector format The original topology drawing is a complex technical task due to the fact that the captured FS has a surface curvature, which manifests itself as an accumulated systematic error in the positioning of the frame sequence during the entire scanning time in the SEM and leads to significant errors in the calculation of the coordinates of the structures; when installing the FS in the cuvette for shooting, the surface of the template may be inclined relative to the plane of image formation in the SEM; when shooting with variable resolution, it may be necessary to compare the shooting frames of both adjacent frames and, possibly, intermediate ones; when shooting curvilinear structures of the OPC, the geometric shape changes relative to the original topology, i.e. their center of gravity can shift significantly, which, during the iterative ILT process, will yield a set of different coordinates of the same structure.

[0009] Currently, the identification of structures and their correlation with the drawing in real production is performed through operator intervention.

[0010] The well-known approach based on manual identification of structures and their correlation with the drawing has a number of disadvantages. [OOP] Thus, the obvious disadvantages of this approach include the need to manually capture each layer structure and the low accuracy of matching structures obtained by SEM imaging with the drawing structures, due to the need to work with images at the boundaries of the process window's technological standards. Furthermore, the manual process requires significant time and computational resources, which consequently increases the overall lithographic process time.

[0012] Also known from the prior art is a solution disclosed in source No. WO2023 / 144548 Al (CAMBRIDGE ENTPR LTD [GB]), published on 03.08.2023. This solution discloses a method for detecting structures based on a positional mark.

[0013] The disadvantages of this solution include low accuracy during automatic survey due to the low accuracy of identifying positional markers at the boundaries of the process window technological standards due to strong distortions, which, as a consequence, leads to low accuracy in matching the topology of the microelectronic component layer with the designed layer.

[0014] Accordingly, the goal of this technical solution is to create a method for automatically capturing and matching layer topology structures to the original drawing with high accuracy during the creation of a microelectronic component. This solution should reduce the time required to design the layer topology. microelectronic component and ensure the possibility of timely detection of inaccuracies in the manufacture of the microelectronic component. DISCLOSURE OF THE INVENTION

[0015] The claimed technical solution proposes a new approach to comparing the topology structures of a microelectronic component layer with the corresponding topology structures of the designed layer.

[0016] The technical problem of comparing the structures of the layer topology of a microelectronic component is solved.

[0017] The technical result achieved by solving this problem is an increase in the accuracy of matching the topology structures of a microelectronic component layer with the topology structures of the designed layer.

[0018] An additional technical result that emerges from solving the above-mentioned problem is the provision of the ability to automatically capture and compare the topology structures of a microelectronic component layer with the topology structures of the designed layer.

[0019] The specified technical results are achieved by implementing a method for comparing the structures of the topology of a microelectronic component layer with the structures of the topology of a designed layer, comprising the stages of: a) obtaining the structure of the designed topology of a layer of a silicon wafer of a microelectronic component; b) obtaining at least one image of the surface of the manufactured silicon wafer of the microelectronic component; c) processing at least one image obtained in step b) using a machine learning model based on a neural network trained to mark the structures of the topology of a layer of a microelectronic component, wherein, during the training, the following is performed: i. forming a set of images of the structures of the topology of the designed layer of the microelectronic component; ii. processing the formed set using a lithograph simulator model; iii. creating a training data set, based on the data obtained in step ii, containing synthetic images of the manufactured layers of the silicon wafer of the microelectronic component; d) forming at least one labeled image of at least one structure of the topology of the layer of the microelectronic component, based on the data obtained in step c); e) comparing at least one labeled image of the structure of the topology of the layer of the manufactured silicon wafer of the microelectronic component with the structure of the designed topology of the layer of the silicon wafer of the microelectronic component; f) forming a set of images containing at least one pair of images corresponding to the image of the structure of the designed topology of the layer of the silicon wafer of the microelectronic component and the image of the same structure in the image of the manufactured layer.

[0020] In one of the particular embodiments of the method, the structures of the designed topology of the silicon wafer layer of the microelectronic component are made in vector format.

[0021] In another particular embodiment of the method, at least one image of the surface of the manufactured silicon wafer of the microelectronic component is obtained by scanning electron microscopy.

[0022] In another particular embodiment of the method, the structure of the topology of the layer of the microelectronic component represents an analog or digital block of the physical topology, or its component, implementing the required logical function and / or carrying the information component.

[0023] In another particular embodiment of the method, the structure of the topology of the layer of the microelectronic component is a connection between blocks and their constituent parts or input-output elements, memory blocks, multipliers, simple or composite markers, represented at least in the form of single or periodic elementary geometric figures and their combinations, made in the form of transparent and opaque sections equivalent to the simplest elements of an electrical circuit.

[0024] In another particular embodiment of the method, during processing of an image by a machine learning model, the following is performed: i. processing the image and constructing a probability distribution characterizing the position and boundaries of the detected positional markers for each image of the frame containing at least one structure; ii. selecting positional markers on each obtained image of the frame; iii. correlating the detected positional markers with known data on their mutual arrangement; iv. detecting the position of the selected structure based on the data obtained in step iii; v. assigning coordinates and a unique identification number to the positional markers.

[0025] In another particular embodiment, the method further comprises determining the completeness of the structure on the marked image of the frame of the topology of the layer of the manufactured silicon wafer of the microelectronic component.

[0026] In another particular embodiment of the method, stitching of adjacent images is performed in the event of the absence of a complete structure in the image.

[0027] In another particular embodiment of the method, during stitching of adjacent images, the following is performed: i. selecting at least two adjacent images of a silicon wafer for alignment; ii. selecting the first of the two images as a reference image and the second of the two images as a comparison object; iii. determining the parameters of the alignment function of the distorted image; iv. aligning the distorted image based on the alignment function; v. gluing at least two images; vi. cropping the images in accordance with the sizes of the compared structures of the silicon wafer topology.

[0028] In another particular embodiment of the method, the processing of the generated set of images of the topology structures of the designed layer The microelectronic component additionally includes the introduction of noise that characterizes the effect of shooting with an electron microscope.

[0029] In another particular embodiment of the method, the synthetic images are images simulating the characteristics of the manufactured layers of the microelectronic component removed from the surface of the silicon wafer using the SEM method. BRIEF DESCRIPTION OF DRAWINGS

[0030] The features of the claimed technical solution and a detailed description are given below in the form of attached drawings.

[0031] Fig. 1 illustrates a block diagram of the implementation of the claimed method.

[0032] Fig. 2 illustrates a particular example of an organized structure in vector format with a unique positional code.

[0033] Fig. 3 illustrates a particular example of organizing a frame with a positional code.

[0034] Fig. 4 illustrates an example of detection of a target structure in an SEM image.

[0035] Fig. 5 illustrates the result of the SEM operation.

[0036] Fig. 6 illustrates the probability distribution characterizing the position and boundaries of the detected position markers for the image of the frame of a layer of a microelectronic component, removed at different exposure doses.

[0037] Fig. 7 illustrates a block diagram of the operating principle of the MO model.

[0038] Fig. 8 illustrates an example of the formation of the topology of a drawing of a layer of a microelectronic component in the form of groups including a sequence of previously selected frames.

[0039] Fig. 9 illustrates an example of creating a synthetic dataset.

[0040] Fig. 10 illustrates an example of SEM images with an inscribed and incomplete frame.

[0041] Fig. 11 illustrates the image stitching algorithm.

[0042] Fig. 12 illustrates an example of a resulting set of images containing an image of the structure of the matched designed topology of a layer of a silicon wafer of a microelectronic component and an image of the same structure in a photograph of the manufactured layer.

[0043] Fig. 13 illustrates an example of the general appearance of a computing device that ensures the implementation of the claimed solution. IMPLEMENTATION OF THE INVENTION

[0044] Below we will describe the concepts and terms necessary for understanding this technical solution.

[0045] A model in machine learning (ML) is a set of artificial intelligence methods whose characteristic feature is not a direct solution to a problem, but learning in the process of applying solutions to many similar problems.

[0046] A photomask (PM) is a plane-parallel silicon wafer onto which a pattern is applied, consisting of a combination of sections that are transparent and opaque to light of a certain wavelength, characterizing the topology of a translucent layer of a microcircuit or a group of layers (manufactured using a lithographic method).

[0047] The mask is what needs to be printed on the FS (requiring its own lithographic process). The mask size is usually several times smaller than the FS dimensions.

[0048] Control structures (CS) Standard topological elements with known geometric parameters intended to confirm the developed OPC-ILT technology.

[0049] The Graphic Design System (GDS)—or GDSII—is a database file format that is the industry standard for exchanging data on integrated circuits and their topologies. This format describes flat geometric shapes, text labels, and other information in a hierarchical format.

[0050] Structures of the layer topology of a microelectronic component - an analog or digital block (blocks) of a real topology, or its component (parts), implementing the required logical function or carrying another information component, implementing the connection between blocks, input-output elements (contact pads), memory blocks, multipliers, simple or composite markers and other components and / or their component parts represented at least in the form of single or periodic elementary geometric figures (squares, rectangles, circles) and their combinations made in the form of transparent and opaque sections equivalent to the simplest elements of an electrical circuit in the circuit image or parts thereof, originally represented in vector format and physically manufactured on a silicon wafer.

[0051] A frame is a unique frame placed around target structures and containing information that allows the structures to be identified and positioned within the frame on GDS and microscope images.

[0052] Scanning electron microscopy (SEM) is a scanning electron microscopy technique. It is designed to obtain high-resolution images of an object's surface (for the particular case of the solution described here—a plane-parallel silicon wafer), as well as information on the composition, structure, and other properties of the near-surface layers. It is based on the interaction of an electron beam with the object being studied.

[0053] The claimed technical solution offers a new approach to creating a method for automatically capturing and matching layer topology structures with the original drawing during the creation of a microelectronic component with high accuracy. Furthermore, the claimed invention enables the alignment and framing of the microelectronic component layer surface relative to the original drawing during capturing.

[0054] The claimed technical solution can be implemented on a computer, in the form of an automated information system (AIS) or a machine-readable medium containing instructions for performing the above-mentioned method.

[0055] The technical solution can also be implemented as a distributed computer system or computing device.

[0056] In this solution, the term “system” refers to a computer system, an electronic computer (EC), a numerical control (NC), a programmable logic controller (PLC), computerized control systems, and any other devices capable of performing a given, clearly defined sequence of computing operations (actions, instructions).

[0057] Thus, the system may comprise or include at least a command processing unit. A command processing unit refers to an electronic unit or integrated circuit (microprocessor) that executes machine instructions (programs).

[0058] The instruction processing unit reads and executes machine instructions (programs) from one or more storage devices, such as devices such as random access memory (RAM) and / or read-only memory (ROM). ROM can include, but is not limited to, hard drives (HDD), flash memory, solid-state drives (SSD), optical storage media (CD, DVD, BD, MD, etc.), etc.

[0059] A program is a sequence of instructions intended for execution by a computer control unit or command processing device.

[0060] The term "instructions" as used in this application may generally refer to software instructions or software commands written in a given programming language to perform a specific function, such as text encoding and decoding, filtering, ranking, text translation into a dialog system, etc. The instructions may be implemented in a variety of ways, including, for example, object-oriented methods. For example, the instructions may be implemented using the Python programming language, C++, Java, Python, various libraries (e.g., MFC; Microsoft Foundation Classes), etc. The instructions that perform the processes described in this solution may be transmitted via both wired and wireless data transmission channels, such as Wi-Fi, Bluetooth, USB, WLAN, LAN, etc.

[0061] Fig. 1 shows a block diagram of a method 100 for comparing the topology structures of a microelectronic component layer with the topology structures of a designed layer (system 200). Said method 100 consists of performing steps aimed at processing images obtained from SEM devices. The processing is typically performed using a system, for example, system 200, which may also represent, for example, a server, a computer, a scanning electron microscope, a computing device, etc. The elements of system 200 are disclosed in more detail in Fig. 13.

[0062] The claimed technical solution can be used to verify the conformity of the manufactured layer topology structure of a microelectronic component with the desired (designed) layer topology structure of the microelectronic component. This verification is an integral part of the lithographic process and significantly affects the final result (the occurrence of deviations in the designed and manufactured topology structure). entails a number of consequences related to the performance of the microelectronic component).

[0063] At step 110, the system, such as system 200, obtains a structure of the designed topology of a layer of a silicon wafer of a microelectronic component.

[0064] Thus, at said step 110, a system such as system 200, for example, via communication channels such as a connecting bus (e.g., memory access), data transmission channels such as the Internet, LAN (local area network), etc., obtains the structure of the designed topology of a layer of a silicon wafer of a microelectronic component. In one particular embodiment, the structure can be loaded via storage media such as removable storage media.

[0065] In another particular embodiment, the structure of the designed topology of a layer of a silicon wafer of a microelectronic component may be implemented in a vector format, for example, in the GDS format.

[0066] In this solution, a microelectronic component refers to electronic components manufactured using microelectronic technologies. These include integrated circuits, transistors, diodes, resistors, capacitors, and other components that can be integrated onto a crystalline substrate. Thus, in one particular embodiment, a microelectronic component may be a microcircuit, integrated circuit chip, etc., without limitation.

[0067] As noted above, a structure may represent an analog or digital block(s) of a real topology, or a component(s) thereof, implementing a required logical function or carrying another information component. Thus, a structure may describe a set of elements implementing a specific microcircuit block, organized in a specific order. In another particular embodiment, a structure may represent a set of the simplest elements of a microcircuit's electrical circuit, such as transistors, etc. Furthermore, in yet another particular embodiment, a structure may represent a set of elements intended for configuring lithograph or SEM equipment, or represent information about selecting a focus exposure dose, etc.

[0068] In turn, topologies include sets of target structures intended for subsequent optimization and assembly, as well as coding structures, positioning markers, debugging, calibration, control structures and other elements.

[0069] Thus, to compare designed structures, positional markers are used. These markers are artificial structures, symbols, or images placed on the layer layout drawing of a microelectronic component. When the system recognizes a positional marker, it can be used to determine its location, orientation, or encoded information.

[0070] Typically, lithography uses markers such as arrays of squares or crosses to facilitate feature detection on wafers. In addition to the specified marker shapes, markers of any geometry can be used. The marker geometry and their relative positions provide a specific feature that can be used to determine the relationships between structures and marker arrays and control characteristics during subsequent fabrication steps.

[0071] It's worth noting that this approach is ineffective when such markers fall on the image boundary, as the imaging process occurs at the boundary of the technical norm (nanostructure), which, accordingly, introduces significant distortions and prevents the identification of these markers. Thus, in order to expand the process window when changing doses and exposure foci, additional distortions are possible, in which some markers will either not be detected with the required accuracy, or other structures will be detected and mistaken for positional markers (see Fig. 6).

[0072] The aim of the present invention, among other things, is to overcome the said problem.

[0073] Returning to step 110, the structure of the designed silicon wafer layer topology of the microelectronic component can be represented in a vector format, such as a GDS drawing. In one particular embodiment, said structure can be pre-organized and supplemented with a unique positional code. Thus, the topological target structures can be combined into rectangular cells (frames), the cells are hierarchically arranged into groups, and the groups form the crystal topology. This approach, in particular, allows for the unambiguous identification of an SEM image with a similar cell drawing in the GDS. An example of the organization of this structure is shown in Fig. 2.

[0074] Accordingly, position markers carry information about the coordinates of a group and / or cell on the crystal topology, frame boundaries, frame coordinates in binary code and other useful information, see Fig. 3.

[0075] Fig. 3 shows the proposed organization of a frame (cell) in a group on the FS: red circles indicate the positional markers of the active frame, purple indicates adjacent positional markers, and green indicates vertical and horizontal markers carrying other technological information in the form of a given encoding.

[0076] Thus, at step 110, the designed topology of the silicon wafer layer of the microelectronic component is obtained in the form of a set of structures organized in a special way, in particular into frames.

[0077] Next, at step 120, at least one image of the surface of the manufactured silicon wafer of the microelectronic component is obtained using SEM.

[0078] As stated above, in order to minimize the influence of undesirable process effects that affect the resulting deviation of the implemented structure relative to the design parameters, it is necessary to manufacture a sample of the microelectronic component layer with the designed structure, since the structures proposed for placement (designed) may not be distributed uniformly over the surface of the drawing.

[0079] Thus, to implement the method 100 it is necessary to: detect the required positioning elements on the drawing of the layer of the silicon wafer of the microelectronic component (Designated as: 1 - 3 in Fig. 4). Detect similar positioning elements on the photograph of the manufactured layer of the silicon wafer of the microelectronic component (Designated as 1 - 3 in Fig. 4). Detect and compare the target structure on the drawing and the photograph of the manufactured layer of the silicon wafer of the microelectronic component (Designated as 4 in Fig. 4). Where the specified designations 1 are position markers, 2 are the cell coding system, 3 are the coding system (designation of boundaries / calibration grid), 4 are the target structure (object of comparison). It is worth noting that the number 2 designates the boundary markers, which can have the form, for example, Crosses at different angles, etc., without limitation. These markers can be used as technical information in automated surveys in the form of binary code.

[0080] The complexity of this method lies in the fact that during the imaging and calibration process, the structures processed by the developed technology through the OPC-ILT optimizer model and equipment simulator undergo changes. Their shape, center coordinates, and contour boundaries may shift relative to the overall drawing coordinate system. The dimensions of these structures can vary widely. The manufacturer physically produces the FSM mask in several stages, including intermediate tests of the target topology in accordance with its technological process and the production of test FTPs. Furthermore, due to the aforementioned distortions, during the recognition of positional markers in the resulting image, these markers cannot always be identified. Another complication is image displacement, which further complicates the comparison of structures.

[0081] The quality of the obtained FS is controlled by the results of shooting the entire surface of the photoresist or part of it, obtained using shooting equipment.

[0082] The device for obtaining an image of the surface of a silicon wafer may be at least one of the following devices: a scanning electron microscope, an atomic force microscope, an electron beam monitoring system, etc.

[0083] An electron microscope, a type of scanning electron microscope (SEM), is capable of creating an image of a sample by scanning its surface with a focused beam of electrons. The electrons interact with the atoms in the sample, generating various signals that contain information about the surface topography and composition of the sample. The electron beam is scanned as a raster image, and the beam position is combined with the intensity of the detected signal to produce an image.

[0084] In one particular embodiment, at step 120, at least one image of a manufactured layer of a silicon wafer of a microelectronic component, for example, a mask of a photomask, is obtained by scanning with an SEM. Thus, in another particular embodiment, when the SEM is operating in scanning mode according to a given program, a sequence of frames is generated (possibly of different physical sizes and obtained from different sections of the FS, see Fig. 5, where 1 are control elements (position markers) corresponding to 1 in Fig. 4, and 4 in Fig. 5 are images of useful structures.

[0085] As can be seen from Fig. 5, the sequence of frames can be shifted relative to each other, which, as indicated above, makes it difficult to compare the structures of topologies.

[0086] The resulting image (photograph) can be transmitted to a system, such as system 200, via wired or wireless communication channels. In another particular embodiment, the image can be stored in the SEM memory for subsequent comparison with the structure of the designed silicon wafer layer topology of the microelectronic component.

[0087] At step 130, at least one image obtained at step 120 is processed using an ML model trained to mark the topology structures of a layer of a microelectronic component, wherein, during training, the following is performed: forming a set of images of the topology structures of the designed layer of the microelectronic component; processing the formed set using a lithograph simulator model; creating a training set of synthetic data containing synthetic images of the manufactured layers of the silicon wafer of the microelectronic component.

[0088] Thus, the specified step 130 can be performed by means of an ML model, for example, a convolutional neural network, designed to detect objects and their coordinates in the original image. For example, such as the model described in the source, see [Zhou et al., 2019] Zhou, X., Wang, D., and Kra. .henbu. .hl, P. (2019). Objects as points. In arXiv preprint arXiv: 1904.07850.

[0089] The task of topology marking involves finding a system of positional markers on the image of a microscope photograph (the indicated markers are located on the drawing of the structure, see step 110) and correlating them with the drawing in vector representation.

[0090] To implement the specified task (marking markers on an image), the neural network of the ML model was modified in this technical solution.

[0091] Thus, the result of the above model is a probability distribution during the analysis, which, for the selected class, determines the corresponding coordinates of the centers of objects.

[0092] Due to the fact that the target structures placed on the drawing are specific and rarely encountered, and also for reasons related to the variability of the process window, the reliability of detection only by the probability map of the detected structures cannot be sufficient.

[0093] As shown in Fig. 6, in some cases (due to changes in dose, survey characteristics, structure geometry, etc.), the model identifies other structures as positional elements (designated by number 3). Fig. 6 shows a visualization of the probability map: Left - obtained at the output of the original ML model; Right - after refinement (1 - correctly detected positional structures, 2 - incorrect detection, 3 - correction of false detection after refinement).

[0094] Accordingly, to address this issue and improve the efficiency of matching microelectronic component layer topology structures, a refinement of the model was implemented. This refinement includes a modification of the resulting model layer responsible for correlating information about all adjacent markers (Fig. 7). In its initial implementation, the ML model has three outputs, designated in Fig. 7 as heatmap, H, and W, offset. The heatmap generates a probability distribution for the positions of position marker centers, which can be conventionally represented as a limited set of classes. The symbols W and H denote the predicted sizes of detected markers as width and height relative to the calculated centers, and offset is the predicted shift in the position of detected markers after spatial reconstruction, as determined by the model.The heatmap union modification involves jointly processing all parameters of the original model and filtering them based on knowledge of the projected distribution and location.

[0095] Fig. 7 schematically illustrates the process of refining a machine learning model. From left to right, the figure shows the original microscope image; the original model calculates a probability map; the refined model correlates the probability map with information about adjacent labels; and the output is a labeled (marked) image.

[0096] To implement this feature, the ML model was trained on artificially created synthetic images of GDS frames passed through a lithograph and microscope simulator model that simulates lithograph and microscope noise.

[0097] To create the training dataset, the following steps were performed, detailed below.

[0098] The first step involved detecting a group of frames in the overall GDS drawing; detecting a specific frame within a selected group in the overall GDS drawing; determining the frame's coordinates and the target structure; and cutting the GDS drawing into a sequence of selected frames. Thus, the target group was extracted from the original vector topology and then cut into the corresponding cells (frames) precisely along their boundaries. An example of this step is shown in Fig. 8.

[0099] Next, in the second step, an artificial data set was created based on the frames.

[0100] At this step, an artificial data set was formed from the initial topology in vector format, which, to the maximum approximation, describes the expected result from the SEM output.

[0101] To create the specified data set, the drawing images were processed by a lithograph simulator model that simulates the effects occurring inside the lithography equipment, as well as the effects obtained as a result of serial imaging with a microscope.

[0102] The result of the processing was the creation of a set of image pairs for all selected cells of the GDS drawing topology in the form shown in Fig. 9.

[0103] In Fig. 9, from left to right: a selected cell in vector format; the same cell in raster image format; an image passed through a rigorous model of a lithograph simulator; an image after the simulator with added noise simulating shooting from a microscope.

[0104] An analytical simulator model, which belongs to a family of models collectively called the diffraction-limited simulator or physical model, can be used as a lithograph simulator model. For example, the Neural-ILT method, based on end-to-end training of a neural network for obtaining OPC structures by predicting the effects of mask image curvature (see, for example, the source, found on the Internet: https: / / www.cse.cuhk.edu.hk / ~byu / papers / C103-ICCAD2020-Neural-ILT.pdf), Neural-ILT includes a model trained on data and accepting as input parameters describing the optical, exposure dose, focus variability and photoresist threshold model.

[0105] Another specific embodiment may utilize a proprietary model, which belongs to a family of models collectively referred to as the diffraction-limited simulator model. This model includes an optical model and a resist model that takes into account lithograph parameters.

[0106] After processing the images for all selected GDS drawing topology cells, a set of image pairs is created containing both the original GDS drawing topology cell images and synthetic images.

[0107] Next, a training data set is formed from the specified pairs of images, containing synthetic images of the manufactured layers of the silicon wafer of the microelectronic component.

[0108] Thus, through training and the above-mentioned refinement of the ML model on synthetic data, the quality of labeling and structure detection is improved.

[0109] Now let us consider directly the process of processing the image obtained at step 120 by the specified ML model. [IT] At the first stage, the image received by the model is processed. Processing an image by the ML model means extracting the useful signal from the noise using neurons. Next, based on the processing results, a probability distribution of the positions and boundaries of the detected positional markers is constructed for each image in the frame containing at least one structure.

[0111] The next step involves selecting positional markers in each resulting image. This selection is based on the highest probabilities obtained in the previous step. In other words, at this stage, the markers with the highest probability are selected, as shown in Figure 6.

[0112] In the third step, the detected positional markers are compared with known data about their relative positions.

[0113] Next, the position of the selected structure is detected.

[0114] Thus, a specific structure has no marker, but the marker belongs to a frame. Accordingly, the position of the structure is determined based on the corresponding dimensions of the structure relative to the frame coordinates measured from the markers.

[0115] The result of the machine learning model at step 130 is the assignment of coordinates and a unique identification number to the positional markers of the structure.

[0116] As noted above, the indicated markers allow for a clear correlation between the structure obtained by SEM imaging and the structure of the drawing.

[0117] At step 140, at least one marked image of at least one structure of the topology of a layer of a microelectronic component is formed.

[0118] At step 140, by processing the image with the machine learning model, which involves obtaining the original image from the microscope, calculating a probability map, and correlating the probability map with information about adjacent markers, a labeled image is obtained. A labeled image is an image in which the coordinates of the positional markers defining the boundaries of the structure have been found and determined. An example of a labeled image is shown in Fig. 7.

[0119] In one particular embodiment, when imaging the surface of a silicon wafer using an SEM, for example, in automatic mode, the images captured automatically may not contain a complete frame and have different physical resolutions. See Fig. 10. Thus, in Fig. 10, on the left is a frame with a completely inscribed frame, on the right is the observed shift in the frame position in the SEM frame.

[0120] When obtaining such a frame, the useful structure may be incomplete, which prevents the obtained frame from being correlated with the drawing. To address this problem, in one particular embodiment, method 100 may further comprise the step of determining the completeness of the structure on the marked image of a layer of the manufactured silicon wafer of the microelectronic component by determining the presence of all positional markers in the frame image. In another particular embodiment, the completeness of the structure is determined by the presence of at least all positional markers corresponding to the frame and, if necessary, other frame elements.

[0121] Thus, in the absence of a complete structure in the image, stitching of adjacent images is performed.

[0122] The stitching of images may also be performed by means of a system such as system 200. During the stitching of adjacent images, the following is performed: selecting at least two adjacent images of a silicon wafer for alignment; selecting the first of the two images as a reference image and the second of the two images as a distorted image; determining the parameters of the alignment function of the distorted image; aligning the distorted image based on the alignment function; gluing at least two images; cropping the images in accordance with the sizes of the compared structures of the topology of the silicon wafer.

[0123] Images that contain a full frame only need to be cropped, while images of the second type need to be matched and stitched with other images that contain the same frame.

[0124] Determining the completeness of a structure can be accomplished by determining the relative positions of frames. The relative positions of frames can be obtained from the SEM image metadata structure, the composition of which varies depending on the microscope type. In general, the metadata structure includes: Image name containing positioning information; Pixel size in meters (width and height); Frame size in meters (width and height); Microscope position coordinates in the microscope's own reference system (X, Y, Z); Resulting image size in pixels (width and height); Frame resolution in pixels. Frame completeness is determined by the presence of all positional markers at the edges of the image according to the known dimensions of the group or frame within the group in the GDS.

[0125] At step 140, the labeled images are analyzed. If a complete frame is missing from the image, a stitching procedure is performed on adjacent frames based on the relative positions of their positional markers (as shown in Fig. 11).

[0126] To carry out the stitching process, the image is aligned by minimizing the function of selecting the parameters for transforming the perspective of the image of the topology of the microelectronic component.

[0127] Thus, at least two adjacent images of the silicon wafer are selected for alignment. One image is taken as the reference T(x, y), the second as the alignment target I(x, y) (the distorted image).

[0128] Since a two-dimensional image belongs to the Euclidean space, any distortion of the image has an inverse transformation function over the elements of this image such that: where x, y are the coordinates of the image element I, p is the set of parameters, W is the alignment function.

[0129] Next, the parameters p in the alignment function are found. This step is accomplished by solving an optimization problem in the form of an iterative nonlinear approximation, evaluation, and subsequent improvement using gradient methods (the alignment algorithm itself is available at the link found online: httDS.7Zcore.ac.uk / download / Ddf / 148003547.pdf): p = arg

[0130] Next, the image is aligned by applying a weighting function with parameters p to it.

[0131] After this, at least two images are glued together and the images are cropped in accordance with the dimensions of the compared structures of the silicon wafer topology.

[0132] Method 100 then proceeds to step 150.

[0133] At step 150, at least one marked image of the structure of the layer topology of the manufactured silicon wafer of the microelectronic component is compared with the structure of the designed layer topology of the silicon wafer of the microelectronic component.

[0134] At this stage, the marked image is compared with the projected frame based on positional markers. That is, the SEM images are compared with the projected images using the known coordinates of the positional markers.

[0135] At step 160, a set of images is formed containing at least one pair of images corresponding to an image of the structure of the designed topology of the layer of the silicon wafer of the microelectronic component and an image of the same structure in a photograph of the manufactured layer.

[0136] At step 160, a set of images is generated containing the mapped structures for subsequent construction and training of the digital twin of the lithographer and, if necessary, introducing changes to process parameters to increase the yield percentage and reduce the time (cycles) of the lithographic process.

[0137] Thus, the resulting data set will include the corresponding images of the printed structure's topology as a digital image and a microscope image of the same structure. An example of the resulting image set is shown in Fig. 12.

[0138] Fig. 13 shows an example of a general view of a computing system 200 that ensures the implementation of the claimed method or is part of a computer system, for example, a server, a personal computer, part of a computing cluster, processing the necessary data for the implementation of the claimed technical solution.

[0139] In general, the system 200 comprises components such as: one or more processors 201, at least one memory 202, data storage means 203, input / output interfaces 204, I / O means 205, network interaction means 206, which are connected via a universal bus.

[0140] The processor 201 performs the basic computing operations necessary for processing the data when performing the method 100. The processor 201 executes the necessary machine-readable instructions contained in the RAM 202.

[0141] Memory 202 is usually in the form of RAM.

[0142] The data storage means 203 can be implemented in the form of HDD, SSD disks, RAID array, flash memory, optical storage devices (CD, DVD, MD, Blue-Ray disks), etc. The means 203 allow for long-term storage of various types of information, for example, images obtained from SEM, the structure of the designed topology of a layer of a silicon wafer of a microelectronic component, etc.

[0143] To organize the operation of the components of the system 200 and to organize the operation of external connected devices, various types of input / output (I / O) interfaces 204 are used. The choice of interface depends on the specific design of the computing device, which may be, but are not limited to: PCI, AGP, PS / 2, IrDa, FireWire, LPT, COM, SATA, IDE, Lightning, USB (2.0, 3.0, 3.1, micro, mini, type C), TRS / Audio jack (2.5, 3.5, 6.35), HDMI, DVI, VGA, Display Port, RJ45, RS232, etc.

[0144] The choice of interfaces 204 depends on the specific implementation of system 200, which can be implemented on the basis of a wide range of devices, for example, a personal computer, laptop, server cluster, smartphone, server, etc.

[0145] The following may be used as I / O data means 205: keyboard, joystick, display (touch display), monitor, touch display, touchpad, mouse, light pen, stylus, touch panel, trackball, speakers, microphone, augmented reality means, optical sensors, tablet, light indicators, projector, camera, etc.

[0146] Network interaction means 206 are selected from devices that provide network reception and transmission of data, for example, an Ethernet card, a WLAN / Wi-Fi module, a Bluetooth module, a BLE module, an NFC module, an IrDa module, an RFID module, a GSM modem, etc. With the help of means 205, the organization of data exchange is ensured between, for example, a system 200, presented in the form of a server and an image capture device, on which the received data can be displayed via a wired or wireless data transmission channel.

[0147] The specific selection of elements of system 200 for the implementation of various software and hardware architectural solutions may vary while maintaining the required functionality provided.

[0148] The submitted application materials disclose preferred embodiments of the technical solution and should not be construed as limiting other, specific embodiments within the scope of the requested legal protection that are obvious to specialists in the relevant technical field. Therefore, the scope of this technical solution is limited only by the scope of the attached claims.

Claims

FORMULA 1. A method for matching the structures of a microelectronic component layer topology with the structures of a designed layer topology, comprising the steps of: a) obtaining the structure of the designed layer topology of a silicon wafer of the microelectronic component; b) obtaining at least one image of the surface of the manufactured silicon wafer of the microelectronic component; c) processing at least one image obtained in step b) using a machine learning model based on a neural network trained to mark up the structures of the layer topology of the microelectronic component, wherein, during the training, the following is performed: i. forming a set of images of the structures of the topology of the designed layer of the microelectronic component; ii. processing the formed set using a lithograph simulator model; iii.creating a training data set, based on the data obtained in step ii, containing synthetic images of the manufactured layers of the silicon wafer of the microelectronic component; d) forming at least one labeled image of at least one structure of the topology of the layer of the microelectronic component, based on the data obtained in step Error! Reference source not found.; e) comparing at least one labeled image of the structure of the topology of the layer of the manufactured silicon wafer of the microelectronic component with the structure of the designed topology of the layer of the silicon wafer of the microelectronic component; f) forming a set of images containing at least one pair of images corresponding to the image of the structure of the designed topology of the layer of the silicon wafer of the microelectronic component and the image of the same structure in the image of the manufactured layer.

2. The method according to paragraph 1, characterized in that the structures of the designed topology of the layer of the silicon wafer of the microelectronic component are made in vector format.

3. The method according to claim 1, characterized in that at least one image of the surface of the manufactured silicon wafer of the microelectronic component is obtained by means of scanning electron microscopy.

4. The method according to paragraph 1, characterized in that the structures of the topology of the layer of the microelectronic component represent an analog or digital block of the physical topology, or a component thereof, implementing the required logical function and / or carrying an information component.

5. The method according to claim 1, characterized in that the structures of the topology of the layer of the microelectronic component represent a connection between blocks or input-output elements, memory blocks, multipliers, simple or composite markers, represented at least in the form of single or periodic elementary geometric figures and their combinations, made in the form of transparent and opaque sections equivalent to the simplest elements of an electrical circuit.

6. The method according to claim 1, characterized in that during processing of the image by the machine learning model the following is performed: i. processing the image and constructing a probability distribution characterizing the position and boundaries of the detected positional markers for each image of the frame containing at least one structure; ii. selecting positional markers on each obtained image of the frame; iii. correlating the detected positional markers with known data on their mutual arrangement; iv. detecting the position of the selected structure on the basis of the data obtained in step iii; v. assigning coordinates and a unique identification number to the positional markers.

7. The method according to claim 1, characterized in that it additionally contains determining the completeness of the structure on the marked image of the structure topology of the layer of the manufactured silicon wafer of the microelectronic component.

8. The method according to paragraph 7, characterized in that adjacent images are stitched together in the event of the absence of a complete structure in the image.

9. The method according to claim 8, characterized in that during stitching of adjacent images the following is performed: i. selecting at least two adjacent images of a silicon wafer for alignment; j. selecting the first of the two images as a reference image and the second of the two images as a distorted image; iii. determining the parameters of the alignment function of the distorted image; iv. aligning the distorted image based on the alignment function; V. gluing at least two images; vi. cropping the images according to the dimensions of the compared structures of the silicon wafer topology.

10. The method according to paragraph 1, characterized in that the processing of the generated set of images of the topology structures of the designed layer of the microelectronic component additionally includes the introduction of noise characterizing the effect of shooting with an electron microscope.

11. The method according to paragraph 1, characterized in that the synthetic images are images simulating the characteristics of the manufactured layers of the microelectronic component removed from the surface of the silicon wafer using the SEM method.

Images