Pixel circuit, driving method, and display apparatus

Abstract

A pixel circuit (21), a driving method, and a display apparatus (1000). The pixel circuit (21) comprises a drive transistor (T1), a data writing sub-circuit (201), a first compensation sub-circuit (202) and a second compensation sub-circuit (205). A first electrode of the drive transistor (T1) is connected to a second node (N2), a second electrode thereof is connected to a third node (N3), a first control electrode thereof is connected to a first node (N1), and a second control electrode thereof is connected to a fourth node (N4); the data writing sub-circuit (201) is coupled to the second node (N2), a first scanning signal terminal (GATE1) and a data signal terminal (DATA); the first compensation sub-circuit (202) is coupled to the first node (N1), the third node (N3) and a second scanning signal terminal (GATE2); the second compensation sub-circuit (205) is coupled to the first node (N1), the fourth node (N4) and a third scanning signal terminal (GATE3); and the second compensation sub-circuit (205) is configured to control the turning-on / off of the first node (N1) and the fourth node (N4) in response to a third scanning signal received at the third scanning signal terminal (GATE3).

Description

Pixel circuit and driving method, and display device

[0001] This application claims priority to Chinese Patent Application No. 202410890031.2, filed on July 3, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit and driving method, and display device. BACKGROUND

[0003] With the development of display technology, display devices (such as mobile phones, notebook computers, or tablet computers, etc.) are increasingly applied to people's lives. Among them, organic light-emitting diode (English: Organic Light-Emitting Diode, abbreviated: OLED) display devices have the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., and therefore are widely concerned. SUMMARY

[0004] In one aspect, a pixel circuit is provided. The pixel circuit includes a driving transistor, a data writing sub-circuit, a first compensation sub-circuit, and a second compensation sub-circuit. The first electrode and the second node of the driving transistor are connected, the second electrode and the third node are connected, the first control electrode and the first node are connected, and the second control electrode and the fourth node are connected. The driving transistor is configured to control the conduction and the cutoff of the circuit between the second node and the third node under the control of the potential of the first node, and to generate a driving current signal according to the potential of the first node and the potential of the second node. The data writing sub-circuit is coupled with the second node, a first scan signal terminal, and a data signal terminal. The data writing sub-circuit is configured to control the conduction and the cutoff of the data signal terminal and the second node in response to a first scan signal received at the first scan signal terminal. The first compensation sub-circuit is coupled with the first node, the third node, and a second scan signal terminal. The first compensation sub-circuit is configured to control the conduction and the cutoff of the first node and the third node in response to a second scan signal received at the second scan signal terminal. The second compensation sub-circuit is coupled with the first node, the fourth node, and a third scan signal terminal. The second compensation sub-circuit is configured to control the conduction and the cutoff of the first node and the fourth node in response to a third scan signal received at the third scan signal terminal.

[0005] In some embodiments, the second compensation sub-circuit includes a second compensation transistor. The first electrode of the second compensation transistor is connected with the first node, the second electrode is connected with the fourth node, and the control electrode is connected with the third scan signal terminal.

[0006] In some embodiments, the first compensation sub-circuit is further coupled with the fourth node.

[0007] In some embodiments, the first compensation sub-circuit comprises a first compensation transistor, a first pole of the first compensation transistor is connected with the third node, a second pole is connected with the first node, a first control pole is connected with the second scan signal terminal, and a second control pole is connected with the fourth node; wherein the first control pole and the second control pole of the first compensation transistor are oppositely arranged.

[0008] In some embodiments, the pixel circuit further comprises a first reset sub-circuit, the first reset sub-circuit is coupled with a first initialization signal terminal, a first reset signal terminal, and the third node; one display frame period comprises a reset stage; the second compensation sub-circuit is configured to, in the reset stage, in response to a third scan signal received at the third scan signal terminal, transmit a first initialization signal received at the first node to the fourth node.

[0009] In some embodiments, the pixel circuit further comprises a light emitting sub-circuit, the light emitting sub-circuit is coupled with a first voltage signal terminal, a light emitting signal terminal, the second node, the third node, and a fifth node; wherein, after the reset stage, the display frame period further comprises a data writing compensation stage and a light emitting stage; the second compensation sub-circuit is further configured to, in the data writing compensation stage, in response to a third scan signal received at the third scan signal terminal, transmit a data signal received at the first node to the fourth node; and in the light emitting stage, in response to a third scan signal received at the third scan signal terminal, control the first node and the fourth node to be turned on.

[0010] In some embodiments, the pixel circuit further comprises a light emitting sub-circuit, the light emitting sub-circuit is coupled with a first voltage signal terminal, a light emitting signal terminal, the second node, the third node, and a fifth node; the fifth node is configured to be coupled with an anode of a light emitting device; wherein, after the reset stage, the display frame period further comprises a data writing compensation stage and a light emitting stage; the second compensation sub-circuit is further configured to, in the data writing compensation stage, in response to a third scan signal received at the third scan signal terminal, control the first node and the fourth node to be turned off; and in the light emitting stage, in response to a third scan signal received at the third scan signal terminal, control the first node and the fourth node to be turned off.

[0011] In some embodiments, the pixel circuit includes a first reset sub-circuit and a light emitting sub-circuit, the first reset sub-circuit is coupled with a first initialization signal terminal, a first reset signal terminal and the third node; the light emitting sub-circuit is coupled with a first voltage signal terminal, a light emitting signal terminal, the second node, the third node and a fifth node; the fifth node is configured to be coupled with an anode of a light emitting device; wherein one display frame period includes a reset phase and a light emitting phase; the second compensation sub-circuit is configured to, in the reset phase, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal; and in the light emitting phase, control the first node and the fourth node to be on in response to the third scan signal received at the third scan signal terminal.

[0012] In some embodiments, between the reset phase and the light emitting phase, the display frame period further includes a data writing compensation phase; the second compensation sub-circuit is configured to, in the data writing compensation phase, transmit a data signal received at the first node to the fourth node in response to a third scan signal received at the third scan signal terminal.

[0013] In some embodiments, between the reset phase and the light emitting phase, the display frame period further includes a data writing compensation phase, and the second compensation sub-circuit is configured to, in the data writing compensation phase, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal.

[0014] In some embodiments, between the reset phase and the light emitting phase, the display frame period further includes a data writing compensation phase; the data writing compensation phase includes a first data writing compensation phase and a second data writing compensation phase. The second compensation sub-circuit is configured to, in the first data writing compensation phase, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal; and in the second data writing compensation phase, transmit a data signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal.

[0015] In another aspect, a driving method of a pixel circuit is provided. The pixel circuit includes a first initialization sub-circuit, a first compensation sub-circuit, a second compensation sub-circuit, a driving transistor, a first node, a second node, a third node, a fourth node, and a fifth node. The driving method includes a reset stage in a display frame period. In the reset stage, the first initialization sub-circuit transmits a first initialization signal received at a first initialization signal terminal to the third node in response to a first reset signal received at a first reset signal terminal. The first compensation sub-circuit transmits the first initialization signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal. The second compensation sub-circuit transmits the first initialization signal received at the first node to the fourth node in response to a third scan signal received at a third scan signal terminal.

[0016] In some embodiments, after the reset stage, the display frame period further includes a data write compensation stage and an emitting stage. In the data write compensation stage, a data write sub-circuit transmits a data signal received at a data signal terminal to the second node in response to a first scan signal received at a first scan signal terminal. The driving transistor transmits the data signal received at the second node to the third node under the control of the potential of the first node. The first compensation sub-circuit transmits the data signal received at the third node to the first node in response to the second scan signal received at the second scan signal terminal. The second compensation sub-circuit transmits the data signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal. In the emitting stage, an emitting sub-circuit transmits a first voltage signal received at a first voltage signal terminal to the second node in response to an emitting signal received at an emitting signal terminal. The driving transistor generates a driving current signal under the control of the data signal at the first node, the data signal at the fourth node, and the first voltage signal at the second node, and transmits the driving current signal to the third node. The emitting sub-circuit further transmits the current signal received at the third node to the fifth node in response to the emitting signal received at the emitting signal terminal. The second compensation sub-circuit controls the first node and the fourth node to be turned on in response to the third scan signal received at the third scan signal terminal.

[0017] In some embodiments, after the reset stage, the display frame period further comprises a data write compensation stage and a light emitting stage; in the data write compensation stage, a data write sub-circuit transfers a data signal received at a data signal terminal to a second node in response to a first scan signal received at a first scan signal terminal; the drive transistor transfers the data signal received at the second node to the third node under the control of the potential of the first node and the potential of the fourth node; a first compensation sub-circuit transfers the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal; and the second compensation sub-circuit transfers the data signal received at the first node to the fourth node in response to a third scan signal received at a third scan signal terminal; in the light emitting stage, a light emitting sub-circuit transfers a first voltage signal received at a first voltage signal terminal to the second node in response to a light emitting signal received at a light emitting signal terminal, and the drive transistor generates a drive current signal and transfers the drive current signal to the third node under the control of the data signal at the first node and the first voltage signal at the second node; the light emitting sub-circuit further transfers a current signal received at the third node to a fifth node in response to the light emitting signal received at the light emitting signal terminal; and the second compensation sub-circuit controls the first node and the fourth node to be cut off in response to the third scan signal received at the third scan signal terminal.

[0018] In another aspect, a driving method of a pixel circuit is provided, for driving the pixel circuit of any of the above embodiments, one display frame period comprising a reset stage and a light emitting stage; in the reset stage, a first reset sub-circuit transfers a first initialization signal received at a first initialization signal terminal to a third node in response to a first reset signal received at a first reset signal terminal; a first compensation sub-circuit transfers the first initialization signal received at the third node to a first node in response to a second scan signal received at a second scan signal terminal; and a second compensation sub-circuit controls the first node and the fourth node to be cut off in response to a third scan signal received at a third scan signal terminal; in the light emitting stage, a light emitting sub-circuit transfers a first voltage signal received at a first voltage signal terminal to a second node in response to a light emitting signal received at a light emitting signal terminal, and the drive transistor generates a drive current signal and transfers the drive current signal to the third node under the control of the data signal at the first node and the first voltage signal at the second node; the light emitting sub-circuit further transfers a current signal received at the third node to a fifth node in response to the light emitting signal received at the light emitting signal terminal; and the second compensation sub-circuit controls the first node and the fourth node to be turned on in response to the third scan signal received at the third scan signal terminal.

[0019] In some embodiments, between the reset stage and the light emitting stage, the display frame period further comprises a data writing compensation stage; in the data writing compensation stage, a data writing sub-circuit transfers the data signal received at the data signal end to a second node in response to a first scan signal received at a first scan signal end; the driving transistor transfers the data signal received at the second node to the third node under the control of the first initialization signal at the first node and the first initialization signal at the fourth node; a first compensation sub-circuit transfers the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal end; and the second compensation sub-circuit controls the first node and the fourth node to be off in response to a third scan signal received at a third scan signal end.

[0020] In some embodiments, between the reset stage and the light emitting stage, the display frame period further comprises a data writing compensation stage; in the data writing compensation stage, a data writing sub-circuit transfers the data signal received at the data signal end to a second node in response to a first scan signal received at a first scan signal end; the driving transistor transfers the data signal received at the second node to the third node under the control of the first initialization signal at the first node and the first initialization signal at the fourth node; a first compensation sub-circuit transfers the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal end; and the second compensation sub-circuit controls the first node and the fourth node to be off in response to a third scan signal received at a third scan signal end.

[0021] In some embodiments, between the reset stage and the light emitting stage, the display frame period further comprises a data write compensation stage; the data write compensation stage comprises a first data write compensation stage and a second data write compensation stage; in the first data write compensation stage, a data write sub-circuit transfers a data signal received at the data signal terminal to a second node in response to a first scan signal received at the first scan signal terminal; a driving transistor transfers the data signal received at the second node to the third node under the control of a first initialization signal at the first node; a first compensation sub-circuit transfers the data signal received at the third node to the first node in response to a second scan signal received at the second scan signal terminal; a second compensation sub-circuit controls the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal; in the second data write compensation stage, the data write sub-circuit transfers the data signal received at the data signal terminal to the second node in response to the first scan signal received at the first scan signal terminal; the driving transistor transfers the data signal received at the second node to the third node under the control of the first initialization signal at the first node; the first compensation sub-circuit transfers the data signal received at the third node to the first node in response to the second scan signal received at the second scan signal terminal; and the second compensation sub-circuit transfers the data signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal.

[0022] In yet another aspect, there is provided a display device comprising the pixel circuit of any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0024] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0025] FIG. 2 is another structural diagram of a display device according to some embodiments;

[0026] FIG. 3 is a structural diagram of a display device comprising a display panel according to some embodiments;

[0027] FIG. 4 is a structural diagram of a display panel comprising a substrate and a pixel circuit according to some embodiments;

[0028] Fig. 5 is a sectional view along section line A-A in Fig. 4;

[0029] Fig. 6 is a structural diagram of a pixel circuit according to some embodiments;

[0030] Fig. 7 is a structural diagram of a pixel circuit including transistors and capacitors according to some embodiments;

[0031] Fig. 8 is a timing diagram of a pixel circuit according to some embodiments;

[0032] Fig. 9 is a structural diagram of a pixel circuit including transistors turned on or turned off according to some embodiments;

[0033] Fig. 10 is another structural diagram of a pixel circuit including transistors turned on or turned off according to some embodiments;

[0034] Fig. 11 is yet another structural diagram of a pixel circuit including transistors turned on or turned off according to some embodiments;

[0035] Fig. 12 is a timing diagram of a third scan signal terminal according to some embodiments;

[0036] Fig. 13 is another timing diagram of a third scan signal terminal according to some embodiments;

[0037] Fig. 14 is yet another structural diagram of a pixel circuit including transistors turned on or turned off according to some embodiments;

[0038] Fig. 15 is yet another structural diagram of a pixel circuit including transistors turned on or turned off according to some embodiments;

[0039] Fig. 16 is yet another structural diagram of a pixel circuit including transistors turned on or turned off according to some embodiments;

[0040] Fig. 17 is another timing diagram of a third scan signal terminal according to some embodiments;

[0041] Fig. 18 is another timing diagram of a third scan signal terminal according to some embodiments;

[0042] Fig. 19 is another timing diagram of a third scan signal terminal according to some embodiments. DETAILED DESCRIPTION

[0043] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0044] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive, and will be taken to mean "including, but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example" or "some examples" are used to indicate that the described embodiment(s) is (are) among numerous possible embodiments of the disclosure. The above terms are not necessarily used to indicate the same embodiment or example. In addition, the specific features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0045] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0046] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. For example, the term "connected" can be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more components are in direct physical or electrical contact with each other. However, the terms "coupled" or "communicatively coupled" can also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0047] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0048] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0049] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected," is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0050] Use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0051] Additionally, use of "based on" means open and inclusive, as the process, step, calculation, or other action based on a stated condition or value can actually be based on additional conditions or values beyond those stated.

[0052] As used herein, "about," "approximately," or "circa" includes the recited value and the mean within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0053] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0054] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0055] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and are not intended to be as actual views of individual layers and regions of devices and structures. As such, the actual structure can include more, less, and / or different layers, regions, and / or elements than those shown in the figures. In addition, the depiction of relative sizes and shapes of regions and elements is not necessarily to scale. Thus, the exemplary embodiments should not be construed as limited to the particular shapes and relative sizes as illustrated in the figures. The exemplary embodiments are intended to be exemplary, and it is contemplated that structures can be scaled up or down with variations as compared with the illustrated exemplary embodiments. For example, the regions and elements illustrated in the figures can be larger or smaller in real size and / or relative to other regions and elements. In addition, the exemplary embodiments are not limited to the illustrated shapes and relative sizes of the regions and elements, and are intended to work with a variety of shapes and relative sizes of regions and elements. For example, the illustrated rectangular etched regions will typically have curved features. Thus, the regions illustrated in the figures are intended to be schematic, and their shapes are not intended to show the actual shape of the regions of a device, and are not intended to limit the scope of the exemplary embodiments.

[0056] In embodiments of the present disclosure, the capacitor can be a capacitor device made separately by a process, for example, by making a special capacitor electrode, each capacitor electrode of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or realized by a transistor itself and other devices, lines, or by parasitic capacitors between lines of the circuit itself.

[0057] In the circuit provided by embodiments of the present disclosure, the first node, the second node, the third node, the fourth node and the fifth node do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0058] In embodiments of the present disclosure, for a P-type transistor, "low level" refers to a level that can make the operated transistor included therein be turned on, and correspondingly, "high level" refers to a level that cannot make the operated transistor included therein be turned on (i.e., the transistor is turned off). For an N-type transistor, "low level" refers to a level that can make the operated transistor included therein be turned off, and correspondingly, "high level" refers to a level that can make the operated transistor included therein be turned on.

[0059] As shown in FIGS. 1 and 2, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays anything whether in motion (e.g., video) or stationary (e.g., still images) and whether textual or graphical.

[0060] Exemplarily, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, a flight display, etc.

[0061] In some examples, as shown in FIG. 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in FIG. 1.

[0062] In yet other examples, as shown in FIG. 2, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in FIG. 2.

[0063] In some embodiments, as shown in FIG. 3, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0064] The display panel 100 has opposite light-emitting and non-light-emitting sides 100A and 100B. The light-emitting side 100A refers to a side (the upper side of the display panel 100 in FIG. 3) at which the display panel 100 can emit light, and the non-light-emitting side 100B refers to the other side (the lower side of the display panel 100 in FIG. 3) opposite the light-emitting side 100A.

[0065] The driving circuit board 200 is disposed on the non-light-emitting side of the display panel 100 and connected to the display panel 100 to provide a light-emitting signal to the display panel 100.

[0066] The housing 300 can be a box-shaped structure having an opening. The display panel 100 and the driving circuit board 200 can be disposed in the housing 300, and the cover plate 400 is disposed on the light-emitting side of the display panel 100 and located at the opening of the housing 300.

[0067] As shown in FIG. 3, the longitudinal section of the housing 300 can be U-shaped, for example. The display panel 100 and the driving circuit board 200 are disposed in the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0068] The type of the display panel 100 described above includes a variety of types, which can be selected and disposed according to actual needs.

[0069] Exemplarily, the display panel 100 can be an organic light-emitting diode (OLED) display panel 100, a quantum dot light-emitting diode (QLED) display panel 100, an active matrix organic light-emitting diode (AMOLED) display panel 100, a liquid crystal display (LCD) display panel 100, a mini / micro light-emitting display (MLED) display panel 100, or the like, which is not specifically limited in the embodiments of the present disclosure.

[0070] In the following, some embodiments of the present disclosure are schematically described with the display panel 100 being an OLED display panel 100 as an example.

[0071] In some embodiments, as shown in FIGS. 4 and 5, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0072] The material adopted by the substrate 10 can include a polymer resin or glass. Exemplarily, the substrate 10 can be flexible, and the material adopted by the substrate 10 includes one of a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formic acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Exemplarily, the substrate 10 can be rigid, including a glass material containing SiO2 as a main component.

[0073] As shown in FIG. 4, a plurality of sub-pixels 20 are disposed on the substrate 10, and the plurality of sub-pixels 20 can be arranged in multiple rows and multiple columns, for example. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0074] The plurality of sub-pixels 20 can include first sub-pixels with a first color, second sub-pixels with a second color, and third sub-pixels with a third color. The first color, the second color, and the third color are three primary colors, for example. The first color is red, the second color is blue, and the third color is green, for example, which are not limited in the embodiments of the present disclosure.

[0075] As shown in FIGS. 4 and 5, the sub-pixel 20 includes a pixel circuit 21 and a light emitting device 22.

[0076] In some embodiments, as shown in FIG. 5, the display panel 100 further includes a pixel circuit stack 30 and a light emitting device stack 40 on the substrate 10 in a direction perpendicular to and away from the substrate 10.

[0077] The pixel circuit stack 30 includes a plurality of pixel circuits 21, and each pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (Capacitor, C for short).

[0078] The transistors 211 used in the circuit provided by the embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as an example.

[0079] For example, the transistor 211 is an oxide thin film transistor, which has a high carrier mobility.

[0080] Alternatively, for example, the transistor 211 is a low-temperature polysilicon thin film transistor, which has a high mobility and fast charging.

[0081] In some examples, the plurality of transistors 211 includes low-temperature polysilicon thin film transistors and oxide thin film transistors. In this way, the low-temperature polysilicon transistors and the oxide transistors can be integrated on one display panel 100, which can reduce the power consumption of the display panel 100 and improve the display quality of the display panel 100.

[0082] As shown in FIG. 5, the transistor 211 includes an active region 2111, a source 2112, a drain 2113, and a gate 2114, and the source 2112 and the drain 2113 are in contact with the active region 2111, respectively. The storage capacitor 212 includes two plates arranged oppositely.

[0083] It should be noted that the source 2112 and the drain 2113 can be exchanged, i.e., 2112 in FIG. 5 represents the drain and 2113 represents the source.

[0084] The structure of the pixel circuit 21 can include various structures, which can be selected according to actual needs. For example, the structure of the pixel circuit 21 can include a "2T1C", "3T1C", "6T1C", "7T1C", "6T2C", or "7T2C" structure. Herein, "T" represents the transistor 211, the number before "T" represents the number of transistors 211, and "C" represents the storage capacitor 212, and the number before "C" represents the number of storage capacitors 212.

[0085] In some examples, the plurality of transistors in the pixel circuit 21 can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit 21 can all be P-type transistors or can all be N-type transistors, which can simplify the process flow, reduce the process difficulty of the display panel 100, and improve the yield of the product.

[0086] In some embodiments, along a direction perpendicular to the substrate 10 and close to the substrate 10, the light emitting device stack 40 includes an anode layer 241, a light emitting functional layer 242, and a cathode layer 243 arranged in a stack, as shown in the figure.

[0087] As shown in FIG. 5, the anode layer 241 includes a plurality of anodes 2411, and the cathode layer 243 includes a plurality of cathodes 2431. One anode 2411 and one cathode 2431 are arranged oppositely. The oppositely arranged anode 2411 and the cathode 2431 and the light emitting functional layer 242 between the anode 2411 and the cathode 2431 form a light emitting device 22.

[0088] The anode 2411 can be electrically connected to the source 2112 or the drain 2113 of the transistor 211 as a driving transistor, for example, as shown in FIG. 5 and FIG. 6, in which the anode 2411 is electrically connected to the drain 2113 of the transistor 211. In this way, the pixel circuit 21 can drive the corresponding light emitting device 22 to emit light.

[0089] The light-emitting functional layer 242 can include only a light-emitting layer, or can further include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), a hole transporting layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL) in addition to the light-emitting layer.

[0090] In some embodiments, as shown in FIG. 5, the display panel 100 further includes an encapsulation layer 50. The encapsulation layer 50 is located on the side of the light-emitting device stack 40 away from the substrate 10, and the encapsulation layer 50 is used to encapsulate the light-emitting device 22 and improve the service life of the light-emitting device 22. The encapsulation layer 50 can be an encapsulation film or an encapsulation substrate, and the specific embodiments of the present disclosure are not limited herein.

[0091] For example, the encapsulation layer 50 can include one encapsulation film, or two or more encapsulation films stacked. For example, as shown in FIG. 5, the encapsulation layer 50 includes a first inorganic encapsulation layer 51, a first organic encapsulation layer 52, and a second inorganic encapsulation layer 53 stacked in a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 52 includes a polymer resin, such as polyimide.

[0092] In some embodiments, as shown in FIG. 6, the pixel circuit 21 includes a driving transistor T1, a data writing sub-circuit 201, a first compensation sub-circuit 202, a first reset sub-circuit 203, and a light-emitting sub-circuit 204.

[0093] In some examples, the driving transistor is a single-gate transistor, the first electrode and the second node N2 of the driving transistor T1 are connected, the second electrode and the third node N3 are connected, and the control electrode and the first node N1 are connected.

[0094] The driving transistor T1 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the potential of the first node N1, and to generate a driving current signal according to the potential of the first node N1 and the potential of the second node N2.

[0095] In some examples, as shown in FIGS. 6 and 7, the data writing sub-circuit 201 is coupled with the second node N2, the first scan signal terminal GATE1 and the data signal terminal DATA. The data writing sub-circuit 201 is configured to control the turn-on and turn-off of the data signal terminal DATA and the second node N2 in response to a first scan signal received at the first scan signal terminal GATE1.

[0096] Exemplarily, the data writing sub-circuit 201 includes a data writing transistor T2. The first pole of the data writing transistor T2 is connected with the data signal terminal DATA, the second pole is connected with the second node N2, and the control pole is connected with the first scan signal terminal GATE1.

[0097] In some examples, as shown in FIGS. 6 and 7, the first compensation sub-circuit 202 is coupled with the first node N1, the third node N3 and the second scan signal terminal GATE2. The first compensation sub-circuit 202 is configured to control the turn-on and turn-off of the first node N1 and the third node N3 in response to a second scan signal received at the second scan signal terminal GATE2.

[0098] Exemplarily, the first compensation sub-circuit 202 includes a first compensation transistor T3. The first pole of the first compensation transistor T3 is coupled with the third node N3, the second pole is coupled with the first node N1, and the control pole is coupled with the second scan signal terminal GATE2.

[0099] In some examples, as shown in FIGS. 6 and 7, the first reset sub-circuit 203 is coupled with the first initialization signal terminal VINIT1, the first reset signal terminal RESET1 and the third node N3. The first reset sub-circuit 203 is configured to control the turn-on and turn-off of the first initialization signal terminal VINIT1 and the third node N3 in response to a first reset signal received at the first reset signal terminal RESET1.

[0100] Exemplarily, the first reset sub-circuit 203 includes a first reset transistor T4. The first pole of the first reset transistor T4 is connected with the first initialization signal terminal VINIT1, the second pole is connected with the third node N3, and the control pole is connected with the second scan signal terminal GATE2.

[0101] In some examples, as shown in FIGS. 6 and 7, the light emitting sub-circuit 204 is coupled with the first voltage signal terminal VDD, the light emitting signal terminal EM, the second node N2, the third node N3 and the fifth node N5. The fifth node N5 is configured to be connected with the anode of the light emitting device 22. The light emitting sub-circuit 204 is configured to control the turn-on and turn-off of the first voltage signal terminal VDD and the second node N2, and control the turn-on and turn-off of the third node N3 and the fifth node N5 in response to a light emitting signal received at the light emitting signal terminal EM.

[0102] Exemplarily, as shown in FIGS. 6 and 7, the light emitting sub-circuit 204 includes a first light emitting sub-circuit 2041 and a second light emitting sub-circuit 2042. The first light emitting sub-circuit 2041 is coupled with the first voltage signal terminal VDD, the first light emitting signal terminal EM1 and the second node N2. The first light emitting sub-circuit 2041 is configured to control the conduction and the cut-off of the first voltage signal terminal VDD and the second node N2 in response to the first light emitting signal received at the first light emitting signal terminal EM1. The second light emitting sub-circuit 2042 is coupled with the third node N3, the second light emitting signal terminal EM2 and the fifth node N5. The second light emitting sub-circuit 2042 is configured to control the conduction and the cut-off of the third node N3 and the fifth node N5 in response to the light emitting signal received at the second light emitting signal terminal EM2. Wherein, the signal received at the first light emitting signal terminal EM1 and the signal received at the second light emitting signal terminal EM2 are the same.

[0103] For example, as shown in FIG. 7, the first light emitting sub-circuit 204 includes a first light emitting transistor T5, the first electrode of the first light emitting transistor T5 is connected with the first voltage signal terminal VDD, the second electrode is connected with the second node N2, and the control electrode is connected with the first light emitting signal terminal EM1. The second light emitting sub-circuit 2042 includes a second light emitting transistor T6, the first electrode of the second light emitting transistor T6 is coupled with the third node N3, the second electrode is coupled with the anode of the light emitting device 22, and the control electrode is coupled with the second light emitting signal terminal EM2.

[0104] Wherein, as shown in FIG. 8, one display frame period P includes a reset stage P1, a data writing compensation stage P2 and a light emitting stage P3.

[0105] As shown in FIGS. 8 and 9, the first reset sub-circuit 203 is configured to transmit the first initialization signal received by the first initialization signal terminal VINIT1 to the third node N3 in the reset stage P1. The first compensation sub-circuit 202 is configured to transmit the first initialization signal received by the third node N3 to the first node N1 in response to the second scan signal received by the second scan signal terminal GATE2 in the reset stage P1.

[0106] In this way, under the control of the first reset signal terminal RESET1, the first initialization signal received by the first initialization signal terminal VINIT1 can be transmitted to the third node N3 through the first reset sub-circuit 203, so that the third node N3 can be initialized, and the problem that the potential of the third node N3 caused by the residual of the last image frame affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display panel 100.

[0107] As shown in FIGS. 8 and 10, the data writing sub-circuit 201 is configured to, in the data writing compensation phase P2, in response to the first scan signal received at the first scan signal terminal GATE1, transfer the data signal received at the data signal terminal DATA to the second node N2, and the driving transistor T1 is configured to, in the data writing compensation phase P2, under the control of the potential of the first node N1, transfer the data signal received at the second node N2 to the third node N3. The first compensation sub-circuit 202 is configured to, in the data writing compensation phase P2, in response to the second scan signal received at the second scan signal terminal GATE2, transfer the data signal received at the third node N3 to the first node N1.

[0108] As shown in FIGS. 8 and 11, the light emitting sub-circuit 204 is configured to transfer the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The driving transistor T1 is configured to, in the light emitting phase P3, under the control of the data signal at the first node N1 and the first voltage signal at the second node N2, generate a driving current signal and transfer the driving current signal to the third node N3. The light emitting sub-circuit 204 is configured to, in the light emitting phase P3, in response to the light emitting signal received at the light emitting signal terminal EM as well, transfer the current signal received at the third node N3 to the fifth node N5 to make the light emitting device 22 emit light.

[0109] In the related art, in the process of emitting light by the display panel, the brightness uniformity of the display panel is poor, resulting in poor display effect of the display panel. The inventors have found that the threshold voltage of the driving transistor will drift (for example, positive or negative), and the pixel circuit can only compensate for the threshold voltage of the driving transistor that has not drifted, and cannot compensate for the threshold voltage of the driving transistor that has drifted, resulting in inconsistent gate-source voltage of the driving transistor in multiple pixel circuits in the case of all sub-pixels being the same gray scale, inconsistent brightness of multiple light emitting devices, and poor brightness uniformity of the display panel.

[0110] To solve the above technical problems, some embodiments of the present disclosure also provide a pixel circuit 21. As shown in FIG. 6, the driving transistor T1 is a double-gate transistor, i.e., the driving transistor T1 includes a first control pole and a second control pole. The first control pole of the driving transistor T1 is connected to the first node N1, and the second control pole is connected to the fourth node N4. The first control pole is the top gate of the driving transistor T1, and the second control pole is the bottom gate of the driving transistor T1.

[0111] On this basis, as shown in FIGS. 6 and 7, the pixel circuit 21 further includes a second compensation sub-circuit 205.

[0112] In some examples, as shown in the figure, the second compensation sub-circuit 205 is coupled with the first node N1, the fourth node N4 and the third scan signal terminal GATE3; the second compensation sub-circuit 205 is configured to control the conduction and the cutoff of the first node N1 and the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.

[0113] Exemplarily, the second compensation sub-circuit 205 includes a second compensation transistor T7, a first electrode of the second compensation transistor T7 is connected with the first node N1, a second electrode of the second compensation transistor T7 is connected with the fourth node N4, and a control electrode of the second compensation transistor T7 is connected with the third scan signal terminal GATE3.

[0114] It should be noted that the calculation formula of the sub-threshold swing of the driving transistor T1 is as follows:

[0115] wherein V g is the gate voltage, I ds is the source-drain current, k is the Boltzmann constant, T is the temperature, q is the electronic charge, C ox is the gate oxide layer capacitance per unit area of the driving transistor. C B is the depletion region capacitance, and C it is the interface trap capacitance of the driving transistor.

[0116] In the case where the second compensation sub-circuit 205 is coupled with the first node N1, the fourth node N4 and the third scan signal terminal GATE3, C B =C TG1 +C BG1 , wherein C TG1 is the capacitance of the depletion region of the first control electrode of the driving transistor T1, and C BG1 is the capacitance of the depletion region of the second control electrode of the driving transistor T1. In this way, according to the drift state of the driving transistor T1, the first control electrode of the driving transistor T1 and the second control electrode of the driving transistor T1 can be controlled to be conducted or cut off by the second compensation sub-circuit 205, the size of the depletion region capacitance can be changed to adjust the size of the sub-threshold swing of the driving transistor T1, thereby compensating the threshold voltage of the driving transistor T1 after the drift, reducing the difference between the gate-source voltage differences of the driving transistors T1 in the plurality of pixel circuits 21, and being conducive to reducing the difference between the luminances of the plurality of light emitting devices 22, and improving the luminance uniformity of the display panel 100.

[0117] In some embodiments, as shown in FIG. 7, the first compensation sub-circuit 202 is further coupled with the fourth node N4.

[0118] In some examples, as shown in FIG. 7, the first compensation sub-circuit 202 includes a first compensation transistor T3. The first electrode and the third node N3 of the first compensation transistor T3 are connected, the second electrode and the first node N1 are connected, the first control electrode is connected with the second scan signal terminal GATE2, and the second control electrode is connected with the fourth node N4. Wherein, the first control electrode and the second control electrode of the first compensation transistor T3 are oppositely arranged.

[0119] At this time, C B =C TG1 +C BG1 +C BG3 , wherein C BG3 is the capacitance of the depletion region of the second control electrode of the first compensation transistor T3. In this way, by controlling the conduction or cutoff of the first control electrode of the driving transistor T1 and the second control electrode of the first compensation transistor T3 through the second compensation sub-circuit 205, the size of the depletion region capacitance can be further changed to adjust the size of the sub-threshold swing of the driving transistor T1, thereby compensating for the threshold voltage of the driving transistor T1 after the drift, reducing the difference between the gate-source voltages of the driving transistor T1 in the plurality of pixel circuits 21, and facilitating reducing the difference between the luminance of the plurality of light emitting devices 22, and improving the luminance uniformity of the display panel 100.

[0120] In some embodiments, as shown in FIG. 8, FIG. 12 and FIG. 13, the second compensation sub-circuit 205 is configured to, in the reset phase P1, in response to the third scan signal received at the third scan signal terminal GATE3, transmit the first initialization signal received at the first node N1 to the fourth node N4.

[0121] In this way, in the reset phase P1, by controlling the conduction of the first node N1 and the fourth node N4 through the second compensation sub-circuit 205, on the one hand, the size of the depletion region capacitance can be changed to adjust the size of the sub-threshold swing of the driving transistor T1, thereby compensating for the threshold voltage of the driving transistor T1 after the drift, reducing the difference between the gate-source voltages of the driving transistor T1 in the plurality of pixel circuits 21, and facilitating reducing the difference between the luminance of the plurality of light emitting devices 22, and improving the luminance uniformity of the display panel 100. On the other hand, the potentials of the top gate and the bottom gate of the driving transistor T1 are the same, which can reduce the risk of the flow of carriers in the active part of the driving transistor T1 to one of the top gate and the bottom gate, thereby reducing the risk of the carriers being captured by the defects in the top gate and the bottom gate, and facilitating reducing the risk of threshold voltage drift.

[0122] In some examples, as shown in FIGS. 9, 10 and 12, the second compensation sub-circuit 205 is further configured to, in the data writing compensation phase P2, in response to the third scan signal received at the third scan signal terminal GATE3, transfer the data signal received at the first node N1 to the fourth node N4; and in the light emitting phase P3, in response to the third scan signal received at the third scan signal terminal GATE3, control the first node N1 and the fourth node N4 to be turned on. That is, in the reset phase P1, the data writing compensation phase P2 and the light emitting phase P3, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned on in response to the third scan signal received at the third scan signal terminal GATE3.

[0123] In this way, on the one hand, threshold voltages with large negative bias (for example, the negative bias is greater than 0.5V) can be compensated, the difference between the gate-source voltage differences of the driving transistors T1 in the plurality of pixel circuits 21 is reduced, which is conducive to reducing the difference between the luminances of the plurality of light emitting devices 22, and improving the luminance uniformity of the display panel 100. On the other hand, by simultaneously compensating the bottom gate and the top gate, the compensation time of the driving transistor T1 can be shortened, the display frame period can be shortened, which is conducive to improving the refresh rate of the display panel 100, and further improving the display effect of the display panel 100.

[0124] In other embodiments, as shown in FIGS. 13, 14 and 15, the second compensation sub-circuit 205 is further configured to, in the data writing compensation phase P2, in response to the third scan signal received at the third scan signal terminal GATE3, control the first node N1 and the fourth node N4 to be turned off; and in the light emitting phase P3, in response to the third scan signal received at the third scan signal terminal GATE3, control the first node N1 and the fourth node N4 to be turned off. That is, in the reset phase P1, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned on in response to the third scan signal received at the third scan signal terminal GATE3. In the data writing compensation phase P2 and the light emitting phase P3, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3.

[0125] In this way, threshold voltages with small positive bias (for example, the positive bias is less than or equal to 0.5V) can be compensated, the difference between the gate-source voltage differences of the driving transistors T1 in the plurality of pixel circuits 21 is reduced, which is conducive to reducing the difference between the luminances of the plurality of light emitting devices 22, and improving the luminance uniformity of the display panel 100.

[0126] In some embodiments, as shown in FIGS. 9, 16, 17, 18 and 19, the second compensation sub-circuit 205 is configured to, in the reset phase P1, control the first node N1 and the fourth node N4 to be off in response to the third scan signal received at the third scan signal terminal GATE3; and in the light emitting phase P3, control the first node N1 and the fourth node N4 to be on in response to the third scan signal received at the third scan signal terminal GATE3.

[0127] In this way, in the reset phase P1, the first node N1 and the fourth node N4 are controlled to be off by the second compensation sub-circuit 205, and in the light emitting phase P3, the first node N1 and the fourth node N4 are controlled to be on by the second compensation sub-circuit 205. The size of the depletion region capacitance can be changed to adjust the size of the sub-threshold swing of the driving transistor T1, thereby compensating for the threshold voltage of the driving transistor T1 after the drift, reducing the difference between the gate-source voltage differences of the driving transistors T1 in the plurality of pixel circuits 21, and facilitating the reduction of the difference between the luminances of the plurality of light emitting devices 22, thereby improving the luminance uniformity of the display panel 100.

[0128] In some examples, as shown in FIGS. 10 and 17, the second compensation sub-circuit 205 is configured to, in the data writing compensation phase P2, pass the data signal received at the first node N1 to the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.

[0129] In this way, on the one hand, the threshold voltage with a small positive bias (for example, the positive bias is less than or equal to 0.5V) can be compensated, and the difference between the gate-source voltage differences of the driving transistors T1 in the plurality of pixel circuits 21 can be reduced, which is conducive to reducing the difference between the luminances of the plurality of light emitting devices 22, thereby improving the luminance uniformity of the display panel 100. On the other hand, compensating for the bottom gate and the top gate at the same time can shorten the compensation time of the driving transistor T1, shorten the display frame period, and facilitate the improvement of the refresh rate of the display panel 100, thereby improving the display effect of the display panel 100.

[0130] In some other examples, as shown in FIGS. 14 and 18, the second compensation sub-circuit 205 is configured to, in the data writing compensation phase P2, control the first node N1 and the fourth node N4 to be off in response to the third scan signal received at the third scan signal terminal GATE3.

[0131] In this way, the threshold voltage with little drift can be compensated, and the difference between the gate-source voltage differences of the driving transistors T1 in the plurality of pixel circuits 21 can be reduced, which is conducive to reducing the difference between the luminances of the plurality of light emitting devices 22, thereby improving the luminance uniformity of the display panel 100.

[0132] In yet some examples, as shown in FIG. 10, FIG. 14 and FIG. 19, the data writing compensation phase P2 includes a first data writing compensation phase P21 and a second data writing compensation phase P22. The second compensation sub-circuit 205 is configured to, in the first data writing compensation phase P21, cut off the first node N1 and the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3. The second compensation sub-circuit 205 is configured to, in the second data writing compensation phase P22, transmit the data signal received at the first node N1 to the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.

[0133] In this way, the threshold voltage with a large positive bias (e.g., a positive bias greater than 0.5V) can be compensated, the difference between the gate-source voltages of the driving transistors T1 in the plurality of pixel circuits 21 is reduced, the difference between the brightness of the plurality of light emitting devices 22 is reduced, and the brightness uniformity of the display panel 100 is improved.

[0134] In some embodiments, as shown in FIG. 6 and FIG. 7, the pixel circuit 21 further includes a second reset sub-circuit 206 coupled with the second initialization signal terminal VINIT2, the second reset signal terminal RESET2 and the fifth node N5. The second reset sub-circuit 206 is configured to control the conduction and cut-off of the second initialization signal terminal VINIT2 and the fifth node N5 in response to the second reset signal received at the second reset signal terminal RESET2.

[0135] In some examples, as shown in FIG. 7, the second reset sub-circuit 206 includes a second reset transistor T8. The first pole of the second reset transistor T8 is connected with the second initialization signal terminal VINIT2, the second pole is connected with the fifth node N5, and the control pole is connected with the second reset signal terminal.

[0136] In this way, under the control of the second reset signal terminal RESET2, the second initialization signal received by the second initialization signal terminal VINIT2 can be transmitted to the fifth node N5 through the second reset sub-circuit 206, so that the fifth node N5 can be initialized, the problem that the potential of the last image frame remaining in the fifth node N5 affects the display image of the next image frame can be improved, and the brightness uniformity of the display panel 100 is improved.

[0137] In some embodiments, the second reset signal received at the second reset signal terminal RESET2 and the first reset signal received at the first reset signal terminal RESET1 are the same. In this way, the reset of the third node N3 and the reset of the fifth node N5 can be controlled through the second scan signal terminal GATE2, so that the circuit structure can be simplified.

[0138] In some embodiments, as shown in FIGS. 6 and 7, the pixel circuit 21 further comprises a first storage sub-circuit 207 coupled with the first voltage signal terminal VDD and the first node N1; the first storage sub-circuit 207 is configured to store the potential of the first node N1.

[0139] Exemplarily, as shown in FIG. 7, the first storage sub-circuit 207 comprises a first storage capacitor C1, a first plate of the first storage capacitor C1 is connected with the first voltage signal terminal VDD, and a second plate is connected with the first node N1.

[0140] The working process of the pixel circuit 21 in one display frame period is described in detail below in combination with a timing diagram. The following embodiments take the driving transistor T1, the data writing transistor T2, the first reset transistor T4, the first light emitting transistor T5, the second light emitting transistor T6 and the second compensation transistor T7 as P-type transistors, and the first compensation transistor T3 as an N-type transistor as examples.

[0141] As shown in FIGS. 8 and 9, the one display frame period comprises a reset phase P1, a data writing and compensation phase P2 and a light emitting phase P3.

[0142] In some embodiments, in the reset phase P1,

[0143] As shown in FIGS. 8, 9, 12 and 13, the first reset sub-circuit 203 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the third node N3 in response to the first reset signal received at the first reset signal terminal RESET1. The first compensation sub-circuit 202 transmits the first initialization signal received at the third node N3 to the first node N1 in response to the second scan signal received at the second scan signal terminal GATE2. The second compensation sub-circuit 205 transmits the first initialization signal received at the first node N1 to the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.

[0144] Exemplarily, each sub-circuit in the pixel circuit 21 comprises a transistor 211 or a storage capacitor 212. As shown in FIGS. 8, 12 and 13, in the reset phase P1, the first reset signal is 0, the third scan signal is 0, the first light emitting signal is 1, the second light emitting signal is 1, the first scan signal is 1, and the second scan signal is 1, wherein “0” represents low level and “1” represents high level.

[0145] In this case, as shown in FIGS. 8, 9, 12 and 13, the first reset signal terminal RESET1 and the third scan signal terminal GATE3 input low level, the second scan signal terminal GATE2 inputs high level, and the first reset transistor T4, the second compensation transistor T7 and the first compensation transistor T3 are all turned on.

[0146] The first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2 and the first scanning signal terminal GATE1 input low level, and the first light-emitting transistor T5, the second light-emitting transistor T6 and the data writing transistor T2 are all turned off.

[0147] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the third node N3 through the first reset transistor T4, the first initialization signal received at the third node N3 is transmitted to the first node N1 through the first compensation transistor T3, and the first initialization signal received at the first node N1 is transmitted to the fourth node N4 through the second compensation transistor T7.

[0148] In some examples, on the basis of the above-mentioned embodiments, as shown in FIG. 10, FIG. 12 and FIG. 13, in the data writing compensation phase P2,

[0149] The data writing sub-circuit 201 transmits the data signal received at the data signal terminal DATA to the second node N2 in response to the first scanning signal received at the first scanning signal terminal GATE1. The driving transistor T1 transmits the data signal received at the second node N2 to the third node N3 under the control of the potential of the first node N1. The first compensation sub-circuit 202 transmits the data signal received at the third node N3 to the first node N1 in response to the second scanning signal received at the second scanning signal terminal GATE2. The second compensation sub-circuit 205 transmits the data signal received at the first node N1 to the fourth node N4 in response to the third scanning signal received at the third scanning signal terminal GATE3.

[0150] Exemplarily, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in FIG. 12, in the data writing compensation phase P2, the first scanning signal is 0, the third scanning signal is 0, the second scanning signal is 1, the first reset signal is 1, the first light-emitting signal is 1, and the second light-emitting signal is 1, wherein “0” represents low level and “1” represents high level.

[0151] In this case, as shown in FIG. 10 and FIG. 12, the first scanning signal terminal GATE1 and the third scanning signal terminal GATE3 input low level, the second scanning signal terminal GATE2 inputs high level, and the data writing transistor T2, the first compensation transistor T3 and the second compensation transistor T7 are all turned on.

[0152] The first reset signal terminal RESET1, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 input low level, and the first reset transistor T4, the first light-emitting transistor T5 and the second light-emitting transistor T6 are all turned off,

[0153] At this time, the data signal received at the data signal terminal DATA is transmitted to the second node N2 through the data writing transistor T2, that is, the potential of the second node N2 is Vdata. As known from the above, the potential of the first node N1 is Vint1. The potential difference between the first node N1 and the second node N2 is Vint1-Vdata. The gate-source potential difference of the driving transistor T1 is greater than the threshold voltage Vth of the driving transistor T1 (Vth=Vth1+Vth2, Vth1 is the threshold voltage of the top gate of the driving transistor T1, and Vth2 is the threshold voltage of the bottom gate), the driving transistor T1 is turned on, and the data signal is transmitted from the third node N3 to the second node N2. The data signal at the second node N2 is transmitted to the first node N1 through the second compensation transistor T7, and the potential of the first node N1 gradually increases from Vin1. When the potential of the first node N1 increases to the larger one of Vdata+Vth1 and Vdata+Vth2, the driving transistor T1 is turned off, and the data writing compensation stage P2 ends. Thus, the data signal Vdata and the larger one of the threshold voltages Vth1 and Vth2 are written into the first storage capacitor C1.

[0154] At this time, the threshold voltage Vth1 of the top gate of the driving transistor T1 is compensated, and the threshold voltage Vth2 of the bottom gate is also compensated. In this way, the compensation time of the driving transistor T1 is shortened by simultaneously compensating the bottom gate and the top gate, the display frame period is shortened, the refresh rate of the display panel 100 is improved, and the display effect of the display panel 100 is improved.

[0155] In the light emitting stage P3,

[0156] The light emitting sub-circuit 204 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the light emitting signal received at the light emitting signal terminal EM. The driving transistor T1 generates a driving current signal under the control of the data signal at the first node N1 and the first voltage signal at the second node N2, and transmits the driving current signal to the third node N3. The light emitting sub-circuit 204 also transmits the current signal received at the third node N3 to the fifth node N5 in response to the light emitting signal received at the light emitting signal terminal EM. The second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned on in response to the third scan signal received at the third scan signal terminal GATE3.

[0157] For example, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in FIG. 12, in the data emitting stage P3, the first light emitting signal is 0, the second light emitting signal is 0, the third scan signal is 0, the second scan signal is 0, the first scan signal is 1, and the first reset signal is 1, where “0” represents low level and “1” represents high level.

[0158] In this case, as shown in FIG. 11 and FIG. 12, the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2 and the third scan signal terminal GATE3 input low level, and the first light-emitting transistor T5, the second light-emitting transistor T6 and the second compensation transistor T7 are all turned on.

[0159] The first scan signal terminal GATE1 and the first reset signal terminal RESET1 input high level, and the second scan signal terminal GATE2 input low level, and the data writing transistor T2, the first compensation transistor T3 and the first reset transistor T4 are all turned off.

[0160] At this time, the first voltage signal at the first voltage signal terminal VDD is transmitted to the second node N2 through the first light-emitting transistor T5, that is, the potential of the second node N2 is Vdd, and according to the above, the potential of the first node N1 is the higher one of Vdata+Vth1 and Vdata+Vth2, the driving transistor T1 generates driving current under the control of the potential of the first node N1 and the potential of the fourth node N4, and the driving transistor T1 works in the saturation region, and according to the saturation current formula, the driving current (the current input to the light-emitting device 22) generated by the driving transistor T1 is:

[0161] Wherein, W / L is the channel width-length ratio of the driving transistor T1; μ is the carrier mobility; Cox is the unit area channel capacitance of the driving transistor T1; Vgs is the gate-source voltage difference of the driving transistor T1; and Vth is the threshold voltage of the driving transistor T1.

[0162] It can be seen that the size of the current Ioled input to the light-emitting device 22 is related to the potential Vdata of the written data signal and the first voltage signal, and is irrelevant to the threshold voltage Vth of the driving transistor T1, so that the problem that the size of the driving current is affected by the different threshold voltages of the driving transistors T1 of the pixel circuits 21 caused by the manufacturing process, and then the display effect is affected, is avoided.

[0163] In other examples, as shown in FIG. 13, FIG. 14 and FIG. 15, different from the above-mentioned embodiment, in the data writing compensation phase P2 and the light-emitting phase P3, the third scan signal is 1, the third scan signal terminal inputs high level, and the second compensation transistor T7 is turned off. The second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3.

[0164] In the data write compensation phase P2, when the potential of the first node N1 rises to Vdata+Vth, the driving transistor T1 is turned off, and the data write compensation phase P2 ends. Thus, the data signal Vdata and the threshold voltage Vth are written into the first storage capacitor C1. In the light emitting phase P3, the potential of the first node N1 is Vdata+Vth, and the driving transistor T1 generates a driving current under the control of the potential of the first node N1 and the potential of the second node N2.

[0165] In some embodiments, in the reset phase P1,

[0166] The first reset sub-circuit 203 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the third node N3 in response to the first reset signal received at the first reset signal terminal RESET1. The first compensation sub-circuit 202 transmits the first initialization signal received at the third node N3 to the first node N1 in response to the second scan signal received at the second scan signal terminal GATE2. The second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3.

[0167] Exemplarily, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in FIGS. 17, 18 and 19, in the reset phase P1, the first reset signal is 0, the second scan signal is 1, the first light emitting signal is 1, the second light emitting signal is 1, the first scan signal is 1, and the third scan signal is 1, wherein “0” represents a low level, and “1” represents a high level.

[0168] In this case, as shown in FIGS. 16, 17, 18 and 19, the first reset signal terminal RESET12 inputs a low level, and the second scan signal terminal GATE2 inputs a high level. The first reset transistor T4 and the first compensation transistor T3 are both turned on.

[0169] The first light emitting signal terminal EM1, the second light emitting signal terminal EM2, the first scan signal terminal GATE1 and the third scan signal terminal GATE3 input a high level. The first light emitting transistor T5, the second light emitting transistor T6, the data write transistor T2 and the second compensation transistor T7 are all turned off.

[0170] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the third node N3 through the first reset transistor T4, and the first initialization signal received at the third node N3 is transmitted to the first node N1 through the first compensation transistor T3.

[0171] In the light emitting phase P3,

[0172] The light emitting sub-circuit 204, in response to the light emitting signal received at the light emitting signal terminal EM, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2, and drives the transistor T1 to generate a driving current signal under the control of the data signal at the first node N1 and the first voltage signal at the second node N2, and transmits the driving current signal to the third node N3. The light emitting sub-circuit 204, in response to the light emitting signal received at the light emitting signal terminal EM, transmits the current signal received at the third node N3 to the fifth node N5. The second compensation sub-circuit 205, in response to the third scan signal received at the third scan signal terminal GATE3, controls the first node N1 and the fourth node N4 to be conductive.

[0173] Exemplarily, each sub-circuit in the pixel circuit 21 includes the transistor 211 or the storage capacitor 212. As shown in FIGS. 17, 18 and 19, in the data writing compensation phase P2, the first light emitting signal is 0, the second light emitting signal is 0, the second scan signal is 0, the third scan signal is 0, the first scan signal is 1, and the first reset signal is 1, wherein “0” represents low level and “1” represents high level.

[0174] In this case, as shown in FIGS. 11, 17, 18 and 19, the first light emitting signal terminal EM1, the second light emitting signal terminal EM2 and the third scan signal terminal GATE3 input low level, and the first light emitting transistor T5, the second light emitting transistor T6 and the second compensation transistor T7 are all conductive.

[0175] The first scan signal terminal GATE1 and the first reset signal terminal RESET1 input high level, and the second scan signal terminal GATE2 inputs low level, and the data writing transistor T2, the first compensation transistor T3 and the first reset transistor T4 are all cut off.

[0176] In some examples, on the basis of the above-mentioned embodiments, in the data writing compensation phase P2,

[0177] The data writing sub-circuit 201, in response to the first scan signal received at the first scan signal terminal GATE1, transmits the data signal received at the data signal terminal DATA to the second node N2. The driving transistor T1, under the control of the potential of the first node N1, transmits the data signal received at the second node N2 to the third node N3. The first compensation sub-circuit 202, in response to the second scan signal received at the second scan signal terminal GATE2, transmits the data signal received at the third node N3 to the first node N1. The second compensation sub-circuit 205, in response to the third scan signal received at the third scan signal terminal GATE3, transmits the data signal received at the first node N1 to the fourth node N4.

[0178] Exemplarily, each sub-circuit in the pixel circuit 21 comprises a transistor 211 or a storage capacitor 212. As shown in FIG. 17, in the data writing compensation phase P2, the first scan signal is 0, the third scan signal is 0, the second scan signal is 1, the first reset signal is 1, the first emission signal is 1, and the second emission signal is 1, wherein "0" represents a low level and "1" represents a high level.

[0179] In this case, as shown in FIG. 10 and FIG. 14, the first scan signal end GATE1 and the third scan signal end GATE3 input a low level, the second scan signal end GATE2 inputs a high level, and the data writing transistor T2, the first compensation transistor T3, and the second compensation transistor T7 are all turned on.

[0180] The first reset signal end RESET1, the first emission signal end EM1, and the second emission signal end EM2 input a low level, and the first reset transistor T4, the first emission transistor T5, and the second emission transistor T6 are all turned off,

[0181] At this time, the data signal received at the data signal end DATA is transmitted to the second node N2 through the data writing transistor T2, that is, the potential of the second node N2 is Vdata. As known from the above, the potential of the first node N1 is Vint1. The potential difference between the first node N1 and the second node N2 is Vint1-Vdata. The gate-source potential difference of the driving transistor T1 is greater than its threshold voltage Vth (Vth=Vth1+Vth2, Vth1 is the threshold voltage of the top gate of the driving transistor T1, and Vth2 is the threshold voltage of the bottom gate), the driving transistor T1 is turned on, and the data signal is transmitted from the third node N3 to the second node N2. The data signal at the second node N2 is transmitted to the first node N1 through the second compensation transistor T7, and the potential of the first node N1 gradually rises from Vin1. When the potential of the first node N1 rises to the larger one of Vdata+Vth1 and Vdata+Vth2, the driving transistor T1 is turned off, and the data writing compensation phase P2 ends. Thus, the data signal Vdata and the larger one of the threshold voltages Vth1 and Vth2 are written into the first storage capacitor C1.

[0182] In other examples, as shown in FIG. 14 and FIG. 18, different from the above-mentioned embodiment, in the data writing compensation phase P2, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal end GATE3.

[0183] At this time, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be off in response to the third scan signal received at the third scan signal terminal Gate3. The third scan signal is 1, and the second compensation transistor T7 is off. In this case, when the potential of the first node N1 rises to Vdata+Vth, the drive transistor T1 is off, and the data writing compensation phase P2 ends. Thus, the data signal Vdata and the threshold voltage Vth are written to the first storage capacitor C1. In the light emitting phase P3, the potential of the first node N1 is Vdata+Vth, and the drive transistor T1 generates a drive current under the control of the potential of the first node N1 and the potential of the second node N2.

[0184] In yet other examples, as shown in FIG. 19, the data writing compensation phase P2 includes a first data writing compensation phase P21 and a second data writing compensation phase P22.

[0185] In the first data writing compensation phase P21,

[0186] As shown in FIG. 14 and FIG. 19, the third scan signal is 1, a high level is input at the third scan signal terminal, and the second compensation transistor T7 is off. The second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be off in response to the third scan signal received at the third scan signal terminal GATE3.

[0187] In the second data writing compensation phase P22,

[0188] As shown in FIG. 10 and FIG. 19, the third scan signal is 0, a low level is input at the third scan signal terminal, and the second compensation transistor T7 is on. The second compensation sub-circuit 205 transmits the data signal received at the first node N1 to the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.

[0189] In the description of this specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0190] The above description is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A pixel circuit, comprising: a driving transistor, a first electrode and a second node of which are connected, a second electrode and a third node of which are connected, a first control electrode and a first node of which are connected, and a second control electrode and a fourth node of which are connected; the driving transistor is configured to control on and off of a circuit between the second node and the third node under control of a potential of the first node; and generate a driving current signal according to the potential of the first node and a potential of the second node; a data writing sub-circuit, coupled with the second node, a first scan signal terminal and a data signal terminal; the data writing sub-circuit is configured to control on and off of the data signal terminal and the second node in response to a first scan signal received at the first scan signal terminal; a first compensation sub-circuit, coupled with the first node, the third node and a second scan signal terminal; the first compensation sub-circuit is configured to control on and off of the first node and the third node in response to a second scan signal received at the second scan signal terminal; a second compensation sub-circuit, coupled with the first node, the fourth node and a third scan signal terminal; the second compensation sub-circuit is configured to control on and off of the first node and the fourth node in response to a third scan signal received at the third scan signal terminal.

2. The pixel circuit of claim 1, wherein, The second compensation sub-circuit comprises: a second compensation transistor, a first electrode of which and the first node are connected, a second electrode of which and the fourth node are connected, and a control electrode of which and the third scan signal terminal are connected.

3. The pixel circuit according to claim 1 or 2, wherein The first compensation sub-circuit is further coupled with the fourth node.

4. The pixel circuit of claim 3, wherein, The first compensation sub-circuit comprises: a first compensation transistor, a first electrode of which and the third node are connected, a second electrode of which and the first node are connected, a first control electrode of which and the second scan signal terminal are connected, and a second control electrode of which and the fourth node are connected; wherein the first control electrode and the second control electrode of the first compensation transistor are oppositely arranged. 5.The pixel circuit according to any one of claims 1 to 4, further comprising a first reset sub-circuit, coupled with a first initialization signal terminal, a first reset signal terminal and the third node; one display frame period comprises a reset phase; the second compensation sub-circuit is configured to, in the reset phase, transmit a first initialization signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal. 6.The pixel circuit of claim 5, further comprising a light emitting sub-circuit coupled with the first voltage signal terminal, a light emitting signal terminal, the second node, the third node, and a fifth node; wherein, After the reset phase, the display frame period further comprises a data writing compensation phase and a light emitting phase; the second compensation sub-circuit is further configured to, in the data writing compensation phase, transmit a data signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal; and in the light emitting phase, control the first node and the fourth node to be on in response to the third scan signal received at the third scan signal terminal. After the reset phase, the display frame period further comprises a data writing compensation phase and a light emitting phase; 7.The pixel circuit of claim 5, further comprising a light emitting sub-circuit coupled to the first voltage signal terminal, a light emitting signal terminal, the second node, the third node, and a fifth node; the fifth node is configured to be coupled to an anode of a light emitting device; wherein, ​ the second compensation sub-circuit is further configured to, in the data write compensation stage, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal; and in the light emitting stage, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal.

8. The pixel circuit according to any one of claims 1-4, comprising: a first reset sub-circuit coupled to a first initialization signal terminal, a first reset signal terminal, and the third node; a light emitting sub-circuit coupled to a first voltage signal terminal, a light emitting signal terminal, the second node, the third node, and a fifth node; the fifth node is configured to be coupled to an anode of a light emitting device; wherein one display frame period comprises a reset stage and a light emitting stage; the second compensation sub-circuit is configured to, in the reset stage, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal; and in the light emitting stage, control the first node and the fourth node to be on in response to a third scan signal received at the third scan signal terminal.

9. The pixel circuit according to claim 8, between the reset stage and the light emitting stage, the display frame period further comprises a data write compensation stage; the second compensation sub-circuit is configured to, in the data write compensation stage, transfer a data signal received at the first node to the fourth node in response to a third scan signal received at the third scan signal terminal.

10. The pixel circuit according to claim 8, between the reset stage and the light emitting stage, the display frame period further comprises a data write compensation stage; the second compensation sub-circuit is configured to, in the data write compensation stage, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal.

11. The pixel circuit according to claim 8, between the reset stage and the light emitting stage, the display frame period further comprises a data write compensation stage; the data write compensation stage comprises a first data write compensation stage and a second data write compensation stage; the second compensation sub-circuit is configured to, in the first data write compensation stage, control the first node and the fourth node to be off in response to a third scan signal received at the third scan signal terminal; and in the second data write compensation stage, transfer a data signal received at the first node to the fourth node in response to a third scan signal received at the third scan signal terminal.

12. A driving method of a pixel circuit, for driving the pixel circuit according to any one of claims 1-11, one display frame period comprising a reset stage; in the reset stage, The first reset sub-circuit transmits a first initialization signal received at a first initialization signal terminal to a third node in response to a first reset signal received at a first reset signal terminal; the first compensation sub-circuit transmits the first initialization signal received at the third node to a first node in response to a second scan signal received at a second scan signal terminal; and the second compensation sub-circuit transmits the first initialization signal received at the first node to a fourth node in response to a third scan signal received at a third scan signal terminal.

13. The driving method of claim 12, wherein the display frame period further comprises a data writing compensation phase and a light emitting phase after the reset phase. In the data writing compensation phase, The data writing sub-circuit transmits the data signal received at the data signal end to the second node in response to the first scan signal received at the first scan signal end; The driving transistor transmits a data signal received at a second node to the third node under the control of the potential of the first node; The first compensation sub-circuit transmits the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal; The second compensation sub-circuit transmits the data signal received at the first node to the fourth node in response to a third scan signal received at a third scan signal terminal; In the light emitting phase, The light emitting sub-circuit transmits a first voltage signal received at a first voltage signal terminal to a second node in response to a light emitting signal received at a light emitting signal terminal; the driving transistor generates a driving current signal under the control of the data signal at the first node, the data signal at the fourth node, and the first voltage signal at the second node, and transmits the driving current signal to the third node; the light emitting sub-circuit further transmits the current signal received at the third node to a fifth node in response to the light emitting signal received at the light emitting signal terminal; and the second compensation sub-circuit controls the first node and the fourth node to be turned on in response to the third scan signal received at the third scan signal terminal.

14. The driving method of claim 12, wherein the display frame period further comprises a data writing compensation phase and a light emitting phase after the reset phase. In the data writing compensation phase, The data writing sub-circuit transmits the data signal received at the data signal terminal to the second node in response to the first scan signal received at the first scan signal terminal; and the driving transistor transmits the data signal received at the second node to the third node under the control of the potential of the first node and the potential of the fourth node. The first compensation sub-circuit transmits the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal; The second compensation sub-circuit transmits the data signal received at the first node to the fourth node in response to a third scan signal received at a third scan signal terminal; In the light emitting phase, The light emitting sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the light emitting signal received at the light emitting signal terminal, and the drive transistor generates a drive current signal under the control of the data signal at the first node and the first voltage signal at the second node, and transmits the drive current signal to the third node; the light emitting sub-circuit also transmits the current signal received at the third node to the fifth node in response to the light emitting signal received at the light emitting signal terminal; the second compensation sub-circuit controls the first node and the fourth node to be off in response to the third scan signal received at the third scan signal terminal.

15. A driving method of a pixel circuit, for driving the pixel circuit according to any one of claims 1-11, one display frame period comprising a reset phase and a light emitting phase; in the reset phase, The first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to a third node in response to a first reset signal received at a first reset signal terminal; and the first compensation sub-circuit transmits the first initialization signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal. the second compensation sub-circuit controls the first node and the fourth node to be off in response to the third scan signal received at the third scan signal terminal; in the light emitting phase, the light emitting sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the light emitting signal received at the light emitting signal terminal, and the drive transistor generates a drive current signal under the control of the data signal at the first node and the first voltage signal at the second node, and transmits the drive current signal to the third node; the light emitting sub-circuit also transmits the current signal received at the third node to the fifth node in response to the light emitting signal received at the light emitting signal terminal; the second compensation sub-circuit controls the first node and the fourth node to be on in response to the third scan signal received at the third scan signal terminal.

16. The driving method according to claim 15, wherein between the reset phase and the light emitting phase, the display frame period further comprises a data writing compensation phase; in the data writing compensation phase, The data writing sub-circuit transmits the data signal received at the data signal terminal to the second node in response to the first scan signal received at the first scan signal terminal; and the driving transistor transmits the data signal received at the second node to the third node under the control of the first initialization signal at the first node and the first initialization signal at the fourth node. the first compensation sub-circuit transmits the data signal received at the third node to the first node in response to the second scan signal received at the second scan signal terminal; the second compensation sub-circuit transmits the data signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal.

17. The driving method according to claim 15, wherein between the reset phase and the light emitting phase, the display frame period further comprises a data writing compensation phase; in the data writing compensation phase, The data writing sub-circuit transmits the data signal received at the data signal terminal to the second node in response to the first scan signal received at the first scan signal terminal; and the driving transistor transmits the data signal received at the second node to the third node under the control of the first initialization signal at the first node and the first initialization signal at the fourth node. the first compensation sub-circuit transmits the data signal received at the third node to the first node in response to the second scan signal received at the second scan signal terminal; the second compensation sub-circuit controls the first node and the fourth node to be off in response to the third scan signal received at the third scan signal terminal.

18. The driving method according to claim 15, wherein between the reset phase and the light emitting phase, the display frame period further comprises a data writing compensation phase; and the data writing compensation phase comprises a first data writing compensation phase and a second data writing compensation phase; in the first data writing compensation phase, the first compensation sub-circuit transmits the data signal received at the third node to the first node in response to the second scan signal received at the second scan signal terminal; and in the second data writing compensation phase, the second compensation sub-circuit transmits the data signal received at the first node to the fourth node in response to the third scan signal received at the third scan signal terminal. The data writing sub-circuit transmits the data signal received at the data signal terminal to the second node in response to the first scan signal received at the first scan signal terminal; and the driving transistor transmits the data signal received at the second node to the third node under the control of the first initialization signal at the first node. The first compensation sub-circuit transmits the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal; The second compensation sub-circuit controls the first node and the fourth node to be cut off in response to a third scan signal received at a third scan signal terminal; In the second data write compensation phase, The data write sub-circuit transmits the data signal received at the data signal terminal to the second node in response to a first scan signal received at a first scan signal terminal; and the driving transistor transmits the data signal received at the second node to the third node under the control of the first initialization signal at the first node; The first compensation sub-circuit transmits the data signal received at the third node to the first node in response to a second scan signal received at a second scan signal terminal; The second compensation sub-circuit transmits the data signal received at the first node to the fourth node in response to a third scan signal received at a third scan signal terminal.

19. A display device comprising the pixel circuit according to any one of claims 1 to 11.

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