Semiconductor memory device

Abstract

Active regions (P1, P2) in which drive transistors (PU1, PU2), which are P-type transistors, are configured are formed in the lower part of a cell. Active regions (P1-P4) in which load transistors (PD1, PD2), which are N-type transistors, are configured are formed in the upper part of the cell. Nanosheets (25, 26) respectively overlap nanosheets (23, 22) in plan view. The X-direction width of the nanosheets (25, 26) is less than that of the nanosheets (22, 23). The positions of the surfaces of the nanosheets (22, 25) exposed from gate wiring (32) are aligned in the X direction.

Description

semiconductor memory device

[0001] The present disclosure relates to a layout structure of a static random access memory (SRAM) cell (hereinafter, also simply referred to as a cell, as appropriate) using a complementary field effect transistor (CFET).

[0002] SRAMs are widely used in semiconductor integrated circuits, and one type of SRAM is a one-port SRAM that has one port for reading and writing data.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Documents 1 and 2 disclose layouts of one-port SRAM cells using CFETs in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate.

[0005] In Patent Document 1, a fork sheet transistor having a gate electrode in a fork shape is used as the nanosheet transistor.

[0006] In Patent Document 2, the six transistors that make up a one-port SRAM cell include a transistor that is made up of a plurality of nanowire transistors.

[0007] US Patent Publication No. 2023 / 0413504 International Publication No. 2020 / 255656

[0008] In Patent Document 1, the nanosheets of the transistors constituting the 1-port SRAM cell all have the same width. However, considering the operating speed and operational stability of the semiconductor memory device, it may be better to make the nanosheets of the transistors have different widths (i.e., drive capabilities). This point is not specifically considered in Patent Document 1.

[0009] In addition, in Patent Document 2, some of the transistors constituting a 1-port SRAM cell are configured with multiple transistors, thereby making each transistor have different drive capabilities. However, in a transistor configured with multiple nanowire transistors, the multiple nanowire transistors must be laid out at a distance from each other, which increases the area of ​​the semiconductor memory device.

[0010] The present disclosure aims to improve the operating speed and stability of a semiconductor memory device and reduce the area of ​​the semiconductor memory device in a layout structure of an SRAM cell using a CFET, in which a fork-sheet transistor is used as the transistor.

[0011] The present disclosure provides a semiconductor memory device including an SRAM cell, the SRAM cell comprising a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second node and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the first, second, fifth, and sixth transistors are transistors of a first conductivity type, and the third and fourth transistors are transistors of a second conductivity type different from the first conductivity type. a second active region forming the channel, source, and drain of the second transistor and including a second nanosheet extending in the first direction as the channel; a third active region formed higher than the first and second active regions in the depth direction and forming the channel, source, and drain of the third transistor and including a third nanosheet extending in the first direction as the channel; a fourth active region formed higher than the first and second active regions in the depth direction and forming the channel, source, and drain of the fourth transistor and including a fourth nanosheet extending in the first direction as the channel; and first to fourth gate wirings surrounding the first to fourth nanosheets in the first direction and a second direction perpendicular to the depth direction and the depth direction, respectively, and wherein the first and third nanosheets area first-side surface, which is one side in the second direction, of the second and fourth nanosheets is exposed from the first and third gate wirings, respectively; a second-side surface, which is the other side in the second direction, of the second and fourth nanosheets is exposed from the second and fourth gate wirings, respectively; the first and third nanosheets overlap in a planar view; the second and fourth nanosheets overlap in a planar view; the third nanosheet has a smaller width in the second direction than the first nanosheet; the fourth nanosheet has a smaller width in the second direction than the second nanosheet; in a planar view, the first-side end of the first nanosheet and the first-side end of the third nanosheet are arranged at the same position in the second direction; and in a planar view, the second-side end of the second nanosheet and the second-side end of the fourth nanosheet are arranged at the same position in the second direction.

[0012] According to the present disclosure, the width of the third and fourth nanosheets in the second direction is smaller than the width of the first and second nanosheets in the second direction. That is, the drive capabilities of the first and second drive transistors are higher than the drive capabilities of the third and fourth transistors. This eliminates the need to include a transistor composed of multiple transistors among the six transistors that make up a one-port SRAM cell, thereby reducing the area of ​​the semiconductor memory device. Furthermore, by setting the drive capabilities of the first and second transistors higher than those of the third and fourth transistors, the operating speed, lower operating voltage limit, and operational stability of the semiconductor memory device can be improved.

[0013] Furthermore, the first-side end of the first nanosheet and the first-side end of the third nanosheet are aligned in the second direction. The second-side end of the second nanosheet and the second-side end of the fourth nanosheet are aligned in the second direction. The first and third nanosheets have their first-side surfaces exposed from the first and third gate wirings, respectively. The second and fourth nanosheets have their second-side surfaces exposed from the second and fourth gate wirings, respectively. That is, in the first and third transistors, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the second direction. In the second and fourth transistors, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the second direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, by aligning the positions of the nanosheet surfaces exposed from the gate wiring in the second direction, the shape of the structure, i.e., the size and installation range in the second direction, can be made constant. This facilitates the manufacture of the semiconductor memory device.

[0014] According to the present disclosure, with respect to an SRAM cell using a CFET, in a layout structure of an SRAM cell using a fork-sheet transistor as a transistor, it is possible to improve the operating speed and operational stability of a semiconductor memory device and reduce the area of ​​the semiconductor memory device.

[0015] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment; 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 3 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 4 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment; 5 is a diagram for explaining a manufacturing method of a semiconductor memory device according to the first embodiment; 6 is another configuration example of a semiconductor integrated circuit device according to the first embodiment; 7 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 8 is a plan view showing an example of a layout structure of an SRAM cell according to the second embodiment; 9 is a plan view showing another example of a layout structure of an SRAM cell according to the second embodiment;

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells. At least some of the plurality of SRAM cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0017] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0018] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, i.e., the part including the nanosheet transistor formed on the side farther from the substrate, and Figure 1(b) shows the lower part of the cell, i.e., the part including the nanosheet transistor formed on the side closer to the substrate. Figure 2(a) is a cross-section along line X1-X1', Figure 2(b) is a cross-section along line X2-X2', Figure 2(c) is a cross-section along line X3-X3', Figure 3(a) is a cross-section along line X4-X4', and Figure 3(b) is a cross-section along line X5-X5'.

[0019] In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction (depth direction).

[0020] 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell includes an SRAM circuit made up of drive transistors PU1 and PU2, load transistors PD1 and PD2, and access transistors PG1 and PG2. The drive transistors PU1 and PU2 and the access transistors PG1 and PG2 are P-type FETs, and the load transistors PD1 and PD2 are N-type FETs.

[0021] The drive transistor PU1 is provided between the power supply VDD and a first node NA, and the load transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the drive transistor PU1 and the load transistor PD1 are connected to a second node NB, and they form an inverter INV1. The drive transistor PU2 is provided between the power supply VDD and the second node NB, and the load transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the drive transistor PU2 and the load transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0022] The access transistor PG1 is provided between the bit line BL and a first node NA, and has its gate connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and has its gate connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0023] In an SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a low level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a low level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a high level while data is written to the first and second nodes NA and NB, respectively, the latch state is established and the data written to the first and second nodes NA and NB is held.

[0024] Furthermore, when the bit lines BL and BLB are discharged to a low level in advance and the word line WL is driven to a low level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the bit line BL is charged to a high level and the bit line BLB is held at a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the bit line BL is held at a low level and the bit line BLB is charged to a high level.

[0025] As described above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0026] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 1 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0027] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0028] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell being inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell being inverted in the Y direction.

[0029] 1B, a BM0 (Backside Metal 0) wiring layer is formed on the back surface of the semiconductor chip on which the transistors are formed. The BM0 wiring layer corresponds to the back surface wiring layer.

[0030] The BM0 wiring layer is formed with a power supply wiring 11 extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0031] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in a plan view.

[0032] In the P-type transistor region, access transistors PG1 and PG2 and drive transistors PU1 and PU2 are formed. The access transistor PG1, the drive transistors PU1 and PU2, and the access transistor PG2 each have a channel structure of two overlapping sheets in a plan view, and each have nanosheets 21 to 24 extending in the Y direction.

[0033] In the active region P1, the portion that becomes the source of the drive transistor PU1 is connected to the power supply wiring 11 through a via 91 that is provided at a position that overlaps the power supply wiring 11 in a planar view. In the active region P2, the portion that becomes the source of the drive transistor PU2 is connected to the power supply wiring 11 through a via 92 that is provided at a position that overlaps the power supply wiring 11 in a planar view.

[0034] As shown in Figure 1A, a plurality of active regions that form the channel, source, and drain of the N-type transistor are formed in the N-type transistor region. Specifically, active regions N1 and N2 are formed in the N-type transistor region. The active regions N1 and N2 are respectively arranged above the active regions P1 and P2 in the Z direction. The active regions N1 and N2 overlap with the active regions P1 and P2, respectively, in a plan view.

[0035] In the N-type transistor region, load transistors PD1 and PD2 are formed. The load transistors PD1 and PD2 have channels formed of two overlapping sheet structures in a plan view, and have nanosheets 25 and 26 extending in the Y direction, respectively.

[0036] The width in the X direction of nanosheets 21 to 24 is twice the width in the X direction of nanosheets 25 and 26. In plan view, the right end of nanosheet 25 and the right end of nanosheet 22 are aligned in the X direction. In plan view, the left end of nanosheet 26 and the left end of nanosheet 23 are aligned in the X direction.

[0037] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0038] Gate wirings (Gate) 31 to 34 are formed extending in the X direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21 in the X and Z directions. The gate wiring 32 surrounds the outer periphery of the nanosheets 23 and 26 in the X and Z directions. The gate wiring 33 surrounds the outer periphery of the nanosheets 22 and 25 in the X and Z directions. The gate wiring 34 surrounds the outer periphery of the nanosheet 24 in the X and Z directions. The gate wiring 31 corresponds to the gate of the access transistor PG1. The gate wiring 32 corresponds to the gates of the drive transistor PU2 and the load transistor PD2. The gate wiring 33 corresponds to the gates of the drive transistor PU1 and the load transistor PD1. The gate wiring 34 corresponds to the gate of the access transistor PG2.

[0039] As shown in FIGS. 2(b) and 3(a), nanosheets 21 to 26 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, the surface of nanosheet 21 on the right side in the X direction is exposed from gate wiring 31, and the surface on the left side in the X direction is covered by gate wiring 31. The surfaces of nanosheets 23 and 26 on the left side in the X direction are exposed from gate wiring 32, and the surfaces on the right side in the X direction are covered by gate wiring 32. The surfaces of nanosheets 22 and 25 on the right side in the X direction are exposed from gate wiring 33, and the surfaces on the left side in the X direction are covered by gate wiring 33. The surface of nanosheet 24 on the left side in the X direction is exposed from gate wiring 34, and the surface on the right side in the X direction is covered by gate wiring 34. That is, the surfaces of nanosheets 21 and 23 facing each other in the X direction are exposed from gate wiring 31 and 32, respectively. The nanosheets 22 and 24 have surfaces that face each other in the X direction exposed from the gate wirings 33 and 34, respectively. The nanosheets 25 and 26 have surfaces that face each other in the X direction exposed from the gate wirings 33 and 32, respectively.

[0040] As shown in FIG. 1B, local interconnects (LI) 41 to 44 are formed extending in the X direction. The local interconnect 41 is connected to a portion in the active region P1 that will become the source of the access transistor PG1. The local interconnect 42 is connected to a portion in the active region P1 that will become the drain of the access transistor PG1 and a portion in the active region P1 that will become the drain of the drive transistor PU1. The local interconnect 43 is connected to a portion in the active region P2 that will become the drain of the drive transistor PU2 and a portion in the active region P2 that will become the drain of the access transistor PG2. The local interconnect 44 is connected to a portion in the active region P2 that will become the source of the access transistor PG2.

[0041] As shown in FIG. 1A, local interconnections 45 to 48 extending in the X direction are formed above the cell. Local interconnection 45 is connected to a portion in active region N2 that will become the source of load transistor PD2. Local interconnection 46 is connected to a portion in active region N1 that will become the drain of load transistor PD1. Local interconnection 47 is connected to a portion in active region N2 that will become the drain of load transistor PD2. Local interconnection 48 is connected to a portion in active region N1 that will become the source of load transistor PD1.

[0042] The local wiring 46 is connected to the gate wiring 32 via a shared contact 51. The local wiring 46 is connected to the local wiring 42 via a via 52. The local wiring 47 is connected to the gate wiring 33 via a shared contact 53. The local wiring 47 is connected to the local wiring 43 via a via 54. The gate wiring 32, the local wirings 42 and 46, the shared contact 51, and the via 52 correspond to a first node NA. The gate wiring 33, the local wirings 43 and 47, the shared contact 53, and the via 54 correspond to a second node NB.

[0043] Wiring lines 61 and 62 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer, which is a metal wiring layer above the active regions N1 and N2. Wiring lines 63 to 66 are also formed. Wiring lines 61 and 62 correspond to bit lines BL and BLB, respectively.

[0044] In a plan view, the wiring 61 overlaps with the active regions P1 and N1 and the power supply wiring 11. In a plan view, the wiring 62 overlaps with the active regions P2 and N2 and the power supply wiring 11. The wiring 61 is connected to the local wiring 41 through a via 55. The wiring 62 is connected to the local wiring 44 through a via 56.

[0045] In the M2 wiring layer, which is the layer above the M1 wiring layer, a wiring 71 extending in the X direction from the left to the right ends of the cell in the drawing and power supply wirings 72 and 73 are formed. The wiring 71 corresponds to the word line WL. The power supply wirings 72 and 73 supply the power supply voltage VSS.

[0046] Wiring 71 is connected to gate wiring 31 through via 81, wiring 63, and via 57. Wiring 71 is connected to gate wiring 34 through via 82, wiring 64, and via 58. Power supply wiring 72 is connected to local wiring 45 through via 83, wiring 65, and via 59. Power supply wiring 73 is connected to local wiring 48 through via 84, wiring 66, and via 60.

[0047] With the above configuration, the X-direction width of nanosheets 25 and 26 is half the X-direction width of nanosheets 22 and 23. In other words, the drive capability of drive transistors PU1 and PU2 is higher than that of load transistors PD1 and PD2. This eliminates the need to include a transistor composed of multiple transistors among the six transistors that make up a one-port SRAM cell, thereby reducing the area of ​​the semiconductor memory device. Furthermore, by setting the drive capability of drive transistors PU1 and PU2 and access transistors PG1 and PG2 higher than that of load transistors PD1 and PD2, the operating speed, lower operating voltage limit, and operational stability of the semiconductor memory device can be improved.

[0048] Furthermore, the right ends of the active regions P1 and N1 in the drawing are positioned at the same position in the X direction. The left ends of the active regions P2 and N2 in the drawing are positioned at the same position in the X direction. That is, the right ends of the active regions P1 and N1 in the drawing are aligned in the X direction. The left ends of the active regions P2 and N2 in the drawing are aligned in the X direction. Furthermore, the right surface of the nanosheet 21 in the drawing is exposed from the gate wiring 31. The right surfaces of the nanosheets 22 and 25 in the drawing are exposed from the gate wiring 33. The left surfaces of the nanosheets 23 and 26 in the drawing are exposed from the gate wiring 32. The left surface of the nanosheet 24 in the drawing is exposed from the gate wiring 34. That is, the positions of the surfaces of the nanosheets 22 and 25 exposed from the gate wiring 33 and the positions of the surfaces of the nanosheet 21 exposed from the gate wiring 31 are aligned in the X direction. The position of the surface of nanosheet 24 exposed from gate wiring 34 and the position of the surface of nanosheets 23 and 26 exposed from gate wiring 32 are aligned in the X direction. In a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, by aligning the positions of the nanosheet surfaces exposed from the gate wiring in the X direction, as in the configuration of FIG. 1, the shape of the structure, i.e., its size and placement area in the X direction, can be made constant. This facilitates the manufacture of semiconductor memory devices.

[0049] Furthermore, the surfaces of the nanosheets 21 and 23 that face each other in the X direction are exposed from the gate wirings 31 and 32, respectively. The surfaces of the nanosheets 22 and 24 that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively. The surfaces of the nanosheets 25 and 26 that face each other in the X direction are exposed from the gate wirings 33 and 32, respectively. This makes it possible to reduce the distance d1 in the X direction between the access transistor PG1 and the drive transistor PU2, the distance d1 in the X direction between the drive transistor PU1 and the access transistor PG2, and the distance d1 in the X direction between the load transistors PD1 and PD2. This allows the area of ​​the semiconductor memory device to be reduced.

[0050] Furthermore, power supply wiring 11 that supplies power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. The power supply wiring 11 overlaps the active regions P1 and P2 in a planar view, and is connected to each other by vias 91 and 92 provided in the overlapping region. Therefore, since the active regions (transistors) and the power supply wiring can be arranged to overlap, the wiring width of the power supply wiring 11 that supplies power supply voltage VDD can be increased, and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and operational stability of the semiconductor memory device.

[0051] Furthermore, a power supply wiring 11 that supplies a power supply voltage VDD is formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. As a result, the wiring formed in the BM0 wiring layer is only the power supply wiring that supplies the power supply voltage VDD, and the wiring width of the power supply wiring 11 can be increased. This reduces the wiring resistance of the power supply wiring and suppresses a power supply voltage drop, thereby improving the operating speed and operational stability of the semiconductor memory device. Furthermore, increasing the wiring width of the power supply wiring 11 reduces the wiring resistance of the wiring that supplies the power supply voltage VDD, thereby improving operational stability, particularly the retention characteristics (static noise margin) of the SRAM cell.

[0052] Furthermore, power supply wiring 72, 73 for supplying the power supply voltage VSS are formed in the M2 wiring layer. As a result, the power supply wiring 72, 73 for supplying the power supply voltage VSS are formed to penetrate the SRAM cell in the X direction and are connected to the power supply wiring 72, 73 of the SRAM cells arranged adjacent to the SRAM cell on both the left and right sides of the SRAM cell in the drawing, so that the cell array is continuous in the X direction. Therefore, it is not necessary to form wiring in the M1 wiring layer that penetrates the SRAM cell in the Y direction and supplies the power supply voltage VSS. This allows the wiring width of the wiring 61, 62 to be increased, thereby reducing the wiring resistance of the bit lines BL, BLB. Furthermore, the distance between the wiring 61, 62 can be increased. This allows the operating speed of the semiconductor memory device to be improved.

[0053] 5A to 5C are diagrams for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Specifically, FIGS. 5A to 5C are cross-sectional views taken along line X6-X6′ in FIG.

[0054] In FIG. 1, nanosheet 22 (23) of drive transistor PU1 (PU2) and nanosheet 25 (26) of load transistor PD1 (PD2) are stacked in the Z direction. As described above, the width of nanosheet 22 (23) in the X direction is half the width of nanosheet 25 (26) in the X direction. That is, in FIG. 1, nanosheets with different widths in the X direction are stacked in the Z direction. In the following explanation, a method for manufacturing a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction will be described using FIGS. 5(a) to 5(c).

[0055] 5A, a laminated semiconductor 210 is formed on a semiconductor substrate 200. The laminated semiconductor 210 is formed by alternately laminating semiconductor layers 220 and 230. Here, silicon (Si) is used as the material for the semiconductor layer 220, and a silicon germanium alloy (SiGe) is used as the material for the semiconductor layer 230.

[0056] 5, the laminated semiconductor 210 includes four semiconductor layers 220. Of the four semiconductor layers 220, the two semiconductor layers 220 (220a) at the top of the drawing correspond to the nanosheet 25 at the top of the cell, and the two semiconductor layers 220 (220b) at the bottom of the drawing correspond to the nanosheet 22 at the bottom of the cell.

[0057] After forming the laminated semiconductor 210 on the semiconductor substrate 200, a mask 241 is formed above the laminated semiconductor 210 in the figure. The width and position of the mask 241 in the X and Y directions are formed to match the width and position of the nanosheet 22 in the X and Y directions. Then, the laminated semiconductor 210 on both the left and right sides of the mask 241 in the X direction in the figure is removed by anisotropic etching. Thereafter, the mask 241 is removed.

[0058] 5B, a mask 242 is formed on the upper right portion of the laminated semiconductor 210 in the drawing. The width and position of the mask 242 in the X and Y directions are formed to match the width and position of the nanosheet 25 in the X and Y directions. Then, the laminated semiconductor 210 on the left side of the mask 242 in the drawing is removed by anisotropic etching. Specifically, the upper portion of the laminated semiconductor 210 arranged on the left side of the mask 242 in the drawing, i.e., the semiconductor layer 220a and the semiconductor layer 230, are removed. Then, after the mask 242 is removed, the load transistor PD1 and the drive transistor PU1 are formed.

[0059] By the manufacturing method described above, it is possible to manufacture a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction, as shown in FIG. 5(c).

[0060] 1, no nanosheets are formed on the upper portions of the nanosheets 21 and 24 in the Z direction. That is, in this embodiment, no nanosheets are formed on the upper portions of the cells, and nanosheets are formed only on the lower portions of the cells. In this case, in FIG. 5(b), no mask 242 is formed on the upper portion of the laminated semiconductor 210, and the upper portions of the laminated semiconductor 210, i.e., the semiconductor layer 220a and the semiconductor layer 230, are all removed. This allows nanosheets (transistors) to be formed only on the lower portions of the cells, and not on the upper portions of the cells.

[0061] (Another Configuration Example) Fig. 6(a) shows another configuration example of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 6(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power supply wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0062] 6(b) shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 6(b), a power supply wiring 11 that supplies VDD is formed in a wiring layer provided on the surface of chip B. The power supply wiring 11 is connected to active region P2 of chip A through via 92. Although not shown in the figure, the power supply wiring 11 is also connected to active region P1 of chip A through via 91.

[0063] 7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 7A shows the upper part of the cell and Fig. 7B shows the lower part of the cell.

[0064] In FIG. 7, compared to FIG. 1, the surfaces of the nanosheets 21 to 26 opposite to the X direction are exposed from the gate wiring.

[0065] Specifically, the surface of nanosheet 21 on the left side in the X direction in the drawing is exposed from gate wiring 31, and the surface on the right side in the X direction in the drawing is covered by gate wiring 31. The surfaces of nanosheets 23 and 26 on the right side in the X direction in the drawing are exposed from gate wiring 32, and the surfaces on the left side in the X direction in the drawing are covered by gate wiring 32. The surfaces of nanosheets 22 and 25 on the left side in the X direction in the drawing are exposed from gate wiring 33, and the surfaces on the right side in the X direction in the drawing are covered by gate wiring 33. The surface of nanosheet 24 on the right side in the X direction in the drawing is exposed from gate wiring 34, and the surface on the left side in the X direction in the drawing is covered by gate wiring 34.

[0066] The gate wiring 31 is connected to the gate wiring 31 arranged on the left side of the SRAM cell in the drawing via a bridge portion 40a extending in the X direction. The gate wiring 34 is connected to the gate wiring 34 arranged on the right side of the SRAM cell in the drawing via a bridge portion 40b extending in the X direction.

[0067] The wiring 71 is connected to the gate wiring 31 through the via 81, the wiring 63, the via 57, and the bridge portion 40a. The wiring 71 is connected to the gate wiring 34 through the via 82, the wiring 64, the via 58, and the bridge portion 40b.

[0068] In FIG. 7 , nanosheets 21, 22, and 25 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 23, 24, and 26 are arranged close to the cell boundary on the right side of the drawing. In the SRAM cell of FIG. 7 , SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the SRAM cells arranged in the X direction, the surfaces of nanosheets 21 facing each other in the X direction are exposed from gate wiring 31. Similarly, the surfaces of nanosheets 22 facing each other and nanosheets 25 facing each other in the X direction are exposed from gate wiring 33. The surfaces of nanosheets 23 facing each other and nanosheets 26 facing each other in the X direction are exposed from gate wiring 32. The surfaces of nanosheets 24 facing each other in the X direction are exposed from gate wiring 36. This reduces the distance d1 in the X direction between the drive transistors PU1, the distance d1 in the X direction between the drive transistors PU2, the distance d1 in the X direction between the load transistors PD1, the distance d1 in the X direction between the load transistors PD2, the distance d1 in the X direction between the access transistors PG1, and the distance d1 in the X direction between the access transistors PG2, thereby reducing the area of ​​the semiconductor memory device.

[0069] In addition, in plan view, the left end of nanosheet 25 and the left end of nanosheet 22 are aligned in the X direction. In plan view, the right end of nanosheet 26 and the right end of nanosheet 23 are aligned in the X direction.

[0070] Furthermore, the left ends of the active regions P1 and N1 in the drawing are positioned at the same position in the X direction. The right ends of the active regions P2 and N2 in the drawing are positioned at the same position in the X direction. That is, the left ends of the active regions P1 and N1 in the drawing are aligned in the X direction. The right ends of the active regions P2 and N2 in the drawing are aligned in the X direction. Furthermore, the left side of the nanosheet 21 in the drawing is exposed from the gate wiring 31. The left side of the nanosheets 22 and 25 in the drawing are exposed from the gate wiring 33. The right side of the nanosheets 23 and 26 in the drawing are exposed from the gate wiring 32. The right side of the nanosheet 24 in the drawing is exposed from the gate wiring 34. That is, the positions of the surfaces of the nanosheets 22 and 25 exposed from the gate wiring 33 and the position of the surface of the nanosheet 21 exposed from the gate wiring 31 are aligned in the X direction. The position of the surface of nanosheet 24 exposed from gate wiring 34 and the position of the surfaces of nanosheets 23 and 26 exposed from gate wiring 32 are aligned in the X direction. This allows the shape of the structure made of an insulator provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the X direction, to be consistent. This facilitates the manufacture of semiconductor memory devices.

[0071] In addition, the same effects as those in FIG. 1 can be obtained.

[0072] 8A and 8B are plan views showing an example of a layout structure of an SRAM cell according to a second embodiment. Specifically, Fig. 8A shows the upper part of the cell, and Fig. 8B shows the lower part of the cell.

[0073] 8, compared to FIG. 1, wires 12 and 13 are arranged in the BM0 wiring layer instead of the power supply wire 11. A power supply wire 67 is arranged in the M1 wiring layer instead of the wires 61 and 62.

[0074] 8B, the BM0 wiring layer is formed with wirings 12 and 13 extending in the Y direction from the top to the bottom of the cell in the drawing. The wirings 12 and 13 correspond to the bit lines BL and BLB, respectively.

[0075] In the active region P1, the portion that becomes the source of the access transistor PG1 is connected to the wiring 12 through a via 93 that is provided at a position that overlaps the wiring 12 in a plan view. In the active region P2, the portion that becomes the source of the access transistor PG2 is connected to the wiring 13 through a via 94 that is provided at a position that overlaps the wiring 13 in a plan view.

[0076] 8A, the M1 wiring layer is formed with a power supply wiring 67 extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 67 supplies a power supply voltage VDD.

[0077] Power supply wiring 67 overlaps with active regions P1, P2, N1, and N2 and wiring 12 and 13 in plan view. Power supply wiring 67 is connected to a portion of active region P2 that will become the source of drive transistor PU2 through via 60a and local wiring 49. Power supply wiring 67 is connected to a portion of active region P1 that will become the source of drive transistor PU1 through via 60b and local wiring 50.

[0078] 8, similar to FIG. 1, the X-direction width of nanosheets 25 and 26 is half the X-direction width of nanosheets 22 and 23. That is, the drive capability of drive transistors PU1 and PU2 is higher than that of load transistors PD1 and PD2. This eliminates the need to include a transistor composed of multiple transistors among the six transistors that make up a one-port SRAM cell, thereby reducing the area of ​​the semiconductor memory device. Furthermore, by setting the drive capability of drive transistors PU1 and PU2 and access transistors PG1 and PG2 higher than that of load transistors PD1 and PD2, the operating speed, lower operating voltage limit, and operational stability of the semiconductor memory device can be improved.

[0079] Furthermore, the right ends of the active regions P1 and N1 in the drawing are positioned at the same position in the X direction. The left ends of the active regions P2 and N2 in the drawing are positioned at the same position in the X direction. That is, the right ends of the active regions P1 and N1 in the drawing are aligned in the X direction. The left ends of the active regions P2 and N2 in the drawing are aligned in the X direction. Furthermore, the right surface of the nanosheet 21 in the drawing is exposed from the gate wiring 31. The right surfaces of the nanosheets 22 and 25 in the drawing are exposed from the gate wiring 33. The left surfaces of the nanosheets 23 and 26 in the drawing are exposed from the gate wiring 32. The left surface of the nanosheet 24 in the drawing is exposed from the gate wiring 34. That is, the positions of the surfaces of the nanosheets 22 and 25 exposed from the gate wiring 33 and the positions of the surfaces of the nanosheet 21 exposed from the gate wiring 31 are aligned in the X direction. The position of the surface of nanosheet 24 exposed from gate wiring 34 and the position of the surfaces of nanosheets 23 and 26 exposed from gate wiring 32 are aligned in the X direction. This allows the shape of the structure made of an insulator provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the X direction, to be consistent. This facilitates the manufacture of semiconductor memory devices.

[0080] Furthermore, the surfaces of the nanosheets 21 and 23 that face each other in the X direction are exposed from the gate wirings 31 and 32, respectively. The surfaces of the nanosheets 22 and 24 that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively. The surfaces of the nanosheets 25 and 26 that face each other in the X direction are exposed from the gate wirings 33 and 32, respectively. This makes it possible to reduce the distance d1 in the X direction between the access transistor PG1 and the drive transistor PU2, the distance d1 in the X direction between the drive transistor PU1 and the access transistor PG2, and the distance d1 in the X direction between the load transistors PD1 and PD2. This allows the area of ​​the semiconductor memory device to be reduced.

[0081] Furthermore, wirings 12 and 13 corresponding to bit lines BL and BLB, respectively, are formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. Wiring 12 overlaps with active region P1 in a planar view and is connected to each other by a via 93 provided in the overlapping region. Wiring 13 overlaps with active region P2 in a planar view and is connected to each other by a via 94 provided in the overlapping region. Therefore, since the active region (transistor) and the bit line can be arranged to overlap, the wiring width of wirings 12 and 13 corresponding to bit lines BL and BLB, respectively, can be increased, and the wiring resistance of the bit line can be reduced. This can improve the operating speed of the semiconductor memory device.

[0082] Furthermore, wirings 12 and 13 corresponding to the bit lines BL and BLB, respectively, are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. As a result, wirings for supplying power supply voltages VDD and VSS are not formed in the BM0 wiring layer, and therefore the wiring widths of the wirings 12 and 13 can be increased. By increasing the wiring widths of the wirings 12 and 13, the wiring resistance of the bit lines BL and BLB can be reduced, thereby improving the operating speed of the semiconductor memory device.

[0083] Furthermore, a power supply wiring 67 that supplies a power supply voltage VDD is formed in the M1 wiring layer, which is a metal wiring layer above the transistors. Power supply wirings 72 and 73 that supply a power supply voltage VSS are formed in the M2 wiring layer. As a result, the only wiring formed in the M1 wiring layer is the power supply wiring 67 that supplies the power supply voltage VDD, allowing the wiring width of the power supply wiring to be increased. This reduces the wiring resistance of the power supply wiring and suppresses power supply voltage drops, thereby improving the operating speed and operational stability of the semiconductor memory device. Furthermore, increasing the wiring width of the power supply wiring 67 reduces the wiring resistance of the wiring that supplies the power supply voltage VDD, thereby improving operational stability, particularly the retention characteristics (static noise margin) of the SRAM cell.

[0084] 9A and 9B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment, in which Fig. 9A shows the upper part of the cell and Fig. 9B shows the lower part of the cell.

[0085] In FIG. 9, compared to FIG. 8, the surfaces of the nanosheets 21 to 26 opposite to the X direction are exposed from the gate wiring.

[0086] The surface of nanosheet 21 on the left side in the X direction in the drawing is exposed from gate wiring 31, and the surface on the right side in the X direction in the drawing is covered by gate wiring 31. The surfaces of nanosheets 23 and 26 on the right side in the X direction in the drawing are exposed from gate wiring 32, and the surfaces on the left side in the X direction in the drawing are covered by gate wiring 32. The surfaces of nanosheets 22 and 25 on the left side in the X direction in the drawing are exposed from gate wiring 33, and the surfaces on the right side in the X direction in the drawing are covered by gate wiring 33. The surface of nanosheet 24 on the right side in the X direction in the drawing is exposed from gate wiring 34, and the surface on the left side in the X direction in the drawing is covered by gate wiring 34.

[0087] The gate wiring 31 is connected to the gate wiring 31 arranged on the left side of the SRAM cell in the drawing via a bridge portion 40a extending in the X direction. The gate wiring 34 is connected to the gate wiring 34 arranged on the right side of the SRAM cell in the drawing via a bridge portion 40b extending in the X direction.

[0088] The wiring 71 is connected to the gate wiring 31 through the via 81, the wiring 63, the via 57, and the bridge portion 40a. The wiring 71 is connected to the gate wiring 34 through the via 82, the wiring 64, the via 58, and the bridge portion 40b.

[0089] In FIG. 9 , nanosheets 21, 22, and 25 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 23, 24, and 26 are arranged close to the cell boundary on the right side of the drawing. In the SRAM cell of FIG. 9 , SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the SRAM cells arranged in the X direction, the surfaces of nanosheets 21 facing each other in the X direction are exposed from gate wiring 31. Similarly, the surfaces of nanosheets 22 facing each other and nanosheets 25 facing each other in the X direction are exposed from gate wiring 33. The surfaces of nanosheets 23 facing each other and nanosheets 26 facing each other in the X direction are exposed from gate wiring 32. The surfaces of nanosheets 24 facing each other in the X direction are exposed from gate wiring 34. This reduces the distance d1 in the X direction between the drive transistors PU1, the distance d1 in the X direction between the drive transistors PU2, the distance d1 in the X direction between the load transistors PD1, the distance d1 in the X direction between the load transistors PD2, the distance d1 in the X direction between the access transistors PG1, and the distance d1 in the X direction between the access transistors PG2, thereby reducing the area of ​​the semiconductor memory device.

[0090] In addition, in plan view, the left end of nanosheet 25 and the left end of nanosheet 22 are aligned in the X direction. In plan view, the right end of nanosheet 26 and the right end of nanosheet 23 are aligned in the X direction.

[0091] Furthermore, the left ends of the active regions P1 and N1 in the drawing are positioned at the same position in the X direction. The right ends of the active regions P2 and N2 in the drawing are positioned at the same position in the X direction. That is, the left ends of the active regions P1 and N1 in the drawing are aligned in the X direction. The right ends of the active regions P2 and N2 in the drawing are aligned in the X direction. Furthermore, the left side of the nanosheet 21 in the drawing is exposed from the gate wiring 31. The left side of the nanosheets 22 and 25 in the drawing are exposed from the gate wiring 33. The right side of the nanosheets 23 and 26 in the drawing are exposed from the gate wiring 32. The right side of the nanosheet 24 in the drawing is exposed from the gate wiring 34. That is, the positions of the surfaces of the nanosheets 22 and 25 exposed from the gate wiring 33 and the position of the surface of the nanosheet 21 exposed from the gate wiring 31 are aligned in the X direction. The position of the surface of nanosheet 24 exposed from gate wiring 34 and the position of the surface of nanosheets 23 and 26 exposed from gate wiring 32 are aligned in the X direction. This allows the shape of the structure made of an insulator provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the X direction, to be constant. This makes it easier to manufacture the semiconductor memory device.

[0092] In addition, the same effects as those in FIG. 8 can be obtained.

[0093] In the above-described embodiments and modifications, each transistor is provided with two nanosheets, but some or all of the transistors may be provided with one nanosheet or three or more nanosheets.

[0094] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0095] In addition, in each of the above-described embodiments and modifications, the shared contacts 51 and 53 may be manufactured in the same process as the contacts (gate-contacts) and local wiring, or may be manufactured in a separate process.

[0096] In addition, in the above-described embodiments and modifications, the width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26, but this is not limited to this. The width in the X direction of the nanosheets 21 to 26 may be determined according to the drive capability of each transistor configured in the SRAM cell.

[0097] Furthermore, in each of the above-described embodiments and variations, the power supply that supplies the power supply voltage VDD to the sources of the drive transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0098] In the present disclosure, with respect to an SRAM cell using a CFET, in a layout structure of an SRAM cell using a fork-sheet transistor as a transistor, it is possible to improve the operating speed and operational stability of a semiconductor memory device and reduce the area of ​​the semiconductor memory device.

[0099] 11, 67, 72, 73 Power supply wiring 91 to 94 Vias 21 to 26 Nanosheets 31 to 34 Gate wiring 12, 13, 61, 62 Wiring PU1, PU2 Drive transistors PD1, PD2 Load transistors PG1, PG2 Access transistors BL, BLB Bit lines WL Word lines

Claims

1. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line that forms a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the first, second, fifth, and sixth transistors are transistors of a first conductivity type, The third and fourth transistors are transistors of a second conductivity type different from the first conductivity type, and the SRAM cell comprises: a first active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in a first direction; a second active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; a third active region formed higher than the first and second active regions in the depth direction, constituting the channel, source, and drain of the third transistor, the channel being a third nanosheet extending in the first direction; and a fourth active region formed higher than the first and second active regions in the depth direction, constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction.the first to fourth nanosheets are provided with a second direction perpendicular to the first direction and the depth direction, and first to fourth gate wirings surrounding the depth direction, respectively; the first and third nanosheets have a first side surface, which is one side in the second direction, exposed from the first and third gate wirings, respectively; the second and fourth nanosheets have a second side surface, which is the other side in the second direction, exposed from the second and fourth gate wirings, respectively; the first and third nanosheets overlap in a planar view; the second and fourth nanosheets overlap in a planar view; the third nanosheet has a smaller width in the second direction than the first nanosheet; the fourth nanosheet has a smaller width in the second direction than the second nanosheet; in a planar view, the first side end of the first nanosheet and the first side end of the third nanosheet are arranged at the same position in the second direction; A semiconductor memory device, wherein, in a planar view, the second side end of the second nanosheet and the second side end of the fourth nanosheet are arranged at the same position in the second direction.

2. A semiconductor memory device according to claim 1, wherein the first active region constitutes the channel, source, and drain of the fifth transistor, and includes a fifth nanosheet extending in the first direction as the channel; the second active region constitutes the channel, source, and drain of the sixth transistor, and includes a sixth nanosheet extending in the first direction as the channel; the SRAM cell comprises fifth and sixth gate wirings surrounding the fifth and sixth nanosheets in the second direction and the depth direction, respectively; the first side surface of the fifth nanosheet is exposed from the fifth gate wiring; the second side surface of the sixth nanosheet is exposed from the sixth gate wiring; in a plan view, the first side end of the first nanosheet, the first side end of the third nanosheet, and the first side end of the fifth nanosheet are arranged at the same position in the second direction; A semiconductor memory device, wherein, in a planar view, the second side end of the second nanosheet, the second side end of the fourth nanosheet, and the second side end of the sixth nanosheet are arranged at the same position in the second direction.

3. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises: a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to sixth transistors, extending in the first direction, overlapping the first and second active regions in a plan view, and connected to the first power supply; a first via formed in a region in the first active region where a region that becomes the source of the first transistor overlaps with the first power supply wiring, connecting the source of the first transistor in the first active region to the first power supply wiring; and a second via formed in a region in the second active region where a region that becomes the source of the second transistor overlaps with the first power supply wiring, connecting the source of the second transistor in the second active region to the first power supply wiring.

4. A semiconductor memory device according to claim 1, wherein the SRAM cell is formed in a metal wiring layer above the first to sixth transistors, extends in the first direction, and comprises a first power supply wiring connected to the first power supply, and the first power supply wiring is connected to a region in the first active region that serves as the source of the first transistor, and a region in the second active region that serves as the source of the second transistor.

5. A semiconductor memory device according to claim 1, wherein the SRAM cell is formed in a metal wiring layer above the first to sixth transistors, extends in the second direction, and comprises third and fourth power supply wirings connected to the second power supply, the third power supply wiring being connected to a region in the third active region that will become the source of the third transistor, and the fourth power supply wiring being connected to a region in the fourth active region that will become the source of the fourth transistor.

6. A semiconductor memory device according to claim 1, wherein the first bit line is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in the first direction, and the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction.

7. A semiconductor memory device according to claim 1, wherein the first bit line is formed in a back wiring layer that is a wiring layer on the back side of the first to sixth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the back wiring layer and includes a second wiring extending in the first direction; and the SRAM cell comprises: a first via formed in a region where a region that becomes the source of the fifth transistor overlaps with the first wiring and connects the source of the fifth transistor with the first wiring; and a second via formed in a region where a region that becomes the source of the fifth transistor overlaps with the second wiring and connects the source of the fifth transistor with the second wiring.

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