Electronic device including printed circuit board

Abstract

An interposer for connecting a printed circuit board may comprise: an interposer substrate including a first surface and a second surface opposite to the first surface; and at least one via-structure located at the interposer substrate. The via-structure may comprise: a first pad disposed on the first surface; a second pad spaced apart from the first pad and disposed inside the interposer substrate, the second pad including a first body and at least one first opening extending through the first body; a third pad spaced apart from the second pad; at least one first via disposed between the first pad and the second pad and connected to the first body of the second pad; and a second via disposed between the second pad and the third pad.

Description

Electronic devices including printed circuit boards

[0001] The disclosure relates to an electronic device including a printed circuit board.

[0002] Technologies are being developed to improve the efficiency of mounting space and / or wiring space within electronic devices by efficiently arranging multiple electrical and / or electronic components within the electronic device.

[0003] However, the above-described content should not be construed as the applicant's recognition of the content described in this document as prior art, but should only be construed as technology (related art) related to the invention described in this document.

[0004] technical issues

[0005] In examples, an electronic device may include a printed circuit board assembly (PCA) comprising two or more printed circuit boards (e.g., a laminated structure). An interposer comprising one or more vias (via structures) may connect the printed circuit boards within the assembly. However, given differences in coefficients of thermal expansion within the materials used to connect the assembly, cracking within the structure may occur.

[0006] Summary of the invention

[0007] An interposer for connecting printed circuit boards according to one embodiment may include an interposer substrate having a first surface and a second surface opposite to the first surface, and at least one via structure disposed on the interposer substrate. The via structure may include a first pad disposed on the first surface, a second pad spaced apart from the first pad and disposed inside the interposer substrate, the second pad including a first body and at least one first opening penetrating the first body, a third pad spaced apart from the second pad, at least one first via disposed between the first pad and the second pad and connected to the first body of the second pad, and a second via disposed between the second pad and the third pad.

[0008] An electronic device according to one embodiment may include a housing and a printed circuit board arranged in an internal space of the housing. The printed circuit board may include a first circuit board, a second circuit board, and at least one interposer arranged between the first circuit board and the second circuit board and connecting the first circuit board and the second circuit board along a height direction. The at least one interposer may include an interposer substrate including a first surface and a second surface opposite to the first surface, and at least one via structure arranged on the interposer substrate. The via structure may include a first pad disposed on the first surface and facing the first circuit board, a second pad spaced apart from the first pad and disposed inside the interposer substrate, a third pad spaced apart from the second pad and disposed inside the interposer substrate, a fourth pad spaced apart from the third pad and disposed on the second surface and facing the second circuit board, a first via disposed between the first pad and the second pad, a second via disposed between the second pad and the third pad, and a third via disposed between the third pad and the fourth pad. The second via may include a core portion in which a dielectric is positioned along the height direction, and a boundary portion positioned to surround the core portion along the height direction. When looking at the first surface, a first connection area where the first via is connected to the second pad may overlap with the boundary portion, and a second connection area where the third via is connected to the third pad may overlap with the boundary portion.

[0009] In one embodiment, a printed circuit board may include a plurality of via structures, including a first via structure and a second via structure for electrically connecting one side and an opposite side of the printed circuit board, and an interposer substrate including a first side and a second side opposite the first side. The first via structure may include a first pad formed on a first side of the interposer substrate, a fourth pad formed on a second side opposite the first side, a second pad formed inside the interposer substrate closer to the first pad than the fourth pad, a third pad formed inside the interposer substrate closer to the fourth pad than the first pad, a second via connected to the second pad and the third pad, a plurality of first vias connected to the first pad and the second pad, and a plurality of third vias connected to the fourth pad and the third pad. The second pad may be formed between the plurality of first vias and may include a first opening connected to the interior of the second via.

[0010] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a block diagram of an electronic device within a network environment according to one embodiment.

[0012] FIG. 2A is a perspective view of an electronic device according to one embodiment, viewed in one direction.

[0013] FIG. 2b is a perspective view of an electronic device according to one embodiment viewed in another direction.

[0014] FIG. 2c is an exploded perspective view of an electronic device according to one embodiment.

[0015] FIG. 3A is a diagram illustrating a plurality of circuit boards and an interposer connected to each other in a printed circuit board according to one embodiment.

[0016] FIG. 3b is a drawing showing a state in which a plurality of interposers are arranged on a circuit board of a printed circuit board according to one embodiment.

[0017] Figure 3c is a drawing that enlarges area A of Figure 3a and shows it in three dimensions.

[0018] FIG. 4a is a cross-sectional view illustrating pads and vias formed in an interposer according to one embodiment.

[0019] FIG. 4b is a cross-sectional view taken along line II of FIG. 4a according to one embodiment.

[0020] FIG. 4c is a cross-sectional view taken along line II-II of FIG. 4a according to one embodiment.

[0021] FIG. 5a is a cross-sectional view taken along line II of FIG. 4a according to one embodiment.

[0022] FIG. 5b is a cross-sectional view taken along line II-II of FIG. 4a according to one embodiment.

[0023] FIG. 6a is a drawing illustrating an embodiment in which the interposer according to FIG. 5b further includes an extension opening.

[0024] FIG. 6b is a drawing illustrating an embodiment in which the interposer according to FIG. 5b further includes an extension opening.

[0025] FIG. 6c is a drawing illustrating an embodiment in which the interposer according to FIG. 5b further includes an extension opening.

[0026] FIG. 7a is a cross-sectional view from above of an embodiment in which a via of an interposer is formed in an arc shape according to one embodiment.

[0027] Fig. 7b is a cross-sectional view of the via of the interposer according to Fig. 7a, viewed from below.

[0028] FIG. 8 is a cross-sectional view of an interposer including a plurality of stacked vias according to one embodiment.

[0029] FIG. 9 is a drawing illustrating an opening formed in a first pad and a fourth pad according to one embodiment, and a plurality of bonding members arranged to surround the opening.

[0030] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted.

[0031]

[0032] FIG. 1 is a block diagram of an electronic device within a network environment according to various embodiments.

[0033] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with at least one of an electronic device (104) or a server (108) via a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0034] The processor (120) may control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) by executing, for example, software (e.g., a program (140)), and may perform various data processing or calculations. According to one embodiment, as at least a part of the data processing or calculation, the processor (120) may store a command or data received from another component (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the command or data stored in the volatile memory (132), and store the resulting data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or an application processor) or a secondary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor)) that may operate independently or together therewith. For example, if the electronic device (101) includes a main processor (121) and a secondary processor (123), the secondary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a specified function. The secondary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0035] The auxiliary processor (123) may control at least a part of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0036] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0037] The program (140) may be stored as software in the memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0038] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0039] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0040] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0041] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (101).

[0042] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0043] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0044] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0045] A haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0046] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0047] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0048] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0049] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0050] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) can support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0051] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas, for example, by the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device via the selected at least one antenna. According to some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0052] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., a bottom surface) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent to a second surface (e.g., a top surface or a side surface) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0053] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0054] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service on its own, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0055] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0056] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0057] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC). Each "module" in this document may include a circuit.

[0058] Various embodiments of the present document may be implemented as software (e.g., a program (140)) including one or more commands stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one command among the one or more commands stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one command called. The one or more commands may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0059] Each "processor" herein may include a processing circuit or may include multiple processors. For example, as used herein, including in the claims, the term "processor" may include various processing circuits including at least one processor, one or more of which may be individually and / or collectively configured to perform various functions described herein in a distributed manner. When "processor," "at least one processor," and "one or more processors" are described herein as being configured to perform multiple functions, these terms include, but are not limited to, situations where one processor performs some of the recited functions and another processor performs other of the recited functions, and situations where a single processor may perform all of the recited functions. Furthermore, the at least one processor may include a combination of processors that perform various recited / disclosed functions, for example, in a distributed manner. The at least one processor may execute program instructions to achieve or perform various functions.

[0060] According to one embodiment, the method according to various embodiments disclosed in the present document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0061] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0062]

[0063] FIG. 2a is a perspective view of an electronic device according to one embodiment viewed in one direction, FIG. 2b is a perspective view of an electronic device according to one embodiment viewed in another direction, and FIG. 2c is an exploded perspective view of an electronic device according to one embodiment.

[0064] Referring to FIGS. 2A to 2C, an electronic device (201) according to one embodiment (e.g., the electronic device (101) of FIG. 1) may include a housing (210) having a first surface (210a) (e.g., a front surface), a second surface (210b) (e.g., a back surface), and a third surface (210c) (e.g., a side surface) surrounding a space between the first surface (210a) and the second surface (210b).

[0065] In one embodiment, the first side (210a) may be formed by a first plate (211a) that is at least partially substantially transparent. For example, the first plate (211a) may include a glass plate or a polymer plate including at least one coating layer. In one embodiment, the second side (210b) may be formed by a second plate (211b) that is substantially opaque. For example, the second plate (211b) may be formed by a coated or colored glass, ceramic, polymer, metal (e.g., aluminum, stainless steel (STS), or magnesium), or a combination thereof. In one embodiment, the third side (210c) may be formed by a frame (211c) that is joined to the first plate (211a) and the second plate (211b) and includes a metal and / or a polymer. In one embodiment, the second plate (211b) and the frame (211c) may be formed seamlessly as one piece. In one embodiment, the second plate (211b) and the frame (211c) may be formed of substantially the same material (e.g., aluminum).

[0066] In one embodiment, the first plate (211a) may include a plurality of first edge regions (212a-1). The plurality of first edge regions (212a-1) may face the second plate (211b) from at least a portion of the first surface (210a). The plurality of first edge regions (212a-1) may contact the frame (211c). The plurality of first edge regions (212a-1) may extend in one direction (e.g., + / - Y direction). The first plate (211a) may include a plurality of second edge regions (212a-2). The plurality of second edge regions (212a-2) may face the second plate (211b) from at least a portion of the first surface (210a). A plurality of second edge regions (212a-2) may be in contact with the frame (211c). The plurality of second edge regions (212a-2) may extend in a direction (e.g., + / - X direction) different from the extension direction (e.g., + / - Y direction) of the plurality of first edge regions (212a-1). The first plate (211a) may include a plurality of third edge regions (212a-3). The plurality of third edge regions (212a-3) may face the second plate (211b) from at least a portion of the first surface (210a). The plurality of third edge regions (212a-3) may be in contact with the frame (211c). A plurality of third edge regions (212a-3) can be arranged between a plurality of first edge regions (212a-1) and a plurality of second edge regions (212a-2).

[0067] In one embodiment, the second plate (211b) may include a plurality of fourth edge regions (212b-1). The plurality of fourth edge regions (212b-1) may face the first plate (211a) from at least a portion of the second surface (210b). The plurality of fourth edge regions (212b-1) may contact the frame (211c). The plurality of fourth edge regions (212b-1) may extend in one direction (e.g., + / - Y direction). The second plate (211b) may include a plurality of fifth edge regions (212b-2). The plurality of fifth edge regions (212b-2) may face the first plate (211a) from at least a portion of the second surface (210b). A plurality of fifth edge regions (212b-2) may be in contact with the frame (211c). The plurality of fifth edge regions (212b-2) may extend in a direction (e.g., + / - X direction) different from the extension direction (e.g., + / - Y direction) of the plurality of fourth edge regions (212b-1). The second plate (211b) may include a plurality of sixth edge regions (212b-3). The plurality of sixth edge regions (212b-3) may face the first plate (211a) from at least a portion of the second surface (210b). The plurality of sixth edge regions (212b-3) may be in contact with the frame (211c). A plurality of sixth edge regions (212b-3) can be arranged between a plurality of fourth edge regions (212b-1) and a plurality of fifth edge regions (212b-2).

[0068] In one embodiment, the electronic device (201) may include a display (261) (e.g., the display module (160) of FIG. 1). In one embodiment, the display (261) may be positioned on the first surface (210a). In one embodiment, the display (261) may be visible through at least a portion of the first plate (211a) (e.g., the plurality of first edge regions (212a-1), the plurality of second edge regions (212a-2), and / or the plurality of third edge regions (212a-3)). In one embodiment, the display (261) may have a shape substantially the same as the shape of the outer edge of the first plate (211a). In some embodiments, the edge of the display (261) may substantially coincide with the outer edge of the first plate (211a).

[0069] In one embodiment, the display (261) may include a touch sensing circuit, a pressure sensor capable of measuring the intensity (pressure) of a touch, and / or a digitizer capable of detecting a magnetic stylus pen.

[0070] In one embodiment, the display (261) may include a screen display area (261a) that is visually exposed and displays content through pixels. In one embodiment, the screen display area (261a) may include a sensing area (261a-1). The sensing area (261a-1) may overlap with at least a portion of the screen display area (261a). The sensing area (261a-1) may allow transmission of an input signal related to a sensor module (276) (e.g., the sensor module (176) of FIG. 1 ). The sensing area (261a-1) may display content similarly to a screen display area (261a) that does not overlap with the sensing area (261a-1). For example, the sensing area (261a-1) may display content while the sensor module (276) is not operating. At least a portion of the camera area (261a-2) may overlap with the screen display area (261a). In one embodiment, the screen display area (261a) may include the camera area (261a-2). The camera area (261a-2) may allow transmission of an optical signal related to the first camera module (280a) (e.g., the camera module (180) of FIG. 1 ). At least a portion of the camera area (261a-2) overlapping the screen display area (261a) may display content similarly to the screen display area (261a) that does not overlap with the camera area (261a-2). For example, the camera area (261a-2) may display content while the first camera module (280a) is not operating.

[0071] In one embodiment, the electronic device (201) may include an audio module (270) (e.g., audio module (170) of FIG. 1). In one embodiment, the audio module (270) may be located on the third surface (210c). In one embodiment, the audio module (270) may obtain sound through at least one hole.

[0072] In one embodiment, the electronic device (201) may include a sensor module (276). In one embodiment, the sensor module (276) may be located on the first surface (210a). The sensor module (276) may form a sensing area (261a-1) in at least a portion of the screen display area (261a). The sensor module (276) may receive an input signal that passes through the sensing area (261a-1) and generate an electrical signal based on the received input signal. For example, the input signal may have a specified physical quantity (e.g., heat, light, temperature, sound, pressure, ultrasound). For example, the input signal may include a signal related to a user's biometric information (e.g., a fingerprint).

[0073] In one embodiment, the electronic device (201) may include a first camera module (280a) (e.g., the camera module (180) of FIG. 1). In one embodiment, the first camera module (280a) may be positioned on the first surface (210a). In one embodiment, at least a portion of the first camera module (280a) may be positioned below the display (261). In one embodiment, the first camera module (280a) may receive an optical signal that passes through the camera area (261a-2).

[0074] In one embodiment, the electronic device (201) may include a second camera module (280b) (e.g., the camera module (180) of FIG. 1). The second camera module (280b) may be positioned on the second surface (210b). In one embodiment, the second camera module (280b) may include multiple camera modules (e.g., a dual camera, a triple camera, or a quad camera).

[0075] In one embodiment, the electronic device (201) may include a flash (280c). The flash (280c) may be located on the second surface (210b). In one embodiment, the flash (280c) may include a light emitting diode or a xenon lamp.

[0076] In one embodiment, the electronic device (201) may include an audio output module (255) (e.g., the audio output module (155) of FIG. 1). In one embodiment, the audio output module (255) may be located on the third surface (210c). In one embodiment, the audio output module (255) may include one or more holes.

[0077] In one embodiment, the electronic device (201) may include an input module (250) (e.g., the input module (150) of FIG. 1). In one embodiment, the input module (250) may be located on the third surface (210c). In one embodiment, the input module (250) may include at least one key input device.

[0078] In one embodiment, the electronic device (201) may include a connection terminal (278) (e.g., connection terminal (178) of FIG. 1). In one embodiment, the connection terminal (278) may be located on the third surface (210c). For example, when the electronic device (201) is viewed in one direction (e.g., +Y direction), the connection terminal (278) may be located substantially in the center of the third surface (210c), and the audio output module (255) may be located on one side (e.g., right) with respect to the connection terminal (278).

[0079] In one embodiment, the electronic device (201) may include a support (240), a first circuit board (251), a second circuit board (252), and a battery (289) (e.g., battery (189) of FIG. 1). At least a portion of the support (240) may form a housing (210) together with the first plate (211a) and the second plate (211b).

[0080] In one embodiment, the support (240) may include a first frame structure (241), a second frame structure (243), and a plate structure (242). The first frame structure (241) may surround an edge of the plate structure (242). The first frame structure (241) may connect an edge of the first plate (211a) and an edge of the second plate (211b). The first frame structure (241) may surround a space between the first plate (211a) and the second plate (211b). At least a portion of the first frame structure (241) may form a third surface (210c) of the electronic device (201). The second frame structure (243) may be positioned between the first frame structure (241) and the second plate (211b). The first frame structure (241) and the second frame structure (243) may at least partially form a frame (211c). The plate structure (242) may include a first portion (242a) for accommodating a first circuit board (251) and a second portion (242b) for accommodating a second circuit board (252). A display (261) may be positioned on one surface (e.g., a lower surface or a +Z-axis direction) of the plate structure (242). The first circuit board (251) and the second circuit board (252) may be positioned on the other surface (e.g., a upper surface or a -Z-axis direction) of the plate structure (242). In one embodiment, the plate structure (242) may include an opening (245). The opening (245) may be positioned between the first portion (242a) and the second portion (242b). The opening (245) can pass through both sides of the plate structure (242). The opening (245) can accommodate a battery (289).

[0081] Meanwhile, one or more of the embodiments disclosed in this document may be applied to electronic devices of various shapes / forms (e.g., foldable electronic devices, slideable electronic devices, digital cameras, digital video cameras, tablets, note-shaped electronic devices, and other electronic devices) in addition to the electronic devices illustrated in FIGS. 2A to 2C.

[0082]

[0083] FIG. 3a is a diagram illustrating a plurality of circuit boards and an interposer connected to each other in a printed circuit board according to one embodiment. FIG. 3b is a diagram illustrating a state in which a plurality of interposers are arranged on the circuit boards of a printed circuit board according to one embodiment. FIG. 3c is a diagram illustrating an enlarged, three-dimensional view of area A of FIG. 3a.

[0084] Referring to FIGS. 3A to 3C, a printed circuit board (300) according to one embodiment (e.g., printed circuit boards (251, 252) of FIG. 2C) may be disposed within an electronic device (e.g., electronic device (201) of any one of FIGS. 1 and 2A to 2C). In one embodiment, the printed circuit board (300) may be formed as a multilayer circuit board structure including one or more circuit boards (310, 315, 320). For example, the printed circuit board (300) may be included or disposed within a multilayer printed circuit board assembly (e.g., a printed circuit board stack including two or more circuit boards).

[0085] In one embodiment, the printed circuit board (300) may include a plurality of circuit boards (310, 315, 320) on which one or more electrical elements (301a, 301b, 301c, 301d) are arranged, and one or more (e.g., at least one) interposers (330) connecting the plurality of circuit boards (310, 315, 320).

[0086] In one embodiment, the plurality of circuit boards (310, 315, 320) may include a first circuit board (310), a second circuit board (320), and a third circuit board (315) that are arranged parallel to each other. In one embodiment, one or more electrical components (301a, 301b, 301c, 301d) may be arranged on the surfaces of each of the first circuit board (310), the second circuit board (320), and the third circuit board (315). For example, the electrical components may be components for performing functions within an electronic device, such as an application processor (AP), a graphics processing unit (GPU), or a power management IC (PMIC).

[0087] In one embodiment, one or more interposers (330) are positioned (e.g., arranged) between circuit boards (310, 315, 320) arranged parallel to each other and can connect the circuit boards (310, 315, 320) arranged parallel to each other in the height direction (e.g., the Z-axis direction of FIG. 3A). For example, the circuit boards (310, 315, 320) can form a stack. In one embodiment, the interposer (330) can include a via structure (331) formed to penetrate the interposer (330) along the height direction of the printed circuit board (300). That is, the via (structure) can extend through the interposer (330). In one embodiment, the via structure (331) of the interposer (330) can electrically connect a pair of adjacent circuit boards (310, 320). For example, the via structure (331) can be electrically directly or indirectly connected to an electrical circuit or electrical element (301a, 301b, 301c, 301d) formed on a pair of circuit boards (310, 320). In one embodiment, the via structure (331) can include a conductive material for electrically connecting the electrical elements (301a, 301b, 301c, 301d) arranged on the circuit boards (310, 320). In one embodiment, the number of via structures (331) can be provided in multiples (e.g., via structures (331a, 331b) of FIG. 3b). That is, for example, one or more (e.g., multiple) via structures (331) may be provided.

[0088] In one embodiment, the via structure (331) of the interposer (330) may be connected to the circuit board (310, 320) by one or more bonding members (340, 350). For example, when two or more interposers connect the circuit boards (e.g., the circuit boards (310, 320)), a first bonding member and a second bonding member may connect each interposer to the circuit board. For example, the first bonding member (340) may connect the first interposer (330a) and the first circuit board (310). The second bonding member (350) may connect the first interposer (330a) and the second circuit board (320).

[0089] In one embodiment, the first interposer (330a) can electrically connect the first circuit board (310) and the second circuit board (320). The second interposer (330b) can electrically connect the first circuit board (310) and the third circuit board (315). For example, the first interposer (330a) can be connected to the first circuit board (310) and the second circuit board (320) through a plurality of bonding members (340, 350). In one embodiment, the plurality of bonding members (340, 350) are disposed between the circuit boards (310, 320) and the first interposer (330a) and can electrically connect the circuit boards (310, 320) and the first interposer (330a). In one embodiment, the plurality of bonding members (340, 350) may be arranged in various shapes, and each of the plurality of bonding members (340, 350) may be arranged in substantially the same shape.

[0090] Meanwhile, although FIGS. 3A to 3C illustrate that the printed circuit board (300) includes three circuit boards (310, 315, 320) and one or more interposers (330) connecting the three circuit boards (310, 315, 320), this is for convenience of explanation, and the number of circuit boards and interposers forming the printed circuit board (300) is not limited thereto. For example, it should be noted that the printed circuit board may include four circuit boards arranged in parallel with each other and one or more interposers connecting the respective circuit boards, or may include four or more circuit boards and a plurality of interposers.

[0091] Referring to FIG. 3B, the interposer (330) may be disposed at an edge portion of the first circuit board (310). For example, the interposer (330) may be disposed (e.g., arranged, positioned) along at least a portion of the periphery of the first circuit board (310) and may connect the first circuit board (310) and the second circuit board (320). For example, the interposer (330) may be disposed in a closed-loop form along the edges of the first circuit board (310) and the second circuit board (320). In one embodiment, when the interposer (330) is disposed at an edge portion of the first circuit board (310), the edge of the first circuit board (310) may be formed in a shape corresponding to the edge of the interposer (330).

[0092] When viewing the interposer (330) according to one embodiment in the height direction (e.g., from above in the Z-axis direction of FIG. 3b), each via structure (331a, 331b) may have a diameter (D3) and be spaced apart from each other by a second displacement (D2) (e.g., a second distance (D2)). In one embodiment, the center axes (X1, X2) of adjacent via structures (331a, 331b) may be positioned spaced apart from each other by a first displacement (D1). In one embodiment, the first displacement (D1) (e.g., the first distance (D1)) formed by the center axes (X1, X2) of adjacent via structures (331a, 331b) may be a displacement between the center axes of pads (e.g., the first pad (432) of FIG. 4a) of the via structures (e.g., the via structures (431) of FIG. 4a).

[0093] In one embodiment, the first distance (D1) may be related to the density and electrical characteristics of the circuit. That is, the distance between the via structures may be arranged or determined based on (or in consideration of) the circuit density (e.g., the density and / or arrangement of structural circuit components). For example, when the first distance (D1) is reduced (i.e., the first distance (D1) becomes smaller), more circuits may be arranged (arranged) in the same area, thereby increasing the circuit density. More circuits may be arranged in a smaller space, thereby improving the integration density. On the other hand, when the first distance (D1) is increased, the design may be simplified, and the number of circuits that can be arranged in the same area may be reduced, thereby decreasing the integration density. A via structure (331) according to an embodiment to be described later (e.g., via structure (431) of FIG. 4a) can form a first displacement (D1) of a small value (i.e., a small distance between the center axes of the via structures) sufficiently to secure a high degree of circuit integration by securing a large diameter (D3) of a pad and, accordingly, securing a small second displacement (D2) spaced apart from each other. For example, the via structure (431) can include a plurality of vias (e.g., via structures (331a, 331b)) spaced apart from each other by a small first displacement (D1) (and / or second displacement (D2)), which is intended to provide a high circuit density in the interposer area as more connections (integrations) are provided. A larger diameter (D3) (i.e., the diameter of the pad on the surface of the via structure / interposer) may also be (additionally) provided to assist circuit integration (connection).

[0094] In one embodiment, the distance (D1) between the central axes (X1, X2) of each of the plurality of via structures (331a, 331b) may be about 550 um or less. For example, the distance (D1) between the central axes (X1, X2) may be about 540 um or less, about 530 um or less, about 520 um or less, about 510 um or less, or about 500 um or less.

[0095]

[0096] FIG. 4A is a cross-sectional view illustrating pads and vias formed in an interposer according to one embodiment. FIG. 4B is a cross-sectional view taken along line II of FIG. 4A according to one embodiment. FIG. 4C is a cross-sectional view taken along line II-II of FIG. 4A according to one embodiment.

[0097] Hereinafter, the height direction of the interposer (430) may be understood to mean the Z-axis direction based on FIG. 4A. However, it should be noted that the height direction of the interposer (430) is not limited thereto and is merely for the purpose of explanation. Hereinafter, "overlapping" between components may mean that at least some of the components overlap (or at least partially overlap) with each other based on the direction in which the components are viewed from a specific direction or in a specific state. For example, "overlapping" between one component and another component may mean that all of one component and all of the other component overlap, all of one component and a part of the other component overlap, a part of one component and the whole of the other component overlap, or a part of one component and a part of the other component overlap. "Non-overlapping" between components may mean that at least some of the components do not overlap (non-overlap) with each other based on the direction in which the components are viewed from a specific direction or in a specific state. For example, a non-overlapping configuration of a work component and another component may mean that all of the work component and all of the other component are non-overlapping, all of the work component and some of the other component are non-overlapping, some of the work component and all of the other component are non-overlapping, or some of the work component and some of the other component are non-overlapping.

[0098] In one embodiment, an interposer (430) (e.g., interposer (330) of FIG. 3a) may include an interposer substrate (4301) and at least one via structure (431) (e.g., via structure (331a or 331b) of FIG. 3b) disposed on the interposer substrate (4301).

[0099] An interposer substrate (4301) according to one embodiment may form an outer appearance of an interposer (430). The interposer substrate (4301) may include a first surface (4301a) and a second surface (4301b). The first surface (4301a) of the interposer substrate (4301) may be arranged in an opposite direction to the second surface (4301b).

[0100] In one embodiment, the via structure (431) may be disposed on the interposer substrate (4301). In one embodiment, the number of via structures (431) disposed on one interposer substrate (4301) may be 1, 2, or more (e.g., multiple via structures). Although FIGS. 4A to 4C illustrate the number of via structures as 1, this is merely for illustration, and more than 1 via structure may be disposed. In one embodiment, the via structure (431) may include, but is not limited to, a first pad (432), a second pad (433), a third pad (434), a fourth pad (435), a first via (436), a second via (437), and a third via (438).

[0101] According to one embodiment, the first pad (432), the second pad (433), the third pad (434), and the fourth pad (435) of the via structure (431) may be formed to extend in a direction (e.g., the Y-axis direction of FIG. 4A) substantially perpendicular to the height direction (e.g., the Z-axis direction of FIG. 4A) of the interposer (430). In one embodiment, electrical signals may be transmitted and / or transferred to each other through the first pad (432), the second pad (433), the third pad (434), the fourth pad (435), the first via (436), the second via (437), and the third via (438) of the via structure (431).

[0102] Hereinafter, unless otherwise stated, the description of the first pad (432) can be substantially equally applied to the fourth pad (435), and the description of the second pad (433) can be substantially equally applied to the third pad (434). The description of the first via (436) according to one embodiment can be substantially equally applied to the third via (438). This also applies to the description of FIGS. 5A to 9.

[0103] In one embodiment, the first pad (432) may be disposed on a first surface (4301a) of the interposer substrate (4301). For example, the first pad (432) may be disposed such that at least a portion thereof is exposed to the outside of the interposer substrate (4301) through the first surface (4301a). In one embodiment, the first pad (432) may include a third body (4321) that forms an outer surface of the first pad (432).

[0104] In one embodiment, the fourth pad (435) may be disposed on the second side (4301b) of the interposer substrate (4301). For example, the fourth pad (435) may be disposed such that at least a portion thereof is exposed to the outside of the interposer substrate (4301) through the second side (4301b). According to one embodiment, the fourth pad (435) may be omitted when the third pad (434), which will be described later, is disposed on the second side (4301b) of the interposer substrate (4301).

[0105] In one embodiment, the first pad (432) and the fourth pad (435) may be connected to a circuit board (e.g., the circuit board (310, 315, 320) of FIG. 3A) by a bonding member (e.g., the bonding member (340, 350) of FIG. 3A), respectively. In one embodiment, the first pad (432) and the fourth pad (435) may be arranged at an edge of the periphery of the circuit board. In one embodiment, the first pad (432) and the fourth pad (435) may have a diameter (e.g., the diameter (D3) of FIG. 3B).

[0106] In one embodiment, the second pad (433) may be spaced apart from the first pad (432) along the height direction of the interposer (430) (e.g., the -Z-axis direction of FIG. 4A). In one embodiment, the second pad (433) may be disposed inside the interposer substrate (4301). In one embodiment, the second pad (433) may include a first body (4331) forming an outer appearance. In one embodiment, a first opening (4330) may be formed in the first body (4331) of the second pad (433). In one embodiment, the first opening (4330) may be formed to penetrate the first body (4331) (e.g., the first opening (4330) may extend through the first body (4331)).

[0107] In one embodiment, the third pad (434) may be spaced apart from the second pad (433) in the height direction of the interposer (430) (e.g., the -Z-axis direction in FIG. 4A) (e.g., the direction toward the second face (4301b) of the interposer). In one embodiment, the third pad (434) may be disposed inside the interposer substrate (4301). However, this is merely an example, and the third pad (434) according to one embodiment may also be disposed on the second face (4301b) of the interposer substrate (4301). In an embodiment, when the third pad (434) is disposed on the second surface (4301b) of the interposer substrate (4301), the second via (437) may be formed to extend from the second pad (433) to the second surface (4301b) of the interposer substrate (4301). In an embodiment, the second pad (433) may include a second body (4341) forming an outer appearance. In an embodiment, a second opening (4340) may be formed in the second body (4341) of the third pad (434) (e.g., the second opening (4340) may extend through the second body (4341) of the third pad (434). In an embodiment, the second opening (4340) may be formed to penetrate the second body (4341).

[0108] Although the via structure (431) according to one embodiment is illustrated as having a first opening (4330) and a second opening (4340) formed therein, this is merely an example and the first opening (4330) and the second opening (4340) do not necessarily have to be formed together. For example, the via structure (431) according to one embodiment may have only the first opening (4330) formed therein and no opening formed in the third pad (434), or may have only the third opening (4340) formed therein and no opening formed in the first pad (433).

[0109] In one embodiment, with respect to the direction facing the first side (4301a) or the second side (4301b) of the interposer (430) (e.g., the Z-axis direction in FIG. 4A), the first pad (432), the second pad (433), the third pad (434), and the fourth pad (435) may overlap each other at least partially. The first pad (432), the second pad (433), the third pad (434), and the fourth pad (435) arranged to overlap each other at least partially may increase the structural stability of the interposer (430).

[0110] According to one embodiment, a first via (436) may be disposed between a first pad (432) disposed on a first surface (4301a) of an interposer (430), and a second pad (433) disposed inside an interposer substrate (4301) and spaced apart from the first pad (432). That is, the first via (436) may extend between the first pad (432) and the second pad (433). In one embodiment, a portion where the first via (436) and the second pad (433) are connected may not overlap with the first opening (4330). For example, the first via (436) may be connected to the second pad (433) at a first connection area (4361) (e.g., a portion or body of the second pad (433)). In one embodiment, the first connection area (4361) where the first via (436) and the second pad (433) are connected may not overlap with the first opening (4330) based on the direction facing the first surface (4301a) of the interposer (430). In one embodiment, the first via (436) may be connected to the first pad (432) at the third connection area (4363). In one embodiment, the area of ​​the third connection area (4363) of the first pad (432) may be wider than the area of ​​the first connection area (4361) of the second pad (433). In one embodiment, the first via (436) may be positioned to contact at least a portion of the periphery of the first pad (432) (e.g., the third body (4321) of the first pad (432)) with respect to a cross-section (e.g., the XY plane of FIG. 4b) perpendicular to the height direction (e.g., the Z-axis direction of FIG. 4b) of the interposer (430).

[0111] In one embodiment, the number of first vias (436) may be one or more. For example, the number of first vias (436) may be one, two, three, or more. In one embodiment, when a plurality of first vias (436) are provided, the plurality of first vias (436a, 436b) may connect the first pad (432) and the second pad (433) so as not to overlap with the first opening (4330) formed in the second pad (433). For example, the plurality of first vias (436a, 436b) may be connected to the second pad (433) in each of the plurality of first connection areas (4361a, 4361b). In one embodiment, each of the plurality of first connection regions (4361a, 4361b) may be non-overlapping with the first opening (4330). In one embodiment, the plurality of first vias (436a, 436b) may be formed to be spaced apart from each other. For example, a first gap (4362) may be formed between the plurality of first vias (436a, 436b). According to one embodiment, a core portion (4371) of a second via (437) may be exposed to the first gap (4362) through the first opening (4330) formed in the second pad (433). That is, the core portion (4371) extends between the second pad (433) and the third pad (434) in the height direction of the interposer substrate (4301) and can be exposed (i.e., can be seen) from the first gap (4362) to the first opening (4330).

[0112] In one embodiment, a plurality of first vias (436a, 436b) may be connected to a first pad (432) in a plurality of third connection areas (4363a, 4363b).

[0113] In one embodiment, the first via (436) may have at least one cross-sectional shape among a circle, an ellipse, and a polygon, based on a cross-section (e.g., an XY cross-section of FIG. 4A) perpendicular to the height direction (e.g., the Z-axis direction of FIG. 4A). In one embodiment, the second via (437) and the third via (438) described below may have the same cross-sectional shape as the first via (436), or may have different cross-sectional shapes.

[0114] According to one embodiment, a third via (438) may connect a fourth pad (435) disposed on a second surface (4301b) of an interposer (430) and a third pad (434) disposed inside an interposer substrate (4301) and spaced apart from the fourth pad (435). In one embodiment, the third via (438) may be positioned so as not to overlap with a second opening (4340) formed in the third pad (434). For example, the third via (438) and the second opening (4340) of the third pad (434) may not overlap with respect to a direction facing the second surface (4301b) of the interposer (430) (e.g., the +Z-axis direction in FIG. 4A). In one embodiment, the third via (438) may be formed symmetrically with respect to the first via (436) with respect to the second via (437). For example, when looking at the first surface (4301a) of the interposer (430), the third via (438) may be formed to overlap with the first via (436). In one embodiment, the third via (438) may be positioned to contact at least a portion of the periphery of the fourth pad (435) with respect to a cross-section (e.g., an XY plane in FIG. 4b) perpendicular to the height direction (e.g., a Z-axis direction in FIG. 4b) of the interposer (430).

[0115] In one embodiment, the number of third vias (438) may be one or more. For example, the number of third vias (438) may be one, two, three, or more. In one embodiment, when a plurality of third vias (438) are provided, the plurality of third vias (438a, 438b) may connect the third pad (434) and the fourth pad (435) so as to not overlap with the second opening (4340) formed in the third pad (434). For example, the plurality of third vias (438a, 438b) may be connected to the third pad (434) at the plurality of second connection areas (4381). In one embodiment, each of the plurality of second connection areas (4381a, 4381b) may not overlap with the second opening (4340). In one embodiment, a plurality of third vias (438) may be formed spaced apart from each other. The plurality of third vias (438a, 438b) may form a second gap (4382). The second gap (4382) formed by the plurality of third vias (438a, 438b) may overlap a second opening (4340) formed in the third pad (434).

[0116] In one embodiment, at least one of the first via (436) or the third via (438) may be formed by laser processing. In one embodiment, at least one of the first via (436) or the third via (438) may be formed of a metal material.

[0117] In one embodiment, the second via (437) may be formed within the interposer substrate (4301). In one embodiment, the second via (437) may be positioned between the second pad (433) and the third pad (434) which are positioned within the interposer substrate (4301). In one embodiment, the second via (437) may be formed by drilling. In one embodiment, the second via (437) may include a core portion (4371) and a boundary portion (4372).

[0118] In one embodiment, the core portion (4371) may form a central portion of the second via (437). For example, the core portion (4371) may be formed along a height direction (e.g., the Z-axis direction of FIG. 4A, e.g., the height direction of the interposer substrate) at the central portion of the second via (437). A dielectric (4371a) may be positioned and / or filled in the core portion (4371) of the second via (437). In one embodiment, when looking at the first side (4301a) of the interposer (430), the core portion (4371) may overlap with the first opening (4330) of the second pad (433). In one embodiment, when looking at the second side (4301b) of the interposer (430), the core portion (4371) may overlap the second opening (4340) of the third pad (434). In one embodiment, the dielectric (4371a) positioned in the core portion (4371) may be exposed to the outside (e.g., the outside of the second via (437)) at least partially on both sides (e.g., both sides in the Z-axis direction of FIG. 4A) through the first opening (4330) of the second pad (433) and the second opening (4340) of the third pad (434).

[0119] In one embodiment, the core portion (4371) (e.g., the dielectric (4371a) positioned in the core portion (4371) of FIG. 4A) and the interposer substrate (4301) may have different thermal expansion coefficients. Since the dielectric (4371a) is substantially exposed to the outside on both sides through the first opening (4330) and the second opening (4340), and the core portion (4371) is exposed through the first opening (4330) and / or the first gap (4362), so that a space for (thermal) expansion exists, the risk of cracks occurring due to different thermal expansion coefficients can be prevented or reduced.

[0120] In one embodiment, the boundary portion (4372) may be positioned to surround the core portion (4371) along a direction parallel to the height direction of the core portion (4371). In one embodiment, the boundary portion (4372) of the second via (437) may include a plating layer surrounding the dielectric (4371a). In one embodiment, the boundary portion (4372) of the second via (437) may overlap with one or more first vias (436) based on a direction facing the first surface (4301a) of the interposer (430).

[0121] In one embodiment, the boundary portion (4372) may overlap with one or more third vias (438) with respect to the direction facing the second side (4301b) of the interposer (430). The first via (436) and the third via (438) may be arranged to overlap with the boundary portion (4372) of the second via (437), and may be arranged to not overlap with the first opening (4330) of the second pad (433) and the second opening (4340) of the third pad (434). The first via (436) connects the first pad (432) and the second pad (433) while being arranged to overlap the boundary portion (4372), and the third via (438) connects the third pad (434) and the fourth pad (435) while being arranged to overlap the boundary portion (4372), thereby increasing the structural stability of the interposer (430). The first via (436) is connected to the second pad (433) so as not to overlap the first opening (4330) in the first connection area (4361), thereby preventing or reducing the occurrence of cracks due to thermal expansion of the dielectric (4371a), and even if cracks occur, preventing the structural stability from being deteriorated by the cracks. The third via (438) is connected to the third pad (434) so ​​as not to overlap with the second opening (4340) in the second connection area (4381), and can prevent or reduce the occurrence of cracks due to thermal expansion of the dielectric (4371a), and even if cracks occur, prevent structural stability from being deteriorated by the cracks.

[0122] In one embodiment, the diameter (4372a) of the boundary portion (4372) may be about 220 um or less, based on a cross-section (e.g., the XY plane of FIG. 4c) perpendicular to the height direction (e.g., the Z-axis direction of FIG. 4c) of the interposer (430). In this document, terms such as “substantially,” “approximately,” “typically,” and “about” when referring to a given parameter, property, or condition may include a degree to which a person skilled in the art would understand that the given parameter, property, or condition is satisfied with a small degree of variance, such as within an acceptable manufacturing tolerance. For example, any particular parameter that is substantially satisfied may be satisfied by at least 90%, or by at least 95%, or by at least 99%. In one embodiment, the diameter (433a) of the second pad (433) may be at least 60 um longer than the diameter (4372a) of the boundary portion (4372). For example, the diameter (433a) of the second pad (433) may be about 280 um, about 285 um, about 290 um, or more.

[0123]

[0124] FIG. 5A is a cross-sectional view taken along line II of FIG. 4A according to one embodiment. FIG. 5B is a cross-sectional view taken along line II-II of FIG. 4A according to one embodiment. In describing FIGS. 5A and 5B, the descriptions given above with respect to FIGS. 1 to 4 may be applied unless otherwise specified.

[0125] Referring to FIGS. 5A and 5B, an interposer according to one embodiment (e.g., interposer (430) of FIG. 4A) may include a first pad (532) (e.g., first pad (432) of FIG. 4A), a second pad (533) (e.g., second pad (433) of FIG. 4A), and a first via (536) (e.g., first via (436) of FIG. 4A) connecting the first pad (532) and the second pad (533). In one embodiment, each of the plurality of first vias (536a, 536b, 536c) may be connected to the first pad (532) so as to contact a periphery of the first pad (532).

[0126] In one embodiment, the first via (536) may be connected to the second pad (533) in the first connection area (5361) (e.g., the first connection area (4361) of FIG. 4A). In one embodiment, each of the plurality of first vias (536a, 536b, 536c) may be connected to the second pad (533) in the plurality of first connection areas (5361a, 5361b, 5361c). In one embodiment, each of the plurality of first connection areas (5361a, 5361b, 5361c) may be non-overlapping with a first opening (5330) (e.g., the first opening (4330) of FIG. 4A) formed in the first body (5331) of the second pad (533) (e.g., the first body (4331) of FIG. 4A). In one embodiment, the first via (536) may be positioned to overlap a boundary portion (5372) (e.g., boundary portion (4372) of FIG. 4a) of a second via (e.g., second via (437) of FIG. 4a).

[0127] Meanwhile, FIGS. 5A and 5B illustrate the first via (536) and do not illustrate the third via (e.g., the third via (438) of FIG. 4A), but it should be noted that the embodiments of FIGS. 5A and 5B can be equally applied to the third via.

[0128]

[0129] FIGS. 6A to 6C are drawings illustrating an embodiment in which the interposer according to FIG. 5B further includes an extension opening.

[0130] Referring to FIGS. 6A to 6C, an interposer according to an embodiment (e.g., an interposer (430) of FIG. 4A) includes a second pad (633) located inside the interposer (e.g., the second pad (433) of FIG. 4A), a third pad (634) (e.g., the third pad (434) of FIG. 4A), a plurality of first vias (636) connected to the second pad (633) (e.g., the plurality of first vias (536) of FIG. 5A), a plurality of third vias (638) connected to the third pad (634) (e.g., the plurality of third vias (438) of FIG. 4A), a first opening (6330) formed in the second pad (633) (e.g., the first opening (4330) of FIG. 4A), at least one first extension opening (6332) formed in the second pad (633), and a third It may include a second opening (6340) formed in the pad (634) (e.g., the second opening (4340) of FIG. 4A), and at least one second extension opening (6342) formed in the third pad (634).

[0131] In one embodiment, the first extension opening (6332) can be formed to penetrate the first body (6331) of the second pad (633) (e.g., the first body (4331) of FIG. 4c). The first extension opening (6332) can extend from the perimeter of the first opening (6330). In one embodiment, the first extension opening (6332) can be formed to non-overlap with each of the first vias (636a, 636b, 636c) that are arranged to overlap with a boundary portion (6372) of a second via (e.g., the second via (437) of FIG. 4a) (e.g., the boundary portion (4372) of FIG. 4a). The first extension opening (6332) according to FIG. 6A is illustrated as extending in three directions from the first opening (6330), but this is merely an example, and the first extension opening (6332) may be formed to extend in one, two, four or more directions from the first opening (6330). The first extension opening (6332) is illustrated as being linear, but this is merely an example, and the first extension opening (6332) may also be formed in a curved or spiral shape.

[0132] Referring to FIG. 6c, in one embodiment, the first extension opening (6332a) may be formed to extend from the first opening (6330) to the periphery of the second pad (633). In one embodiment, the second pad (633) may be separated into at least two parts (633a, 633b, 633c) by the first extension opening (6332a).

[0133] In one embodiment, the second extension opening (6342) can be formed through the second body (6341) of the third pad (634) (e.g., the second body (4341) of FIG. 4a). The second extension opening (6342) can extend from the periphery of the second opening (6340). In one embodiment, the second extension opening (6342) can be formed non-overlapping with each of the third vias (638a, 638b, 638c) that are arranged to overlap with a boundary portion (6372) (e.g., the boundary portion (4372) of FIG. 4a) of the second via (e.g., the second via (437) of FIG. 4a). The second extension opening (6342) according to FIG. 6B is illustrated as extending in three directions from the second opening (6340), but this is merely an example, and the second extension opening (6342) may be formed to extend in one, two, four or more directions from the second opening (6340). The second extension opening (6342) is illustrated as being linear, but this is merely an example, and the second extension opening (6342) may also be formed in a curved or spiral shape.

[0134] According to one embodiment, the first extension opening (6332) and the second extension opening (6342) can increase the size of the opening formed in the pad of the interposer (e.g., the interposer (430) of FIG. 4A). In one embodiment, when the size of the opening increases, the risk of cracking due to expansion of the dielectric (e.g., the dielectric (4371a) of FIG. 4A) located in the core portion (e.g., the core portion (4371) of FIG. 4A) of the second via (e.g., the second via (437) of FIG. 4A) located inside the interposer can be prevented or reduced.

[0135]

[0136] FIG. 7a is a cross-sectional view from above of an embodiment in which a via of an interposer is formed in an arc shape according to one embodiment. FIG. 7b is a cross-sectional view from below of the via of the interposer according to FIG. 7a. Reference may be made to the drawings and descriptions thereof previously illustrated.

[0137] Referring to FIGS. 7A and 7B, an interposer according to an embodiment (e.g., an interposer (430) of FIG. 4A) may include a first pad (732) (e.g., a first pad (432) of FIG. 4A), a plurality of first vias (736) connected to the first pad (732) (e.g., a plurality of first vias (436) of FIG. 4A), a second pad (733) (e.g., a second pad (433) of FIG. 4A), a first opening (7330) formed in a first body (7331) of the second pad (733) (e.g., a first opening (4330) of FIG. 4A), and a second via (e.g., a second via (437) of FIG. 4A).

[0138] In one embodiment, each of the plurality of first vias (736a, 736b) may have an arc-shaped cross-sectional shape in which two arcs (736a-1 (e.g., an arc forming an inner arc or boundary of the cross-sectional arc), 736a-2 (e.g., an arc forming an outer arc or boundary of the cross-sectional arc)) are connected relative to a cross-section (e.g., an XY plane in FIG. 7a) perpendicular to a height direction (e.g., a Z-axis direction in FIG. 7a) of the interposer. In one embodiment, the arc-shaped cross-sectional shape of the first via (736) may be formed to surround (e.g., at least partially surround) a first opening (7330) formed in the second pad (733). In one embodiment, the arc-shaped cross-sectional shape of the first via (736) may be positioned so as to not overlap with the first opening (7330) and to overlap with a boundary portion (7372) of the second via (e.g., the boundary portion (4372) of FIG. 4A). In one embodiment, the third via (e.g., the third via (438) of FIG. 4A) may have substantially the same arc-shaped cross-sectional shape as the first via (736). In one embodiment, when the first via (736) and the third via have arc-shaped cross-sectional shapes, the area of ​​the via that contacts the first pad (732), the second pad (733), the third pad (e.g., the third pad (434) of FIG. 4A), and the fourth pad (e.g., the fourth pad (435) of FIG. 4A) of the interposer may increase. As the contact area of ​​the via to the pad of the interposer increases, the structural stability of the interposer can be increased.

[0139] In one embodiment, the first via (736) is illustrated as two vias (736a, 736b) having an arcuate cross-sectional shape, but this is only an example, and the number of first vias (736) may be 1, 2, 3 or more. In one embodiment, the first via (736) may have an integral arcuate cross-sectional shape surrounding the first opening (7330) with respect to a cross-section perpendicular to the height direction. In one embodiment, the number of third vias (e.g., the third via (438) of FIG. 4A) may be 1, 2, 3 or more. For example, the third via may have an integral arcuate cross-sectional shape surrounding the second opening (e.g., the second opening (4340) of FIG. 4A) with respect to a cross-section perpendicular to the height direction.

[0140]

[0141] FIG. 8 is a cross-sectional view of an interposer including a plurality of stacked vias according to one embodiment.

[0142] Referring to FIG. 8, an interposer (830) according to an embodiment (e.g., an interposer (430) of FIG. 4A) includes an interposer substrate (8301) (e.g., an interposer substrate (4301) of FIG. 4A), a first pad (832) (e.g., a first pad (432) of FIG. 4A) and a fourth pad (835) (e.g., a fourth pad (435) of FIG. 4A) at least partially exposed to the outside of the interposer, a second pad (833) (e.g., a second pad (433) of FIG. 4A) and a third pad (834) (e.g., a third pad (434) of FIG. 4A) disposed inside the interposer, a first via (836) (e.g., a first via (436) of FIG. 4A) connecting the first pad (832) and the second pad (833) and a first laminate. It may include a second via (837) (e.g., the second via (437) of FIG. 4a) connecting the second pad (833) and the third pad (834), a third via (838) (e.g., the third via (438) of FIG. 4a) connecting the third pad (834) and the fourth pad (835), and a second stacked via (839b).

[0143] In one embodiment, the first stacked via (839a) may be stacked along the height direction of the interposer (e.g., the Z-axis direction of FIG. 8) between the first via (836) and the second pad (833). In one embodiment, the second stacked via (839b) may be stacked along the height direction of the interposer between the third pad (834) and the third via (838). In one embodiment, the number of the first stacked via (839a) and the second stacked via (839b) may be 1, 2, 3, or more, respectively. In one embodiment, the first stacked via (839a) may increase the distance between the first pad (832) and the second pad (833). In one embodiment, the second stacked via (839b) may increase the distance between the third pad (834) and the fourth pad (835). In one embodiment, increasing the distance between pads of an interposer can reduce signal interference and facilitate thermal management.

[0144]

[0145] FIG. 9 is a drawing illustrating an opening formed in a first pad and a fourth pad according to one embodiment, and a plurality of bonding members arranged to surround the opening.

[0146] Referring to FIG. 9, a printed circuit board according to one embodiment (e.g., printed circuit board (300) of FIG. 3A) may include a first circuit board (e.g., first circuit board (310) of FIG. 3A), a second circuit board (e.g., second circuit board (320) of FIG. 3A), an interposer (930) (e.g., interposer (430) of FIG. 4A), a first bonding member (940) (e.g., first bonding member (340) of FIG. 3A), and a second bonding member (950) (e.g., second bonding member (350) of FIG. 3A).

[0147] An interposer (930) according to one embodiment comprises an interposer substrate (9301) (e.g., an interposer substrate (4301) of FIG. 4A), a first pad (932) (e.g., a first pad (432) of FIG. 4A) and a fourth pad (935) (e.g., a fourth pad (435) of FIG. 4A) at least partially exposed to the outside of the interposer (930), a second pad (933) (e.g., a second pad (433) of FIG. 4A) and a third pad (934) (e.g., a third pad (434) of FIG. 4A) disposed inside the interposer (930), a first via (936) (e.g., a first via (436) of FIG. 4A) connecting the first pad (932) and the second pad (933), and a second via (936) connecting the second pad (933) and the third pad (934). A third via (938) (e.g., the third via (438) of FIG. 4a) connecting a via (937) (e.g., the second via (437) of FIG. 4a), a third pad (934), and a fourth pad (935) may be included. In one embodiment, a first opening (9330) (e.g., the first opening (4330) of FIG. 4a) may be formed in the second pad (933). In one embodiment, a first bonding member (940) (e.g., the first bonding member (340) of FIG. 3a) may connect a first circuit board (e.g., the first circuit board (310) of FIG. 3a) and a first pad (932) of an interposer (930). In one embodiment, the first bonding member (940) may be in contact with the first pad (932). In one embodiment, a second bonding member (950) (e.g., the second bonding member (350) of FIG. 3A) can connect a second circuit board (e.g., the second circuit board (320) of FIG. 3A) and a fourth pad (935) of an interposer (930). In one embodiment, the second bonding member (950) can be in contact with the fourth pad (935).

[0148] In one embodiment, the first pad (932) may include a third body (9321) and a third opening (9320) formed through the third body (9321). A first bonding member (940) may be disposed in the third opening (9320) according to one embodiment. For example, the first bonding member (940) may be disposed to surround the third opening (9320).

[0149] In one embodiment, the fourth pad (935) may include a fourth body (9351) and a fourth opening (9350) formed through the fourth body (9351). A second bonding member (950) may be disposed in the fourth opening (9350) according to one embodiment. For example, the second bonding member (950) may be disposed to surround the fourth opening (9350).

[0150] In one embodiment, with respect to a direction (e.g., the Z-axis direction of FIG. 9) facing the first surface (e.g., the first surface (4301a) of FIG. 4a) of the interposer (930), a third opening (9320) formed in the first pad (932) and a first opening (9330) formed in the second pad (933) may at least partially overlap. In one embodiment, with respect to a direction facing the first surface of the interposer (930), a second opening (9340) formed in the third pad (934) and a fourth opening (9350) formed in the fourth pad (935) may at least partially overlap.

[0151]

[0152] In one embodiment, an interposer (330; 430; 830; 930) of an electronic device (201) comprises: an interposer substrate (4301; 8301; 9301) comprising a first surface (4301a) and a second surface (4301b) opposite to the first surface (4301a); a first pad (432; 532; 732; 832; 932) disposed on the first surface (4301a); a second pad (433; 533; 633; ​​733; 833; 933) disposed inside the interposer substrate (4301; 8301; 9301) and spaced apart from the first pad (432; 532; 732; 832; 932); A third pad (434;634;834;934) spaced apart from the second pad (433;533;633;733;833;933) and arranged inside the interposer substrate (4301;8301;9301); A fourth pad (435;835;935) spaced apart from the third pad (434;634;834;934) and arranged on the second surface (4301b); A first via (436;536;636;736;836;936) configured to connect the first pad (432;532;732;832;932) and the second pad (433;533;633;733;833;933); A second via (437;837;937) connecting the second pad (433;533;633;733;833;933) and the third pad (434;634;834;934); and a third via (438;638;838;938) connecting the third pad (434;634;834;934) and the fourth pad (435;835;935), wherein the second via (437;837;937) comprises: a core portion (4371) having a height direction; And a boundary portion (4372; 6372; 7372) positioned to surround the core portion (4371) along the height direction, and when looking at the first surface (4301a), the first connection area (4361; 5361) in which the first via (436; 536; 636; 736; 836; 936) is connected to the second pad (433; 533; 633; ​​733; 833; 933) is formed by the boundary portion (4372;The second connection area (4381) overlapping with the third via (438;638;838;938) and connecting the third pad (434;634;834;934) may overlap with the boundary portion (4372;6372;7372).

[0153] In one embodiment, the second pad (433; 533; 633; ​​733; 833; 933) includes a first body (4331; 5331; 6331; 7331); and a first opening (4330; 5330; 6330; 7330; 9330) penetrating the first body (4331; 5331; 6331; 7331) and overlapping the core portion (4371) when viewed from the first surface (4301a), and the third pad (434; 634; 834; 934) includes a second body (4341; 6341); And it may include a second opening (4340; 6340; 9340) penetrating the second body (4341; 6341) and overlapping the core portion (4371) when looking at the first surface (4301a).

[0154] In one embodiment, the first connection area (4361; 5361) may not overlap with the first opening (4330; 5330; 6330; 7330; 9330), and the second connection area (4381) may not overlap with the second opening (4340; 6340; 9340).

[0155] In one embodiment, the first vias (436; 536; 636; 736; 836; 936) and the third vias (438; 638; 838; 938) are each provided in multiple numbers, and each of the plurality of first connection areas (4361; 5361) in which the plurality of first vias (436; 536; 636; 736; 836; 936) are connected to the second pads (433; 533; 633; ​​733; 833; 933) does not overlap with the first openings (4330; 5330; 6330; 7330; 9330), and the plurality of third vias (438; 638; 838; 938) are connected to the third pads (434; 634; 834; 934) in multiple numbers. Each of them may be non-overlapping with the second opening (4340; 6340; 9340).

[0156] In one embodiment, a first gap (4362) is formed between the plurality of first vias (436; 536; 636; 736; 836; 936), a second gap (4382) is formed between the plurality of third vias (438; 638; 838; 938), and the first gap (4362) may overlap the first openings (4330; 5330; 6330; 7330; 9330), and the second gap (4382) may overlap the second openings (4340; 6340; 9340).

[0157] In one embodiment, each of the first vias (736) and each of the third vias (438; 838; 938) may have an arcuate cross-sectional shape in which two arcs (736a-1; 736a-2) are connected, based on a cross-section perpendicular to the height direction.

[0158] In one embodiment, a dielectric (4371a) is positioned in the core portion (4371), and the dielectric (4371a) can be exposed to the outside through the first opening (4330; 5330; 6330; 7330; 9330) and the second opening (4340; 6340; 9340).

[0159] In one embodiment, the second pad (633) may further include a first extension opening (6332) penetrating the first body (6331) and extending from a perimeter of the first opening (6330), and the third pad (634) may further include a second extension opening (6342) penetrating the second body (6341) and extending from a perimeter of the second opening (6340).

[0160] In one embodiment, the first pad (932) may include a third body (9321); and a third opening (9320) penetrating the third body (9321), and the fourth pad (935) may include a fourth body (9351); and a fourth opening (9350) penetrating the fourth body (9351).

[0161] In one embodiment, when looking at the first side (4301a), the first opening (9330) and the third opening (9320) may overlap, and the second opening (9340) and the fourth opening (9350) may overlap.

[0162] In one embodiment, the first via (436; 536; 636; 736; 836; 936) may have an integral arcuate cross-sectional shape surrounding the first opening (4330; 5330; 6330; 7330; 9330) based on a cross-section perpendicular to the height direction, and the third via (438; 638; 838; 938) may have an integral arcuate cross-sectional shape surrounding the second opening (4340; 6340; 9340) based on a cross-section perpendicular to the height direction.

[0163] In one embodiment, when looking at the first side (4301a), the first pad (432; 532; 732; 832; 932), the second pad (433; 533; 633; ​​733; 833; 933), the third pad (434; 634; 834; 934) and the fourth pad (435; 835; 935) may overlap at least partially with each other, and when looking at the first side (4301a), the first via (436; 536; 636; 736; 836; 936) and the third via (438; 638; 838; 938) may overlap with each other.

[0164] In one embodiment, based on a cross-section perpendicular to the height direction, the first via (436; 536; 636; 736; 836; 936) may be positioned to contact at least a portion of the perimeter of the first pad (432; 532; 732; 832; 932), and the third via (438; 638; 838; 938) may be positioned to contact at least a portion of the perimeter of the fourth pad (435; 835; 935).

[0165] In one embodiment, based on a cross-section perpendicular to the height direction, the first via (436; 536; 636; 736; 836; 936) and the third via (438; 638; 838; 938) may each have a cross-sectional shape of any one of a circle, an ellipse, and a polygon.

[0166] In one embodiment, the via structure may further include one or more first stacked vias (839a) stacked along the height direction between the first vias (436; 536; 636; 736; 836; 936) and the second pads (433; 533; 633; ​​733; 833; 933); and one or more second stacked vias (839b) stacked along the height direction between the third pads (434; 634; 834; 934) and the third vias (438; 638; 838; 938).

[0167] In one embodiment, based on a cross-section perpendicular to the height direction, the diameter (4372a) of the boundary portion (4372; 6372; 7372) is 220 um or less, and the diameter (433a) of the second pad (433; 533; 633; ​​733; 833; 933) may be 60 um or longer than the diameter (4372a) of the boundary portion (4372; 6372; 7372).

[0168] In one embodiment, the distance between the center axis (X1) of the first via (436; 536; 636; 736; 836; 936) and the center axis (X2) of the second via (437; 837; 937) may be 220 um or less.

[0169] In one embodiment, based on a cross-section perpendicular to the height direction, the area of ​​the third connection area (4363) where the first via (436; 536; 636; 736; 836; 936) is connected to the first pad (432; 532; 732; 832; 932) may be wider than the area of ​​the first connection area (4361; 5361).

[0170] In one embodiment, an electronic device (201) includes a housing (210); and a printed circuit board (300) disposed in an internal space of the housing (210), wherein the printed circuit board (300) includes a first circuit board (310); a second circuit board (320); and one or more interposers (330; 430; 830; 930) disposed between the first circuit board (310) and the second circuit board (320) and connecting the first circuit board (310) and the second circuit board (320) along a height direction, wherein the one or more interposers (330; 430; 830; 930) include an interposer substrate (4301; 8301; 9301) including a first surface (4301a) and a second surface (4301b) opposite to the first surface (4301a); A first pad (432; 532; 732; 832; 932) disposed on the first surface (4301a) and facing the first circuit board (310); a second pad (433; 533; 633; ​​733; 833; 933) spaced apart from the first pad (432; 532; 732; 832; 932) and disposed inside the interposer substrate (4301; 8301; 9301); a third pad (434; 634; 834; 934) spaced apart from the second pad (433; 533; 633; ​​733; 833; 933) and disposed inside the interposer substrate (4301; 8301; 9301); A fourth pad (435; 835; 935) spaced apart from the third pad (434; 634; 834; 934), arranged on the second surface (4301b), and facing the second circuit board (320); a first via (436; 536; 636; 736; 836; 936) connecting the first pad (432; 532; 732; 832; 932) and the second pad (433; 533; 633; ​​733; 833; 933); a second via (437; 837; 937) connecting the second pad (433; 533; 633; ​​733; 833; 933) and the third pad (434; 634; 834; 934); And the third pad (434;634;834;934) and the fourth pad (435;835;935) including a third via (438;638;838;938) connecting the second via (437;837;937), the core portion (4371) in which the dielectric (4371a) is positioned along the height direction; And a boundary portion (4372;6372;7372) positioned to surround the core portion (4371) along the height direction, and when looking at the first surface (4301a), a first connection area (4361;5361) in which the first via (436;536;636;736;836;936) is connected to the second pad (433;533;633;733;833;933) may overlap with the boundary portion (4372;6372;7372), and a second connection area (4381) in which the third via (438;638;838;938) is connected to the third pad (434;634;834;934) may overlap with the boundary portion (4372;6372;7372).

[0171] In one embodiment, the second pad (433; 533; 633; ​​733; 833; 933) includes a first body (4331; 5331; 6331; 7331); and a first opening (4330; 5330; 6330; 7330; 9330) penetrating the first body (4331; 5331; 6331; 7331) and overlapping the core portion (4371) when viewed from the first surface (4301a), and the third pad (434; 634; 834; 934) includes a second body (4341; 6341); And a second opening (4340; 6340; 9340) penetrating the second body (4341; 6341) and overlapping the core portion (4371) when looking at the first surface (4301a), and the first vias (436; 536; 636; 736; 836; 936) and the third vias (438; 638; 838; 938) are each provided in multiple numbers, and each of the plurality of first connection areas (4361; 5361) in which the plurality of first vias (436; 536; 636; 736; 836; 936) are connected to the second pad (433; 533; 633; ​​733; 833; 933) is connected to the first Each of the plurality of second connection areas (4381) that do not overlap with the openings (4330; 5330; 6330; 7330; 9330) and in which the plurality of third vias (438; 638; 838; 938) are connected to the third pads (434; 634; 834; 934) does not overlap with the second openings (4340; 6340; 9340), and the dielectric (4371a) can be exposed to the outside through the first openings (4330; 5330; 6330; 7330; 9330) and the second openings (4340; 6340; 9340).

[0172] In one embodiment, the electronic device (201) may further include a first bonding member (340; 940) connecting the first circuit board (310) and the interposer (330; 430; 830; 930); and a second bonding member (350; 950) connecting the second circuit board (320) and the interposer (330; 430; 830; 930).

[0173] In one embodiment, the first bonding member (340; 940) contacts the first pad (432; 532; 732; 832; 932), the second bonding member (350; 950) contacts the fourth pad (435; 835; 935), the first pad (432; 532; 732; 832; 932) includes a third body (4321; 7321; 9321); and a third opening (9320) penetrating the third body (4321; 7321; 9321), and the fourth pad (435; 835; 935) includes a fourth body (9351); And the fourth opening (9350) penetrating the fourth body (9351) is included, and the first bonding member (340; 940) is arranged to surround the third opening (9320) of the first pad (432; 532; 732; 832; 932), and the second bonding member (350; 950) can be arranged to surround the fourth opening (9350) of the fourth pad (435; 835; 935).

[0174] In one embodiment, an interposer (330; 430; 830; 930) of an electronic device (201) comprises: an interposer substrate (4301; 8301; 9301) comprising a first surface (4301a) and a second surface (4301b) opposite to the first surface (4301a); a first pad (432; 532; 732; 832; 932) disposed on the first surface (4301a); a second pad (433; 533; 633; ​​733; 833; 933) disposed inside the interposer substrate (4301; 8301; 9301) and spaced apart from the first pad (432; 532; 732; 832; 932); A third pad (434;634;834;934) spaced apart from the second pad (433;533;633;733;833;933) and arranged inside the interposer substrate (4301;8301;9301); A fourth pad (435;835;935) spaced apart from the third pad (434;634;834;934) and arranged on the second surface (4301b); A plurality of first vias (436;536;636;736;836;936) connecting the first pad (432;532;732;832;932) and the second pad (433;533;633;733;833;933); A second via (437;837;937) connecting the second pad (433;533;633;733;833;933) and the third pad (434;634;834;934); and a plurality of third vias (438;638;838;938) connecting the third pad (434;634;834;934) and the fourth pad (435;835;935), wherein the second via (437;837;937) comprises: a core portion (4371) having a height direction; And a boundary portion (4372; 6372; 7372) positioned to surround the core portion (4371) along the height direction, and the second pad (433; 533; 633; ​​733; 833; 933) comprises a first body (4331; 5331; 6331; 7331); and the first body (4331; 5331; 6331;7331) and includes a first opening (4330; 5330; 6330; 7330; 9330) overlapping with the core portion (4371) when looking at the first surface (4301a), and the third pad (434; 634; 834; 934) includes a second body (4341; 6341); And a second opening (4340; 6340; 9340) penetrating the second body (4341; 6341) and overlapping the core portion (4371) when looking at the first surface (4301a), and a plurality of first connection areas (4361; 5361) in which the plurality of first vias (436; 536; 636; 736; 836; 936) are connected to the second pads (433; 533; 633; ​​733; 833; 933) when looking at the first surface (4301a), each of the plurality of second connection areas (4361; 5361) overlapping the boundary portion (4372; 6372; 7372), and a plurality of third vias (438; 638; 838; 938) are connected to the third pads (434; 634; 834; 934) Each of the regions (4381) overlaps with the boundary portions (4372;6372;7372), each of the plurality of first connection regions (4361;5361) does not overlap with the first openings (4330;5330;6330;7330;9330), and each of the plurality of second connection regions (4381) may not overlap with the second openings (4340;6340;9340).

[0175] In one embodiment, the printed circuit board (300) may include a plurality of via structures (331) including a first via structure (331a) and a second via structure (331b) for electrically connecting one side and an opposite side of the printed circuit board (300); and an interposer substrate (4301; 8301; 9301) including a first side (4301a) and a second side (4301b) opposite to the first side (4301a). The first via structure (331a) may include a first pad (432; 532; 732; 832; 932) formed on the first side (4301a) of the interposer substrate (4301; 8301; 9301); A fourth pad (435; 835; 935) formed on a second surface (4301b) opposite to the first surface (4301a); a second pad (433; 533; 633; ​​733; 833; 933) formed inside the interposer substrate (4301; 8301; 9301) closer to the first pad (432; 532; 732; 832; 932) than the fourth pad (435; 835; 935); a third pad (434; 634; 834; 934) formed inside the interposer substrate (4301; 8301; 9301) closer to the fourth pad (435; 835; 935) than the first pad (432; 532; 732; 832; 932); It may include a second via (437;837;937) connected to the second pad (433;533;633;733;833;933) and the third pad (434;634;834;934); a plurality of first vias (436;536;636;736;836;936) connected to the first pad (432;532;732;832;932) and the second pad (433;533;633;733;833;933); and a plurality of third vias (438;638;838;938) connected to the fourth pad (435;835;935) and the third pad (434;634;834;934).The second pads (433; 533; 633; ​​733; 833; 933) may include first openings (4330; 5330; 6330; 7330; 9330) formed between the plurality of first vias (436; 536; 636; 736; 836; 936) and connected to the interior of the second vias (437; 837; 937).

[0176] In one embodiment, the second via (437; 837; 937) includes a boundary portion (4372; 6372; 7372) forming a boundary of the second via (437; 837; 937), and at least one of the plurality of first vias (436; 536; 636; 736; 836; 936) may be formed to overlap at least a portion of the boundary portion (4372; 6372; 7372).

[0177] In one embodiment, the first opening (4330; 5330; 6330; 7330; 9330) may include a first extension opening (6332; 6332a) formed in a portion of the boundary portion (4372; 6372; 7372).

[0178] In one embodiment, the internal space of the boundary portion (4372; 6372; 7372) is filled with a core portion (4371) formed of a non-conductive material, and a portion of the core portion (4371) can be exposed between the plurality of first vias (436; 536; 636; 736; 836; 936) through the first openings (4330; 5330; 6330; 7330; 9330).

[0179] In one embodiment, the diameter of the boundary portion (4372; 6372; 7372) is 220 um or less, and the diameter of the second pad (433; 533; 633; ​​733; 833; 933) may be at least 60 um longer than the diameter of the boundary portion (4372; 6372; 7372).

[0180] In one embodiment, the distance between the central axis (X1) of the first via structure (331a) and the central axis (X2) of the second via structure (331b) may be 550 um or less.

[0181] In one embodiment, the area where at least one of the plurality of first vias (436; 536; 636; 736; 836; 936) is connected to the first pad (432; 532; 732; 832; 932) may be formed to be wider than the area where at least one of the plurality of first vias (436; 536; 636; 736; 836; 936) meets the second pad (433; 533; 633; ​​733; 833; 933).

[0182] In one embodiment, the third pad (434; 634; 834; 934) may include a second opening (4340; 6340; 9340) formed between the plurality of third vias (438; 638; 838; 938) and connected to the interior of the second vias (437; 837; 937).

[0183] In one embodiment, the interposer substrate (4301; 8301; 9301) may form at least a portion of an interposer.

[0184] Additional embodiments according to the present invention are described below.

[0185] Paragraph 1. In an interposer (330; 430; 830; 930) for connecting printed circuit boards (300), an interposer substrate (4301; 8301; 9301) including a first surface (4301a) and a second surface (4301b) opposite to the first surface (4301a); And at least one via structure (331; 331a; 331b; 431) disposed on the interposer substrate (4301; 8301; 9301) (e.g., extending through the interposer substrate (4301; 8301; 9301)), wherein the via structure (331; 331a; 331b; 431) comprises: a first pad (432; 532; 732; 832; 932) disposed on the first surface (4301a); a second pad (433; 533; 633; ​​733; 833; 933) disposed inside the interposer substrate (4301; 8301; 9301) and spaced apart from the first pad (432; 532; 732; 832; 932); A third pad (434;634;834;934) spaced apart from the second pad (433;533;633;733;833;933) (e.g., in the direction of the second surface (4301b)); At least one first via (436;536;636;736;836;936) arranged between the first pad (432;532;732;832;932) and the second pad (433;533;633;733;833;933); And a second via (437;837;937) disposed (e.g., extending) between the second pad (433;533;633;733;833;933) and the third pad (434;634;834;934), wherein the second pad (433;533;633;733;933) comprises a first body (4331;5331;6331;7331) and at least one first opening (4330;5330;6330;7330;9330) penetrating the first body, wherein the at least one first via is connected to the first body (4331;5331;6331;7331) of the second pad (433;533;633;733;833;933). Interposer (330;430;830;930)

[0186] Paragraph 2. In paragraph 1, the second via (437; 837; 937) includes a core portion (4371) having a height direction (e.g., extending in the height direction of the interposer substrate between the second pad and the third pad); and a boundary portion (4372; 6372; 7372) positioned (e.g., configured) to surround the core portion (4371) along the height direction, and when looking at the first surface (e.g., when looking from the first surface), the first opening (4330; 5330; 6330; 7330; 9330) of the second pad (433; 533; 633; ​​733; 833; 933) overlaps at least a portion of the core portion.

[0187] Paragraph 3. In paragraph 1 or paragraph 2, the core portion (4371) and the interposer substrate (4301; 8301; 9301) (e.g., materials of the core portion and the interposer substrate) have different thermal expansion coefficients, the interposer (330; 430; 830; 930).

[0188] Paragraph 4. An interposer (330; 430; 830; 930), wherein in any one of paragraphs 1 to 3, a dielectric (4371a) is positioned in the core portion (4371), and the dielectric (4371a) is exposed to the outside through the first opening (4330; 5330; 6330; 7330; 9330).

[0189] Paragraph 5. An interposer (330; 430; 830; 930), wherein in any one of paragraphs 1 to 4, the first vias (436; 536; 636; 736; 836; 936) are provided in plurality, and the plurality of first vias (436; 536; 636; 736; 836; 936) are each connected to the first body of the second pad.

[0190] Paragraph 6. In any one of paragraphs 1 to 5, the third pad (434; 634; 834; 934) is disposed inside the interposer substrate (4301; 8301; 9301), and the via structure (331; 331a; 331b; 431) is spaced apart from the third pad (434; 634; 834; 934) and disposed on the second surface (4301b); And further comprising at least one third via (438;638;838;938) disposed between the third pad (434;634;834;934) and the fourth pad (435;835;935), wherein the third pad (434;634;834;934) comprises a second body (4341;6341), wherein the third via (438;638;838;938) is connected to the second body (4341;6341); and at least one second opening (4340;6340;9340) penetrating the second body (4341;6341).

[0191] Paragraph 7. In any one of paragraphs 1 to 6, the first via (736) has an arc-shaped cross-sectional shape in which two arcs (736a-1; 736a-2) are connected based on a cross-section perpendicular to the height direction of the first via (736). An interposer (330; 430; 830; 930).

[0192] Paragraph 8. An interposer (330; 430; 830; 930) according to any one of paragraphs 1 to 7, wherein the second pad (633) further includes a first extension opening (6332; 6332a) penetrating the first body (6331) and extending from a periphery of the first opening (6330).

[0193] Paragraph 9. An interposer (330; 430; 830; 930) in any one of paragraphs 1 to 8, wherein the second pad (633) is separated into at least two parts (633a; 633b; 633c) by the first extension opening (6332a).

[0194] Paragraph 10. In any one of paragraphs 1 to 9, the first pad (932) comprises: a third body (9321); and an interposer (330; 430; 830; 930) including a third opening (9320) penetrating the third body (9321).

[0195] Paragraph 11. An interposer (330; 430; 830; 930), wherein in any one of paragraphs 1 to 10, the via structure (331; 331a; 331b; 431) further includes at least one first stacked via (839a) stacked along the height direction between the first via (436; 536; 636; 736; 836; 936) and the second pad (433; 533; 633; ​​733; 833; 933).

[0196] Paragraph 12. An interposer (330; 430; 830; 930), wherein, in any one of paragraphs 1 to 11, a diameter (4372a) of the boundary portion (4372; 6372; 7372) is 220 um or less, and a diameter (433a) of the second pad (433; 533; 633; ​​733; 833; 933) is 60 um or longer than the diameter (4372a) of the boundary portion (4372; 6372; 7372).

[0197] Paragraph 13. An interposer (330; 430; 830; 930), wherein in any one of paragraphs 1 to 12, the via structures (331; 331a; 331b; 431) are provided in plurality, and the distance (D1) between the center axes (X1; X2) of each of the plurality of via structures (331; 331a; 331b; 431) is 550 um or less.

[0198] Paragraph 14. An interposer (330;430;830;930), wherein in any one of paragraphs 1 to 13, the area of ​​the third connection area (4363) where the first via (436;536;636;736;836;936) is connected to the first pad (432;532;732;832;932) is wider than the area of ​​the first connection area (4361;5361) where the first via (436;536;636;736;836;936) is connected to the second pad (433;533;633;733;833;933).

[0199] Paragraph 15. An interposer (330; 430; 830; 930) in any one of paragraphs 1 to 14, wherein the first via (436; 536; 636; 736; 836; 936) is formed by laser processing, and the second via (437; 837; 937) is formed by drilling.

[0200] Paragraph 16. In an electronic device (201), a housing (210) is provided; and a printed circuit board (300) is arranged in an internal space of the housing (210), wherein the printed circuit board (300) comprises: a first circuit board (310); a second circuit board (320); And one or more interposers (330; 430; 830; 930) disposed between the first circuit board (310) and the second circuit board (320) and configured to connect the first circuit board (310) and the second circuit board (320) along a height direction (e.g., a height direction of the interposer, the printed circuit board, and the printed circuit board stack), wherein the one or more interposers (330; 430; 830; 930) include an interposer substrate (4301; 8301; 9301) including a first surface (4301a) and a second surface (4301b) opposite to the first surface (4301a); And at least one via structure (331; 331a; 331b; 431) disposed on the interposer substrate (4301; 8301; 9301), wherein the via structure (331; 331a; 331b; 431) comprises: a first pad (432; 532; 732; 832; 932) disposed on the first surface (4301a) and facing the first circuit board (310); a second pad (433; 533; 633; ​​733; 833; 933) spaced apart from the first pad (432; 532; 732; 832; 932) and disposed inside the interposer substrate (4301; 8301; 9301); A third pad (434;634;834;934) spaced apart from the second pad (433;533;633;733;833;933) and arranged inside the interposer substrate (4301;8301;9301); A fourth pad (435;835;935) spaced apart from the third pad (434;634;834;934) and arranged on the second surface (4301b) and facing the second circuit board (320); A first via (436;536;636;736;836) arranged between the first pad (432;532;732;832;932) and the second pad (433;533;633;733;833;933);936); a second via (437; 837; 937) disposed between the second pad (433; 533; 633; ​​733; 833; 933) and the third pad (434; 634; 834; 934); and a third via (438; 638; 838; 938) disposed between the third pad (434; 634; 834; 934) and the fourth pad (435; 835; 935), wherein the second via (437; 837; 937) comprises: a core portion (4371) in which a dielectric (4371a) is positioned along the height direction; And an electronic device (201) including a boundary portion (4372;6372;7372) positioned to surround the core portion (4371) along the height direction, and when looking at the first surface (4301a), a first connection area (4361;5361) in which the first via (436;536;636;736;836;936) is connected to the second pad (433;533;633;733;833;933) overlaps with the boundary portion (4372;6372;7372), and a second connection area (4381) in which the third via (438;638;838;938) is connected to the third pad (434;634;834;934) overlaps with the boundary portion (4372;6372;7372).;

[0201] Paragraph 17. In paragraph 16, the second pad (433; 533; 633; ​​733; 833; 933) includes a first body (4331; 5331; 6331; 7331); and a first opening (4330; 5330; 6330; 7330; 9330) penetrating the first body (4331; 5331; 6331; 7331) and overlapping the core portion (4371) when looking at the first surface (4301a), and the third pad (434; 634; 834; 934) includes a second body (4341; 6341); And a second opening (4340; 6340; 9340) penetrating the second body (4341; 6341) and overlapping the core portion (4371) when looking at the first surface (4301a), and the first vias (436; 536; 636; 736; 836; 936) and the third vias (438; 638; 838; 938) are each provided in multiple numbers, and each of the plurality of first connection areas (4361; 5361) in which the plurality of first vias (436; 536; 636; 736; 836; 936) are connected to the second pad (433; 533; 633; ​​733; 833; 933) is connected to the first An electronic device (201), wherein each of a plurality of second connection areas (4381) that do not overlap with the openings (4330; 5330; 6330; 7330; 9330) and wherein the plurality of third vias (438; 638; 838; 938) are connected to the third pads (434; 634; 834; 934) does not overlap with the second openings (4340; 6340; 9340), and the dielectric (4371a) is exposed to the outside through the first openings (4330; 5330; 6330; 7330; 9330) and the second openings (4340; 6340; 9340).

[0202] Paragraph 18. In paragraph 16 or paragraph 17, the electronic device (201) further includes a first bonding member (340; 940) connecting the first circuit board (310) and the interposer (330; 430; 830; 930); and a second bonding member (350; 950) connecting the second circuit board (320) and the interposer (330; 430; 830; 930).

[0203] Paragraph 19. In any one of paragraphs 16 to 18, the first bonding member (340; 940) contacts the first pad (432; 532; 732; 832; 932), the second bonding member (350; 950) contacts the fourth pad (435; 835; 935), the first pad (432; 532; 732; 832; 932) comprises a third body (4321; 7321; 9321); and a third opening (9320) penetrating the third body (4321; 7321; 9321), and the fourth pad (435; 835; 935) comprises a fourth body (9351); And an electronic device (201) comprising a fourth opening (9350) penetrating the fourth body (9351), wherein the first bonding member (340; 940) is arranged to surround the third opening (9320) of the first pad (432; 532; 732; 832; 932), and the second bonding member (350; 950) is arranged to surround the fourth opening (9350) of the fourth pad (435; 835; 935).

[0204] Paragraph 20. A printed circuit board (300), comprising a plurality of via structures (331) including a first via structure (331a) and a second via structure (331b) for electrically connecting one side and an opposite side of the printed circuit board (300); and an interposer substrate (4301; 8301; 9301) including a first side (4301a) and a second side (4301b) opposite to the first side (4301a), wherein the first via structure (331a) comprises a first pad (432; 532; 732; 832; 932) formed on the first side (4301a) of the interposer substrate (4301; 8301; 9301); A fourth pad (435; 835; 935) formed on a second surface (4301b) opposite to the first surface (4301a); a second pad (433; 533; 633; ​​733; 833; 933) formed inside the interposer substrate (4301; 8301; 9301) closer to the first pad (432; 532; 732; 832; 932) than the fourth pad (435; 835; 935); a third pad (434; 634; 834; 934) formed inside the interposer substrate (4301; 8301; 9301) closer to the fourth pad (435; 835; 935) than the first pad (432; 532; 732; 832; 932); Second vias (437;837;937) connected to the second pads (433;533;633;733;833;933) and the third pads (434;634;834;934); a plurality of first vias (436;536;636;736;836;936) connected to the first pads (432;532;732;832;932) and the second pads (433;533;633;733;833;933); And a plurality of third vias (438;638;838;938) connected to the fourth pad (435;835;935) and the third pad (434;634;834;934), and the second pad (433;533;633;733;833;933) is formed between the plurality of first vias (436;536;636;736;836;936), and the second via (437;837;A printed circuit board (300) comprising a first opening (4330; 5330; 6330; 7330; 9330) connected to the interior of the 937);

[0205]

[0206] All examples, embodiments, and features disclosed in this disclosure may be combined in any suitable manner, unless otherwise described as incompatible or mutually exclusive. Furthermore, features of various examples and embodiments may be omitted unless described as essential.

Claims

1. In the interposer (330; 430; 830; 930) for connecting printed circuit boards (300), An interposer substrate (4301; 8301; 9301) comprising a first side (4301a) and a second side (4301b) opposite to the first side (4301a); and At least one via structure (331; 331a; 331b; 431) disposed on the interposer substrate (4301; 8301; 9301), The above via structure (331; 331a; 331b; 431) is A first pad (432; 532; 732; 832; 932) arranged on the first surface (4301a); A second pad (433;533;633;733;833;933) spaced apart from the first pad (432;532;732;832;932) and positioned inside the interposer substrate (4301;8301;9301); A third pad (434;634;834;934) spaced apart from the second pad (433;533;633;733;833;933) in the direction of the second surface (4301b); At least one first via (436;536;636;736;836;936) extending between the first pad (432;532;732;832;932) and the second pad (433;533;633;733;833;933); and A second via (437;837;937) extending between the second pad (433;533;633;733;833;933) and the third pad (434;634;834;934) is included, An interposer (330;430;830;930), wherein the second pad (433;533;633;733;933) comprises a first body (4331;5331;6331;7331) and at least one first opening (4330;5330;6330;7330;9330) penetrating the first body, and wherein the at least one first via connects the second pad (433;533;633;733;833;933) to the first body (4331;5331;6331;7331).

2. In paragraph 1, The above second via (437;837;937) is, A core portion (4371) extending between the second pad (433) and the third pad (434) in the height direction of the interposer substrate (4301); and It includes a boundary portion (4372; 6372; 7372) configured to surround the core portion (4371) along the height direction, When looking at the first surface (4301a), the first opening (4330; 5330; 6330; 7330; 9330) of the second pad (433; 533; 633; ​​733; 833; 933) overlaps at least a portion of the core portion, interposer (330; 430; 830; 930).

3. In paragraph 2, Based on the cross section perpendicular to the above height direction, The diameter (4372a) of the above boundary portion (4372; 6372; 7372) is 220 um or less, The diameter (433a) of the second pad (433;533;633;733;833;933) is 60um or longer than the diameter (4372a) of the boundary portion (4372;6372;7372), the interposer (330;430;830;930).

4. In paragraph 2 or 3, The interposer (330; 430; 830; 930) has different thermal expansion coefficients, the core portion (4371) and the interposer substrate (4301; 8301; 9301).

5. In any one of paragraphs 2 to 4, A dielectric (4371a) is positioned in the above core portion (4371), The above dielectric (4371a) is exposed to the outside of the second via (437;837;937) through the first opening (4330;5330;6330;7330;9330) of the interposer (330;430;830;930).

6. In any one of paragraphs 1 to 5, The at least one first via (436;536;636;736;836;936) comprises a plurality of first vias (436;536;636;736;836;936), The above plurality of first vias (436; 536; 636; 736; 836; 936) are each connected to the first body of the second pad, interposer (330; 430; 830; 930).

7. In any one of paragraphs 1 to 6, The first via (736) includes an arc-shaped cross-section and surrounds the first opening (7330) formed in the second pad (733), the interposer (330; 430; 830; 930).

8. In any one of paragraphs 1 to 7, The above second pad (633) is Further comprising a first extension opening (6332; 6332a) penetrating the first body (6331) and extending from the periphery of the first opening (6330), The interposer (330; 430; 830; 930) wherein the second pad (633) is separated into at least two parts (633a; 633b; 633c) by the first extension opening (6332a).

9. In any one of paragraphs 1 to 8, The above via structure (331; 331a; 331b; 431) is An interposer (330;430;830;930) further comprising at least one first stacked via (839a) stacked along the height direction of the interposer substrate (4301;8301;9301) between the first via (436;536;636;736;836;936) and the second pad (433;533;633;733;833;933).

10. In any one of paragraphs 1 to 9, An interposer (330;430;830;930), wherein the width of the third connection area (4363) where the first via (436;536;636;736;836;936) is connected to the first pad (432;532;732;832;932) is wider than the width of the first connection area (4361;5361) where the first via (436;536;636;736;836;936) is connected to the second pad (433;533;633;733;833;933).

11. In any one of paragraphs 1 to 10, The above at least one via structure (331;331a;331b;431) includes a plurality of via structures (331;331a;331b;431), An interposer (330; 430; 830; 930) in which the distance (D1) between the center axes (X1; X2) of each of the plurality of via structures (331; 331a; 331b; 431) is 550 um or less.

12. In any one of paragraphs 1 to 11, The third pad (434; 634; 834; 934) is placed inside the interposer substrate (4301; 8301; 9301), At least one via structure (331; 331a; 331b; 431) above, A fourth pad (435; 835; 935) spaced apart from the third pad (434; 634; 834; 934) and arranged on the second surface (4301b); and Further comprising at least one third via (438;638;838;938) extending between the third pad (434;634;834;934) and the fourth pad (435;835;935), The above third pad (434;634;834;934) is As a second body (4341;6341), the third via (438;638;838;938) is connected to the second body (4341;6341); and An interposer (330; 430; 830; 930) comprising at least one second opening (4340; 6340; 9340) penetrating the second body (4341; 6341).

13. In the electronic device (201), Housing (210); and It includes a printed circuit board (300) placed in the internal space of the above housing (210), The above printed circuit board (300) is First circuit board (310); Second circuit board (320); and An electronic device (201) comprising at least one interposer (330; 430; 830; 930) according to claim 12, which is disposed between the first circuit board (310) and the second circuit board (320) and connects the first circuit board (310) and the second circuit board (320) in a stack.

14. In paragraph 13, The above electronic device (201) A first bonding member (340; 940) connecting the first circuit board (310) and the interposer (330; 430; 830; 930); and An electronic device (201) further comprising a second bonding member (350; 950) connecting the second circuit board (320) and the interposer (330; 430; 830; 930).

15. In paragraph 14, The first bonding member (340; 940) is in contact with the first pad (432; 532; 732; 832; 932), The second bonding member (350;950) is in contact with the fourth pad (435;835;935), The above first pad (432; 532; 732; 832; 932) is Third body (4321; 7321; 9321); and Includes a third opening (9320) penetrating the third body (4321; 7321; 9321), The above fourth pad (435; 835; 935) is 4th body (9351); and Including a fourth opening (9350) penetrating the fourth body (9351), The first bonding member (340; 940) is arranged to surround the third opening (9320) of the first pad (432; 532; 732; 832; 932), An electronic device (201) wherein the second bonding member (350; 950) is arranged to surround the fourth opening (9350) of the fourth pad (435; 835; 935).

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